Semiconductor equipment

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor chip CHP3 is provided, having a transformer for non-contact communication between different potentials. This semiconductor chip CHP3 comprises a p-type semiconductor substrate SUB3, a p-type semiconductor region PR1 formed on the surface of the semiconductor substrate SUB3, and a transformer provided above the semiconductor substrate SUB3. The transformer includes: a lower layer inductor 300; a lead wiring portion electrically connected to the lower layer inductor 300; and an upper layer inductor 100 magnetically coupled with the lower layer inductor 300. The lead wiring portion has wiring 10a opposed to the p-type semiconductor region PR1.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a semiconductor device that enables signal transmission between different potentials by using, for example, a pair of inductively coupled inductors.

Background Art

[0002] Japanese Unexamined Patent Application Publication No. 2011-82212 (Patent Document 1) describes a technique that enables an increase in the coil cross-sectional area without hindering miniaturization in order to reduce the series resistance that occupies most of the parasitic resistance component of the coil constituting a transformer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, there is a transformer (digital isolator) that enables non-contact signal transmission by using a pair of inductively coupled inductors. According to this transformer, since signal transmission in a non-contact state is possible, an advantage is obtained in that electrical noise from one circuit can be suppressed from adversely affecting the other circuit. Therefore, by using a semiconductor device having a transformer, the signal transmission quality can be improved.

[0005] In this regard, semiconductor devices containing transformers use bonding wires to electrically connect the circuit and the transformer. This can lead to the generation of high-frequency noise due to parasitic inductance in the bonding wires, potentially degrading signal transmission quality. Therefore, there is room for improvement in semiconductor devices containing transformers from the perspective of improving signal transmission quality. In other words, in semiconductor devices containing transformers, measures to suppress the degradation of signal transmission quality caused by parasitic inductance in bonding wires are desirable. [Means for solving the problem]

[0006] One embodiment of a semiconductor device is a semiconductor device having a transformer that performs contactless communication between different potentials. This semiconductor device comprises a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type formed on the surface of the semiconductor substrate, and a transformer provided above the semiconductor substrate. Here, the transformer includes a lower inductor, a lead-out wiring section electrically connected to the lower inductor, and an upper inductor magnetically coupled to the lower inductor, and the lead-out wiring section has a first wiring facing the first semiconductor region.

[0007] A semiconductor device in one embodiment includes a first chip on which a first circuit to which a first potential is applied is formed, a second chip on which a second circuit to which a second potential is applied is formed, a third chip on which a transformer for contactless communication between different potentials is formed, a first bonding wire that electrically connects the first chip and the third chip, and a second bonding wire that electrically connects the second chip and the third chip. Here, the third chip includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type formed on the surface of the semiconductor substrate, and a transformer provided above the semiconductor substrate. In this case, the transformer includes a lower inductor, a lead-out wiring section electrically connected to the lower inductor, and an upper inductor magnetically coupled to the lower inductor, and the lead-out wiring section includes a first wiring facing the first semiconductor region. [Effects of the Invention]

[0008] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example configuration of a drive control unit that drives a load circuit. [Figure 2] This is an explanatory diagram showing an example of signal transmission. [Figure 3] This diagram shows a two-chip configuration. [Figure 4] This diagram shows a 3-chip configuration. [Figure 5] This is a conceptual diagram showing a semiconductor device with a "two-chip configuration". [Figure 6] This is a conceptual diagram showing a semiconductor device with a "3-chip configuration". [Figure 7] This is a circuit diagram showing the configuration of a low-pass filter. [Figure 8] This is a conceptual diagram illustrating the application of the basic concept to a semiconductor device with a "3-chip configuration" that includes a transformer. [Figure 9] This is a cross-sectional view showing a schematic configuration of a semiconductor device in its implemented form. [Figure 10] This is a plan view showing the planar layout of a semiconductor chip in its implemented form. [Figure 11] This is a schematic cross-sectional view of a semiconductor chip in its materialized form, and is a cross-sectional view taken along line AA in Figure 10. [Figure 12] This is an example of a plan view showing a lower-layer inductor, the wiring connected to this lower-layer inductor, and the lower-layer pad connected to the wiring. [Figure 13] This is another example of a plan view showing a lower-layer inductor, the wiring connected to this lower-layer inductor, and the lower-layer pad connected to the wiring. [Figure 14] This is yet another example of a plan view showing a lower inductor, the wiring connected to this lower inductor, and the lower pad connected to the wiring. [Figure 15] It is a cross-sectional view showing a modification of the embodiment shown in FIG. 11.

Embodiments for Carrying Out the Invention

[0010] In all the drawings for explaining the embodiments, the same members are generally denoted by the same reference numerals, and the repeated explanations thereof are omitted. Note that, for the sake of clarity of the drawings, even in a plan view, hatching may be added.

[0011] <Circuit Configuration> FIG. 1 is a diagram showing a configuration example of a drive control unit that drives a load circuit such as a motor.

[0012] As shown in FIG. 1, the drive control unit includes a control circuit CC, a transformer TR1, a transformer TR2, a drive circuit DR, and an inverter INV, and is electrically connected to a load circuit LOD.

[0013] The transmission circuit TX1 and the reception circuit RX1 are circuits for transmitting a control signal output from the control circuit CC to the drive circuit DR. On the other hand, the transmission circuit TX2 and the reception circuit RX2 are circuits for transmitting a signal output from the drive circuit DR to the control circuit CC. The control circuit CC is a circuit having a function of controlling the drive circuit DR. The drive circuit DR is a circuit that operates an inverter INV for controlling the load circuit LOD based on the control from the control circuit CC.

[0014] A power supply potential VCC1 is supplied to the control circuit CC, and the control circuit CC is grounded by a ground potential GND1. On the other hand, a power supply potential VCC2 is supplied to the inverter INV, and the inverter INV is grounded by a ground potential GND2. At this time, for example, the power supply potential VCC1 is smaller than the power supply potential VCC2 supplied to the inverter INV. In other words, the power supply potential VCC2 supplied to the inverter INV is larger than the power supply potential VCC1.

[0015] A transformer TR1, consisting of inductively coupled (magnetically coupled) coils (inductors) CL1a and CL1b, is interposed between the transmitting circuit TX1 and the receiving circuit RX1. This allows signals to be transmitted from the transmitting circuit TX1 to the receiving circuit RX1 via the transformer TR1. As a result, the drive circuit DR can receive the control signal output from the control circuit CC via the transformer TR1.

[0016] In this way, by using inductive coupling to electrically isolate the transformer TR1, the transmission of electrical noise from the control circuit CC to the drive circuit DR can be suppressed while transmitting the control signal from the control circuit CC to the drive circuit DR. As a result, malfunctions of the drive circuit DR caused by the superposition of electrical noise on the control signal can be suppressed, thereby improving the operational reliability of the semiconductor device.

[0017] The coils CL1a and CL1b that make up the transformer TR1 each function as inductors. The transformer TR1 functions as a magnetic coupling element consisting of the inductively coupled coils CL1a and CL1b.

[0018] Similarly, a transformer TR2, consisting of inductively coupled coils CL2b and CL2a, is interposed between the transmitting circuit TX2 and the receiving circuit RX2. This allows signals to be transmitted from the transmitting circuit TX2 to the receiving circuit RX2 via the transformer TR2. As a result, the control circuit CC can receive the signal output from the drive circuit DR via the transformer TR2.

[0019] In this way, by using inductive coupling to electrically isolate the transformer TR2, it is possible to transmit signals from the drive circuit DR to the control circuit CC while suppressing the transmission of electrical noise from the drive circuit DR to the control circuit CC. As a result, malfunctions of the control circuit CC caused by the superposition of electrical noise on the signal can be suppressed, thereby improving the operational reliability of the semiconductor device.

[0020] Transformer TR1 is composed of coils CL1a and CL1b. Coils CL1a and CL1b are not connected by a conductor but are magnetically coupled. Therefore, when current flows through coil CL1a, an induced electromotive force is generated in coil CL1b in response to the change in current, causing an induced current to flow. In this case, coil CL1a is the primary coil and coil CL1b is the secondary coil. Thus, transformer TR1 utilizes the electromagnetic induction phenomenon that occurs between coils CL1a and CL1b. Specifically, when a signal is sent from the transmitting circuit TX1 to coil CL1a of transformer TR1, causing a current to flow, the receiving circuit RX1 detects the induced current generated in coil CL1b of transformer TR1, and the receiving circuit RX1 can receive a signal corresponding to the control signal output from the transmitting circuit TX1.

[0021] Similarly, the transformer TR2 is composed of coils CL2a and CL2b, which are not connected by a conductor but are magnetically coupled. As a result, when current flows through coil CL2b, an induced electromotive force is generated in coil CL2a in response to the change in that current, causing an induced current to flow. In this way, by sending a signal from the transmitting circuit TX2 to coil CL2b of the transformer TR2 and causing a current to flow, the receiving circuit RX2 can detect the induced current generated in coil CL2a of the transformer TR2, and thereby receive a signal corresponding to the control signal output from the transmitting circuit TX2.

[0022] Signal transmission and reception between the control circuit CC and the drive circuit DR are performed via two paths: one from the transmitting circuit TX1 to the receiving circuit RX1 via transformer TR1, and another from the transmitting circuit TX2 to the receiving circuit RX2 via transformer TR2. In other words, signals can be transmitted and received between the control circuit CC and the drive circuit DR by receiving the signal transmitted by the transmitting circuit TX1 to the receiving circuit RX1, and by receiving the signal transmitted by the transmitting circuit TX2 to the receiving circuit RX2. As described above, transformer TR1 is involved in the transmission of signals from the transmitting circuit TX1 to the receiving circuit RX1, while transformer TR2 is involved in the transmission of signals from the transmitting circuit TX2 to the receiving circuit RX2. This allows the drive circuit DR to drive the inverter INV for operating the load circuit LOD in response to the signal transmitted from the control circuit CC.

[0023] The control circuit CC and the drive circuit DR have different reference potential voltage levels. Specifically, in the control circuit CC, the reference potential is fixed to the ground potential GND1, while, as shown in Figure 1, the drive circuit DR is electrically connected to the inverter INV. The inverter INV has, for example, a high-side IGBT (Insulated Gate Bipolar Transistor) and a low-side IGBT. The inverter INV controls the load circuit LOD by controlling the on / off state of the high-side IGBT and the low-side IGBT via the drive circuit DR. Specifically, the on / off control of the high-side IGBT is performed by controlling the potential applied to the gate electrode of the high-side IGBT by the drive circuit DR. Similarly, the on / off control of the low-side IGBT is performed by controlling the potential applied to the gate electrode of the low-side IGBT by the drive circuit DR.

[0024] Here, for example, the ON control of the low-side IGBT is achieved by applying "emitter potential (0V) + threshold voltage (15V)" to the gate electrode, with the emitter potential (0V) of the low-side IGBT connected to the ground potential GND2 as the reference. On the other hand, for example, the OFF control of the low-side IGBT is achieved by applying "emitter potential (0V)" to the gate electrode, with the emitter potential (0V) of the low-side IGBT connected to the ground potential GND2 as the reference.

[0025] Therefore, the on / off control of the low-side IGBT is performed by whether or not a threshold voltage (15V) is applied to the gate electrode, with 0V as the reference potential.

[0026] On the other hand, for example, the ON control of a high-side IGBT is also performed by using the emitter potential of the high-side IGBT as the reference potential, and applying "reference potential + threshold voltage (15V)" to the gate electrode relative to this reference potential.

[0027] However, the emitter potential of the high-side IGBT is not fixed to the ground potential GND2, unlike the emitter potential of the low-side IGBT. In other words, in the inverter INV, the high-side IGBT and the low-side IGBT are connected in series between the power supply potential VCC2 and the ground potential GND2. The inverter INV controls the low-side IGBT to turn off when the high-side IGBT is turned on, and to turn on when the high-side IGBT is turned off. Therefore, when the high-side IGBT is off, the low-side IGBT is on, and the emitter potential of the high-side IGBT becomes the ground potential GND2 due to the on low-side IGBT.

[0028] On the other hand, when the high-side IGBT is ON, the low-side IGBT is OFF, so the emitter potential of the high-side IGBT becomes the IGBT bus voltage. In this case, the ON / OFF control of the high-side IGBT is performed by whether or not to apply "reference potential + threshold voltage (15V)" to the gate electrode, using the emitter potential of the high-side IGBT as the reference potential.

[0029] As mentioned above, the emitter potential of the high-side IGBT varies depending on whether the high-side IGBT is on or off. That is, the emitter potential of the high-side IGBT varies from the ground potential GND2 (0V) to the power supply potential VCC2 (e.g., 800V). Therefore, in order to turn on the high-side IGBT, it is necessary to apply "IGBT bus voltage (800V) + threshold voltage (15V)" to the gate electrode, using the emitter potential of the high-side IGBT as the reference potential. For this reason, the drive circuit DR that controls the on / off state of the high-side IGBT needs to know the emitter potential of the high-side IGBT. For this reason, the drive circuit DR is configured to receive the emitter potential of the high-side IGBT as input. As a result, the drive circuit DR receives a reference potential of 800V, and the drive circuit DR controls the high-side IGBT to turn on by applying a threshold voltage of 15V (15V) to the gate electrode of the high-side IGBT relative to this 800V reference potential. Therefore, a high potential of approximately 800V is applied to the drive circuit DR.

[0030] Thus, the drive control unit has a control circuit CC that handles low potentials (tens of volts) and a drive circuit DR that handles high potentials (hundreds of volts). Therefore, signal transmission between the control circuit CC and the drive circuit DR requires signal transmission between circuits with different potentials.

[0031] In this regard, since the signal transmission between the control circuit CC and the drive circuit DR is carried out via transformers TR1 and TR2, signal transmission between circuits of different potentials is possible.

[0032] As described above, in transformers TR1 and TR2, a large potential difference may occur between the primary and secondary coils. Conversely, because a large potential difference may occur, the primary and secondary coils are magnetically coupled rather than connected by a conductor and used for signal transmission. Therefore, when forming transformer TR1, it is important to make the dielectric breakdown voltage between coil CL1a and coil CL1b as high as possible from the viewpoint of improving the operational reliability of the semiconductor device. Similarly, when forming transformer TR2, it is important to make the dielectric breakdown voltage between coil CL2b and coil CL2a as high as possible from the viewpoint of improving the operational reliability of the semiconductor device.

[0033] <Example of signal transmission> Figure 2 is an explanatory diagram showing an example of signal transmission.

[0034] In Figure 2, the transmitting circuit TX1 extracts the edge portion of the square wave signal SG1 input to the transmitting circuit TX1 to generate a signal SG2 with a constant pulse width, and sends signal SG2 to the coil CL1a (primary coil) of the transformer TR1. When the current caused by this signal SG2 flows through the coil CL1a (primary coil) of the transformer TR1, a corresponding signal SG3 flows through the coil CL1b (secondary coil) of the transformer TR1 due to induced electromotive force. This signal SG3 is amplified by the receiving circuit RX1 and further modulated into a square wave, so that the square wave signal SG4 is output from the receiving circuit RX1. In this way, the receiving circuit RX1 can output signal SG4 corresponding to the signal SG1 input to the transmitting circuit TX1. In this manner, a signal can be transmitted from the transmitting circuit TX1 to the receiving circuit RX1. Signal transmission from the transmitting circuit TX2 to the receiving circuit RX2 can be performed in the same way.

[0035] <2-chip configuration> The transmit / receive circuit section of the drive control unit described above is formed, for example, on two separate semiconductor chips. Specifically, Figure 3 shows a two-chip configuration. In Figure 3, the semiconductor chip CHP1 has a transmit circuit TX1, a transformer TR1, and a receive circuit RX2. On the other hand, the semiconductor chip CHP2 has a receive circuit RX1, a drive circuit DR, a transmit circuit TX2, and a transformer TR2. In such a two-chip configuration, for example, the transformer TR1 is formed on the same semiconductor chip CHP1 as the transmit circuit TX1 and the receive circuit RX2. Therefore, integration of the transformer TR1, the transmit circuit TX1, and the receive circuit RX2 becomes possible. Similarly, the transformer TR2 is formed on the same semiconductor chip CHP2 as the drive circuit DR, the receive circuit RX1, and the transmit circuit TX2. Therefore, integration of the transformer TR2, the drive circuit DR, the receive circuit RX1, and the transmit circuit TX2 becomes possible.

[0036] However, in a two-chip configuration, the manufacturing process for semiconductor chip CHP1 becomes more complex because, for example, the transformer TR1, the transmit circuit TX1, and the receive circuit RX2 must be formed on a single semiconductor chip. Similarly, in a two-chip configuration, the manufacturing process for semiconductor chip CHP2 becomes more complex because, for example, the transformer TR2, the drive circuit DR, the receive circuit RX1, and the transmit circuit TX2 must be formed on a single semiconductor chip. As a result, the manufacturing costs of semiconductor chips CHP1 and CHP2 increase.

[0037] <3-chip configuration> Therefore, it is being considered to implement the aforementioned transmitting and receiving circuit section using a three-chip configuration instead of a two-chip configuration. The novel three-chip configuration will be described below.

[0038] Figure 4 shows a three-chip configuration. In Figure 4, semiconductor chip CHP1 has a transmit circuit TX1 and a receive circuit RX2. Semiconductor chip CHP2 has a drive circuit DR, a receive circuit RX1 and a transmit circuit TX2. In other words, semiconductor chip CHP1 has a first circuit (transmitter circuit TX1 and receive circuit RX2) configured to apply a first potential. Semiconductor chip CHP2 has a second circuit (drive circuit DR, receive circuit RX1 and transmit circuit TX2) configured to apply a second potential. Meanwhile, semiconductor chip CHP3 has transformers TR1 and TR2.

[0039] As a result, in a 3-chip configuration, the semiconductor chip CHP3 has only transformers TR1 and TR2 formed on it. In other words, in a 3-chip configuration, semiconductor chip CHP3 can be used regardless of the configuration of semiconductor chips CHP1 and CHP2. Therefore, a 3-chip configuration offers the advantage of increasing the variations of usable semiconductor chips CHP1 and CHP2. In other words, the versatility of semiconductor chip CHP3 on which transformers TR1 and TR2 are formed can be increased. Furthermore, since semiconductor chip CHP3 on which transformers TR1 and TR2 are formed does not contain transistors, it can be formed only through the wiring process, resulting in a simplification of the manufacturing process. Therefore, a 3-chip configuration makes it possible to reduce manufacturing costs, thereby enabling the production of highly competitive products.

[0040] <Consideration of improvements> As described above, there is a semiconductor device with a so-called "two-chip configuration" in which a transformer is mounted on either a first semiconductor chip on which one circuit is formed, or a second semiconductor chip on which the other circuit is formed. Figure 5 is a conceptual diagram showing a semiconductor device with a "two-chip configuration". In Figure 5, the semiconductor chip CHP1 has a transmitting circuit TX1 and a transformer TR1 formed on it, while the semiconductor chip CHP2 has a receiving circuit RX1 formed on it. The semiconductor chips CHP1 and CHP2 are electrically connected by bonding wires W2. In other words, the receiving circuit RX1 and the transformer TR1 are electrically connected by bonding wires W2, but the transmitting circuit TX1 and the transformer TR1 are electrically connected by wiring provided within the semiconductor chip CHP1. In this way, a semiconductor device with a "two-chip configuration" is constructed.

[0041] However, in recent years, there has been research into optimizing the transformer manufacturing process independently of the circuit manufacturing process by forming the transformer on a separate chip from the chip on which the circuit is formed. This is because optimizing the transformer manufacturing process by placing the transformer on a chip independent of the circuit is thought to reduce the product cost of semiconductor devices, thereby enabling the provision of competitive products.

[0042] In other words, in order to manufacture competitive products, it is being considered to manufacture a semiconductor device with a so-called "three-chip configuration," in which one circuit is formed on a first semiconductor chip, the other circuit is formed on a second semiconductor chip, and a transformer is formed on a third semiconductor chip, and the semiconductor device is composed of these first, second, and third semiconductor chips. Figure 6 is a conceptual diagram showing a semiconductor device with a "three-chip configuration." In Figure 6, a transmitting circuit TX1 is formed on semiconductor chip CHP1, while a receiving circuit RX1 is formed on semiconductor chip CHP2. A transformer TR1 is formed on semiconductor chip CHP3. Semiconductor chips CHP1 and CHP3 are electrically connected by bonding wire W1, while semiconductor chips CHP2 and CHP3 are electrically connected by bonding wire W2. In this way, a semiconductor device with a "three-chip configuration" is constructed.

[0043] As described above, in a semiconductor device with a "3-chip configuration," semiconductor chip CHP1 and semiconductor chip CHP3 are electrically connected by bonding wire W1, and semiconductor chip CHP2 and semiconductor chip CHP3 are electrically connected by bonding wire W2. In other words, not only are the receiving circuit RX1 and transformer TR1 electrically connected by bonding wire W2, but the transmitting circuit TX1 and transformer TR1 are also electrically connected by bonding wire W1.

[0044] As a result, semiconductor devices with a "3-chip configuration" have more bonding wires than those with a "2-chip configuration," leading to an increase in the parasitic inductance of the bonding wires. In other words, the parasitic inductance added to the signal transmission path increases in semiconductor devices with a "3-chip configuration." Consequently, there are concerns that the increased parasitic inductance in semiconductor devices with a "3-chip configuration" will result in an increase in high-frequency noise, leading to a deterioration in signal transmission quality. Specifically, in semiconductor devices with a "3-chip configuration," the effect of parasitic inductance is greater than in semiconductor devices with a "2-chip configuration," resulting in a particularly pronounced deterioration in signal transmission quality caused by parasitic inductance.

[0045] Thus, while "3-chip configuration" semiconductor devices are attractive in that they have the potential to provide competitive products, improvements are needed from the perspective of enhancing the performance of the semiconductor device, such as improving signal transmission quality. In other words, in "3-chip configuration" semiconductor devices, it is desirable to improve the performance of the semiconductor device by suppressing the generation of high-frequency noise that occurs due to the increase in parasitic inductance.

[0046] Therefore, this embodiment incorporates measures to overcome the areas for improvement that become apparent in semiconductor devices with a "3-chip configuration." The technical concept behind this embodiment, which incorporates these measures, will be explained below.

[0047] <Basic Concept in the Embodiment> The basic concept in this embodiment is not to reduce parasitic inductance, which is a factor that generates high-frequency noise, but rather to utilize parasitic inductance, which is a factor that generates high-frequency noise, to reduce high-frequency noise. Specifically, the basic concept is to improve signal transmission quality by suppressing the transmission of high-frequency noise in semiconductor devices having transformers by configuring a low-pass filter using parasitic inductance. According to this basic concept, since high-frequency noise is attenuated by the low-pass filter, signal transmission quality can be improved.

[0048] Figure 7 is a circuit diagram showing the configuration of the low-pass filter LF.

[0049] In Figure 7, the low-pass filter LF consists of an inductor IL placed between the input terminal IN and the output terminal OUT, and a capacitance CP placed between the output terminal OUT and ground. In a low-pass filter LP configured in this way, even if high-frequency noise is superimposed on the signal input from the input terminal IN, this high-frequency noise flows to ground through the capacitance CP. As a result, the high-frequency noise contained in the signal output from the output terminal OUT is reduced. This is because, if the capacitance of the capacitance CP is C and the angular frequency is ω (=2πf: f is the frequency), then the impedance of the capacitance CP is 1 / ωC.

[0050] In other words, the impedance of the capacitance CP decreases as the frequency increases, meaning that signals and noise flow more easily through the capacitance CP as the frequency increases. Therefore, by passing through the low-pass filter LP, the high-frequency noise contained in the signal flows to ground via the capacitance CP, resulting in a reduction of high-frequency noise in the signal output from the low-pass filter LP. In this way, the signal transmission quality can be improved by inserting the low-pass filter LP into the signal transmission path.

[0051] Figure 8 is a conceptual diagram illustrating the application of the basic concept to a semiconductor device with a "three-chip configuration" that includes a transformer. In Figure 8, the bonding wire W1 that electrically connects the semiconductor chip CHP3 having the transformer TR1 and the semiconductor chip CHP1 having the transmitting circuit TX1 functions as the inductor of the low-pass filter LF shown in Figure 7. Meanwhile, a new capacitance CP is provided between the transformer TR1 formed on the semiconductor chip CHP3 and ground. This capacitance CP is the same capacitance CP shown in Figure 7. As a result, in Figure 8, a low-pass filter can be mounted on the semiconductor chip CHP3 on which the transformer TR1 is formed, thereby realizing the basic concept.

[0052] As a result, the basic concept is realized in Figure 8, and in the semiconductor device with the "3-chip configuration" shown in Figure 8, even if a bonding wire W1 having parasitic inductance that causes high-frequency noise is added, the high-frequency noise can be attenuated by the low-pass filter. This makes it possible to improve the signal transmission quality compared to the semiconductor device with the "3-chip configuration" shown in Figure 1.

[0053] The following describes the manifestations of the fundamental ideas.

[0054] <Method of Realization> <<Configuration of semiconductor device>> Figure 9 is a cross-sectional view showing a schematic configuration of a semiconductor device in an actualized form.

[0055] In Figure 9, the semiconductor device includes semiconductor chip CHP1, semiconductor chip CHP2, and semiconductor chip CHP3 on which a transformer is formed. Semiconductor chip CHP1 is mounted, for example, on a die pad DP1, which is a chip mounting area, via conductive adhesive PST1. On the other hand, semiconductor chip CHP2 is mounted, for example, on a die pad DP2, which is a chip mounting area, via conductive adhesive PST2. Semiconductor chip CHP3 is mounted on the die pad DP2 via conductive adhesive PST3.

[0056] Here, die pads DP1 and DP2 are each made of, for example, copper. Conductive adhesives PST1 and PST2 are each made of, for example, silver paste or solder.

[0057] The semiconductor chip CHP1 has a transmitting circuit TX1 and a receiving circuit RX2 formed on it, as shown in Figure 4. As shown in Figure 9, the semiconductor chip CHP1 has a semiconductor substrate SUB1 and a multilayer wiring layer MWL1 formed on the semiconductor substrate SUB1. Multiple transistors Q1 are formed on the semiconductor substrate SUB1, and the multilayer wiring layer MWL1 is formed above the semiconductor substrate SUB1 on which the multiple transistors Q1 are formed. Wiring is formed on each layer of the multilayer wiring layer MWL1, and this wiring is electrically connected to the transistors Q1. The transmitting circuit TX1 and the receiving circuit RX2 are formed by the electrically connected transistors Q1 and wiring. Multiple interlayer insulating films are stacked on the multilayer wiring layer MWL1, but they are shown as a single unit in Figure 9.

[0058] Next, the semiconductor chip CHP2 has a drive circuit DR, a receiver circuit RX1, and a transmit circuit TX2 formed on it, as shown in Figure 4. As shown in Figure 9, the semiconductor chip CHP2 has a semiconductor substrate SUB2 and a multilayer wiring layer MWL2 formed on the semiconductor substrate SUB2. Multiple transistors Q2 are formed on the semiconductor substrate SUB2, and the multilayer wiring layer MWL2 is formed above the semiconductor substrate SUB2 on which the multiple transistors Q2 are formed. Wiring is formed on each layer of the multilayer wiring layer MWL2, and the wiring is electrically connected to the transistors Q2. The drive circuit DR, the receiver circuit RX1, and the transmit circuit TX2 are formed by the electrically connected transistors Q2 and wiring. Multiple interlayer insulating films are stacked on the multilayer wiring layer MWL2, but they are shown as a single unit in Figure 9.

[0059] Next, as shown in Figure 9, the semiconductor chip CHP3 has a transformer formed thereon that performs contactless communication between different potentials. Specifically, the semiconductor chip CHP3 comprises, for example, a p-type (first conductivity type) semiconductor substrate SUB3, a p-type semiconductor region PR1 formed on the surface of the semiconductor substrate SUB3, and a transformer provided above the semiconductor substrate SUB. In this case, the p-type semiconductor region PR1 has a higher impurity concentration than the semiconductor substrate SUB3. The transformer also includes a lower inductor 300 and an upper inductor 100 positioned opposite the lower inductor 300. Thus, the lower inductor 300 and the upper inductor 100 are configured to be magnetically coupled. In the semiconductor chip CHP3, multiple interlayer insulating films are laminated on the semiconductor substrate SUB3, but they are shown as a single unit in Figure 9.

[0060] The upper inductor 100 is electrically connected to a circuit (second circuit) provided on the semiconductor chip CHP2 via a bonding wire W2. Also, as shown in Figure 9, the lower inductor 300 is electrically connected to a circuit (first circuit) provided on the semiconductor chip CHP1 via a bonding wire W1.

[0061] For example, in Figure 9, the upper inductor 100 is made up of a spiral inductor, and similarly, the lower inductor 300 is also made up of a spiral inductor.

[0062] The semiconductor device in the embodiment is configured as described above.

[0063] <<Planar layout configuration of semiconductor chips>> Next, we will explain the planar layout configuration of the semiconductor chip CHP3.

[0064] Figure 10 is a plan view showing the planar layout configuration of the semiconductor chip CHP3.

[0065] In Figure 10, the planar shape of the semiconductor chip CHP3 is rectangular, and a seal ring SR is provided on the periphery of the semiconductor chip CHP3. In a plan view, upper inductors 100 and 200 are provided so as to be surrounded by the seal ring SR. Here, upper inductor 100 has a tap pad 1a, a spiral wiring 1b connected to the tap pad 1a, and a transformer pad 1c connected to the spiral wiring 1b. Similarly, upper inductor 200 has a tap pad 2a, a spiral wiring 2b connected to the tap pad 2a, and a transformer pad 2c connected to the spiral wiring 2b.

[0066] Furthermore, in a plan view, tap pad 3a and trans pad 3c, and tap pad 4a and trans pad 4c are provided so as to be surrounded by the seal ring SR. The tap pad 3a and transform pad 3c are tap pads and transform pads of a lower inductor (not shown) formed below the upper inductor 100. That is, a lower inductor that is paired with the upper inductor 100 is formed below the upper inductor 100, and the tap pad 3a and transform pad 3c, which are drawn out from this lower inductor via wiring, are formed on the same layer as the upper inductor 100.

[0067] Similarly, the tap pad 4a and transform pad 4c are the tap pad and transform pad of a lower inductor (not shown) formed below the upper inductor 200. That is, a lower inductor that is paired with the upper inductor 200 is formed below the upper inductor 200, and the tap pad 4a and transform pad 4c, which are drawn out from this lower inductor via wiring, are formed on the same layer as the upper inductor 200.

[0068] Here, for example, a high-side reference potential of approximately 800V is applied to the upper inductor 100 and upper inductor 200. In contrast, a low-side reference potential of approximately 0V is applied to the lower inductor (tap pad 3a and transformer pad 3c) and lower inductor (tap pad 4a and transformer pad 4c). In other words, the lower inductor paired with the upper inductor 100 is applied with a reference potential different from the reference potential applied to the upper inductor 100. Similarly, the lower inductor paired with the upper inductor 200 is applied with a low-side reference potential different from the high-side reference potential applied to the upper inductor 200.

[0069] <<Cross-sectional structure of a semiconductor chip>> Next, we will describe the cross-sectional structure of the semiconductor chip CHP3.

[0070] Figure 11 is a cross-sectional view taken along line AA in Figure 10.

[0071] In Figure 11, the semiconductor chip CHP3 has a semiconductor substrate SUB3. The semiconductor substrate SUB3 is made of, for example, single-crystal silicon containing p-type impurities, and the impurity concentration of the semiconductor substrate SUB3 is, for example, 1 × 10⁻⁶ 15 / cm 3 Therefore, a p-type semiconductor region PR1 with a higher impurity concentration than the semiconductor substrate SUB3 is formed on the surface of the semiconductor substrate SUB3. The p-type semiconductor region PR1 is a region in the semiconductor substrate SUB3 in which p-type impurities have been introduced, and the impurity concentration of the p-type semiconductor region PR1 is, for example, 1 × 10⁻⁶. 20 / cm 3 This is the case. A wiring layer consisting of multiple layers is formed on this p-type semiconductor region PR1. Multiple interlayer insulating films, multiple wirings, multiple plugs, and a sealing ring SR are formed on the wiring layer consisting of multiple layers. In Figure 11, the illustration of the multiple interlayer insulating films is omitted. Furthermore, a lower layer inductor 300 having spiral wiring 3b is formed within the wiring layer consisting of multiple layers. This lower layer inductor 300 is formed, for example, over one or two layers and is electrically connected to the lead wiring section.

[0072] An interlayer insulating film is formed on the semiconductor substrate SUB3, and the lower layer inductor 300 and the lead-out wiring section are formed on the interlayer insulating film. In other words, the interlayer insulating film is located between the semiconductor substrate SUB3 and the lower layer inductor 300, between the semiconductor substrate SUB3 and the wiring 10a, and between the semiconductor substrate SUB3 and the lower layer pad 11a. Multiple interlayer insulating films and multiple wirings are laminated on the interlayer insulating film, the lower layer inductor 300, the wiring 10a, and the lower layer pad 11a. The lead-out wiring section has wiring 10a and wiring 10b, and wiring 10a and wiring 10b are connected, for example, by a plug. The lead-out wiring section also has a lower layer pad 11a connected to wiring 10a and a lower layer pad 11b connected to wiring 10b, and the lower layer pad 11a and lower layer pad 11b are connected, for example, by a plug. Furthermore, the lead-out wiring section is electrically connected to a multilayer structure 12 formed on the lower layer pad 11b and connected to the lower layer pad 11b, and to a transformer pad 3c, which is an upper layer pad connected to the multilayer structure 12.

[0073] The multilayer structure 12 is a structure consisting of multiple wires and multiple plugs that connect the lower pad 11b and the transformer pad 3c. The lower pad 11a is the portion of the wiring, including wire 10a, that overlaps with the multilayer structure 12. The lower pad 11b is the portion of the wiring, including wire 10b, that overlaps with the multilayer structure 12. Wires 10a and 10b are configured so as not to overlap with the multilayer structure 12.

[0074] In other words, the lower inductor 300 is electrically connected to the transformer pad 3c via a lead-out wiring section formed within a multi-layer wiring structure. Furthermore, an upper inductor 100 is formed on the multi-layer wiring structure. Specifically, the upper inductor 100 is formed so as to overlap with the lower inductor 300, and this upper inductor 100 has spiral wiring 1b and a transformer pad 1c. The upper part of the lower inductor 300, wiring 10b and lower pad 11b are formed in the same layer, and the lower part of the lower inductor 300, wiring 10a and lower pad 11a are formed in the same layer.

[0075] A surface protective film PAS and a polyimide resin film PI are formed to cover the upper inductor 100, the transpad 1c, and the transpad 3c. The surface protective film PAS and the polyimide resin film PI are provided with openings that expose a portion of the surface of the transpad 3c and a portion of the surface of the transpad 1c. The surface protective film PAS is composed of a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film.

[0076] For example, the bonding wire W1 is electrically connected to the transpad 3c (upper pad) exposed from the opening (see Figure 9). In other words, the transpad 3c, which is the upper pad, is configured to be connectable to the bonding wire W1.

[0077] In Figure 11, the wiring 10a is positioned opposite the p-type semiconductor region PR1, and capacitance CP is formed by the opposing p-type semiconductor region PR1 and wiring 10a. In other words, the p-type semiconductor region PR1 is configured to include a region that overlaps planarly with the wiring 10a, and capacitance CP is formed by the planar overlapping regions of the p-type semiconductor region PR1 and the wiring 10a. A low-pass filter is then formed by this capacitance CP and the inductance of the bonding wire W1 connected to the transpad 3c.

[0078] Next, Figure 12 is a plan view showing a lower-layer inductor 300, a wiring 10a connected to the lower-layer inductor 300, and a lower-layer pad 11a connected to the wiring 10a. As shown in Figure 12, the lower-layer inductor 300 is composed of spiral-shaped inductor wiring, and this lower-layer inductor 300 is connected to the wiring 10a. The wiring 10a is then connected to the lower-layer pad 11a. Here, the width of the wiring 10a (width in the Y direction) is greater than the width L of the inductor wiring. The width L of the inductor wiring is the length of the inductor wiring in a direction perpendicular to the direction in which the inductor wiring extends. Figure 12 shows an example of the width L of a part of the inductor wiring that extends in the direction in which the inductor wiring extends shown in Figure 12. For example, if another part of the inductor wiring extends in the direction perpendicular to which the inductor wiring extends shown in Figure 12, the width L of the other part of the inductor wiring is the length of the inductor wiring in the direction in which the inductor wiring extends shown in Figure 12. For example, the width L of the inductor wiring is about 7 μm, while the width of the wiring 10a is about 70 μm.

[0079] The semiconductor chip CHP3 is constructed in the manner described above.

[0080] <<Characteristics of the Embodiment>> Next, we will explain the characteristic features of the embodiment.

[0081] The first characteristic feature of the embodiment is that, for example, as shown in Figure 11, the p-type semiconductor region PR1 is formed on the surface of the semiconductor substrate SUB3 such that the p-type semiconductor region PR1 and the wiring 10a have opposing regions. In other words, the characteristic feature of the embodiment is that the p-type semiconductor region PR1 is formed on the surface of the semiconductor substrate SUB3 such that the p-type semiconductor region PR1 and the wiring 10a have overlapping regions.

[0082] As a result, according to the first feature point of the embodiment, a capacitance CP is formed by the opposing p-type semiconductor regions PR1 and wiring 10a. In other words, the p-type semiconductor region PR1 is configured to include a region that overlaps planarly with the wiring 10a, and a capacitance CP is formed by the planar overlapping regions of the p-type semiconductor region PR1 and the wiring 10a. A low-pass filter is then formed by this capacitance CP and the inductance of the bonding wire W1 connected to the transpad 3c. As a result, according to the first feature point, in a semiconductor device with a "3-chip configuration," even if a bonding wire W1 having parasitic inductance that causes high-frequency noise is added, the low-pass filter can attenuate the high-frequency noise. As a result, according to the first feature point of the embodiment, the signal transmission quality can be improved in a semiconductor device with a "3-chip configuration."

[0083] Next, a second characteristic feature of the embodiment is that, for example, as shown in Figure 12, the width of the wiring 10a (width in the Y direction) is made larger than the width L of the inductor wiring of the lower layer inductor 300. This makes it possible to increase the opposing area between the wiring 10a and the p-type semiconductor region PR1 located below the wiring 10a. This means that the capacitance value of the capacitance CP formed by the opposing p-type semiconductor region PR1 and the wiring 10a can be increased. As a result, according to the second characteristic feature of the embodiment, the capacitance value of the capacitance CP required for the low-pass filter can be easily secured. Furthermore, by adjusting the width of the wiring 10a, the cutoff frequency of the low-pass filter can be adjusted. For example, as shown in Figure 13, the width of the wiring 10a (width in the Y direction) may be larger than the width of the lower layer pad 11a (width in the Y direction). Also, as shown in Figure 14, the wiring 10a may be composed of a combination of a portion with a first width L1 in the Y direction and a portion with a second width L2 in the Y direction that is smaller than the first width L1. In other words, as shown in Figure 14, the wiring 10a may be configured to have portions with different widths in the Y direction.

[0084] <<Variation>> For example, the p-type semiconductor region PR1 may not only have a region that overlaps planarly with the wiring 10a, but may also be formed to overlap planarly with the spiral wiring of the lower inductor 300. Furthermore, the p-type semiconductor region PR1 may be formed over the entire surface of the semiconductor substrate SUB3, for example, as shown in Figure 15. In this case, the patterning process for forming the p-type semiconductor region PR1 becomes unnecessary. Thus, the configuration in which the p-type semiconductor region PR1 is formed over the entire surface of the semiconductor substrate SUB3 is useful in that it can improve the signal transmission quality of the semiconductor device while simplifying the manufacturing process of the semiconductor device.

[0085] Although the present invention has been specifically described above based on its embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0086] 1a Tap Pad 1b Spiral wiring 1c Transpad 2a Tap Pad 2b Spiral wiring 2c Transpad 3a Tap Pad 3b Spiral wiring 3c Transpad 4a Tap Pad 4c Transpad 10a wiring 10b Wiring 11a Lower pad 11b Lower pad 12 Multilayer structure 100 Upper layer inductor 200 Upper layer inductor 300 Lower layer inductor CC control circuit CHP1 semiconductor chip CHP2 semiconductor chip CHP3 semiconductor chip CL1a coil CL1b coil CL2a coil CL2 and Coil CP capacity DP1 die pad DP2 die pad DR drive circuit GND1 Ground potential GND2 Ground potential IL Inductor INV Inverter LOD load circuit LP Low-Pass Filter MWL1 Multilayer wiring layer MWL2 multilayer wiring layer PAS surface protection film PI polyimide resin film PR1 p-type semiconductor region PST1 Conductive adhesive PST2 conductive adhesive PST3 conductive adhesive Q1 Transistor Q2 Transistor RX1 Receiver Circuit RX2 receiving circuit SG1 signal SG2 signal SG3 signal SG4 signal SR Seal Ring SUB1 Semiconductor substrate SUB2 Semiconductor Substrate SUB3 Semiconductor Substrate TR1 Transformer TR2 Transformers TX1 Transmitter Circuit TX2 Transmitter Circuit VCC1 power supply potential VCC2 power supply potential W1 bonding wire W2 bonding wire

Claims

1. A semiconductor device having a transformer that performs contactless communication between different potentials, A first-type conductive semiconductor substrate and A first semiconductor region of the first conductivity type formed on the surface of the semiconductor substrate, The transformer provided above the semiconductor substrate, Equipped with, The aforementioned transformer is Lower inductor and The lower inductor and the lead wiring section electrically connected thereto, The upper inductor is magnetically coupled to the lower inductor, Includes, The lead-out wiring portion is a semiconductor device having a first wiring facing the first semiconductor region.

2. In the semiconductor device described in claim 1, The first semiconductor region is a semiconductor device having a higher impurity concentration than the semiconductor substrate.

3. In the semiconductor device described in claim 1, The lower inductor is composed of spiral-shaped inductor wiring. A semiconductor device in which the width of the first wiring is greater than the width of the inductor wiring.

4. In the semiconductor device described in claim 1, The aforementioned wiring section is, The first wiring connected to the lower inductor, The lower pad connected to the first wiring, A multilayer structure connected to the aforementioned lower pad, The upper pad connected to the aforementioned multilayer structure, It has, The aforementioned lower pad is wiring that overlaps with the multilayer structure, The first wiring is configured so as not to overlap with the multilayer structure. The aforementioned upper pad is configured to be connectable to bonding wires, in a semiconductor device.

5. In the semiconductor device according to claim 4, The lower layer inductor, the first wiring, and the lower layer pad are formed in the same layer. The multilayer structure is a semiconductor device formed on the lower layer pad.

6. In the semiconductor device according to claim 4, A capacitance is formed by the first semiconductor region and the first wiring that are facing each other. A semiconductor device in which a low-pass filter can be configured by the inductance of the bonding wire and the capacitance of the bonding wire.

7. In the semiconductor device according to claim 4, The semiconductor substrate further comprises an interlayer insulating film formed on the semiconductor substrate, A semiconductor device wherein the interlayer insulating film is disposed between the semiconductor substrate and the lower layer inductor, between the semiconductor substrate and the first wiring, and between the semiconductor substrate and the lower layer pad.

8. In the semiconductor device according to claim 4, The upper layer pad and the upper layer inductor further have a surface protective film formed to cover them, The surface protective film has an opening that exposes a portion of the surface of the upper pad, and is a semiconductor device.

9. In the semiconductor device described in claim 1, The semiconductor device comprises a first semiconductor region which includes a region that overlaps planarly with the first wiring.

10. In the semiconductor device described in claim 1, The semiconductor device comprises a first semiconductor region which includes a region that overlaps planarly with the lower inductor.

11. In the semiconductor device described in claim 1, The first semiconductor region is formed on the entire surface of the semiconductor substrate, and is a semiconductor device.

12. In the semiconductor device according to claim 4, A first chip having a first circuit formed on it that is configured to apply a first potential, A second chip having a second circuit formed on it that is configured to apply a second potential, The third chip on which the transformer is formed, A semiconductor device further having [the following].

13. A first chip having a first circuit formed on it that is configured to apply a first potential, A second chip having a second circuit formed on it that is configured to apply a second potential, A third chip has a transformer formed on it that performs contactless communication between different potentials, A first bonding wire electrically connects the first chip and the third chip, A second bonding wire electrically connects the second chip and the third chip, It has, The third chip is, A first-type conductive semiconductor substrate and A first semiconductor region of the first conductivity type formed on the surface of the semiconductor substrate, The transformer provided above the semiconductor substrate, It has, The aforementioned transformer is Lower inductor and The lower inductor and the lead wiring section electrically connected thereto, The upper inductor is magnetically coupled to the lower inductor, Includes, The lead-out wiring portion includes a first wiring facing the first semiconductor region, and is a semiconductor device.

14. In the semiconductor device according to claim 13, The first bonding wire is configured to electrically connect the first circuit and the lower layer inductor. A capacitance is formed by the first semiconductor region and the first wiring that are facing each other. A semiconductor device in which a low-pass filter is configured by the inductance of the first bonding wire and the capacitance.

15. In the semiconductor device according to claim 13, The first semiconductor region is a semiconductor device having a higher impurity concentration than the semiconductor substrate.

16. In the semiconductor device according to claim 13, The aforementioned wiring section is, The first wiring connected to the lower inductor, The lower pad connected to the first wiring, A multilayer structure connected to the aforementioned lower pad, The upper pad connected to the aforementioned multilayer structure, It has, The aforementioned lower pad is wiring that overlaps with the multilayer structure, The first wiring is configured so as not to overlap with the multilayer structure. The aforementioned upper pad is configured to be connectable to bonding wires, in a semiconductor device.

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