Inverter pulse insulation test device

Abstract

The present invention provides an inverter pulse insulation test device comprising a pulse generation circuit and a surge voltage generation circuit. The pulse generation circuit outputs a voltage having a simulated drive voltage waveform that includes intermittent pulses. The surge voltage generation circuit generates a surge voltage at each of a rise and a fall of each pulse of the drive voltage waveform to change the drive voltage waveform and outputs a voltage having the changed drive voltage waveform. The surge voltage generation circuit has: a variable resistor and a variable inductor connected in series to each other; and a variable capacitor.

Description

Technical Field

[0004] , ,

[0001] The present disclosure relates to an inverter pulse insulation test device.

Background Art

[0002] Patent Document 1 discloses an insulation inspection device and an insulation inspection method for an inverter-driven motor. Patent Document 2 discloses a rotating electric machine driven by an inverter (particularly, an inverter-driven rotating electric machine with a rated voltage of 700 Vrms or less), a method for inspecting partial discharge of the phase insulation of the rotating electric machine, and a device for inspecting partial discharge of the phase insulation. Patent Document 3 discloses a method capable of realizing a discharge resistance test for the windings of a multi-channel variable frequency motor. Patent Document 4 discloses a method for a discharge resistance test for the windings of an inverter-driven motor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0005] In the control of inverter-driven motors, pulse control methods such as PWM (Pulse Width Modulation) control are widely employed. In pulse control methods, voltage pulses are generated by high-speed switching of power devices. However, surge voltages are generated at the rising and falling edges of the voltage pulses due to the inductance of the wiring from the power device to the motor. If the surge voltage becomes excessive, partial discharge occurs in the motor windings, and the insulation performance of the resin covering the windings deteriorates. Increasing the thickness of the insulation coating on the windings to suppress partial discharge leads to a larger motor. Furthermore, the higher the carrier frequency of pulse control, the more frequently partial discharges occur, and the faster the deterioration of insulation performance progresses. Therefore, it is desirable to accurately test and evaluate the degree of deterioration of insulating materials such as the insulation coating of the windings due to the surge voltage contained in the voltage pulses.

[0006] The purpose of this disclosure is to provide an inverter pulse insulation test apparatus that can accurately test and evaluate the degree of deterioration of insulating materials due to surge voltages contained in voltage pulses. [Means for solving the problem]

[0007] One aspect of this disclosure is an inverter pulse isolation test apparatus. The inverter pulse isolation test apparatus comprises a pulse generation circuit and a surge voltage generation circuit. The pulse generation circuit has a first output terminal and outputs a voltage having a simulated drive voltage waveform including intermittent pulses from the first output terminal. The surge voltage generation circuit has an input terminal electrically connected to the first output terminal of the pulse generation circuit and a second output terminal connected to the motor under test. The surge voltage generation circuit generates a surge voltage at the rising and falling edges of each pulse of the drive voltage waveform input from the input terminal to change the drive voltage waveform and outputs a voltage having the changed drive voltage waveform from the second output terminal. The surge voltage generation circuit comprises a variable resistor and a variable inductor connected in series with each other, and a variable capacitance capacitor. One end of the series circuit of the variable resistor and variable inductor constitutes the input terminal of the surge voltage generation circuit. The other end of the series circuit is connected to the second output terminal of the surge voltage generation circuit. One end of the variable capacitance capacitor is connected to the node between the other end of the series circuit and the second output terminal. The other end of the variable capacitance capacitor is connected to a constant potential line.

[0008] The above-described device allows for accurate testing and evaluation of the degree of deterioration of insulating materials caused by surge voltages contained in voltage pulses.

[0009] In the above apparatus, the pulse generation circuit may output a voltage having a two-level or three-level inverter drive waveform as the drive voltage waveform. The pulse generation circuit may include a first semiconductor switch, a second semiconductor switch, a bridge full-wave rectifier, and a third semiconductor switch. One end of the first semiconductor switch is connected to a positive voltage terminal, and the other end of the first semiconductor switch is connected to a first output terminal. One end of the second semiconductor switch is connected to a negative voltage terminal, and the other end of the second semiconductor switch is connected to a first output terminal. The bridge full-wave rectifier has two input terminals and two output terminals, with one of the two input terminals connected to a reference potential line, and one of the two output terminals connected to a first output terminal. One end of the third semiconductor switch is connected to the other input terminal of the bridge full-wave rectifier, and the other end of the third semiconductor switch is connected to the other output terminal of the bridge full-wave rectifier.

[0010] In the above-described apparatus, the pulse generation circuit may include a plurality of semiconductor switches for forming a drive voltage waveform, and a first control unit that generates a plurality of optical trigger signals to control each of the plurality of semiconductor switches. The first control unit may then provide each of the plurality of optical trigger signals to each of the plurality of semiconductor switches.

[0011] The above-described device may further include a second control unit and an input operation unit. The second control unit controls the drive voltage waveform in the pulse generation circuit. The input operation unit receives an input operation regarding the number of intermittent pulses and provides the second control unit with information regarding the number of intermittent pulses input by the input operation. The second control unit may then determine the number of intermittent pulses according to the information.

[0012] The above-described apparatus may further include a second control unit and an input operation unit. The second control unit controls the drive voltage waveform in the pulse generation circuit. The input operation unit receives input operations related to the drive voltage waveform and provides the second control unit with information regarding the drive voltage waveform input by the input operations. The second control unit may determine the drive voltage waveform according to the information. The information regarding the drive voltage waveform may include at least one of the following: information regarding whether the intermittent pulse consists only of positive-polarity pulses, only of negative-polarity pulses, or includes both positive-polarity and negative-polarity pulses; information regarding whether the intermittent pulse is output continuously until the end of the test or output in bursts within a preset period; information regarding the amplitude of the intermittent pulse; information regarding the frequency of the intermittent pulse; and information regarding the time width of each pulse constituting the intermittent pulse. [Effects of the Invention]

[0013] According to this disclosure, it is possible to provide an inverter pulse insulation test apparatus that can accurately test and evaluate the degree of deterioration of the winding insulation coating due to surge voltage contained in the voltage pulse. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 is a schematic diagram showing the configuration of an inverter pulse isolation test apparatus according to one embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of a pulse generation circuit configuration. [Figure 3] Figure 3 is a circuit diagram showing an example configuration of a surge voltage generation circuit. [Figure 4] Figure 4 is a circuit diagram showing another example configuration of a surge voltage generation circuit. [Figure 5] Figure 5 is a circuit diagram showing yet another example configuration of a surge voltage generation circuit. [Figure 6] Sections (a), (b), and (c) of Figure 6 schematically show positive voltage pulses containing surge voltage output from a surge voltage generation circuit. [Figure 7] FIG. 7 is a diagram schematically showing an example of a bipolar drive voltage waveform including a surge voltage. [Figure 8] FIG. 8 is a diagram schematically showing an example of a drive voltage waveform including a surge voltage. [Figure 9] FIG. 9 is a diagram schematically showing an example of a drive voltage waveform including a surge voltage. [Figure 10] FIG. 10 is a diagram schematically showing an example of a drive voltage waveform including a surge voltage. [Figure 11] FIG. 11 is a diagram schematically showing an example of a drive voltage waveform including a surge voltage. [Figure 12] FIG. 12 is a diagram schematically showing an example of a drive voltage waveform not including a surge voltage. [Figure 13] FIG. 1 is a diagram schematically showing an example of a drive voltage waveform not including a surge voltage. [Figure 14] FIG. 14 is a diagram schematically showing an example of a drive voltage waveform including a surge voltage. [Figure 15] Parts (a) to (e) of FIG. 15 are diagrams showing drive voltage waveforms including a surge voltage measured by a test apparatus. [Figure 16] Parts (a) to (e) of FIG. 16 are diagrams showing drive voltage waveforms measured by a test apparatus. [Figure 17] FIG. 17 is a block diagram showing an example of a system configuration of a test apparatus according to an embodiment. [Figure 18] FIG. 18 is a diagram showing an example of a two-level PWM drive waveform. [Figure 19] FIG. 19 is a diagram showing an example of a three-level PWM drive waveform. [Figure 20] Part (a) of FIG. 20 schematically shows a rectangular wave before a surge voltage occurs. Part (b) of FIG. 20 schematically shows a rectangular wave after a surge voltage occurs.

MODE FOR CARRYING OUT THE INVENTION

[0015] Specific examples of the inverter pulse isolation test apparatus of this disclosure will be described below with reference to the drawings. However, the present invention is not limited to these examples, and is intended to include all modifications within the meaning and scope of the claims, as defined by the claims. In the following description, the same elements in the drawings are denoted by the same reference numerals, and redundant descriptions are omitted.

[0016] Figure 1 is a schematic diagram showing the configuration of an inverter pulse insulation test apparatus (hereinafter simply referred to as the test apparatus) 1 according to one embodiment. The test apparatus 1 is used, for example, to perform insulation evaluation of an inverter drive motor and the windings, insulating coating resin, and insulating components used therein. Alternatively, the test apparatus 1 is used for insulation evaluation of magnet wires, insulation evaluation of surface insulating coatings such as magnet wires, insulation evaluation of electrical components, and their life evaluation and Vt testing. As shown in Figure 1, the test apparatus 1 of this embodiment includes a pulse generation circuit 10 and a surge voltage generation circuit 20.

[0017] The pulse generation circuit 10 has an output terminal 10b (first output terminal) and outputs a voltage from the output terminal 10b that has a simulated drive voltage waveform including intermittent voltage pulses. The drive voltage waveform includes, for example, a 1-level, 2-level, or 3-level inverter drive waveform to simulate PWM (Pulse Width Modulation) control.

[0018] Figure 2 is a circuit diagram showing an example configuration of the pulse generation circuit 10. The pulse generation circuit 10 shown in Figure 2 includes a positive polarity DC power supply V1, a negative polarity DC power supply V2, resistors Rp1 and Rp2, capacitors C1 and C2, and discharge resistors Rd1 and Rd2. Furthermore, the pulse generation circuit 10 includes a plurality of semiconductor switches HVS1, HVS2 and HVS3 (three in the illustrated example) for forming the drive voltage waveform, and a bridge full-wave rectifier BR1.

[0019] The positive DC power supply V1 and the negative DC power supply V2 constitute the power supply section of the pulse generation circuit 10. The positive DC power supply V1 and the negative DC power supply V2 are connected in series with each other. Node N3 between the positive DC power supply V1 and the negative DC power supply V2 is connected to the reference potential line GND and is defined as the reference potential (0V). The end of the positive DC power supply V1 opposite to the reference potential is a positive high-voltage terminal 11 (+HV). The end of the negative DC power supply V2 opposite to the reference potential is a negative high-voltage terminal 12 (-HV). In one example, the absolute value of the potential of the positive high-voltage terminal 11 is equal to the absolute value of the potential of the negative high-voltage terminal 12.

[0020] Capacitors C1 and C2 constitute the energy storage section of the pulse generation circuit 10. Capacitors C1 and C2 are connected in series with each other. The node between capacitors C1 and C2 is connected to the reference potential line GND and is defined as the reference potential (0V). The end of capacitor C1 opposite to the reference potential is connected to node N1. Node N1 is connected to the positive high-voltage terminal 11 via resistor Rp1. The end of capacitor C2 opposite to the reference potential is connected to node N2. Node N2 is connected to the negative high-voltage terminal 12 via resistor Rp2. Capacitor C1 stores positive polarity energy. Capacitor C2 stores negative polarity energy. The inductive components of capacitors C1 and C2 should be as small as possible.

[0021] Discharge resistors Rd1 and Rd2 are connected in series with each other. The node between discharge resistors Rd1 and Rd2 is connected to the reference potential line GND and is defined as the reference potential (0V). The end of discharge resistor Rd1 opposite to the reference potential is connected to node N1. The end of discharge resistor Rd2 opposite to the reference potential is connected to node N2. In other words, discharge resistor Rd1 is connected in parallel with capacitor C1, and discharge resistor Rd2 is connected in parallel with capacitor C2.

[0022] The semiconductor switches HVS1, HVS2, and HVS3 constitute the semiconductor switch section of the pulse generation circuit 10. The semiconductor switches HVS1, HVS2, and HVS3 are field-effect transistors (FETs) made of, for example, SiC semiconductors. The semiconductor switch HVS1 is the first semiconductor switch in this embodiment. One end of the semiconductor switch HVS1 is connected to node N1 and also to the positive high-voltage terminal 11 via resistor Rp1. Resistor Rp1 is a charge protection resistor. The other end of the semiconductor switch HVS1 is connected to the output terminal 10b via resistor Rs1, which is a non-inductive protection resistor. Resistor Rs1 protects the semiconductor switch HVS1 so that its output current does not exceed its maximum rated current. The semiconductor switch HVS1 outputs a positive polarity voltage pulse.

[0023] The semiconductor switch HVS2 is the second semiconductor switch in this embodiment. One end of the semiconductor switch HVS2 is connected to the negative high-voltage terminal 12 via a resistor Rp2. Resistor Rp2 is a charge protection resistor. The other end of the semiconductor switch HVS2 is connected to the output terminal 10b via a non-inductive protection resistor Rs2. Resistor Rs2 protects the semiconductor switch HVS2 so that its output current does not exceed its maximum rated current. The semiconductor switch HVS2 outputs a negative polarity voltage pulse. The semiconductor switch HVS2 is controlled so as not to conduct simultaneously with the semiconductor switch HVS1.

[0024] The bridge full-wave rectifier BR1 has two input terminals and two output terminals. One of the two input terminals of the bridge full-wave rectifier BR1 is connected to the reference potential line GND and to node N3 between the positive DC power supply V1 and the negative DC power supply V2. One of the two output terminals of the bridge full-wave rectifier BR1 is connected to output terminal 10b via a non-inductive protection resistor Rs3. The resistor Rs3 protects the semiconductor switch HVS3 so that its output current does not exceed its maximum rated current.

[0025] Resistors Rs1, Rs2, and Rs3 constitute the protection section of the pulse generation circuit 10. Because resistors Rs1, Rs2, and Rs3 are non-inductive resistors, overshoot voltages occurring in the voltage pulse can be suppressed when outputting a drive voltage waveform that does not contain surge voltage (see Figures 12 and 13).

[0026] The semiconductor switch HVS3 is the third semiconductor switch in this embodiment. One end of the semiconductor switch HVS3 is connected to the other input terminal of the bridge full-wave rectifier BR1. The other end of the semiconductor switch HVS3 is connected to the other output terminal of the bridge full-wave rectifier BR1. The semiconductor switch HVS3 accelerates the fall time of the positive and negative voltage pulses, allowing these voltage pulses to quickly return to the reference potential.

[0027] Refer to Figure 1 again. The surge voltage generation circuit 20 has an input terminal 20a electrically connected to the output terminal 10b of the pulse generation circuit 10, and an output terminal 20b (second output terminal) connected to the output terminal 13 of the test apparatus 1. The surge voltage generation circuit 20 is a waveform adjustment unit that causes the drive voltage waveform, which is a rectangular wave input from the input terminal 20a, to resonate and vibrate using an RLC circuit. As a result, the surge voltage generation circuit 20 generates surge voltages at the rising and falling edges of each voltage pulse of the drive voltage waveform, thereby changing the drive voltage waveform, and outputs a voltage with the changed drive voltage waveform from the output terminal 20b. In addition, the surge voltage generation circuit 20 allows the resonance conditions to be freely changed by making the resistance, inductance, and capacitance values ​​of the RLC circuit variable.

[0028] A current sensor 41 is provided in the wiring between the output terminal 20b of the surge voltage generation circuit 20 and the output terminal 13 of the test device 1. The current sensor 41 measures the magnitude of the current output from the output terminal 20b. The current sensor 41 can be, for example, a current transformer type, a Hall element type, or a resistive type. A high-voltage probe 42 for measuring the voltage waveform is connected to the node between the output terminal 20b of the surge voltage generation circuit 20 and the output terminal 13 of the test device 1. In order to accurately adjust the drive voltage waveform including the surge voltage, it is desirable that the high-voltage probe 42 be highly accurate and fast. As the high-voltage probe 42, for example, a high-voltage probe of model number EP-50K (voltage division ratio 1 / 2000) manufactured by Nissin Pulse Electronics Co., Ltd. can be used. Alternatively, for example, a high-voltage probe of model number EP-100K (voltage division ratio 1 / 5000) manufactured by Nissin Pulse Electronics Co., Ltd. can be used. The current sensor 41 and the high-voltage probe 42 constitute the measurement unit of the test device 1. The output signals from the current sensor 41 and the high-voltage probe 42 are provided to the oscilloscope 43 and displayed in real time.

[0029] The object under test M is connected between the output terminal 13 of the test apparatus 1 and the reference potential line GND. In Figure 1, the object under test M is schematically represented by a capacitance symbol. The object under test M is, for example, the coating resin on the windings of a motor.

[0030] Figure 3 is a circuit diagram showing a surge voltage generation circuit 20A as an example of the configuration of the surge voltage generation circuit 20. The surge voltage generation circuit 20A shown in Figure 3 has a series circuit 21A and a variable capacitance capacitor section 22A. The series circuit 21A includes a variable resistor section 23A and a variable inductor section 24A connected in series with each other. One end of the series circuit 21A constitutes the input terminal 20a of the surge voltage generation circuit 20A. The other end of the series circuit 21A is connected to the output terminal 20b of the surge voltage generation circuit 20A. In the series circuit 21A, the order of the variable resistor section 23A and the variable inductor section 24A does not matter. That is, the variable inductor section 24A may be connected between the variable resistor section 23A and the input terminal 20a, or the variable resistor section 23A may be connected between the variable inductor section 24A and the input terminal 20a. One end of the variable capacitance capacitor section 22A is connected to node N4 between the other end of the series circuit 21A and the output terminal 20b. The other end of the variable capacitance capacitor section 22A is connected to a constant potential line (for example, a reference potential line GND).

[0031] In one example, the resistance value of the variable resistor 23A is controlled by the motor M1. Specifically, the motor M1 moves the slider 23b that contacts the resistor 23a of the variable resistor 23A, thereby controlling the contact position of the slider 23b with respect to the resistor 23a. The contact position of the slider 23b is detected by a sensor. The relationship between the contact position of the slider 23b and the resistance value of the variable resistor 23A is predetermined, and based on this relationship and the detection result from the sensor, the contact position of the slider 23b is controlled to achieve the desired resistance value. The motor M1 is controlled by a computer 52 (see Figure 17), which will be described later. Alternatively, the resistance value of the variable resistor 23A may be adjusted manually.

[0032] Similarly, the inductance of the variable inductor section 24A is controlled by the motor M2. Specifically, the motor M2 moves the slider 24b that contacts the inductor 24a of the variable inductor section 24A, thereby controlling the contact position of the slider 24b with respect to the inductor 24a. The contact position of the slider 24b is detected by a sensor. The relationship between the contact position of the slider 24b and the inductance of the variable inductor section 24A is predetermined, and based on this relationship and the detection result from the sensor, the contact position of the slider 24b is controlled to achieve the desired inductance. The motor M2 is controlled by a computer 52 (see Figure 17), which will be described later. Alternatively, the inductance of the variable inductor section 24A may be adjusted manually.

[0033] The variable capacitance capacitor section 22A functions as a parallel resonant capacitor. The capacitance value of the variable capacitance capacitor section 22A is controlled by the motor M3. The capacitance value of the variable capacitance capacitor section 22A is detected by a sensor, and the capacitance value of the variable capacitance capacitor section 22A is controlled to reach a desired value. The capacitance value of the variable capacitance capacitor section 22A is controlled by the computer 52 (see Figure 17), which will be described later. Alternatively, the capacitance value of the variable capacitance capacitor section 22A may be adjusted manually.

[0034] The configuration of the variable inductor section 24A is not limited to the contact movement method using the slider 24b as described above. For example, the variable inductor section 24A may have other configurations, such as inserting a movable magnetic or diamagnetic material into an air-core coil. In the configuration in which a movable magnetic or diamagnetic material is inserted into an air-core coil, the inductance changes depending on the insertion depth of the magnetic or diamagnetic material into the air-core coil.

[0035] The minimum resistance value of the variable resistor section 23A is 0Ω, and the maximum resistance value of the variable resistor section 23A is, for example, in the range of 400Ω to 1kΩ. The resistance value of the variable resistor section 23A can be adjusted steplessly within this range. The minimum inductance of the variable inductor section 24A is 0H, and the maximum inductance of the variable inductor section 24A is, for example, in the range of 200μH to 500μH. The resistance value of the variable inductor section 24A can be adjusted steplessly within this range. The maximum capacitance value of the variable capacitance capacitor section 22A is, for example, in the range of 1nF to 10nF. The variable capacitance capacitor section 22A may be omitted (in other words, its capacitance may be 0) if the capacitance of the test object M is large.

[0036] The surge voltage generation circuit 20A allows for continuous variation of resistance, inductance, and capacitance values, enabling fine adjustment of the drive voltage waveform. In addition, the surge voltage generation circuit 20A enables automatic control of resistance, inductance, and capacitance values.

[0037] Figure 4 is a circuit diagram showing surge voltage generation circuit 20B as another example of the configuration of surge voltage generation circuit 20. The surge voltage generation circuit 20B shown in Figure 4 has a series circuit 21B and a variable capacitance capacitor section 22B. The series circuit 21B includes a variable resistor section 23B and a variable inductor section 24B connected in series with each other. One end of the series circuit 21B constitutes the input terminal 20a of the surge voltage generation circuit 20B. The other end of the series circuit 21B is connected to the output terminal 20b of the surge voltage generation circuit 20B. In the series circuit 21B, the order of the variable resistor section 23B and the variable inductor section 24B does not matter. That is, the variable inductor section 24B may be connected between the variable resistor section 23B and the input terminal 20a, or the variable resistor section 23B may be connected between the variable inductor section 24B and the input terminal 20a. One end of the variable capacitance capacitor section 22B is connected to the node between the other end of the series circuit 21B and the output terminal 20b. The other end of the variable capacitance capacitor section 22B is connected to a constant potential line (for example, a reference potential line GND).

[0038] The variable resistor section 23B includes N non-inductive fixed resistors R(1) to R(N) connected in series with each other, and N switches YR(1) to YR(N) connected in parallel to each of the N resistors R(1) to R(N). N is an integer greater than or equal to 2. When the nth switch YR(n) (n is an integer between 1 and N) becomes conductive, the corresponding resistor R(n) is bypassed. The resistance value of the variable resistor section 23B is determined according to the combination of switches YR(1) to YR(N) that become conductive. Switches YR(1) to YR(N) are, for example, electromagnetic relays.

[0039] The variable inductor section 24B includes M inductors L(1) to L(M) and (M+1) switches YL(0) to YL(M), where M is an integer greater than or equal to 2. The inductances of inductors L(1) to L(M) are fixed. One end of switch YL(0) is connected to the variable resistor section 23B. The other end of switch YL(0) is connected to the output terminal 20b. Each of the inductors L(1) to L(M) is connected in series with each of the switches YL(1) to YL(M). The M series circuits, each containing each inductor L and each switch YL, are connected in parallel to each other between the variable resistor section 23B and the output terminal 20b. In the illustrated example, each inductor L(1) to L(M) is connected between each switch YL(1) to YL(M) and the variable resistor 23B, but each switch YL(1) to YL(M) may also be connected between each inductor L(1) to L(M) and the variable resistor 23B. When the m-th switch YL(m) (where m is an integer between 1 and M) becomes conductive, the corresponding inductor L(m) becomes active. The inductance of the variable inductor 24B is determined according to the combination of switches YL(1) to YL(M) that become conductive. When the 0th switch YL(0) becomes conductive, the inductance of the variable inductor 24B can be set to 0. Switches YL(0) to YL(M) are, for example, electromagnetic relays.

[0040] The variable capacitance capacitor section 22B functions as a parallel resonant capacitor. The variable capacitance capacitor section 22B includes Q capacitors Cd(1) to Cd(Q) and Q switches YC(1) to YC(Q), where Q is an integer greater than or equal to 2. The capacitance values ​​of capacitors Cd(1) to Cd(Q) are fixed. Each capacitor Cd(1) to Cd(Q) is connected in series with each switch YC(1) to YC(Q). The Q series circuits, each containing a capacitor Cd and each switch YC, are connected in parallel with each other at the node between the variable inductor section 24B and the output terminal 20b, and between the reference potential line GND. In the illustrated example, each capacitor Cd(1) to Cd(Q) is connected between each switch YC(1) to YC(Q) and the reference potential line GND, but each switch YC(1) to YC(Q) may be connected between each capacitor Cd(1) to Cd(Q) and the reference potential line GND. When the q-th switch YC(q) (where q is an integer between 1 and Q) becomes conductive, the corresponding capacitor Cd(q) becomes active. The capacitance value of the variable capacitance capacitor section 22B is determined according to the combination of switches YC(1) to YC(Q) that become conductive. Switches YC(1) to YC(Q) are, for example, electromagnetic relays.

[0041] Figure 5 is a circuit diagram showing a surge voltage generation circuit 20C as yet another configuration example of the surge voltage generation circuit 20. The surge voltage generation circuit 20C shown in Figure 5 has a series circuit 21C and a variable capacitance capacitor section 22C. The series circuit 21C includes a variable resistor section 23C and a variable inductor section 24C connected in series with each other. One end of the series circuit 21C constitutes the input terminal 20a of the surge voltage generation circuit 20C. The other end of the series circuit 21C is connected to the output terminal 20b of the surge voltage generation circuit 20C. In the series circuit 21C, the order of the variable resistor section 23C and the variable inductor section 24C does not matter. That is, the variable inductor section 24C may be connected between the variable resistor section 23C and the input terminal 20a, or the variable resistor section 23C may be connected between the variable inductor section 24C and the input terminal 20a. One end of the variable capacitance capacitor section 22C is connected to the node between the other end of the series circuit 21C and the output terminal 20b. The other end of the variable capacitance capacitor section 22C is connected to a constant potential line (for example, a reference potential line GND).

[0042] The variable resistor section 23C includes N resistors R(1) to R(N) connected in series with each other, and N detachable busbars TB(1) to TB(N) connected in parallel to each of the N resistors R(1) to R(N). The busbars TB(1) to TB(N) are made of copper, for example. The configuration of the variable resistor section 23C is the same as that of the variable resistor section 23B described above, except that each of the switches YR(1) to YR(N) is replaced by each of the busbars TB(1) to TB(N). When the nth busbar TB(n) is installed, the corresponding resistor R(n) is bypassed. The resistance value of the variable resistor section 23C is determined according to the combination of busbars TB(1) to TB(N) that are installed.

[0043] The variable inductor section 24C includes M inductors L(1) to L(M) and a detachable busbar TBL. The busbar TBL is made of copper, for example. The inductances of the inductors L(1) to L(M) are fixed and different from each other. One end of each inductor L(1) to L(M) is connected to the variable resistor section 23C. The other end of each inductor L(1) to L(M) is connected to terminals AL(1) to AL(M), respectively, which are connectable to one end of the busbar TBL. The variable inductor section 24C further includes terminal AL(0), which is connectable to one end of the busbar TBL, and terminal ATB, which is connectable to the other end of the busbar TBL. Terminal AL(0) is connected to the variable resistor section 23C without an inductor. Terminal ATB is connected to the output terminal 20b. In the illustrated example, each of the inductors L(1) to L(M) is positioned between the variable resistor section 23C and a circuit element including the busbar TBL and terminals AL(1) to AL(M), but the circuit element including the busbar TBL and terminals AL(1) to AL(M) may be positioned between each of the inductors L(1) to L(M) and the variable resistor section 23C. When one end of the busbar TBL is connected to the m-th terminal AL(m), the corresponding inductor L(m) becomes active. The inductance of the inductor L(m) selected by the busbar TBL becomes the inductance of the variable inductor section 24C.

[0044] The variable capacitance capacitor section 22C functions as a parallel resonant capacitor. The variable capacitance capacitor section 22C includes Q capacitors Cd(1) to Cd(Q) and Q detachable busbars TBC(1) to TBC(Q). The capacitance values ​​of capacitors Cd(1) to Cd(Q) are fixed. Each capacitor Cd(1) to Cd(Q) may be connected in series with each busbar TBC(1) to TBC(Q). The Q series circuits, each containing each capacitor Cd and each busbar TBC, are connected in parallel with each other at the node between the variable inductor section 24C and the output terminal 20b, and between the reference potential line GND. In the illustrated example, each capacitor Cd(1) to Cd(Q) is connected between each busbar TBC(1) to TBC(Q) and the reference potential line GND, but each busbar TBC(1) to TBC(Q) may be connected between each capacitor Cd(1) to Cd(Q) and the reference potential line GND. When the q-th busbar TBC(q) is installed, the corresponding capacitor Cd(q) becomes active. The capacitance value of the variable capacitance capacitor section 22C is determined according to the combination of busbars TBC(1) to TBC(Q) that are installed.

[0045] In the surge voltage generation circuit 20B shown in Figure 4, or the surge voltage generation circuit 20C shown in Figure 5, the resistance value of the variable resistor section 23B or 23C, the inductance of the variable inductor section 24B or 24C, and the capacitance value of the variable capacitance capacitor section 22B or 22C can be varied in steps. These surge voltage generation circuits 20B and 20C may be used when fine adjustment of the drive voltage waveform is not required, or when a specific drive voltage waveform is used for testing. Compared to the surge voltage generation circuit 20A shown in Figure 3, the surge voltage generation circuits 20B and 20C have the advantages of a simpler configuration, easier setup and operation, and higher practicality. In addition, the surge voltage generation circuit 20B allows for automatic control of the resistance value, inductance, and capacitance value.

[0046] The combinations of the variable resistors 23A to 23C, the variable inductors 24A to 24C, and the variable capacitance capacitors 22A to 22C described above are not limited to the examples given. For example, the variable resistor 23A, the variable inductor 24B, and the variable capacitance capacitor 22C may be combined, or other combinations may also be used. Figure 6 schematically shows a positive voltage pulse containing a surge voltage output from the surge voltage generation circuit 20. Part (a) of Figure 6 shows the case when the resistance value R of the variable resistor section 23A (23B or 23C) is sufficiently smaller than the square root of the ratio (L / Cc) between the combined capacitance C of the variable capacitor section 22A (22B or 22C) and the stray capacitance of the test object M, and the inductance L of the variable inductor section 24A (24B or 24C), i.e.

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[0047] The amplitude of the voltage pulse P1, i.e., the peak voltage +Vp, can be freely adjusted by the set voltage of the positive polarity DC power supply V1. The time width tw1 of the voltage pulse P1 can be freely adjusted by the conduction time of the semiconductor switch HVS1. Similarly, the amplitude of the negative polarity voltage pulse, i.e., the peak voltage, can be freely adjusted by the set voltage of the negative polarity DC power supply V2. The time width of the negative polarity voltage pulse can be freely adjusted by the conduction time of the semiconductor switch HVS2. The peak value Vs and half-width tw2 of the surge voltage contained in the voltage pulse P2 are determined by the LC resonant oscillation due to the inductance L and the combined capacitance Cc. The oscillation period T of the surge voltage is expressed by the following equation (4).

number

[0048] As described above, the peak value, half-width, and oscillation frequency of the surge voltage can be freely set by adjusting the resistance R, inductance L, and combined capacitance Cc. In addition, the amplitude and duration of the voltage pulse (fundamental wave) output from the pulse generation circuit 10 can be freely set by adjusting the set voltage of the positive polarity DC power supply V1 (or negative polarity DC power supply V2) and the conduction time of the semiconductor switch HVS1 (or semiconductor switch HVS2). Therefore, the test apparatus 1 of this embodiment can perfectly simulate the actual surge voltage oscillation waveform generated in an inverter-driven motor.

[0049] Figure 7 schematically shows an example of a bipolar drive voltage waveform including a surge voltage. In this example, a first pulse group PG1 consisting of multiple positive voltage pulses Pp including a surge voltage, and a second pulse group PG2 consisting of multiple negative voltage pulses Pn including a surge voltage, are output alternately from the surge voltage generation circuit 20 with a time interval (dead time) Δt. In this example, the positive voltage pulses Pp and negative voltage pulses Pn are output in bursts within a predetermined period for each. In the first pulse group PG1, the repetition period t1 of the voltage pulses Pp is constant. In the second pulse group PG2, the repetition period t2 of the voltage pulses Pn is constant.

[0050] Figure 8 schematically shows an example of a drive voltage waveform including a surge voltage. In this example, a positive voltage pulse Pp including a surge voltage is output continuously from the surge voltage generation circuit 20 until the end of the test. The repetition period t1 of the voltage pulse Pp is constant.

[0051] Figure 9 schematically shows an example of a drive voltage waveform including a surge voltage. In this example, multiple first pulse groups PG1, each consisting of multiple positive voltage pulses Pp including a surge voltage, are output from the surge voltage generation circuit 20 at time intervals Δt from each other. In this example, the positive voltage pulses Pp are output in bursts within a predetermined period. In the first pulse group PG1, the repetition period t1 of the voltage pulses Pp is constant.

[0052] Figure 10 schematically shows an example of a drive voltage waveform including a surge voltage. In this example, a negative polarity voltage pulse Pn including a surge voltage is output continuously from the surge voltage generation circuit 20 until the end of the test. The repetition period t2 of the voltage pulse Pn is constant.

[0053] Figure 11 schematically shows an example of a drive voltage waveform including a surge voltage. In this example, multiple second pulse groups PG2, each consisting of multiple negative voltage pulses Pn including a surge voltage, are output from the surge voltage generation circuit 20 at time intervals Δt from each other. In this example, the negative voltage pulses Pn are output in bursts within a predetermined period. In the second pulse group PG2, the repetition period t2 of the voltage pulses Pn is constant.

[0054] Figure 12 schematically shows an example of a drive voltage waveform that does not include surge voltage. In this example, a single positive voltage pulse Pp that does not include surge voltage and a single negative voltage pulse Pn that does not include surge voltage are output alternately from the surge voltage generation circuit 20 with a time interval Δt. Such a drive voltage waveform that does not include surge voltage is realized by short-circuiting the inductor in the surge voltage generation circuit 20 to form a non-inductive circuit. That is, in the surge voltage generation circuit 20A shown in Figure 3, the slider 24b of the variable inductor section 24A is moved to a position that bypasses the inductor 24a. In the surge voltage generation circuit 20B shown in Figure 4, only switch YL(0) among switches YL(0) to YL(M) is made conductive. In the surge voltage generation circuit 20C shown in Figure 5, one end of the busbar TBL is connected to terminal AL(0). The rise and fall times of the voltage pulses Pp and Pn are adjusted by the resistance values ​​of the variable resistor sections 23A, 23B, or 23C. The diagram shows, superimposed, cases where the rise and fall are steep and cases where they are gradual.

[0055] Figure 13 schematically shows an example of a drive voltage waveform that does not include surge voltage. In this example, a single positive voltage pulse Pp and a single negative voltage pulse Pn, both free of surge voltage, are alternately output from the surge voltage generation circuit 20 without any time interval (i.e., Δt=0 in Figure 12). Such a drive voltage waveform that does not include surge voltage is realized by short-circuiting the inductor in the surge voltage generation circuit 20 to form a non-inductive circuit, similar to the drive voltage waveform shown in Figure 12. By setting the time width of voltage pulse Pp and voltage pulse Pn to be equal, and by making the absolute value of the peak voltage +Vp of voltage pulse Pp equal to the absolute value of the peak voltage -Vp of voltage pulse Pn, a positive and negative symmetrical drive voltage waveform with a 50% duty cycle is obtained. The rise and fall times of voltage pulses Pp and Pn are adjusted by the resistance values ​​of the variable resistors 23A, 23B, or 23C. The diagram shows, superimposed, cases where the rise and fall are steep and cases where they are gradual.

[0056] The drive voltage waveforms, which do not include surge voltage, shown in Figures 12 and 13, can be used to compare with the drive voltage waveforms that include surge voltage (see, for example, Figure 14) with respect to the insulation and lifespan of the test object M.

[0057] In Figures 7 to 13, the absolute value of the surge voltage peak value Vs is, for example, between 3kVp and 20kVp. In one embodiment, the absolute values ​​of the surge voltage peak value Vs are set to 3kVp, 6kVp, 10kVp, and 20kVp. The configurable range for the frequency (reciprocal of the repetition periods t1 and t2) of the voltage pulses Pp and Pn is, for example, 1kHz to 100kHz. The configurable range for the rise time and fall time of the voltage pulses Pp and Pn is, for example, 20ns to 100ns.

[0058] Figures 15 and 16 show the drive voltage waveforms measured in test apparatus 1. Sections (a) to (e) of Figure 15 show a single positive voltage pulse Pp including surge voltage. Sections (a), (d), and (e) of Figure 16 show the case where a positive voltage pulse Pp and a negative voltage pulse Pn are output alternately. Sections (b) and (c) of Figure 16 show the case where a first pulse group PG1 consisting of multiple positive voltage pulses Pp and a second pulse group PG2 consisting of multiple negative voltage pulses Pn are output alternately with a time interval (see Figure 7). Sections (a), (b), and (c) of Figure 16 show the drive voltage waveform without surge voltage. Sections (d) and (e) of Figure 16 show the drive voltage waveform including surge voltage.

[0059] Figure 17 is a block diagram showing an example of the system configuration of the test apparatus 1 of this embodiment. As shown in Figure 17, in addition to the configuration described above, the test apparatus 1 further comprises a combined interface 51, a computer 52, a display unit 53, a printer 54, an input operation unit 55, a low-voltage power supply 56, a partial discharge measuring instrument 57, and a constant temperature chamber 58 for housing the object to be tested M.

[0060] The low-voltage power supply 56 provides power supply voltage to the semiconductor switches HVS1 to HVS3 and the control elements. The low-voltage power supply 56, together with the positive-polarity DC power supply V1 and the negative-polarity DC power supply V2, constitutes the power supply section of the pulse generation circuit 10.

[0061] The aggregate interface 51 is electrically connected to the computer 52. The group consisting of the aggregate interface 51 and the computer 52 also serves as the first control unit and the second control unit in this embodiment. The aggregate interface 51 is connected to the semiconductor switches HVS1 to HVS3 via optical fibers. The computer 52 provides optical trigger signals LT1 to LT3 to each of the semiconductor switches HVS1 to HVS3, respectively, through the aggregate interface 51. The computer 52 forms a drive voltage waveform by controlling the on / off timing of the semiconductor switches HVS1 to HVS3 using the optical trigger signals LT1 to LT3. The time width of the positive voltage pulse is equal to the time width of the optical trigger signal LT1 to semiconductor switch HVS1. The time width of the negative voltage pulse is equal to the time width of the optical trigger signal LT2 to semiconductor switch HVS2.

[0062] The combined interface 51 is electrically connected to a positive DC power supply V1, a negative DC power supply V2, variable resistors 23A, 23B or 23C, variable inductors 24A, 24B or 24C, variable capacitance capacitors 22A, 22B or 22C, a current sensor 41, a high-voltage probe 42, a partial discharge measuring instrument 57, and a constant temperature bath 58. The computer 52 outputs control signals to the positive DC power supply V1, the negative DC power supply V2, the variable resistors 23A, 23B or 23C, the variable inductors 24A, 24B or 24C, the variable capacitance capacitors 22A, 22B or 22C, and the constant temperature bath 58 through the combined interface 51. The computer 52 controls the voltage values ​​of the positive DC power supply V1 and the negative DC power supply V2 by the control signals. The computer 52 also controls the resistance values ​​of the variable resistors 23A, 23B or 23C by the control signals. Computer 52 controls the inductance of the variable inductor section 24A, 24B, or 24C by control signals. Computer 52 controls the capacitance value of the variable capacitance capacitor section 22A, 22B, or 22C by control signals. Computer 52 controls the temperature of the constant temperature chamber 58 by control signals, and also receives signals indicating the temperature inside the constant temperature chamber 58, and collects and records temperature data.

[0063] The computer 52 can determine the magnitude of the current output from the surge voltage generation circuit 20 from the signal from the current sensor 41. The computer 52 can also determine the magnitude of the voltage output from the surge voltage generation circuit 20 from the signal from the high-voltage probe 42. As shown in Figure 15, the output signals from the current sensor 41 and the high-voltage probe 42 may each be split into two, one of which may be sent to the combined interface 51 and used by the computer 52 for overcurrent protection, data acquisition, and recording. The other signal may be sent to the oscilloscope 43, and the drive voltage waveform and current waveform output from the surge voltage generation circuit 20 may be displayed in real time on the oscilloscope 43. If the output signal from the current sensor 41 exceeds a value set in advance by the operator due to dielectric breakdown or ground fault of the test object M, the computer 52 quickly shuts off the operating semiconductor switches HVS1 to HVS3 and simultaneously shuts off the positive polarity DC power supply V1 and the negative polarity DC power supply V2 immediately. In addition, the computer 52 informs the operator via the display unit 53 that the test object M has an abnormality.

[0064] The computer 52 can determine the magnitude of the partial discharge occurring in the test object M from the signal from the partial discharge measuring instrument 57. Based on the signal from the partial discharge measuring instrument 57, the computer 52 determines whether or not a partial discharge is occurring, detects the partial discharge initiation voltage, and analyzes the strength of the partial discharge. For example, the partial discharge detector (model number NPD-1) manufactured by Nissin Pulse Electronics Co., Ltd. is used as the partial discharge measuring instrument 57. This partial discharge detector can measure a wider frequency band than conventional partial discharge detectors and can accurately measure partial discharge charge amounts of a few pC (picocoulons).

[0065] The display unit 53, the printer 54, and the input operation unit 55 are electrically connected to the computer 52. The computer 52 displays the test results on the display unit 53. The computer 52 prints the test results on the printer 54. The display unit 53 and the printer 54 are used for data processing of test results, recording of test results, and creating reports. The display unit 53 may also display the operating status of the test apparatus 1.

[0066] The input operation unit 55 receives input of setting parameters and execution commands from the operator. The setting parameters received by the input operation unit 55 are displayed on the display unit 53. The input operation unit 55 may be a keyboard connected to a computer 52, or it may be a touch panel provided on the display unit 53.

[0067] The setting parameters accepted by the input operation unit 55 may include information regarding whether the intermittent voltage pulses included in the drive voltage waveform consist only of positive voltage pulses Pp, as shown in Figure 8 or Figure 9, or only of negative voltage pulses Pn, as shown in Figure 10 or Figure 11, or whether they include both voltage pulses Pp and Pn, as shown in Figure 7, Figure 12, or Figure 13. The setting parameters may also include information regarding whether the intermittent voltage pulses included in the drive voltage waveform are output continuously until the end of the test, as shown in Figure 8 or Figure 10, or whether they are output in bursts within a preset period, as shown in Figure 7, Figure 9, or Figure 11. The setting parameters may also include information regarding the amplitude of the voltage pulses included in the drive voltage waveform, i.e., the peak voltages +Vp and -Vp of the voltage pulses Pp and Pn. The setting parameters may also include information regarding the frequency (1 / t1 or 1 / t2) of the intermittent voltage pulses Pp and Pn included in the drive voltage waveform. The setting parameters may include information about the time width tw1 of the intermittent voltage pulses Pp and Pn included in the drive voltage waveform. The setting parameters may include at least one or all of the group consisting of the aforementioned time interval Δt, the power supply voltage +HV of the positive polarity DC power supply V1, the power supply voltage -HV of the negative polarity DC power supply V2, the resistance value R of the variable resistor section 23A (23B or 23C), the inductance L of the variable inductor section 24A (24B or 24C), and the capacitance value C of the variable capacitance capacitor section 22A (22B or 22C). The input operation unit 55 provides these setting parameters, input by the input operation, to the computer 52.

[0068] In addition, the input operation unit 55 receives input operations regarding the number of intermittent voltage pulses (repetition counts) included in the drive voltage waveform output from the pulse generation circuit 10, that is, the number of voltage pulses Pp and Pn included in the first pulse group PG1 and the second pulse group PG2, respectively. The input operation unit 55 provides the computer 52 with information regarding the number of intermittent voltage pulses input through the input operations.

[0069] The effects obtained by the test apparatus 1 of this embodiment, as described above, will be explained along with the problems of the conventional method. Conventionally, the PWM control method has been widely used to control each phase of an electric motor. Figure 18 shows an example of a 2-level PWM drive waveform. Figure 19 shows an example of a 3-level PWM drive waveform. In these figures, the vertical axis represents voltage and the horizontal axis represents time. In the figures, a rectangular wave PWM output waveform B1 and the output waveform B2 after the PWM output waveform B1 has passed through an LC filter are shown superimposed. The output waveform B2 is a sine wave.

[0070] In the PWM control method, the PWM output waveform B1 is formed by the high-speed switching operation of semiconductor switches. However, surge voltages are significantly generated in the rising and falling edges of the rectangular wave included in the PWM output waveform B1 due to the wiring inductance leading to the electric motor. Part (a) of Figure 20 schematically shows the rectangular wave before the surge voltage is generated. Part (b) of Figure 20 schematically shows the rectangular wave after the surge voltage is generated. The larger the peak value of the surge voltage entering the electric motor, the more partial discharge occurs in the insulation resin of the windings, and the more the insulation deterioration of the electric motor and windings progresses.

[0071] While the mechanism by which partial discharge caused by surge voltage leads to insulation degradation is known, the correlation between the partial discharge inception voltage (PDIV) and the amount of discharged charge has not yet been quantitatively evaluated. Furthermore, partial discharge in a PWM output waveform, where pulse groups consisting of multiple positive voltage pulses and pulse groups consisting of multiple negative voltage pulses alternate, has also not yet been quantitatively evaluated. In addition, there has been no existing test equipment capable of performing insulation evaluation, including partial discharge (a precursor phenomenon to insulation breakdown in electric motors due to surge voltage), life evaluation through repeated operation, and Vt accelerated degradation testing.

[0072] To address the above issues, the test apparatus 1 of this embodiment can simulate a PWM output waveform using a pulse generation circuit 10, and furthermore, can add a surge voltage to the simulated PWM output waveform using a surge voltage generation circuit 20. In addition, since the resistance, inductance, and capacitance values ​​of the CLR resonant circuit of the surge voltage generation circuit 20 are variable, the peak value, half-width, and number of oscillations of the surge voltage can be freely set. Therefore, it is possible to accurately simulate the surge voltage generated in actual PWM control, and to accurately perform insulation evaluation against partial discharge, life evaluation by repeated operation, and Vt accelerated degradation tests. Furthermore, it is possible to perform quantitative evaluation of the correlation between PDIV and the amount of discharged charge, and quantitative evaluation of partial discharge for a PWM output waveform in which pulse groups consisting of multiple positive voltage pulses and pulse groups consisting of multiple negative voltage pulses are repeated alternately.

[0073] The configuration of the test apparatus 1 in this embodiment is such that all operating functions are separated and unitized, and each unit is equipped with a wealth of fault detection functions, which can automatically notify the operator of the occurrence of a fault through the display unit 53, etc. If repair is necessary, the faulty unit can be easily replaced as a whole, and the recovery work can be carried out quickly even by someone other than the manufacturer of the test apparatus 1.

[0074] As in this embodiment, the pulse generation circuit 10 may include a semiconductor switch HVS1, a semiconductor switch HVS2, a bridge full-wave rectifier BR1, and a semiconductor switch HVS3. A circuit that accelerates the falling time of positive and negative voltage pulses and quickly restores these voltage pulses to a reference potential is also called a ground (GND) circuit, focusing on its function. Originally, in order to make the falling potentials of positive and negative voltage pulses the reference potential, a total of two semiconductor switches are required: one semiconductor switch corresponding to the positive voltage pulse and one semiconductor switch corresponding to the negative voltage pulse. However, in this embodiment, by using a bridge full-wave rectifier BR1, the ground circuit is configured with only one semiconductor switch HVS3. This simplifies the circuit configuration. Furthermore, the pulse generation circuit 10 can output a voltage having a 2-level or 3-level inverter drive waveform as the drive voltage waveform.

[0075] As in this embodiment, the pulse generation circuit 10 may include a plurality of semiconductor switches HVS1 to HVS3 for forming a drive voltage waveform, and a combined interface 51 and a computer 52 that generate a plurality of optical trigger signals LT1 to LT3 for controlling the plurality of semiconductor switches HVS1 to HVS3, respectively. The combined interface 51 may provide each of the plurality of optical trigger signals LT1 to LT3 to each of the plurality of semiconductor switches HVS1 to HVS3. By providing each of the semiconductor switches HVS1 to HVS3 with an optical trigger signal LT1 to LT3, the effects of noise can be reduced and malfunctions can be prevented.

[0076] As in this embodiment, the input operation unit 55 may receive an input operation regarding the number of voltage pulses Pp included in the first pulse group PG1 and / or the number of voltage pulses Pn included in the second pulse group PG2, and provide the computer 52 with information regarding the number of voltage pulses Pp and Pn input by the input operation. The computer 52 may then determine the number of voltage pulses Pp included in the first pulse group PG1 and / or the number of voltage pulses Pn included in the second pulse group PG2 according to that information. In this case, the number of voltage pulses Pp included in the first pulse group PG1 and / or the number of voltage pulses Pn included in the second pulse group PG2 can be freely and easily set.

[0077] As in this embodiment, the input operation unit 55 receives an input operation relating to the drive voltage waveform and provides information regarding the drive voltage waveform input by the input operation to the computer 52, and the computer 52 may determine the drive voltage waveform according to the information. The information regarding the drive voltage waveform may include at least one of the following: information on whether the intermittent pulse consists only of positive polarity pulses, only of negative polarity pulses, or includes both positive and negative polarity; information on whether the intermittent pulse is output continuously until the end of the test or output in bursts within a preset period; information on the amplitude of the intermittent pulse; information on the frequency of the intermittent pulse; and information on the time width of each pulse constituting the intermittent pulse. In this case, the drive voltage waveform can be configured arbitrarily, so the test conditions can be freely set.

[0078] The inverter pulse isolation test apparatus according to this disclosure is not limited to the embodiments described above, and various other modifications are possible. For example, in the above embodiment, a variable non-inductive resistor is used in the variable resistor section of the surge voltage generation circuit, but the type of resistor used in the variable resistor section is not limited to this, and for example, an electronically controlled equivalent variable resistor may be used. [Explanation of symbols]

[0079] 1...Inverter pulse isolation test device, 10...Pulse generation circuit, 10b...Output terminal (first output terminal), 11,12...High voltage terminal, 13...Output terminal, 20,20A,20B,20C...Surge voltage generation circuit, 20a...Input terminal, 20b...Output terminal (second output terminal), 21A,21B,21C...Series circuit, 22A,22B,22C...Capacitance variable capacitor section, 23A,23B,23C...Variable resistor section, 23a...Resistor, 23b...Sliding Mouthpiece, 24A, 24B, 24C... Variable inductor section, 24a... Inductor, 24b... Slider, 41... Current sensor, 42... High voltage probe, 43... Oscilloscope, 51... Integrated interface, 52... Computer, 53... Display unit, 54... Printer, 55... Input operation unit, 56... Low voltage power supply, 57... Partial discharge measuring instrument, 58... Constant temperature bath, ATB, AL(0)~AL(M)... Terminals, BR1... Bridge full-wave rectifier, C1, C2 ...capacitor, Cd(1)~Cd(Q)...capacitor, GND...reference potential line, HVS1...semiconductor switch (first semiconductor switch), HVS2...semiconductor switch (second semiconductor switch), HVS3...semiconductor switch (third semiconductor switch), L(1)~L(Q)...inductor, LT1~LT3...optical trigger signal, M...test object, M1,M2,M3...motor, N1,N2,N3,N4...node, P1,P2...voltage pin Rs(1)~R(N)...resistors, Rd1,Rd2...discharge resistors, Rp1,Rp2,Rs1,Rs2,Rs3...resistors, TBL,TB(1)~TB(N),TBC(1)~TBC(Q)...busbars, V1...positive polarity DC power supply, V2...negative polarity DC power supply, YC(1)~YC(Q),YL(0)~YL(M),YR(0)~YR(N)...switches

Claims

1. A pulse generation circuit having a first output terminal and outputting a voltage having a simulated drive voltage waveform including intermittent pulses from the first output terminal, A surge voltage generating circuit having an input terminal electrically connected to the first output terminal of the pulse generating circuit and a second output terminal connected to the object under test, which generates a surge voltage at the rising and falling edges of each pulse of the drive voltage waveform input from the input terminal to change the drive voltage waveform, and outputs a voltage having the changed drive voltage waveform from the second output terminal, Equipped with, The surge voltage generation circuit is, A variable resistor and a variable inductor connected in series with each other, A variable capacitance capacitor, It has, One end of the series circuit of the variable resistor and the variable inductor constitutes the input terminal of the surge voltage generation circuit. The other end of the series circuit is connected to the second output terminal of the surge voltage generating circuit. One end of the variable capacitance capacitor is connected to the node between the other end of the series circuit and the second output terminal. The other end of the variable capacitance capacitor is connected to a constant potential line. The pulse generation circuit is A first semiconductor switch, with one end connected to a positive voltage terminal and the other end connected to the first output terminal, A second semiconductor switch, with one end connected to a negative voltage terminal and the other end connected to the first output terminal, A bridge full-wave rectifier having two input terminals and two output terminals, wherein one of the two input terminals is connected to a reference potential line, and one of the two output terminals is connected to the first output terminal, A third semiconductor switch, one end of which is connected to the other input terminal of the bridge full-wave rectifier and the other end of which is connected to the other output terminal of the bridge full-wave rectifier, An inverter pulse insulation test apparatus having the following features.

2. The inverter pulse isolation test apparatus according to claim 1, wherein the pulse generation circuit outputs a voltage having two-level or three-level inverter drive waveforms as the drive voltage waveform.

3. The pulse generation circuit includes a first control unit that generates a plurality of optical trigger signals to control the first semiconductor switch, the second semiconductor switch, and the third semiconductor switch, respectively. The inverter pulse isolation test apparatus according to claim 1, wherein the first control unit provides each of the plurality of optical trigger signals to the first semiconductor switch, the second semiconductor switch, and the third semiconductor switch, respectively.

4. A second control unit that controls the drive voltage waveform in the pulse generation circuit, An input operation unit receives an input operation regarding the number of intermittent pulses and provides the information regarding the number of intermittent pulses input by the input operation to the second control unit, Furthermore, The inverter pulse isolation test apparatus according to any one of claims 1 to 3, wherein the second control unit determines the number of intermittent pulses according to the information.

5. A second control unit that controls the drive voltage waveform in the pulse generation circuit, An input operation unit receives an input operation related to the drive voltage waveform and provides information regarding the drive voltage waveform input by the input operation to the second control unit, Furthermore, The second control unit determines the drive voltage waveform according to the information, The information regarding the aforementioned drive voltage waveform is, Information regarding whether the intermittent pulses consist only of positive-polarity pulses, only of negative-polarity pulses, or include both positive-polarity and negative-polarity pulses, Information regarding whether the aforementioned intermittent pulses are output continuously until the end of the test or in bursts within a predetermined period, Information regarding the amplitude of the intermittent pulses, Information regarding the frequency of the aforementioned intermittent pulses, Information regarding the time width of each pulse constituting the aforementioned intermittent pulse, An inverter pulse insulation test apparatus according to any one of claims 1 to 3, comprising at least one of the following pieces of information.

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