Power supply control device and power supply control method

Abstract

To provide a power supply control device and a power supply control method capable of preventing instantaneous interruption of power feeding to a second load without affecting a switch in a case where failures of a first power supply are resolved.SOLUTION: A power supply control device comprises an intersystem switch, a battery switch, and a control unit. Each of the intersystem switch and the battery switch includes a pair of FETs connected in series so that directions of their parasitic diodes are reverse to each other. The control unit, when detecting failures of a first power supply, feeds power from a second power supply to a second load, and when the failures of the first power supply are resolved, performs recovery control. The control unit, when performing the recovery control, controls the FETs of the battery switch so that a current flows from the second power supply to the second load via the parasitic diodes, after that, controls the FETs of the intersystem switch so that a current flows from the first power supply to the second load via the parasitic diode, and thereafter, turns OFF the battery switch and then turns ON the intersystem switch.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed embodiments relate to a power supply control device and a power supply control method.

Background Art

[0002] There is a power supply control device including an inter-system switch that conducts and interrupts a first system that supplies power from a first power supply to a first load and a second system that supplies power from a second power supply to a second load, a battery switch that conducts and interrupts the second power supply and the second system, and a control unit (see, for example, Patent Document 1).

[0003] When the control unit detects a failure of the first power supply, it interrupts the inter-system switch, conducts the battery switch, and performs fail-safe control to supply the power of the second power supply to the second load. When the failure of the first power supply is resolved, it conducts the inter-system switch and performs return control to interrupt the battery switch.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When the failure of the first power supply is resolved, if the power supply control device conducts the inter-system switch after interrupting the battery switch, power supply to the second load is interrupted momentarily from when the battery switch is interrupted until the inter-system switch is conducted.

[0006] Therefore, when the failure of the first power supply is resolved, if the power supply control device conducts the inter-system switch and then turns off the battery switch, it can prevent momentary interruption of power supply. However, when the potential difference between the first power supply and the second power supply is large, a large current flows and has an adverse effect on the switch.

[0007] One embodiment, made in view of the above, aims to provide a power control device and a power control method that can prevent momentary interruption of power supply to the second load without adversely affecting the switch when the failure of the first power supply is resolved. [Means for solving the problem]

[0008] A power control device according to one embodiment comprises an inter-system switch, a battery switch, and a control unit. The inter-system switch connects and disconnects a first system that supplies power from a first power source to a first load and a second system that supplies power from a second power source to a second load. The battery switch connects and disconnects the second power source and the second system. When the control unit detects a failure of the first power source, it performs fail-safe control by disconnecting the inter-system switch and connecting the battery switch to supply power from the second power source to the second load, and when the failure of the first power source is resolved, it performs recovery control by connecting the inter-system switch and disconnecting the battery switch. The inter-system switch and the battery switch include a circuit in which a pair of FETs (Field Effect Transistors) with parasitic diodes facing opposite directions are connected in series. When the control unit performs the recovery control, it turns off one of the FETs of the battery switch and turns on the other FET so that current flows from the second power supply to the second load via the parasitic diode, then turns off one of the FETs of the inter-system switch and turns on the other FET so that current flows from the first power supply to the second load via the parasitic diode, then turns off both of the FETs of the battery switch, and then turns on both of the FETs of the inter-system switch. [Effects of the Invention]

[0009] A power control device and power control method according to one embodiment of the system have the effect of preventing a momentary interruption of power supply to the second load without adversely affecting the switch when the failure of the first power supply is resolved. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is an explanatory diagram showing an example configuration of a power supply control device according to an embodiment. [Figure 2] Figure 2 is an explanatory diagram showing an example of operation of the power control device according to the embodiment. [Figure 3] Figure 3 is an explanatory diagram showing an example of operation of the power control device according to the embodiment. [Figure 4] Figure 4 is an explanatory diagram showing an example of operation of the power control device according to the embodiment. [Figure 5] Figure 5 is an explanatory diagram showing an example of operation of the power control device according to the embodiment. [Figure 6] Figure 6 is an explanatory diagram showing an example of operation of the power control device according to the embodiment. [Figure 7] Figure 7 is a flowchart showing an example of a process performed by the control unit of the power control device according to this embodiment. [Figure 8] Figure 8 is an explanatory diagram showing an example of the configuration of a power control device according to a modified embodiment. [Figure 9] Figure 9 is a timing chart showing the state of the power control device during recovery control according to a modified embodiment. [Modes for carrying out the invention]

[0011] Embodiments of the power control device and power control method will be described in detail below with reference to the attached drawings. However, the present invention is not limited to the embodiments described below. In the following description, a power supply device mounted on a vehicle equipped with an autonomous driving function to supply power to a load will be used as an example; however, the power supply device according to the embodiment may be mounted on a vehicle without an autonomous driving function.

[0012] [1. Configuration of the power control unit] First, referring to FIG. 1, a configuration example of the power control device 1 according to the embodiment will be described. FIG. 1 is an explanatory diagram showing a configuration example of the power control device 1 according to the embodiment. As shown in FIG. 1, the power control device 1 is connected to a first power source 10, a first load 101, and a second load 102.

[0013] The first load 101 includes loads for autonomous driving. For example, the first load 101 includes a steering motor, an electric brake device, and a radar that operate during autonomous driving. In addition, the first load 101 also includes general loads such as a display, an air conditioner, an audio, a video, and various lights.

[0014] The second load 102 includes loads for autonomous driving. For example, the first load 101 includes a steering motor, an electric brake device, and an in-vehicle camera that operate during autonomous driving. Hereinafter, a case will be described as an example in which, among the loads for autonomous driving, the radar is included in the first load 101 and not in the second load 102, and the in-vehicle camera is included in the second load 102 and not in the first load 101.

[0015] The first power source 10 is a main power source that supplies power to the first load 101 and the second load 102 during normal times without a power failure. The first power source 10 is, for example, a lead battery mounted on a vehicle. Note that the first power source 10 may be any secondary battery other than a lead battery.

[0016] The power control device 1 includes an inter-system switch 41 that connects the first system 110 and the second system 120, a battery switch 42, a second power source 20, and a control unit 3. The second power source 20 is an auxiliary power source that supplies power to the second load 102 when the first power source 10 fails. The second power source 20 is, for example, a lithium-ion battery. Note that the second power source 20 may be any secondary battery other than a lithium-ion battery.

[0017] The first system 110 is a power supply system that supplies the power of the first power source 10 to the first load 101. The second system 120 is a power supply system that supplies the power of the second power source 20 to the second load 102. The inter-system switch 41 conducts and disconnects the first system 110 and the second system 120. The battery switch 42 conducts and disconnects the second power source 20 and the second system 120.

[0018] The inter-system switch 41 is connected to the first load 101 and the first power source 10 by a harness. Also, the inter-system switch 41 is connected to the second load 102 by the same harness (not shown) and is connected to the battery switch 42 by the wiring of a printed board (not shown) in the power control device 1. Problems with harness connections and means for solving the problems will be described in a modified example later.

[0019] The inter-system switch 41 includes a circuit in which a pair of FETs (Field Effect Transistors) with the directions of parasitic diodes opposite to each other are connected in series. For example, the inter-system switch 41 includes a circuit in which a first FET 61 with the anode of the parasitic diode 51 on the second system 120 side and a second FET 62 with the anode of the parasitic diode 52 on the first system 110 side are connected in series.

[0020] For the first FET 61, the drain is connected to the first power source 10 and the first load 101, the source is connected to the source of the second FET 62, and the gate is connected to the control unit 3. For the second FET 62, the drain is connected to the second load 102 and the battery switch 42, and the gate is connected to the control unit 3.

[0021] Also, the battery switch 42 includes a circuit in which a pair of FETs with the directions of parasitic diodes opposite to each other are connected in series. For example, the battery switch 42 includes a circuit in which a third FET 63 with the anode of the parasitic diode 53 on the second power source 20 side and a fourth FET 64 with the anode of the parasitic diode 54 on the second load 102 side are connected in series.

[0022] The drain of the third FET 63 is connected to the inter-system switch 41 and the second load 102, the source is connected to the source of the fourth FET 64, and the gate is connected to the control unit 3. The drain of the fourth FET 64 is connected to the second power supply 20, and the gate is connected to the control unit 3.

[0023] In the following, the state of the inter-system switch 41 and the battery switch 42 may be changed from the disconnected state to the conductive state by turning it on, or from the conductive state to the disconnected state by turning it off. Also, in the following, the state of the first FET 61, the second FET 62, the third FET 63, and the fourth FET 64 may be changed from the disconnected state to the conductive state by turning it on, or from the conductive state to the disconnected state by turning it off.

[0024] The control unit 3 includes a microcomputer with a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), and various circuits. The control unit 3 may be partially or entirely composed of hardware such as an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array).

[0025] The control unit 3 performs detection of failures of the first power supply 10 and the second power supply 20, and controls the operation of the inter-system switch 41 and the battery switch 42 by executing a program stored in ROM by the CPU using RAM as a working area.

[0026] For example, when the control unit 3 detects a failure of the first power supply 10, it performs fail-safe control by turning off the inter-system switch 41 and turning on the battery switch 42 to supply power from the second power supply 20 to the second load 102. Subsequently, when the failure of the first power supply 10 is resolved, the control unit 3 performs recovery control by turning on the inter-system switch 41 and turning off the battery switch 42.

[0027] In this case, when the control unit 3 performs recovery control, for example, if it turns off the battery switch 42 and then turns on the inter-system switch 41, the power supply to the second load 102 may be momentarily interrupted during the period from when the battery switch 42 is turned off to when the inter-system switch 41 is turned on, which may cause problems with vehicle control.

[0028] For example, the automatic driving control system normally uses an on-board camera and radar to perform automatic driving control. When the first power supply 10 fails and fail control is initiated, the camera becomes unusable, and the system uses radar to perform automatic driving control.

[0029] Subsequently, once the failure of the first power supply 10 is resolved, the on-board camera will start operating, but it takes a certain amount of time from startup until it can perform initial processing and other tasks to become ready to capture images. Therefore, if the power supply to the radar is momentarily interrupted when the automatic driving control system performs recovery control, both the on-board camera and radar will be unusable, which may impair vehicle control.

[0030] Furthermore, when the control unit 3 performs a recovery control, for example, by turning on the inter-system switch 41 and then turning off the battery switch 42, it can prevent a momentary interruption in the power supply to the second load 102. However, in the power control device 1, at this time, a state occurs where the first power supply 10 and the second power supply 20 are temporarily directly connected, and if the potential difference between the first power supply 10 and the second power supply 20 is large, a large current may flow, potentially adversely affecting the inter-system switch 41 and the battery switch 42.

[0031] Therefore, when performing recovery control, the control unit 3 turns off one FET (the third FET 63) and turns on the other FET (the fourth FET 64) of the battery switch 42 so that current flows from the second power supply 20 to the second load 102 via the parasitic diode 53. Subsequently, the control unit 3 turns off one FET (the second FET 62) and turns on the other FET (the first FET 61) of the inter-system switch 41 so that current flows from the first power supply 10 to the second load 102 via the parasitic diode 52. After that, the control unit 3 turns off both FETs (the third FET 63 and the fourth FET 64) of the battery switch 42, and then turns on both FETs (the first FET 61 and the second FET 62) of the inter-system switch 41.

[0032] As a result, when the power control device 1 performs a recovery control, it can continue supplying power to the second load 102 using the parasitic diodes 52 and 53, while blocking the flow of current from the first power supply 10 to the second power supply 20 and from the second power supply 20 to the first power supply 10 using the parasitic diodes 52 and 53. Therefore, when the power control device 1 performs a recovery control, it can prevent a momentary interruption of power supply to the second load 102 without adversely affecting the inter-system switch 41 and the battery switch 42, thereby preventing malfunctions of the second load 102.

[0033] [2. Example of Power Control Device Operation] Next, an example of the operation of the power control device 1 will be specifically described with reference to Figures 2 to 6. Figures 2 to 6 are explanatory diagrams showing an example of the operation of the power control device 1 according to the embodiment.

[0034] [2.1. Normal operation] As shown in Figure 2, under normal conditions where there is no failure in the first power supply 10, the control unit 3 turns on the first FET 61 and the second FET 62, and turns off the third FET 63 and the fourth FET 64, thereby supplying power from the first power supply 10 to the first load 101 and the second load 102.

[0035] [2.2. Fail-safe control] As shown in Figure 3, the control unit 3 detects the failure of the first power supply 10 when, for example, a ground fault 200 occurs in the first system 110. For example, the control unit 3 detects the occurrence of a ground fault 200 and the failure of the first power supply 10 when a voltage below a ground fault threshold is detected for a predetermined period of time by a voltage sensor (not shown) that detects the voltage of the first power supply 10.

[0036] When the control unit 3 detects a ground fault 200 in the first power supply 10, it performs fail-safe control by turning off the first FET 61 and the second FET 62, and turning on the third FET 63 and the fourth FET 64, thereby supplying power from the second power supply 20 to the second load 102.

[0037] [2.3. Recovery Control] For example, when a voltage exceeding a ground fault threshold is detected by a voltage sensor (not shown) that detects the voltage of the first power supply 10, the control unit 3 determines that the failure of the first power supply 10 has been resolved and starts recovery control.

[0038] As shown in Figure 4, when the control unit 3 performs recovery control, it first turns off the third FET 63. As a result, the control unit 3 continues to supply power from the second power supply 20 to the second load 102 via the parasitic diodes 53 of the fourth FET 64 and the third FET 63.

[0039] Subsequently, as shown in Figure 5, the control unit 3 turns on the first FET 61. This allows power from the second power supply 20 to be supplied to the second load 102, while power from the first power supply 10 is supplied to the second load 102 via the parasitic diodes 52 of the first FET 61 and the second FET 62.

[0040] Furthermore, even if the voltage of the first power supply 10 is higher than the voltage of the second power supply 20, the current flow from the first power supply 10 to the second power supply 20 can be blocked by the parasitic diode 53 of the third FET 63. Also, even if the voltage of the second power supply 20 is higher than the voltage of the first power supply 10, the current flow from the second power supply 20 to the first power supply 10 can be blocked by the parasitic diode 52 of the second FET 62.

[0041] Subsequently, as shown in Figure 6, the control unit 3 turns off the fourth FET 64 and then turns on the second FET 62. This allows the control unit 3 to return to the normal operating state shown in Figure 2. In this way, the control unit 3 can reliably eliminate the momentary interruption of power supply to the second load 102 during the recovery control.

[0042] [2.4. Processes executed by the control unit 3] Next, referring to Figure 7, the processes executed by the control unit 3 of the power control device 1 according to this embodiment will be described. Figure 7 is a flowchart showing an example of the processes executed by the control unit 3 of the power control device 1 according to this embodiment.

[0043] During normal operation, the control unit 3 repeatedly executes the process shown in Figure 7. For this reason, when the power control device 1 starts the process shown in Figure 7, the first FET 61 and the second FET 62 are turned on, and the third FET 63 and the fourth FET 64 are turned off.

[0044] As shown in Figure 7, during normal operation, the control unit 3 first determines whether or not it has detected a failure of the first power supply 10 (step S101). If the control unit 3 determines that it has not detected a failure of the first power supply 10 (step S101, No), it terminates the process and restarts the process from step S101.

[0045] Furthermore, if the control unit 3 determines that it has detected a failure of the first power supply 10 (step S101, Yes), it shuts off the inter-system switch 41 and conducts the battery switch 42 to perform fail-safe control (step S102). After that, the control unit 3 determines whether or not the failure of the first power supply 10 has been resolved (step S103).

[0046] If the control unit 3 determines that the failure of the first power supply 10 has not been resolved (step S103, No), it repeats the determination process in step S103 until the failure of the first power supply 10 is resolved. Then, if the control unit 3 determines that the failure of the first power supply 10 has been resolved (step S103, Yes), it starts recovery control and first turns off the third FET 63 (step S104).

[0047] Subsequently, the control unit 3 turns on the first FET 61 (step S105). Then, the control unit 3 turns off the fourth FET 64 (step S106). Then, the control unit 3 turns on the second FET 62 (step S107). As a result, the power control device 1 returns to its normal operating state. Therefore, the control unit 3 terminates processing and restarts processing from step S101.

[0048] [3. Variant examples of power supply control devices] Next, a modified power control device 1a according to the embodiment will be described with reference to Figures 8 and 9. Figure 8 is an explanatory diagram showing an example of the configuration of the power control device 1a according to the modified embodiment. Figure 9 is a timing chart showing the state of the power control device 1a according to the modified embodiment during recovery control.

[0049] Here, for components shown in Figure 8 that are the same as those shown in Figure 1, the same reference numerals as those shown in Figure 1 are used to omit redundant explanations. In the power control device 1 described earlier, when the battery switch 42 is turned from on to off during the recovery control, a surge may occur due to the impedance of the harness, potentially reducing the power supplied to the second load 102.

[0050] Therefore, as shown in Figure 8, the modified power control device 1a includes a switching control circuit 7 that controls the speed at which the battery switch 42 is turned off. When the control unit 3a performs recovery control, the switching control circuit 7 gradually turns the battery switch 42 from a conductive state to a disconnected state. In other words, the switching control circuit 7 reduces the switching speed of the battery switch 42, slowly turning the battery switch 42 from on to off.

[0051] As a result, the power control device 1a can prevent malfunctions of the second load 102 by suppressing the reduction in power supplied to the second load 102 due to surges caused by the switching of the battery switch 42.

[0052] The switching control circuit 7 includes a current detection circuit 71, an integration circuit 72, and a drive circuit 73. The current detection circuit 71 detects the current flowing through the second system 120. The integration circuit 72 integrates the detection result from the current detection circuit 71. The drive circuit 73 turns off the battery switch 42 at a switching speed corresponding to the integration result from the integration circuit 72.

[0053] Specifically, the current detection circuit 71 includes a resistor R1 connected between the second power supply 20 and the battery switch 42, and an operational amplifier A1 that amplifies the voltage difference across resistor R1 and outputs it to the integrating circuit 72.

[0054] The integrating circuit 72 includes an operational amplifier A2 and a capacitor C. The non-inverting input terminal (+) of operational amplifier A2 is connected to the output terminal of the current sensing circuit 71 via resistor R2. A voltage of, for example, 5V is applied to the inverting input terminal (-) of operational amplifier A2 via resistors R3 and R4.

[0055] Furthermore, the inverting input terminal (-) of op-amp A2 is connected to the drain of transistor T1 via resistors R3 and R5. The source of transistor T1 is connected to ground. The gate of transistor T1 is supplied with the slow-off start signal voltage from control unit 3 via resistor R6.

[0056] Capacitor C is connected between the inverting input terminal (-) of op-amp A2 and the output terminal of op-amp A2. The output terminal of op-amp A2 is connected to the base of transistor T2 via resistor R7. The emitter of transistor T2 is connected to ground. The collector of transistor T2 is connected to the input terminal of drive circuit 73.

[0057] The drive circuit 73 comprises two transistors T3 and T4 connected in series. Transistor T3 has its collector connected to its base via resistors R8 and R9, and its emitter connected to the gate of a fourth FET 64 included in the battery switch 42 via resistor R10. A gate drive voltage is applied to the collector of transistor T3.

[0058] Transistor T4 has its collector connected to the gate of the fourth FET 64, which is included in the battery switch 42, via resistor R11, and its emitter connected to ground. The gate drive voltage is applied to the bases of the two transistors T3 and T4 via resistors R8 and R9. In addition, the collector voltage of transistor T2 is applied to the bases of the two transistors T3 and T4 via resistor R9.

[0059] When performing recovery control, the control unit 3a turns off the third FET 63, then turns on the first FET 61 to start the operation of the switching control circuit 7, turns off the fourth FET 64 at a switching speed corresponding to the integration result of the integrating circuit 72, and then turns on the second FET 62. In this way, the control unit 3a can suppress the generation of surges by slowly turning off the fourth FET 64 with a simple circuit configuration.

[0060] Specifically, when the control unit 3a starts the recovery control, it turns off the third FET 63, then turns on the first FET 61, and switches the slow OFF start signal from Lo (low level) to Hi (high level) at time t1, for example, as shown in Figure 9. This causes the switching control circuit 7 to start operating (step S1).

[0061] At this time, since the fourth FET 64 is turned on, current flows from the second power supply 20 to the second load 102 in the second system 120. Therefore, the current detection circuit 71 outputs an output voltage to the integrating circuit 72 according to the detection result of the current flowing through the second system 120.

[0062] As a result, the output of the integrating circuit 72 slowly increases (step S2). Subsequently, as the output voltage of the integrating circuit 72 increases and transistor T2 gradually turns on, the output voltage of the drive circuit 73 gradually decreases, and the fourth FET 64 slowly turns off (step S3).

[0063] Then, the output voltage of the drive circuit 73 gradually decreases, and when it falls below the threshold Vth, the current flowing through the battery switch 42 also slowly decreases (step S4). As a result, the current flowing through the battery switch 42 decreases, and the output voltage of the current detection circuit 71 also decreases (step S5). Then, the current of the second system 120 decreases rapidly, and the rise in the output voltage of the integrating circuit 72 also becomes slower (step S6).

[0064] In this way, when the power control device 1a performs recovery control, it can suppress the occurrence of surges by slowly shutting off the battery switch 42, thereby preventing malfunctions of the second load 102 due to a decrease in the power supplied to the second load 102.

[0065] Furthermore, after executing the processes of steps S101 to S105 shown in Figure 7, the control unit 3a of the power control device 1a switches the slow OFF start signal from Lo to Hi instead of the process in step S106, and after the fourth FET 64 is turned off, it turns off the second FET 62. As a result, the control unit 3a can perform the recovery control according to the modified example described above.

[0066] Further effects and modifications can be readily derived by those skilled in the art. Therefore, broader aspects of the present invention are not limited to the specific details and representative embodiments expressed and described above. Accordingly, various modifications are possible without departing from the spirit or scope of the overall concept of the invention as defined by the appended claims and their equivalents. [Explanation of Symbols]

[0067] 1,1a Power supply control device 3,3a Control Unit 10 1st power supply 20 2nd power supply 41 Inter-system switches 42 Battery Switch 51, 52, 53, 54 Parasitic diodes 61 First FET 62 Second FET 63 The third FET 64. The fourth FET 7. Switching control circuit 71 Current detection circuit 72 Integral circuit 73 Drive Circuit 101 1st load 102 2nd load 110 1st system 120 2nd system 200 Ground fault A1, A2 operational amplifiers C Capacitor R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11 Resistor T1, T2, T3, T4 Transistors

Claims

1. A system switch that connects and disconnects a first system that supplies power from a first power source to a first load, and a second system that supplies power from a second power source to a second load, The second power supply and the battery switch for connecting and disconnecting the second system, The system includes a control unit that, upon detecting a failure of the first power supply, performs fail-safe control by shutting off the inter-system switch and conducting the battery switch to supply power from the second power supply to the second load, and performs recovery control by conducting the inter-system switch and shutting off the battery switch when the failure of the first power supply is resolved. The aforementioned inter-system switch and the battery switch include a circuit in which a pair of FETs (Field Effect Transistors) are connected in series, with the parasitic diodes facing in opposite directions. When performing the recovery control, the control unit turns off one of the FETs of the battery switch and turns on the other FET so that current flows from the second power supply to the second load via the parasitic diode, then turns off one of the FETs of the inter-system switch and turns on the other FET so that current flows from the first power supply to the second load via the parasitic diode, then turns off both of the FETs of the battery switch, and then turns on both of the FETs of the inter-system switch. Power supply control device.

2. The aforementioned inter-system switch is The circuit includes a first FET whose parasitic diode anode is on the second system side and a second FET whose parasitic diode anode is on the first system side, connected in series. The aforementioned battery switch is The circuit includes a third FET whose parasitic diode anode is on the second power supply side and a fourth FET whose parasitic diode anode is on the second load side, connected in series. The control unit, When performing the recovery control, the third FET is turned off, then the first FET is turned on, then the fourth FET is turned off, and then the second FET is turned on. The power control device according to claim 1.

3. The system includes a switching control circuit that controls the speed at which the battery switch is turned off. The power control device according to claim 2.

4. The aforementioned switching control circuit is A current detection circuit for detecting the current flowing through the second system, An integrating circuit that integrates the detection result of the current detection circuit, The circuit includes a drive circuit that turns off the battery switch at a switching speed corresponding to the integration result of the integration circuit, The power control device according to claim 3.

5. The control unit, When performing the recovery control, the third FET is turned off, then the first FET is turned on, then the switching control circuit is started, the fourth FET is turned off at a switching speed corresponding to the integration result of the integrating circuit, and then the second FET is turned on. The power control device according to claim 4.

6. The circuit includes a pair of FETs connected in series, with the parasitic diodes facing opposite directions, and an inter-system switch that connects and disconnects a first system that supplies power from a first power supply to a first load and a second system that supplies power from a second power supply to a second load. The circuit includes a pair of FETs connected in series, with the parasitic diodes facing opposite directions, and a battery switch for connecting and disconnecting the second power supply and the second system. The power control device includes a control unit which, upon detecting a failure of the first power supply, performs fail-safe control by shutting off the inter-system switch and conducting the battery switch to supply power from the second power supply to the second load, and when the failure of the first power supply is resolved, performs recovery control by conducting the inter-system switch and shutting off the battery switch, When performing the recovery control, one of the FETs of the battery switch is turned off and the other FET is turned on so that current flows from the second power supply to the second load via the parasitic diode, then one of the FETs of the inter-system switch is turned off and the other FET is turned on so that current flows from the first power supply to the second load via the parasitic diode, then both FETs of the battery switch are turned off, and then both FETs of the inter-system switch are turned on. Power control method.

Images