Indication device

Abstract

To provide a display device with a light-transmitting structure in which a light-receiving device on the rear side can normally receive light.SOLUTION: A display device includes: a substrate having a display area in which an image can be displayed and a non-display area outside the display area; a plurality of subpixels included in the display area and each including a plurality of light-emitting elements; and a plurality of data lines for supplying data signals for image display to the plurality of subpixels. The display area includes a first area capable of transmitting light and a second area located outside the first area. The second area includes an upper area located above the first area and a lower area located below the first area. The plurality of data lines include a first data line passing through all the upper area, the first area and the lower area, an upper data line arranged in the upper area, a lower data line arranged in the lower area, and a bypass line electrically connecting the upper data line and the lower data line and bypassing the first area.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] With the development of technology, in addition to an image display function, a display device can provide a photographing function and various sensing functions. For this purpose, the display device must include electronic devices (also referred to as light receiving devices or sensors) such as a camera and a sensing sensor.

[0003] Since the electronic device needs to receive light from the front of the display device, it must be installed at a position where light is received. Therefore, in a conventional display device, a camera (camera lens) and a sensing sensor have to be exposed on the front surface. As a result, the bezels of the display device become large, or there are significant constraints on the design of the display device.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present disclosure can provide a display device having a light transmission structure in which an electronic device that needs to receive light is not exposed on the front surface and the electronic device can normally receive light (for example, visible light, infrared light, or ultraviolet light).

[0005] Embodiments of the present disclosure can provide a display device that can improve the transmittance of an optical region (first region) through which light can pass.

[0006] Embodiments of the present disclosure can provide a display device having a structure that reduces the metal ratio in an optical region (first region) through which light can pass.

[0007] Embodiments of the present disclosure can provide a display device having a panel structure that can improve the sensing performance of a sensing sensor that uses light transmitted through an optical region (first region).

[0008] Embodiments of this disclosure can provide a display device having a panel structure that can improve the camera performance of a camera that uses light transmitted through an optical region (first region). [Means for solving the problem]

[0009] A display device according to an embodiment of the present disclosure may include a substrate comprising a display area capable of displaying an image and a non-display area outside the display area, a plurality of subpixels included in the display area, each comprising a plurality of light-emitting elements, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels.

[0010] The display area may include a first area that can transmit light and a second area located outside the first area.

[0011] The second region may include an upper region located above the first region and a lower region located below the first region. The upper region, the first region, and the lower region may be partitioned regions when viewed from above.

[0012] Multiple data lines may include a first data line that extends from the upper region through the first region to the lower region, an upper data line located in the upper region, a lower data line located in the lower region, and bypass wiring that electrically connects the upper and lower data lines and bypasses the first region.

[0013] The bypass wiring may include a first bypass wiring connected to the upper data line, a second bypass wiring connected to the lower data line, and a third bypass wiring connecting the first and second bypass wirings.

[0014] Bypass wiring can include lateral bypass wiring extending laterally and vertical bypass wiring extending vertically. The first and second bypass wiring may be lateral bypass wiring, and the third bypass wiring may be vertical bypass wiring.

[0015] Lateral bypass wiring may be arranged on a first metal layer, while longitudinal bypass wiring may be arranged on a second metal layer different from the first metal layer.

[0016] Multiple light-emitting elements may each contain multiple pixel electrodes.

[0017] The multiple pixel electrodes may include a first pixel electrode located in the upper region and contained within a first subpixel, a second pixel electrode located in the upper region and contained within a second subpixel, a third pixel electrode located in the first region and contained within a third subpixel, a fourth pixel electrode located in the first region and contained within a fourth subpixel, a fifth pixel electrode located in the lower region and contained within a fifth subpixel, and a sixth pixel electrode located in the lower region and contained within a sixth subpixel.

[0018] The first data line can be connected to the first subpixel, the third subpixel, and the fifth subpixel.

[0019] The upper data line can be connected to the second subpixel.

[0020] The lower data line can be connected to the sixth subpixel.

[0021] In the display device according to the embodiment of this disclosure, the third pixel electrode and the fourth pixel electrode can be electrically connected.

[0022] The emission colors of the first, second, third, fourth, fifth, and sixth subpixels may be the same.

[0023] Each of the first subpixel, the second subpixel, the third subpixel, the fifth subpixel, and the sixth subpixel may include a light-emitting element and a subpixel circuit that drives the light-emitting element. The subpixel circuit may include two or more transistors.

[0024] The fourth subpixel includes a light-emitting element, but may not include a subpixel circuit. In this case, the light-emitting element of the fourth subpixel can be driven by the subpixel circuit of the third subpixel.

[0025] The drive current output from the subpixel circuit of the third subpixel can be supplied to the third pixel electrode and the fourth pixel electrode.

[0026] The display device according to an embodiment of the present disclosure may be disposed in the first region and further include a connection wiring that electrically connects the third pixel electrode and the fourth pixel electrode.

[0027] The third pixel electrode, the connection wiring, and the fourth pixel electrode can be integrally configured.

[0028] The plurality of pixel electrodes may be disposed in the upper region and further include a seventh pixel electrode included in the seventh subpixel, an eighth pixel electrode included in the eighth subpixel disposed in the second region, and a ninth pixel electrode included in the ninth subpixel disposed in the lower region.

[0029] The plurality of data lines may further include a second data line connected to the seventh subpixel, the eighth subpixel, and the ninth subpixel.

[0030] The emission colors of the seventh subpixel, the eighth subpixel, and the ninth subpixel may be different from the emission colors of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel, and the sixth subpixel.

[0031] The second data line can intersect and superimpose the portion where the third and fourth pixel electrodes are connected (i.e., the connection wiring).

[0032] As an example, in the first and second regions, the first data line and the second data line may be located within the same metal layer and spaced apart on the same plane.

[0033] In another example, in the second region, the first data line and the second data line may be located within the same metal layer. In at least a portion of the first region, the first data line and the second data line may be located within different metal layers.

[0034] For example, in the second region, the first data line and the second data line may be located within the same metal layer and spaced apart from each other on the same plane. The first region may include a transparent region and an opaque region. In the transparent region, the first data line and the second data line may be located within different metal layers and overlap vertically. In the opaque region, the first data line and the second data line may be located within the same metal layer and spaced apart from each other on the same plane.

[0035] The display device according to the embodiments of the present disclosure may further include an electronic device located below the substrate, overlapping with the first region, and performing a predetermined operation using light transmitted through the first region.

[0036] A display device according to an embodiment of the present disclosure may include a substrate having a display area capable of displaying an image and a non-display area outside the display area, a plurality of subpixels included in the display area and each having a plurality of pixel electrodes, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels.

[0037] The display area may include a first area that can transmit light and a second area located outside the first area.

[0038] The second region may include an upper region located above the first region and a lower region located below the first region.

[0039] The multiple pixel electrodes may include a first pixel electrode located in the upper region and contained within a first subpixel, a second pixel electrode located in the upper region and contained within a second subpixel, a third pixel electrode located in the first region and contained within a third subpixel, a fourth pixel electrode located in the first region and contained within a fourth subpixel, a fifth pixel electrode located in the lower region and contained within a fifth subpixel, and a sixth pixel electrode located in the lower region and contained within a sixth subpixel.

[0040] Multiple data lines may include a first data line that extends from the upper region through the first region to the lower region and connects to the first, third, and fifth subpixels; an upper data line located in the upper region and connected to the second subpixel; and a lower data line located in the lower region and connected to the sixth subpixel.

[0041] The third pixel electrode and the fourth pixel electrode can be electrically connected.

[0042] The display device according to the embodiments of the present disclosure may further include connecting wiring arranged in a first region and electrically connecting a third pixel electrode and a fourth pixel electrode.

[0043] According to embodiments of this specification, it is possible to provide a display device having a light-transmitting structure that allows an electronic device to receive light (e.g., visible light, infrared light, or ultraviolet light) to be received normally without the electronic device being fully exposed.

[0044] According to embodiments of this disclosure, a display device can be provided that can improve the transmittance of an optical region (first region) through which light can pass.

[0045] According to embodiments of this disclosure, a display device can be provided that has a structure for reducing the metal ratio in an optical region (first region) through which light can pass.

[0046] According to embodiments of this disclosure, it is possible to provide a display device having a panel structure that can improve the sensing performance of a sensing sensor that uses light transmitted through an optical region (first region).

[0047] According to embodiments of this disclosure, it is possible to provide a display device having a panel structure that can improve the camera performance of a camera that uses light transmitted through an optical region (first region).

[0048] The effects described herein are not limited to those stated above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. [Brief explanation of the drawing]

[0049] [Figure 1a] This disclosure shows a display device according to an embodiment of this disclosure. [Figure 1b] This disclosure shows a display device according to an embodiment of this disclosure. [Figure 1c] This disclosure shows a display device according to an embodiment of this disclosure. [Figure 2] This is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 3] A display panel according to an embodiment of this disclosure is shown. [Figure 4] In the display panel according to the embodiment of this disclosure, a general area, a first optical area, and a second optical area are shown. [Figure 5] The signal lines arranged on the display panel according to an embodiment of this disclosure are shown. [Figure 6] This is a plan view of the optical region of a display panel according to an embodiment of the present disclosure. [Figure 7] This is a plan view of the optical region of a display panel according to an embodiment of the present disclosure. [Figure 8] This is a cross-sectional view of a portion of the optical region of a display panel according to an embodiment of the present disclosure. [Figure 9] This is a cross-sectional view of a portion of the optical region of a display panel according to an embodiment of the present disclosure. [Figure 10] This shows the signal intensity during reception processing for light passing through the optical region of the display panel according to the embodiments of this disclosure. [Figure 11] This is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 12] This is a cross-sectional view of a portion of the optical region of a display panel according to an embodiment of the present disclosure. [Figure 13] This is a cross-sectional view of a portion of the optical region of a display panel according to an embodiment of the present disclosure. [Figure 14] These are cross-sectional views of parts of Figures 12 and 13. [Figure 15] These are cross-sectional views of parts of Figures 12 and 13. [Figure 16] These are cross-sectional views of parts of Figures 12 and 13. [Figure 17] These are cross-sectional views of parts of Figures 12 and 13. [Figure 18] These are cross-sectional views of parts of Figures 12 and 13. [Figure 19] This is a cross-sectional view of the connection area between the vertical bypass wiring and the horizontal bypass wiring in a display panel according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0050] Some embodiments of this disclosure will be described in detail below with reference to illustrative drawings. In assigning reference numerals to components in each drawing, the same reference numerals may be used for identical components, even if they appear in other drawings, whenever possible. In describing the present invention, if a specific description of a relevant known configuration or function is deemed to obscure the gist of this disclosure, such detailed description will be omitted. Where "includes," "has," "consists of," etc., as used herein, other parts may be added unless "only" is used. When a component is expressed singly, it may include multiple components unless otherwise explicitly stated.

[0051] Furthermore, in describing the components of this disclosure, terms such as 1st, 2nd, A, B, (a), (b), etc., may be used. These terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of such components.

[0052] In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in one or more of the two or more components that are “linked,” “joined,” or “connected” to each other.

[0053] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0054] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0055] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings. Figures 1a, 1b, and 1c show a display device 100 according to an embodiment of this disclosure.

[0056] Referring to Figures 1a, 1b, and 1c, the display device 100 according to the embodiment of the present disclosure may include a display panel 110 for displaying an image and one or more electronic devices 11, 12.

[0057] The display panel 110 may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. Multiple subpixels and various signal lines for driving multiple subpixels may be arranged in the display area. The non-display area NDA may be an area outside the display area DA. Various signal lines may be arranged in the non-display area NDA, and various drive circuits may be connected to the non-display area NDA. The non-display area NDA may be bent so as not to be visible from the front, or covered by a case (not shown). The non-display area NDA is also called a bezel or bezel area.

[0058] The display device 100 according to the embodiments of this disclosure may include one or more electronic devices 11, 12 located below the display panel 110 (on the opposite side of the viewing surface). Here, one or more electronic devices 11, 12 may be provided separately from the display panel 110.

[0059] One or more electronic devices 11, 12 may be devices that receive light transmitted through the display panel 110 and perform predetermined functions using the received light.

[0060] For example, one or more electronic devices 11, 12 may include one or more imaging devices such as cameras (image sensors), proximity sensors, and sensing sensors such as illuminance sensors. Here, for example, the sensing sensor may be an infrared sensor.

[0061] Light necessary for the operation of one or more electronic devices 11, 12 can enter the front (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to one or more electronic devices 11, 12 located at the bottom of the display panel 110 (opposite the viewing surface). For example, the light necessary for the operation of one or more electronic devices 11, 12 and that passes through the display panel 110 may include one or more of the following: visible light, infrared light, ultraviolet light, etc.

[0062] Referring to Figures 1a, 1b, and 1c, in the display panel 110 according to an embodiment of the present disclosure, the display area DA may include a general area NA and one or more optical areas OA1, OA2. The one or more optical areas OA1, OA2 may be areas that overlap with one or more optical electronic devices 11, 12.

[0063] As illustrated in Figure 1a, the display area DA may include a general area NA and a first optical area OA1. Here, at least a portion of the first optical area OA1 can be superimposed on the first optical electronic device 11.

[0064] As illustrated in Figure 1b, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of Figure 1b, a general area NA may exist between the first optical area OA1 and the second optical area OA2. Here, at least a portion of the first optical area OA1 may overlap with the first electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second electronic device 12.

[0065] As illustrated in Figure 1c, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example in Figure 1c, there is no general area NA between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 are in contact with each other. Here, at least a portion of the first optical area OA1 may overlap with the first electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optical electronic device 12.

[0066] One or more optical regions OA1, OA2 must have both an image display structure and a light transmission structure. That is, since one or more optical regions OA1, OA2 are part of the display region DA, one or more optical regions OA1, OA2 must have light-emitting regions of subpixels for image display. Furthermore, one or more optical regions OA1, OA2 must have a light transmission structure formed to allow light to pass through one or more electronic devices 11, 12.

[0067] One or more electronic devices 11, 12 are located behind (below, opposite the viewing surface) the display panel 110 and receive light that has passed through the display panel 110.

[0068] One or more optical electronic devices 11, 12 are not exposed on the front (viewing surface) of the display panel 110. Therefore, when the user looks at the front of the display device 100, the electronic devices 11, 12 are not visible to the user.

[0069] For example, the first electronic device 11 may be a camera that receives light in the visible light wavelength range (visible light), and the second electronic device 12 may be a sensing sensor such as a proximity sensor or an illuminance sensor. For example, the sensing sensor may be an infrared sensor that senses light in the infrared wavelength range (infrared light). Conversely, the first electronic device 11 may be a sensing sensor and the second electronic device 12 may be a camera.

[0070] For the sake of explanation, the following explanation will use the example that the first electronic device 11 is a camera and the second electronic device 12 is an infrared-based sensing sensor. Here, the camera may be a camera lens or an image sensor.

[0071] If the first electronic device 11 is a camera, this camera is located behind (below) the display panel 110, but it may also be a front camera that photographs the front of the display panel 110. Therefore, the user can take a picture (selfie) while looking at the viewing surface of the display panel 110, via a camera that is not visible on the viewing surface.

[0072] The general region NA and one or more optical regions OA1 and OA2 included in the display region DA may be regions where an image can be displayed. However, the general region NA is a region where a light-transmitting structure does not need to be formed, while one or more optical regions OA1 and OA2 may be regions where a light-transmitting structure should be formed.

[0073] Therefore, one or more optical regions OA1, OA2 should have a transmittance above a certain level, while the general region NA may have no light transmittance or a low transmittance below a certain level.

[0074] For example, one or more optical regions OA1, OA2 and the general region NA may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure.

[0075] For example, the number of subpixels per unit area in one or more optical regions OA1 and OA2 may be less than the number of subpixels per unit area in the general region NA. That is, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the general region NA. Here, the number of subpixels per unit area may have the same meaning as resolution, pixel density, or pixel integration. For example, the unit of the number of subpixels per unit area can also be expressed as PPI (Pixels Per Inch), which means the number of pixels in one inch.

[0076] For example, the number of subpixels per unit area in the first optical region OA1 may be less than the number of subpixels per unit area in the general region NA. The number of subpixels per unit area in the second optical region OA2 may be greater than or equal to the number of subpixels per unit area in the first optical region OA1, but less than the number of subpixels per unit area in the general region NA.

[0077] On the other hand, as one method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, the pixel density difference design method can be applied, as described above. According to the pixel density difference design method, the display panel 110 can be designed such that the number of subpixels per unit area of ​​at least one of the first optical region OA1 and the second optical region OA2 is less than the number of subpixels per unit area of ​​the general region NA.

[0078] However, in some cases, a different approach can be taken to increase the transmittance of at least one of the first optical region OA1 and the second optical region OA2, by applying a pixel size difference design method. According to the pixel size difference design method, the display panel 110 can be designed such that the number of subpixels per unit area in at least one of the first optical region OA1 and the second optical region OA2 is the same as or similar to the number of subpixels per unit area in the general region NA, but the size of each subpixel SP (i.e., the light-emitting region size) located in at least one of the first optical region OA1 and the second optical region OA2 is smaller than the size of each subpixel SP (i.e., the light-emitting region size) located in the general region NA.

[0079] For the sake of explanation, the following description assumes that the pixel density difference design method is applied, out of two methods (pixel density difference design method and pixel size difference design method) for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2. Therefore, in the following, a small number of subpixels per unit area may correspond to a small subpixel size, and a large number of subpixels per unit area may correspond to a large subpixel size.

[0080] The first optical region OA1 can have various shapes, such as a circle, ellipse, square, hexagon, or octagon. The second optical region OA2 can have various shapes, such as a circle, ellipse, square, hexagon, or octagon. The first optical region OA1 and the second optical region OA2 may have the same shape or different shapes.

[0081] Referring to Figure 1c, when the first optical region OA1 and the second optical region OA2 are in contact, the entire optical region including the first optical region OA1 and the second optical region OA2 can have various shapes, such as circular, elliptical, square, hexagonal, or octagonal. For the sake of explanation, in the following, we will use the example that the first optical region OA1 and the second optical region OA2 are both circular.

[0082] In the display device 100 according to the embodiment of this disclosure, if the first electronic device 11, which is not exposed to the outside and is hidden at the bottom of the display panel 110, is a camera, then the display device 100 according to the embodiment of this disclosure can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0083] According to this, in the case of the display device 100 according to the embodiment of the present disclosure, a notch or camera hole for camera exposure does not need to be formed in the display panel 110, so there is no reduction in the area of ​​the display area DA. As a result, a notch or camera hole for camera exposure does not need to be formed in the display panel 110, so the size of the bezel area can be reduced, eliminating design constraints and potentially increasing the degree of freedom in design.

[0084] In the display device 100 according to the embodiments of this disclosure, even though one or more electronic devices 11, 12 are hidden behind the display panel 110, one or more electronic devices 11, 12 must be able to receive light normally and perform predetermined functions normally.

[0085] Furthermore, in the display device 100 according to the embodiment of this disclosure, even though one or more electronic devices 11, 12 are arranged hidden behind the display panel 110 and overlapping with the display area DA, normal image display must be possible in one or more optical areas OA1, OA2 that overlap with the one or more electronic devices 11, 12 within the display area DA.

[0086] As the aforementioned first optical region OA1 is designed as a transmissive region, the image display characteristics in the first optical region OA1 may differ from those in the general region NA.

[0087] Furthermore, if the design of the first optical region OA1 is modified to improve image display characteristics, the transmittance of the first optical region OA1 may decrease.

[0088] Accordingly, embodiments of this disclosure present a structure for a first optical region OA1 that can prevent variations in image quality between the first optical region OA1 and the general region NA, and can improve transmittance in the first optical region OA1.

[0089] Furthermore, the embodiments of this disclosure present a structure for a second optical region OA2 that can improve image quality and transmittance in the second optical region OA2, not only for the first optical region OA1 but also for the second optical region OA2.

[0090] In the display device 100 according to the embodiment of this disclosure, the first optical region OA1 and the second optical region OA2 are similar in that they are regions through which light can be transmitted, but their applications may differ.

[0091] Therefore, in the display device 100 according to the embodiment of the present disclosure, the structure of the first optical region OA1 and the structure of the second optical region OA2 are basically similar or identical, but the resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure may differ from each other.

[0092] Figure 2 is a system configuration diagram of the display device 100 according to an embodiment of the present disclosure.

[0093] Referring to Figure 2, the display device 100 is a component for displaying an image and may include a display panel 110 and a display driving circuit. The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 220, a gate driving circuit 230, and a display controller 240, etc.

[0094] The display panel 110 may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. The non-display area NDA may be the outer area of ​​the display area DA, or it may also be called the bezel area. All or part of the non-display area NDA may be an area visible from the front of the display device 100, or an area that is bent and not visible from the front of the display device 100.

[0095] The display panel 110 may include a substrate SUB and a plurality of subpixels SP arranged on the substrate SUB. Furthermore, the display panel 110 may further include various types of signal lines to drive the plurality of subpixels SP.

[0096] The display device 100 according to the embodiments of this disclosure may be a liquid crystal display device or the like, or it may be a self-emissive display device in which the display panel 110 emits light itself. When the display device 100 according to the embodiments of this disclosure is a self-emissive display device, each of the plurality of subpixels SP may include an element-emitting element. For example, the display device 100 according to the embodiments of this disclosure may be an organic light-emitting display device in which the element-emitting element is realized by an organic light-emitting diode (OLED). As another example, the display device 100 according to the embodiments of this disclosure may be an inorganic light-emitting display device in which the element-emitting element is realized by an inorganic-based light-emitting diode. As yet another example, the display device 100 according to the embodiments of this disclosure may be a quantum dot display device in which the element-emitting element is realized by a quantum dot, which is a semiconductor crystal that emits light itself.

[0097] The structure of each of the multiple subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display device that emits light from the subpixels SP itself, each subpixel SP may include a light-emitting element that emits light itself, one or more transistors, and one or more capacitors.

[0098] For example, some types of signal lines may include multiple data lines DL that transmit data signals (also called data voltages or image signals) and multiple gate lines GL that transmit gate signals (also called scan signals).

[0099] Multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple data lines DL can be arranged extending in a first direction. Each of the multiple gate lines GL can be arranged extending in a second direction. Here, the first direction may be the column direction and the second direction may be the row direction. Alternatively, the first direction may be the row direction and the second direction may be the column direction. For the sake of explanation, the following example will assume that each of the multiple data lines DL is arranged in the column direction and each of the multiple gate lines GL is arranged in the row direction.

[0100] The data drive circuit 220 is a circuit for driving multiple data lines DL and can output data signals to multiple data lines DL. The gate drive circuit 230 is a circuit for driving multiple gate lines GL and can output gate signals to multiple gate lines GL.

[0101] The display controller 240 is a device for controlling the data drive circuit 220 and the gate drive circuit 230, and can control the drive timing for multiple data lines DL and the drive timing for multiple gate lines GL.

[0102] The display controller 240 can supply a data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and can supply a gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0103] The display controller 240 can receive input image data from the host system 250 and supply image data (Data) to the data drive circuit 220 based on the input image data.

[0104] The data drive circuit 220 receives digital image data (Data) from the display controller 240, converts the received image data (Data) into analog data signals, and outputs them to multiple data lines DL.

[0105] The gate drive circuit 230 is supplied with various gate drive control signals GCS, a first gate voltage corresponding to the turn-on level voltage, and a second gate voltage corresponding to the turn-off level voltage, generates a gate signal, and can supply the generated gate signal to multiple gate lines GL.

[0106] For example, the data drive circuit 220 may be connected to the display panel 110 by tape automated bonding (TAB), connected to the bonding pad of the display panel 110 by chip-on-glass (COG) or chip-on-panel (COP) methods, or implemented by chip-on-film (COF) methods and connected to the display panel 110.

[0107] The gate drive circuit 230 can be connected to the display panel 110 by tape automated bonding (TAB), by a chip-on-glass (COG) or chip-on-panel (COP) method to the bonding pad of the display panel 110, or by a chip-on-film (COF) method. Alternatively, the gate drive circuit 230 may be a gate-in-panel (GIP) type and formed in the non-display area (NDA) of the display panel 110. The gate drive circuit 230 may be placed on the substrate or connected to the substrate. That is, in the case of the GIP type, the gate drive circuit 230 can be placed in the non-display area (NDA) of the substrate. In the case of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., the gate drive circuit 230 can be connected to the substrate.

[0108] On the other hand, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed in the display area DA of the display panel 110. For example, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed so as not to overlap with the subpixel SP, or it may be placed so as to partially or entirely overlap with the subpixel SP.

[0109] The data drive circuit 220 may be connected to one side of the display panel 110 (for example, the top or bottom). Depending on the drive method, panel design method, etc., the data drive circuit 220 may be connected to both sides of the display panel 110 (for example, the top and bottom), or to two or more of the four sides of the display panel 110.

[0110] The gate drive circuit 230 may be connected to one side of the display panel 110 (for example, the left or right side). Depending on the drive method, panel design method, etc., the gate drive circuit 230 may be connected to both sides of the display panel 110 (for example, the left and right sides), or to two or more of the four sides of the display panel 110.

[0111] The display controller 240 can be implemented as a separate component from the data drive circuit 220, or it can be implemented as an integrated circuit by integrating it with the data drive circuit 220.

[0112] The display controller 240 may be a timing controller used in conventional display technology, a control device that can perform other control functions in addition to the timing controller, a control device different from the timing controller, or a circuit within the control device. The display controller 240 can be implemented as various circuits or electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0113] The display controller 240 can be mounted on a printed circuit board, a flexible printed circuit board, etc., and can be electrically connected to the data drive circuit 220 and the gate drive circuit 230 via the printed circuit board, flexible printed circuit board, etc.

[0114] The display controller 240 can send and receive signals with the data drive circuit 220 according to one or more predetermined interfaces. For example, the interfaces may include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Clock Point-Point Interface) interface, or an SPI (Serial Peripheral Interface).

[0115] The display device 100 according to the embodiments of this disclosure may include, in addition to an image display function, a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or pen, or to detect the touch position, in order to further provide a touch sensing function.

[0116] The touch sensing circuit may include a touch drive circuit 260 that drives and senses a touch sensor and generates and outputs touch sensing data, and a touch controller 270 that can detect a touch or determine the touch position using the touch sensing data.

[0117] The touch sensor may include multiple touch electrodes. The touch sensor may further include multiple touch lines for electrically connecting the multiple touch electrodes to the touch drive circuit 260.

[0118] The touch sensor may be located outside the display panel 110 in the form of a touch panel, or it may be located inside the display panel 110. When the touch sensor is located outside the display panel 110 in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 110 can be manufactured separately and joined together during the assembly process. An external type touch panel may include a touch panel substrate and multiple touch electrodes on the touch panel substrate.

[0119] If the touch sensor is located inside the display panel 110, it may be formed on the substrate SUB during the manufacturing process of the display panel 110, along with signal lines and electrodes related to display driving.

[0120] The touch drive circuit 260 can supply a touch drive signal to at least one of the multiple touch electrodes, sense at least one of the multiple touch electrodes, and generate touch sensing data.

[0121] The touch sensing circuit can perform touch sensing using either a self-capacitance sensing method or a mutual-capacitance sensing method.

[0122] When a touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., finger, pen, etc.). According to the self-capacitance sensing method, each of the multiple touch electrodes can act as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or some of the multiple touch electrodes and sense all or some of the multiple touch electrodes.

[0123] When a touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between touch electrodes. According to the mutual capacitance sensing method, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0124] The touch drive circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented as separate devices or as a single device. Furthermore, the touch drive circuit 260 and the data drive circuit 220 may be implemented as separate devices or as a single device.

[0125] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or touch sensing circuit.

[0126] The display device 100 according to the embodiments of this disclosure may be a mobile terminal such as a smartphone or tablet, or it may be a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display of various types and sizes capable of displaying information or images.

[0127] As described above, the display area DA in the display panel 110 may include a general area NA and one or more optical areas OA1, OA2. The general area NA and one or more optical areas OA1, OA2 are areas on which an image can be displayed. However, the general area NA is an area on which a light-transmitting structure does not need to be formed, while the one or more optical areas OA1, OA2 are areas on which a light-transmitting structure should be formed.

[0128] As mentioned above, in the display panel 110, the display area DA may include one or more optical areas OA1 and OA2 along with the general area NA. However, for the sake of explanation, we will assume that the display area DA includes both the first optical area OA1 and the second optical area OA2 (Figures 1b and 1c).

[0129] Figure 3 shows a display panel 110 according to an embodiment of the present disclosure.

[0130] Referring to Figure 3, multiple subpixels SP may be arranged in the display area DA of the display panel 110. The multiple subpixels SP may be arranged in the general area NA, the first optical area OA1, and the second optical area OA2, which are included in the display area DA.

[0131] Referring to Figure 3, each of the multiple subpixels SP may include a light-emitting element ED and a pixel circuit SPC configured to drive the light-emitting element ED.

[0132] Referring to Figure 3, the subpixel circuit SPC may include a drive transistor DT for driving the light-emitting element ED, a scan transistor ST for transmitting the data voltage VDATA to the drive transistor DT, and a storage capacitor Cst for maintaining a constant voltage for one frame.

[0133] The drive transistor DT may include a first node N1, a second node N2, and a third node N3.

[0134] The first node N1 can be electrically connected to the light-emitting element ED. The second node N2 may be connected to the scan transistor ST. The third node N3 can be connected to the drive voltage line VDDL.

[0135] The first node N1 can be electrically connected to the pixel electrode PE of the light-emitting element ED. A data voltage VDATA can be applied to the second node N2. A drive voltage VDD can be applied to the third node N3.

[0136] The first node N1 is either a source node or a drain node, the second node N2 is a gate node, and the third node N3 can be either a drain node or a source node. For the sake of explanation, the following example will be given where, in a drive transistor DT, the first node N1 is a source node, the second node N2 is a gate node, and the third node N3 is a drain node.

[0137] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0138] The pixel electrode PE may be an electrode placed on each subpixel SP. For example, the pixel electrode PE can be electrically connected directly or indirectly (via another transistor) to the first node N1 of the driving transistor DT of each subpixel SP.

[0139] The common electrode CE may be an electrode commonly placed across multiple subpixels SP. For example, the common electrode CE can be electrically connected to a base voltage line VSSL. A base voltage VSS, which is a type of common drive voltage, can be applied to the common electrode CE via the base voltage line VSSL.

[0140] For example, the pixel electrode PE may be the anode electrode, and the common electrode CE may be the cathode electrode. Conversely, the pixel electrode PE may be the cathode electrode, and the common electrode CE may be the anode electrode. In the following explanation, for the sake of clarity, we will assume that the pixel electrode PE is the anode electrode and the common electrode CE is the cathode electrode.

[0141] The intermediate layer EL may include the light-emitting layer EML and the common intermediate layer EL_COM.

[0142] The light-emitting layer (EML) may, for example, be placed in each of several subpixels (SP), or, for example, be placed in common across several subpixels (SP). The common intermediate layer (EL_COM) can be placed in common across several subpixels (SP).

[0143] The emissive layer EML can be placed in each emissive region EA, and the common intermediate layer EL_COM can be placed in common across multiple emissive regions EA and non-emissive regions.

[0144] The common intermediate layer EL_COM may include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 is located between the pixel electrode PE and the light-emitting layer EML and may include at least one layer (e.g., an organic layer). The second common intermediate layer COM2 is located between the light-emitting layer EML and the common electrode CE and may include at least one layer (e.g., an organic layer).

[0145] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL) and a hole transfer layer (HTL). The second common intermediate layer COM2 may include an electron transfer layer (ETL) and an electron injection layer (EIL).

[0146] The hole injection layer injects holes from the pixel electrode PE into the hole transport layer, the hole transport layer transports the holes to the light-emitting layer EML, the electron injection layer injects electrons from the common electrode CE into the electron transport layer, and the electron transport layer transports the electrons to the light-emitting layer EML.

[0147] Each light-emitting element ED can be composed of the overlapping portion of the pixel electrode PE, the light-emitting layer EML within the intermediate layer EL, and the common electrode CE. Each light-emitting element ED can form a predetermined light-emitting region EA. For example, the light-emitting region EA can be defined as the region where the pixel electrode PE, the light-emitting layer EML of the intermediate layer EL, and the common electrode CE overlap.

[0148] For example, the light-emitting element ED may be an organic-based organic light-emitting diode (OLED), an inorganic-based inorganic light-emitting diode, or a quantum dot light-emitting element. If the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL in the light-emitting element ED may include an organic layer containing organic material.

[0149] The scan transistor ST is controlled to turn on and off by a scan signal SC, which is a type of gate signal applied via a scan signal line SCL, which is a type of gate line GL, and can be electrically connected between the second node N2 of the drive transistor DT and the data line DL.

[0150] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the drive transistor DT.

[0151] The subpixel circuit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DT and ST and one capacitor Cst, as shown in Figure 3, and may optionally include one or more transistors or one or more capacitors.

[0152] The storage capacitor Cst may be an intentionally designed external capacitor located outside the drive transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that may exist between the first node N1 and the second node N2 of the drive transistor DT. The drive transistor DT and the scan transistor ST may each be either an n-type or p-type transistor.

[0153] Since the circuit elements within each subpixel SP (particularly the light-emitting elements ED, which are realized with organic light-emitting diodes (OLEDs) containing organic materials) are vulnerable to external moisture and oxygen, a sealing layer ENCAP may be placed on the display panel 110 to prevent external moisture and oxygen from penetrating the circuit elements (particularly the light-emitting elements ED). The sealing layer ENCAP can be placed in a manner that covers the light-emitting elements ED.

[0154] Referring to Figure 3, the display device 100 according to an embodiment of the present disclosure may include a touch sensor layer TSL including a plurality of sensor electrodes for sensing a user's touch, a touch drive circuit 260 configured to sense the plurality of sensor electrodes, and a touch controller 270 configured to determine the presence or absence of a touch or the touch coordinates using the sensing results (touch sensing data) of the touch drive circuit 260.

[0155] The touch sensor layer TSL may be integrated into the display panel 110. For example, the touch sensor layer TSL can be placed on the sealing layer ENCAP within the display panel 110.

[0156] The display panel 110 may further include a plurality of touch routing wires for electrically connecting a plurality of touchpads TP to which the touch driving circuit 260 is electrically connected, and a plurality of sensor electrodes included in the touch sensor layer TSL, to the plurality of touchpads TP to which the touch driving circuit 260 is connected.

[0157] Figure 4 shows a display panel 110 according to an embodiment of the present disclosure, including a general area NA, a first optical area OA1, and a second optical area OA2.

[0158] Referring to Figure 4, the display panel 110 according to the embodiment of the present disclosure may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. The display area DA may include a first optical area OA1, a second optical area OA2, and a general area NA.

[0159] Since the first optical region OA1, the second optical region OA2, and the general region NA are included in the display region DA, a display structure can be formed. For example, each of the first optical region OA1, the second optical region OA2, and the general region NA may contain multiple light-emitting regions EA.

[0160] Furthermore, the first optical region OA1 and the second optical region OA2 are regions through which light can be transmitted, while the general region NA may be a region through which light cannot be transmitted or through which light can be transmitted to a very small extent. The general region NA can mean a region through which light cannot be transmitted, excluding the first optical region OA1 and the second optical region OA2. Here, light transmission may mean that light passes between the front and back surfaces of the display panel 110.

[0161] The first optical region OA1 may overlap with the first electronic device 11. The second optical region OA2 may overlap with the second electronic device 12.

[0162] The first optical region OA1 and the second optical region OA2 may each have a light-transmitting structure. However, the first optical region OA1 and the second optical region OA2 may have different structural characteristics. For example, the transmittance of the first optical region OA1 may be higher than that of the second optical region OA2. The resolution or the number of subpixels per unit area of ​​the first optical region OA1 may be less than that of the second optical region OA2.

[0163] The first electronic device 11 can perform a defined operation using light in a first wavelength band from among the light transmitted through the first optical region OA1. The second electronic device 12 can perform a defined operation using light in a second wavelength band different from the first wavelength band from among the light transmitted through the second optical region OA2.

[0164] The first wavelength band may include one or more wavelength bands from among the visible light wavelength band, the infrared wavelength band, the ultraviolet wavelength band, etc. The second wavelength band may include one or more wavelength bands from among the visible light wavelength band, the infrared wavelength band, and the ultraviolet wavelength band, etc., but may be different from the first wavelength band.

[0165] For example, the first electronic device 11 may be a camera, and the second electronic device 12 may be a sensing sensor. The first electronic device 11 can perform camera operations using light in the visible light wavelength band corresponding to a first wavelength band among the light transmitted through the first optical region OA1. The second electronic device 12 can perform sensing operations using light in the infrared wavelength band corresponding to a second wavelength band among the light transmitted through the second optical region OA2.

[0166] Referring to Figure 4, the first optical region OA1 and the second optical region OA2 can each be circular or octagonal, etc. However, they are not limited to these, and the first optical region OA1 and the second optical region OA2 can each have various shapes such as elliptical, polygonal, or irregular shapes.

[0167] The first optical region OA1 and the second optical region OA2 may have the same shape. Alternatively, the first optical region OA1 and the second optical region OA2 may have different shapes.

[0168] Referring to Figure 4, the display area DA can include multiple light-emitting areas EA. Since the general area NA, the first optical area OA1, and the second optical area OA2 are areas included in the display area DA, each of the general area NA, the first optical area OA1, and the second optical area OA2 can include multiple light-emitting areas EA.

[0169] Multiple light-emitting regions EA may include light-emitting regions that emit three or more colors of light. For example, multiple light-emitting regions EA may include a first-color light-emitting region that emits a first color of light, a second-color light-emitting region that emits a second color of light, and a third-color light-emitting region that emits a third color of light.

[0170] For example, if the first color of light is red, the second color of light is green, and the third color of light is blue, the first color light emission region is sometimes called the red light emission region EA_R, the second color light emission region is sometimes called the green light emission region EA_G, and the third color light emission region is sometimes called the blue light emission region EA_B.

[0171] The red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B may have the same size (light-emitting area size). Alternatively, at least one of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B may have a different size (light-emitting area size) from the rest.

[0172] As mentioned above, the first, second, and third colors may be various different colors, for example, the first, second, and third colors may include red, green, and blue. For the sake of explanation, the following example will use the case where the first color is red, the second color is green, and the third color is blue. However, it is not limited to this.

[0173] If the first color is red, the second color is green, and the third color is blue, then the size of the blue emission region EA_B (luminescence area size) may be the largest among the sizes of the red emission region EA_R, the green emission region EA_G, and the blue emission region EA_B (luminescence area size).

[0174] A light-emitting element ED located in the red light-emitting region EA_R may include a light-emitting layer EL that emits red light. A light-emitting element ED located in the green light-emitting region EA_G may include a light-emitting layer EL that emits green light. A light-emitting element ED located in the blue light-emitting region EA_B may include a light-emitting layer EL that emits blue light.

[0175] Of the light-emitting layers EL that emit red light, green light, and blue light, the organic material contained in the blue light-emitting layer EL may be the most susceptible to material degradation. As a result, by designing the blue light-emitting region EA_B to be the largest, the current density supplied to the light-emitting element ED located in the blue light-emitting region EA_B may be the lowest. Therefore, the degree of degradation of the light-emitting element ED located in the blue light-emitting region EA_B may be similar to the degree of degradation of the light-emitting element ED located in the red light-emitting region EA_R and the light-emitting element ED located in the green light-emitting region EA_G.

[0176] Therefore, variations in degradation between the light-emitting elements ED located in the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B are eliminated or reduced, thereby improving image quality.

[0177] Referring to Figure 4, each of the multiple first transmission regions TA1 contained in the first optical region OA1 can have various shapes, such as circular, elliptical, polygonal, or irregular. Each of the multiple second transmission regions TA2 contained in the second optical region OA2 can have various shapes, such as circular, elliptical, polygonal, or irregular.

[0178] Multiple first transparent regions TA1 may have the same shape. Alternatively, some of the multiple first transparent regions TA1 may have a different shape from the rest. Multiple second transparent regions TA2 may have the same shape. Alternatively, some of the multiple second transparent regions TA2 may have a different shape from the rest.

[0179] The first transparent region TA1 and the second transparent region TA2 can have the same shape. Alternatively, the first transparent region TA1 and the second transparent region TA2 can have different shapes.

[0180] Referring to Figure 4, all general regions NA can correspond to opaque regions. That is, a general region NA can include opaque regions NTA that contain multiple luminescent regions EA. In other words, the entire general region NA can be an opaque region NTA, and a general region NA does not necessarily have to include a transmissive region TA.

[0181] The first optical region OA1 may further include a non-transmitting region NTA containing a plurality of light-emitting regions EA, and a plurality of first transmitting regions TA1. The non-transmitting regions NTA included in the first optical region OA1 may be regions through which no light is transmitted at all, or they may be regions through which light is transmitted with a lower transmittance than that of the first transmitting regions TA1.

[0182] The second optical region OA2 may further include a non-transmitting region NTA containing a plurality of light-emitting regions EA, and a plurality of second transmitting regions TA2. The non-transmitting regions NTA included in the second optical region OA2 may be regions through which no light is transmitted at all, or they may be regions through which light is transmitted with a lower transmittance than that of the second transmitting regions TA2.

[0183] On the other hand, the common electrode CE may include a plurality of common electrode holes CH corresponding to a plurality of apertures. The plurality of common electrode holes CH may be formed in the first optical region OA1 and the second optical region OA2. That is, the positions in which the plurality of common electrode holes CH are formed may be in the first optical region OA1 and the second optical region OA2.

[0184] Referring to Figure 4, in the common electrode CE, the positions where multiple common electrode holes CH are formed can correspond to multiple first transmission regions TA1 included in the first optical region OA1. Furthermore, in the common electrode CE, the positions where multiple common electrode holes CH are formed can correspond to multiple second transmission regions TA2 included in the second optical region OA2. This makes it possible to improve the transmittance of both the first optical region OA1 and the second optical region OA2.

[0185] Figure 5 shows the signal line SL arranged on the display panel 110 according to an embodiment of the present disclosure.

[0186] Referring to Figure 5, the display panel 110 according to the embodiment of the present disclosure may include a plurality of subpixels SP and a plurality of signal lines SL for driving the plurality of subpixels SP.

[0187] Referring to Figure 5, each of the multiple subpixels SP may include a light-emitting element ED and a subpixel circuit SPC for driving it. The light-emitting element ED can form a light-emitting region EA.

[0188] Referring to Figure 5, the multiple signal lines SL can supply various drive signals necessary to drive the multiple subpixels SP to the multiple subpixels SP.

[0189] For example, the various drive signals may include a data signal VDATA for driving the data line DL, a scan signal SC for driving the gate line GL, and so on. The various drive signals may further include a drive voltage VDD for driving the drive voltage line VDDL, and a base voltage VSS for driving the base voltage line VSSL connected to the common electrode CE.

[0190] Therefore, the multiple signal lines may include multiple data lines DL for supplying data signals VDATA and multiple gate lines GL for supplying gate signals such as scan signals SC. The multiple signal lines may further include a drive voltage line VDDL for supplying a drive voltage VDD and a base voltage line VSSL for supplying a base voltage VSS.

[0191] Referring to Figure 5, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2.

[0192] Referring to Figure 5, each of the general region NA, the first optical region OA1, and the second optical region OA2 may contain multiple light-emitting regions EA. Each of the general region NA, the first optical region OA1, and the second optical region OA2 may have multiple light-emitting elements ED and multiple subpixel circuits SPC.

[0193] Referring to Figure 5, multiple signal lines SL can include multiple general signal lines SL_NA and multiple specific signal lines SL_OA.

[0194] Multiple general signal lines SL_NA may be signal lines that are located only in the general region NA, without passing through the first optical region OA1 and the second optical region OA2.

[0195] Multiple specific signal lines SL_OA may be signal lines that pass through at least one of the first optical region OA1 and the second optical region OA2.

[0196] For example, multiple general signal lines SL_NA may include multiple data lines DL_NA and multiple gate lines GL_NA that do not pass through the first optical region OA1 and the second optical region OA2.

[0197] For example, a plurality of specific signal lines SL_OA may include a plurality of data lines DL_OA and a plurality of gate lines GL_OA that pass through at least one of the first optical region OA1 and the second optical region OA2.

[0198] As described above, as multiple specific signal lines SL_OA pass through at least one of the first optical region OA1 and the second optical region OA2, the transmission characteristics of the first optical region OA1 and the second optical region OA2 can be affected by the multiple specific signal lines SL_OA.

[0199] On the other hand, in the common electrode CE, the positions where multiple common electrode holes CH are formed can correspond to multiple first transmission regions TA1 included in the first optical region OA1. Furthermore, the positions where multiple common electrode holes CH are formed in the common electrode CE can correspond to multiple second transmission regions TA2 included in the second optical region OA2. This makes it possible to improve the transmittance of both the first optical region OA1 and the second optical region OA2.

[0200] To further increase the transmittance of the first optical region OA1, when multiple specific signal lines SL_OA pass through the first optical region OA1, the multiple specific signal lines SL_OA can be arranged to bypass multiple common electrode holes CH corresponding to multiple first transmission regions TA1. Similarly, to further increase the transmittance of the second optical region OA2, when multiple specific signal lines SL_OA pass through the second optical region OA2, the multiple specific signal lines SL_OA can be arranged to bypass multiple common electrode holes CH corresponding to multiple second transmission regions TA2.

[0201] In this case, the multiple specific signal lines SL_OA that pass through at least one of the first optical region OA1 and the second optical region OA2 may have a longer wiring length than the multiple general signal lines SL_NA that do not pass through the first optical region OA1 and the second optical region OA2.

[0202] As a result, multiple specific signal lines SL_OA and multiple general signal lines SL_NA may have different electrical characteristics (e.g., different wiring resistances, different signal transmission delays, etc.). This can lead to a change in the driving characteristics between subpixel SPs connected to multiple specific signal lines SL_OA and subpixel SPs connected to multiple general signal lines SL_NA, potentially resulting in a decrease in image quality.

[0203] On the other hand, during the manufacturing of the display panel 110, a process for patterning a common electrode CE having multiple common electrode holes CH can be carried out. At this time, if variations occur in the patterning process of the common electrode CE, variations in the transmittance of the multiple common electrode holes CH of the common electrode CE may occur, and transmittance deviations between the multiple common electrode holes CH may also occur.

[0204] Therefore, the display panel 110 according to the embodiment of the present disclosure can have a structure that reduces wiring characteristic deviation.

[0205] According to the wiring characteristic deviation reduction structure of the embodiment of this disclosure, it is possible to reduce the electrical characteristic deviation (e.g., wiring resistance deviation, signal transmission delay deviation, etc.) between a plurality of specific signal lines SL_OA that pass through at least one of the first optical region OA1 and the second optical region OA2 and a plurality of general signal lines SL_NA that do not pass through the first optical region OA1 and the second optical region OA2.

[0206] Furthermore, the display panel 110 according to the embodiment of this disclosure may have a structure that reduces the range of transmittance fluctuations.

[0207] According to the transmittance fluctuation range reduction structure of the embodiment of this disclosure, even if process fluctuations occur, the transmittance fluctuation range between multiple common electrode holes CH can be reduced. Here, the multiple common electrode holes CH can correspond to multiple first transmission regions TA1 within a first optical region OA1, or to multiple second transmission regions TA2 within a second optical region OA2.

[0208] In the following, for the sake of explanation, the first optical region OA1 and the second optical region OA2 will be referred to as optical region OA, and the first transmission region TA1 within the first optical region OA1 and the second transmission region TA2 within the second optical region OA2 will be referred to as transmission region TA.

[0209] In the following, an improved structure for the transmission characteristics of the optical region OA of the display panel 110 according to an embodiment of the present disclosure will be described with reference to various illustrative drawings.

[0210] Figures 6 and 7 are plan views of the optical region OA of the display panel 110 according to an embodiment of the present disclosure.

[0211] The display panel 110 according to the embodiments of this disclosure may include a substrate SUB including a display area DA on which an image is displayed, a plurality of signal lines SL arranged on the substrate SUB, and a common electrode CE arranged on the substrate SUB.

[0212] The display area DA may include an optical area OA through which light is transmitted, and a general area NA located outside the optical area OA. The general area NA may include multiple light-emitting areas EA.

[0213] The optical region OA may include multiple transmission regions TA and non-transmission regions NTA excluding the multiple transmission regions TA.

[0214] The non-transparent region NTA included in the optical region OA may include multiple light-emitting regions EA formed by multiple light-emitting elements ED. Furthermore, multiple subpixel circuits SPC can be arranged within the non-transparent region NTA included in the optical region OA.

[0215] The common electrode CE may contain multiple common electrode holes CH. The locations where the multiple common electrode holes CH are formed may be in the optical region OA. That is, the multiple common electrode holes CH may be located within the optical region OA.

[0216] Multiple common electrode holes CH can be positioned to correspond to multiple transmission regions TA, respectively.

[0217] As mentioned above, the multiple signal lines SL may include multiple general signal lines SL that do not pass through the optical region OA, and multiple specific signal lines SL_OA that pass through the optical region OA.

[0218] For example, multiple specific signal lines SL_OA passing through the optical region OA may include multiple data lines DL. Multiple specific signal lines SL_OA passing through the optical region OA may include multiple gate lines GL.

[0219] Referring to Figure 6, multiple data lines DL passing through the optical region OA can be arranged while bypassing multiple transmission regions TA.

[0220] This makes it possible to improve the transmittance of optical optical equipment (OA).

[0221] Referring to Figure 7, multiple data lines DL passing through the optical region OA can be positioned across at least one of the multiple transmission regions TA without bypassing them.

[0222] This reduces the length deviation between multiple data lines DL that pass through the optical region OA and multiple data lines DL that do not pass through the optical region OA, thereby reducing the signal transmission characteristic deviation (wiring characteristic deviation).

[0223] Referring to Figure 7, each of the multiple common electrode holes CH can overlap with multiple data lines DL that pass through the optical region OA.

[0224] Each of the multiple common electrode holes CH exemplified in Figures 6 and 7 may be triangular. This is just one example, and common electrode holes CH can have a variety of shapes.

[0225] Figures 8 and 9 are cross-sectional views of a portion of the optical region of a display panel according to an embodiment of the present disclosure. Figure 8 is a cross-sectional view taken along line AB in Figure 6, and Figure 9 is a cross-sectional view taken along line CD in Figure 7.

[0226] Referring to Figures 8 and 9, the display panel 110 according to the embodiment of the present disclosure may include a substrate SUB containing a display area DA on which an image is displayed, a plurality of signal lines SL arranged on the substrate SUB, and a common electrode CE arranged on the substrate SUB.

[0227] Referring to Figures 8 and 9, the optical region OA can include multiple light-emitting regions EA and multiple transmission regions TA.

[0228] Referring to Figures 8 and 9, the common electrode CE can include multiple common electrode holes CH. The multiple common electrode holes CH can be positioned to correspond to multiple transmission regions TA, respectively.

[0229] Referring to Figures 8 and 9, the display panel 110 according to an embodiment of the present disclosure may further include a pixel electrode PE disposed in one of a plurality of light-emitting regions EA included in the optical region OA, a drive transistor DT disposed in the optical region OA for supplying a drive current to the pixel electrode PE, a capacitor Cst disposed in the optical region OA, a bank 833 disposed on the pixel electrode (PE) and having an opening, and an intermediate layer EL disposed between the bank 833 and the common electrode CE, and located on a portion of the pixel electrode PE through the opening of the bank 833.

[0230] The region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE are superimposed constitutes one light-emitting element ED and can correspond to one light-emitting region EA.

[0231] The drive transistor DT and capacitor Cst may be placed in multiple non-transparent regions NTA within the optical region OA, other than the transparent regions TA.

[0232] Referring to Figures 8 and 9, the display panel 110 according to the embodiment of the present disclosure may further include scan transistors ST arranged in multiple areas other than the transmission area TA within the optical area OA.

[0233] Referring to Figures 8 and 9, the scan transistor ST can be connected to the data line DL, which is one of several specific signal lines SL_OA.

[0234] Referring to Figures 8 and 9, a data line DL, which is one of several specific signal lines SL_OA connected to the scan transistor ST, can be placed within a metal layer located between the source and drain electrodes of the drive transistor DT and the pixel electrode PE.

[0235] Referring to Figures 8 and 9, the display panel 110 according to the embodiment of the present disclosure may further include a sealing layer ENCAP disposed on a common electrode CE, and a touch sensor metal TSM disposed on the sealing layer ENCAP and positioned in the general region NA and the optical region OA.

[0236] Referring to Figures 8 and 9, the touch sensor metal TSM can overlap with bank 833. Among the touch sensor metal TSMs, the touch sensor metal TSMs placed in the optical region OA can be located in the non-transparent region NTA, which is the optical region OA excluding the multiple light-emitting regions EA and multiple transmission regions TA.

[0237] The vertical structure of the display panel 110 will be described in more detail below with reference to Figures 8 and 9.

[0238] Referring to Figures 8 and 9, the display panel 110 according to the embodiment of the present disclosure may include a transistor formation section, a light-emitting element formation section, and a sealing section when viewed from a vertical structure, and may further include a touch sensor section.

[0239] Referring to Figures 8 and 9, the display panel 110 according to the embodiment of the present disclosure may include a substrate SUB, a first buffer layer 811 on the substrate SUB, a first gate insulating layer 812 on the first buffer layer 811, a first interlayer insulating layer 813 on the first gate insulating layer 812, a second buffer layer 821 on the first interlayer insulating layer 813, a second gate insulating layer 822 on the second buffer layer 821, a second interlayer insulating layer 823 on the second gate insulating layer 822, a first planarization layer 831 on the second interlayer insulating layer 823, and a second planarization layer 832 on the first planarization layer 831.

[0240] The display panel 110 according to embodiments of the present disclosure may further include a first gate metal layer located between a first gate insulating layer 812 and a first interlayer insulating layer 813, a first source-drain metal layer located between a second interlayer insulating layer 823 and a first planarization layer 831, and a second source-drain metal layer located between a first planarization layer 831 and a second planarization layer 832.

[0241] The display panel 110 according to the embodiments of the present disclosure may further include a second gate metal layer between the first interlayer insulating layer 813 and the second buffer layer 821, and a third gate metal layer between the second gate insulating layer 822 and the second interlayer insulating layer 823.

[0242] The display panel 110 according to the embodiments of the present disclosure may further include a first active layer ACT1 between a first buffer layer 811 and a first gate insulating layer 812, and a second active layer ACT2 between a second buffer layer 821 and a second gate insulating layer 822.

[0243] Referring to Figures 8 and 9, the transistor formation section may include a substrate SUB, a first buffer layer 811 on the substrate SUB, various transistors DT, ST, storage capacitors Cst, and various electrodes or signal wiring formed on the first buffer layer BUF.

[0244] Referring to Figures 8 and 9, the substrate SUB may include a first substrate SUB1 and a second substrate SUB2, and may include a substrate interlayer IPD between the first substrate SUB1 and the second substrate SUB2. For example, each of the first substrate SUB1 and the second substrate SUB2 may be polyimide (PI). For example, the substrate interlayer IPD may be an inorganic layer that can block moisture penetration.

[0245] Referring to Figures 8 and 9, the first buffer layer 811 may be single-layer or multi-layer. If the first buffer layer 811 is multi-layer, it may include a multi-buffer layer 811a and an active buffer layer 811b.

[0246] Various transistors DT, ST, storage capacitors Cst, and various electrodes or signal wiring can be formed on the first buffer layer 811.

[0247] For example, transistors DT and ST formed on the first buffer layer 811 may be made of the same material and located on the same layer. Alternatively, as shown in Figures 8 and 9, the drive transistor DT and the scan transistor ST may be made of different materials and located on different layers.

[0248] Referring to Figures 8 and 9, the drive transistor DT, the scan transistor ST, and the storage capacitor Cst may be included in the subpixel circuit section SPC for driving the light-emitting element ED included in the optical region OA.

[0249] The scan transistor ST may include an active layer ACT1, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1.

[0250] The drive transistor DT may include an active layer ACT2, a gate electrode GE2, a source electrode SE2, and a second drain electrode DE2.

[0251] The active layer ACT2 of the drive transistor DT can be positioned higher than the active layer ACT1 of the scan transistor ST. Depending on the height of the active layer, upper and lower transistors can be distinguished. The drive transistor DT is sometimes called the "upper transistor," and the scan transistor ST is sometimes called the "lower transistor."

[0252] The source electrode SE1 and drain electrode DE1 of the lower transistor, the scan transistor ST, can be located in the "first source-drain metal layer". The gate electrode GE1 of the lower transistor, the scan transistor ST, can be located in the "first gate metal layer".

[0253] The source electrode SE2 and drain electrode DE1 of the upper transistor, the driving transistor DT, can be located in the "first source-drain metal layer". The gate electrode GE2 of the upper transistor, the driving transistor DT, can be located in another "third gate metal layer" that is above the first and second gate metal layers.

[0254] A first buffer layer 811 may be placed beneath the active layer ACT1 of the scan transistor ST, and a second buffer layer 821 may be placed beneath the active layer ACT2 of the drive transistor DT. That is, the active layer ACT1 of the scan transistor ST can be located on the first buffer layer 811, and the active layer ACT2 of the drive transistor DT can be located on the second buffer layer 821. Here, the second buffer layer 821 can be located higher than the first buffer layer 811.

[0255] The active layer ACT1 of the scan transistor ST is placed on the first buffer layer 811, and the first gate insulating layer 812 may be placed on the active layer ACT1 of the scan transistor ST. The gate electrode GE1 of the scan transistor ST can be placed on the first gate insulating layer 812, and the first interlayer insulating layer 813 can be placed on the gate electrode GE1 of the scan transistor ST.

[0256] Here, the active layer ACT1 of the scan transistor ST may include a channel region overlapping with the gate electrode GE1, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0257] A second buffer layer 821 can be placed on the first interlayer insulating layer 813.

[0258] The active layer ACT2 of the drive transistor DT can be placed on the second buffer layer 821, and the second gate insulating layer 822 can be placed on the active layer ACT2 of the drive transistor DT. The gate electrode GE2 of the drive transistor DT can be placed on the second gate insulating layer 822, and the second interlayer insulating layer 823 can be placed on the gate electrode GE2 of the drive transistor DT.

[0259] Here, the active layer ACT2 of the drive transistor DT may include a channel region overlapping with the gate electrode GE2, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0260] The source electrode SE2 and drain electrode DE2 of the drive transistor DT can be placed on the second interlayer insulating layer 823. Similarly, the source electrode SE1 and drain electrode DE1 of the scan transistor ST may also be placed on the second interlayer insulating layer 823.

[0261] The source electrode SE1 and drain electrode DE1 of the scan transistor ST can be connected to the source connection region and drain connection region of the active layer ACT1 of the scan transistor ST, respectively, through through-holes in the second interlayer insulating layer 823, the second gate insulating layer 822, the second buffer layer 821, the first interlayer insulating layer 813, and the first gate insulating layer 812.

[0262] The source electrode SE2 and drain electrode DE2 of the drive transistor DT can be connected to the source connection region and drain connection region of the active layer ACT2 of the drive transistor DT, respectively, through through holes in the second interlayer insulating layer 823 and the second gate insulating layer 822.

[0263] The storage capacitor Cst may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0264] The first capacitor electrode PLT1 of the storage capacitor Cst can be electrically connected directly or indirectly to the gate electrode GE2 of the drive transistor DT, and the second capacitor electrode PLT2 of the storage capacitor Cst can be electrically connected directly or indirectly to the source electrode SE2 of the drive transistor DT.

[0265] The first capacitor electrode PLT1 of the storage capacitor Cst may be located within a first gate metal layer composed of a first gate metal. The second capacitor electrode PLT2 of the storage capacitor Cst may be located within a second gate metal layer composed of a second gate metal.

[0266] On the other hand, the lower metal BML can be placed below the active layer ACT2 of the drive transistor DT. The lower metal BML can overlap all or part of the active layer ACT2 of the drive transistor DT. The lower metal BML can include the second gate metal of the second gate metal layer.

[0267] For example, the lower metal BML can be electrically connected to the gate electrode GE2 of the drive transistor DT. In another example, the lower metal BML can also act as a light shield, blocking light incident from below. In this case, the lower metal BML may be electrically connected to the source electrode SE2 of the drive transistor DT.

[0268] Referring to Figures 8 and 9, the first planarization layer 831 can be placed on the drive transistor DT and the scan transistor ST. That is, the first planarization layer 831 can be placed on the source electrode SE2 and drain electrode DE2 of the drive transistor DT and on the source electrode SE1 and drain electrode DE1 of the scan transistor ST.

[0269] Referring to Figures 8 and 9, a second source-drain metal layer can be present between the first planarization layer 831 and the second planarization layer 832.

[0270] The source electrode SE2 of the drive transistor DT and the pixel electrode PE of the light-emitting element ED can be electrically connected via a relay pattern formed in the second source-drain metal layer.

[0271] Referring to Figures 8 and 9, the data line DL passing through the permeable region TA can be formed within the second source-drain metal layer. That is, the data line DL passing through the permeable region TA can include the second source-drain metal.

[0272] Referring to Figures 8 and 9, the active layer ACT2 of the upper transistor, the driving transistor DT, and the active layer ACT1 of the lower transistor, the scanning transistor ST, can be made of different semiconductor materials.

[0273] For example, the active layer ACT2 of the upper transistor, the driving transistor DT, can include an oxide semiconductor material. For example, oxide semiconductor materials can include IGZO (Indium gallium zinc oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), and others.

[0274] For example, the active layer ACT1 of the lower transistor, the scan transistor ST, may be made of a different semiconductor material than the active layer ACT2 of the upper transistor, the drive transistor DT.

[0275] For example, the active layer ACT1 of the lower transistor, the scan transistor ST, can include a silicon-based semiconductor material. For example, the silicon-based semiconductor material can include low-temperature polycrystalline silicon (LTPS).

[0276] Referring to Figures 8 and 9, the light-emitting element forming part can be positioned on the second planarization layer PNL2.

[0277] The light-emitting element forming portion can include a light-emitting element ED formed on the second planarization layer PNL2. The light-emitting element ED can be disposed in the optical region OA.

[0278] Referring to FIGS. 8 and 9, the light-emitting element ED can be constituted by the superposition of a pixel electrode PE, an intermediate layer EL, and a common electrode CE. That is, the light-emitting element ED may be a portion where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap.

[0279] The pixel electrode PE can be disposed on the second planarization layer 832.

[0280] A bank 833 can be disposed on the pixel electrode PE.

[0281] The bank 833 can include a plurality of bank holes, and a part of the pixel electrode PE can be exposed through the plurality of bank holes. That is, the plurality of bank holes formed in the bank 833 can overlap a part of the pixel electrode PE.

[0282] The intermediate layer EL can be disposed on the bank 833. The intermediate layer EL can contact a part of the pixel electrode PE through the bank hole.

[0283] At least one spacer may exist between the intermediate layer EL and the bank 833. The spacer can include the same material as the bank 833.

[0284] The common electrode CE can be disposed on the intermediate layer EL. The common electrode CE can include a plurality of common electrode holes CH. The plurality of common electrode holes CH formed in the common electrode CE can be disposed in the optical region OA.

[0285] The common electrode hole CH can correspond in position to the transmission region TA.

[0286] Referring to Figure 8, the data line DL can be positioned to avoid the transparent region TA. Therefore, the data line DL does not exist in the transparent region TA.

[0287] Referring to Figure 9, the data line DL can be positioned while passing through the transparent region TA. Therefore, the data line DL is present in the transparent region TA. For example, the data line DL may be a transparent wiring containing a transparent material.

[0288] Referring to Figures 8 and 9, the sealing portion can be placed on the cathode electrode CE. The sealing portion may include a sealing layer ENCAP formed on the common electrode CE.

[0289] The sealing layer ENCAP may be a layer that prevents moisture and oxygen from penetrating the light-emitting element ED, which is placed beneath the sealing layer ENCAP. In particular, the sealing layer ENCAP can prevent moisture or oxygen from penetrating the intermediate layer EL, which may include an organic layer. Here, the sealing layer ENCAP may consist of a single layer or a multilayer structure.

[0290] The ENCAP sealing layer may include a first sealing layer 841, a second sealing layer 842, and a third sealing layer 843.

[0291] For example, the sealing layer ENCAP may include alternating inorganic and organic layers. In this case, for example, the first sealing layer 841 and the third sealing layer 843 may be inorganic layers, and the second sealing layer 842 may be an organic layer. If the second sealing layer 842 is composed of an organic layer, the second sealing layer 842 can serve as a planarizing layer.

[0292] On the other hand, the display panel 110 according to the embodiments of the present disclosure may have a touch sensor embedded in it. In this case, the display panel 110 according to the embodiments of the present disclosure may include a touch sensor layer TSL on the sealing layer ENCAP.

[0293] The touch sensor layer TSL may include a touch sensor metal TSM and a bridge metal BRG, and may further include insulating layer configurations such as a sensor buffer layer 851, an inter-sensor insulating layer 852, and a sensor protective layer 853.

[0294] The sensor buffer layer 851 can be placed on the sealing layer ENCAP.

[0295] The bridge metal BRG can be placed on the sensor buffer layer 851, and the inter-sensor insulating layer 852 can be placed on the bridge metal BRG.

[0296] The touch sensor metal TSM can be placed on the sensor interlayer insulating layer 852. A portion of the touch sensor metal TSM can be connected to the corresponding bridge metal BRG through holes in the sensor interlayer insulating layer 852.

[0297] The touch sensor metal TSM and bridge metal BRG may be placed in the general area NA and in the non-transparent area NTA within the optical area OA.

[0298] When the display panel 110 has an upper light-emitting structure, and the touch sensor metal TSM and bridge metal BRG are placed in the non-transparent area NTA within the optical area OA, the touch sensor metal TSM and bridge metal BRG can be positioned so as not to overlap with the light-emitting area EA of the non-transparent area NTA.

[0299] Multiple touch sensor metal TSMs can constitute a single touch electrode (or a single touch electrode line), be arranged in a mesh, and be electrically connected. Some parts of a touch sensor metal TSM can be electrically connected via a bridge metal BRG to constitute a single touch electrode (or a single touch electrode line).

[0300] The sensor protection layer 853 can be positioned while covering the touch sensor metal TSM and the bridge metal BRG.

[0301] On the other hand, when the display panel 110 is of a type incorporating a touch sensor, at least a part of the touch sensor metal TSM located on the encapsulation layer ENCAP in the display area DA extends and can be electrically connected to a pad located outside the outer inclined surface of the encapsulation layer ENCAP. Here, the pad may be arranged in the non-display area NDA or may be a metal pattern to which the touch drive circuit 260 is electrically connected.

[0302] Referring to FIGS. 8 and 9, the display device 100 according to an embodiment of the present disclosure may include an electronic device 800 located under the substrate SUB and overlapping the optical area OA. The electronic device 800 can be one of the first electronic device 11 and the second electronic device 12 (see FIGS. 1a, 1b, and 1c).

[0303] The electronic device 800 can perform a defined operation according to the first light in the first wavelength band among the light received through the optical area OA. For example, the first wavelength band may correspond to the wavelength band of visible light or the wavelength band of infrared light.

[0304] FIG. 10 shows the signal intensity during reception processing of light passing through the optical area OA of the display panel 110 according to an embodiment of the present disclosure.

[0305] Referring to FIG. 10, the light incident on the upper surface of the display panel 110 passes through (transmits through) the optical area OA of the display panel 110 and is received by the electronic device 800 located below the display panel 110 and overlapping the optical area OA.

[0306] The electronic device 800 can execute a predetermined operation using the received light.

[0307] Depending on the amount of light received by the electronic device 800, the performance and quality of the operation executed by the electronic device 800 may change.

[0308] For example, if the electronic device 800 is an infrared sensor that detects nearby objects, the performance and quality of the sensing operation performed using infrared light may change depending on the amount of infrared light that passes through the optical area OA of the display panel 110.

[0309] The amount of infrared light transmitted through the optical region OA of the display panel 110 can correspond to the value (intensity) of the point spread function (PSF). Here, the value (intensity) of the point spread function can correspond to the infrared signal strength during reception processing by the electronic device 800. The value of the point spread function can be an indicator of the sensing performance of the infrared sensor.

[0310] When the metal ratio within the optical region (OA) is high, that is, when the transmittance of the optical region (OA) is low, the value of the point spread function, which is an indicator of the sensing performance of an infrared sensor, may decrease.

[0311] When the metal ratio within the optical region (OA) decreases, that is, when the transmittance of the optical region (OA) increases, the value of the point spread function, which is an indicator of the sensing performance of an infrared sensor, may increase.

[0312] As another example, if the electronic device 800 is an image sensor (camera), the performance and quality of camera operations performed using visible light may change depending on the amount of visible light transmitted through the optical area OA of the display panel 110.

[0313] The amount of visible light transmitted through the optical region OA of the display panel 110 can correspond to the value (intensity) of the modulation transfer function (MTF). Here, the value of the modulation transfer function can correspond to the signal intensity (intensity) of visible light during reception processing by the electronic device 800. Here, the value of the modulation transfer function is an indicator of camera performance and can represent the sharpness level.

[0314] When the metal ratio within the optical region (OA) is high, that is, when the transmittance of the optical region (OA) is low, the value of the modulation transfer function, which is an indicator of camera performance, may decrease.

[0315] When the metal ratio within the optical region (OA) decreases, that is, when the transmittance of the optical region (OA) increases, the value of the modulation transfer function, which is an indicator of camera performance, may increase.

[0316] The following describes a transmittance improvement structure for the optical region OA of the display panel 110 according to embodiments of this disclosure. The transmittance improvement structure for the optical region OA may include a structure that can reduce the metal ratio in the optical region OA.

[0317] In the following, for the sake of clarity, the optical region OA will be referred to as the first region OA, and the general region NA will be referred to as the second region NA.

[0318] Figure 11 is a plan view of the display panel 110 according to an embodiment of the present disclosure.

[0319] Referring to Figure 11, the display panel 110 according to an embodiment of the present disclosure may include a substrate SUB that includes a display area DA capable of displaying an image and a non-display area NDA outside the display area DA, a plurality of subpixels SP included in the display area DA and each containing a plurality of light-emitting elements ED, and a plurality of data lines DL for supplying data signals for image display to the plurality of subpixels SP.

[0320] Referring to Figure 11, the display area DA may include a first area OA that can transmit light and a second area NA located outside the first area OA. The second area NA may include an upper area NA1 located above the first area OA and a lower area NA2 located below the first area OA.

[0321] In Figure 11, as an example, the first region OA is shown by a dotted circle, and the second region NA may be the region outside the dotted circle. The upper region NA1 of the second region NA may be the region located above the first region OA within the outer region of the first region OA. The lower region NA2 of the second region NA may be the region located below the first region OA within the outer region of the first region OA.

[0322] Referring to Figure 11, multiple subpixels SP placed in the display area DA can include the first to twelfth subpixels (SP1 to SP12).

[0323] Referring to Figure 11, the multiple subpixels SP located in the upper region NA1 of the second region NA may include the first subpixel SP1, the second subpixel SP2, the seventh subpixel SP7, and the tenth subpixel SP10.

[0324] Referring to Figure 11, the multiple subpixels SP located in the lower region NA2 of the second region NA may include the fifth subpixel SP5, the sixth subpixel SP6, the ninth subpixel SP9, and the twelfth subpixel SP12.

[0325] Referring to Figure 11, the multiple subpixels SP located in the first region OA may include a third subpixel SP3, a fourth subpixel SP4, an eighth subpixel SP8, and an eleventh subpixel SP11.

[0326] Referring to Figure 11, for example, multiple subpixels SP arranged in the display area DA may include red subpixels that emit red light, green subpixels that emit green light, and blue subpixels that emit blue light.

[0327] Referring to Figure 11, multiple subpixels SP located in the display area DA can each contain multiple pixel electrodes PE. For example, the multiple pixel electrodes PE may include a red pixel electrode PE(R) contained in a red subpixel, a green pixel electrode PE(G) contained in a green subpixel, and a blue pixel electrode PE(B) contained in a blue subpixel.

[0328] Referring to Figure 11, the multiple data lines DL arranged in the display area DA may include a red data line DL(R) that supplies data signals to red subpixels, green data lines DL(G), DL(G)_U, DL(G)_D that supply data signals to green subpixels, and a blue data line DL(B) that supplies data signals to blue subpixels.

[0329] Referring to Figure 11, multiple data lines DL located in the display area DA can be placed in the second area NA, which is the general area NA.

[0330] Referring to Figure 11, some of the data lines DL (R), DL (G), and DL (B) located in the second region NA can pass through the first region OA, which is the optical region OA.

[0331] However, some of the data lines DL located in the second region NA, specifically DL(G)_U and DL(G)_D, can be positioned by bypassing the first region OA, which is the optical region OA, without passing through it.

[0332] For example, the upper data line DL(G)_U may be located in the upper region NA1 of the second region NA, and the lower data line DL(G)_D may be located in the lower region NA2 of the second region NA. The upper data line DL(G)_U and the lower data line DL(G)_D may be electrically connected via a bypass wiring BW that bypasses the first region OA. The upper data line DL(G)_U, the lower data line DL(G)_D, and the bypass wiring BW are electrically connected to correspond to a single data line, and such a single data line can bypass the first region OA without passing through it.

[0333] For example, referring to Figure 11, multiple data lines DL may include a first data line DL1 that passes through the upper region NA1, the first region OA, and the lower region NA2.

[0334] In the example in Figure 11, the first data line DL1 may be a green data line DL(G) for supplying data signals to the green subpixels located in the upper region NA1, the first region OA, and the lower region NA2, respectively. However, this is merely illustrative and not limited to it.

[0335] Multiple data lines DL may further include an upper data line DL(G)_U located in the upper region NA1 of the second region NA, a lower data line DL(G)_D located in the lower region NA2 of the second region NA, and a bypass wiring BW that electrically connects the upper data line DL(G)_U and the lower data line DL(G)_D and bypasses the first region OA. Here, the upper data line DL(G)_U, the lower data line DL(G)_D, and the bypass wiring BW are electrically connected to function as a single data line.

[0336] In the example in Figure 11, the upper data line DL(G)_U may be a green data line DL(G)_U for supplying a data signal to a green subpixel located in the upper region NA1, and the lower data line DL(G)_D may be a green data line DL(G)_D for supplying a data signal to a green subpixel located in the lower region NA2. However, this is merely an example and is not limited thereto.

[0337] Referring to Figure 11, the bypass wiring BW may include a first bypass wiring BW1 connected to the upper data line DL(G)_U, a second bypass wiring BW2 connected to the lower data line DL(G)_D, and a third bypass wiring BW3 connecting the first bypass wiring BW1 and the second bypass wiring BW2.

[0338] Referring to Figure 11, the bypass wiring BW can include a lateral bypass wiring H_BW extending laterally and a vertical bypass wiring V_BW extending vertically. Referring to Figure 11, the lateral bypass wiring H_BW, the upper data line DL(G)_U, and the lower data line DL(G)_D can form a mesh configuration.

[0339] Referring to Figure 11, the intersection of the bypass wiring BW and the upper data line DL(G)_U, and the intersection of the bypass wiring BW and the lower data line DL(G)_D, can have connection points. For example, a first connection point can be formed at the intersection of the upper data line DL(G)_U and the first bypass wiring BW1, which is the lateral bypass wiring H_BW. A second connection point can be formed at the intersection of the lower data line DL(G)_D and the second bypass wiring BW2, which is the lateral bypass wiring H_BW. A third connection point can be formed at the intersection of the first bypass wiring BW1, which is the lateral bypass wiring H_BW, and the third bypass wiring BW3, which is the vertical bypass wiring V_BW. A fourth connection point can be formed at the intersection of the second bypass wiring BW2, which is the lateral bypass wiring H_BW, and the third bypass wiring BW3, which is the vertical bypass wiring V_BW.

[0340] Referring to Figure 11, the lateral bypass wiring H_BW may include the first bypass wiring BW1 and the second bypass wiring BW2, and the longitudinal bypass wiring V_BW may include the third bypass wiring BW3.

[0341] The horizontal bypass wiring H_BW and the vertical bypass wiring V_BW can intersect and overlap in the vertical direction.

[0342] Therefore, the lateral bypass wiring H_BW and the longitudinal bypass wiring V_BW can be placed in different metal layers. For example, the lateral bypass wiring H_BW may be placed in a first metal layer, and the longitudinal bypass wiring V_BW may be placed in a second metal layer different from the first metal layer. For example, the first metal layer may be a first source-drain metal layer, and the second metal layer may be a second source-drain metal layer.

[0343] Referring to Figure 11, the multiple pixel electrodes PE contained in each of the multiple light-emitting elements ED may include a first pixel electrode PE1 located in the upper region NA1 and included in the first subpixel SP1, a second pixel electrode PE2 located in the upper region NA1 and included in the second subpixel SP2, a third pixel electrode PE3 located in the first region OA and included in the third subpixel SP3, a fourth pixel electrode PE4 located in the first region OA and included in the fourth subpixel SP4, a fifth pixel electrode PE5 located in the lower region NA2 and included in the fifth subpixel SP5, and a sixth pixel electrode PE6 located in the lower region NA2 and included in the sixth subpixel SP6.

[0344] Referring to Figure 11, the first data line DL1 can be connected to the first subpixel SP1 of the upper region NA1, the third subpixel SP3 of the first region OA, and the fifth subpixel SP5 of the lower region NA2.

[0345] The first data line DL1 can supply data signals to the first subpixel SP1 in the upper region NA1, the third subpixel SP3 in the first region OA, and the fifth subpixel SP5 in the lower region NA2.

[0346] Referring to Figure 11, the upper data line DL(G)_U may be connected to the second subpixel SP2 located in the upper region NA1, and the lower data line DL(G)_D may be connected to the sixth subpixel SP6 located in the lower region NA2.

[0347] Referring to Figure 11, the display panel 110 according to the embodiment of the present disclosure may further include a connecting wire CW that electrically connects a third pixel electrode PE3 and a fourth pixel electrode PE4.

[0348] The connecting wiring CW can be placed in the first region OA, which is the optical region OA.

[0349] Referring to Figure 11, the emission colors of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5, and the sixth subpixel SP6 may be the same.

[0350] In the example shown in Figure 11, the emission colors of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5, and the sixth subpixel SP6 may be green light, but this is merely an example and is not limited to this.

[0351] Referring to Figure 11, some of the multiple subpixels SP3, SP4 located in the first region OA (for example, a third subpixel SP3) may include a light-emitting element ED and a subpixel circuit SPC.

[0352] A subpixel circuit SPC, which is part of a group of subpixels SP3 and SP4 located in the first region OA (for example, a third subpixel SP3), may include a drive transistor DT, a scan transistor ST, a storage capacitor Cst, and the like (see Figure 3).

[0353] Referring to Figure 11, a subpixel circuit SPC contained in a portion of a plurality of subpixels SP3, SP4 located in the first region OA (for example, a third subpixel SP3) may include a red subpixel circuit SPC(R) contained in a red subpixel, a green subpixel circuit SPC(G) contained in a green subpixel, and a blue subpixel circuit SPC(B) contained in a blue subpixel.

[0354] Referring to Figure 11, some of the subpixels SP located in the first region OA (e.g., the fourth subpixel SP4) include a light-emitting element ED but do not include a subpixel circuit SPC.

[0355] Referring to the example in Figure 11, the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fifth subpixel SP5, and the sixth subpixel SP6 can each include a light-emitting element ED and a subpixel circuit SPC(G) that drives the light-emitting element ED. Here, the subpixel circuit SPC(G) can include two or more transistors DT, ST.

[0356] Referring to the example in Figure 11, the fourth subpixel SP4 includes a light-emitting element ED, but does not necessarily include a subpixel circuit SPC(G). The light-emitting element ED of the fourth subpixel SP4 may be driven by the subpixel circuit SPC(G) of the third subpixel SP3.

[0357] As a result, the drive current output from the subpixel circuit SPC(G) of the third subpixel SP3 is supplied to the third pixel electrode PE3, and can also be supplied to the fourth pixel electrode PE4 via the connecting wiring CW.

[0358] Referring to Figure 11, the multiple pixel electrodes PE may further include a seventh pixel electrode PE7 located in the upper region NA1 and included in the seventh subpixel SP7, an eighth pixel electrode PE8 located in the first region OA and included in the eighth subpixel SP8, and a ninth pixel electrode PE9 located in the lower region NA2 and included in the ninth subpixel SP9.

[0359] Multiple data lines DL may further include a second data line DL2 connected to the seventh subpixel SP7 of the upper region NA1, the eighth subpixel SP8 of the first region OA, and the ninth subpixel SP9 of the lower region NA2.

[0360] In the example in Figure 11, the second data line DL2 may be a blue data line DL(B) for supplying data signals to the blue subpixels located in the upper region NA1, the first region OA, and the lower region NA2, respectively. However, this is merely illustrative and not limited to it.

[0361] The emission colors of the seventh subpixel SP7 in the upper region NA1, the eighth subpixel SP8 in the first region OA, and the ninth subpixel SP9 in the lower region NA2 may differ from the emission colors of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5, and the sixth subpixel SP6, respectively.

[0362] For example, the emission colors of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5, and the sixth subpixel SP6 may be green light, while the emission colors of the seventh subpixel SP7 in the upper region NA1, the eighth subpixel SP8 in the first region OA, and the ninth subpixel SP9 in the lower region NA2 may be blue light. However, this is merely an example and is not limited thereto.

[0363] Referring to Figure 11, the second data line DL2 can intersect and overlap with the connecting wire CW. The first data line DL1 can also intersect and overlap with the connecting wire CW.

[0364] Referring to Figure 11, the multiple pixel electrodes PE may further include a 10th pixel electrode PE10 located in the upper region NA1 and included in the 10th subpixel SP10, an 11th pixel electrode PE11 located in the first region OA and included in the 11th subpixel SP11, and a 12th pixel electrode PE12 located in the lower region NA2 and included in the 12th subpixel SP12.

[0365] Referring to Figure 11, the multiple data lines DL may further include a third data line DL3 connected to the 10th subpixel SP10 of the upper region NA1, the 11th subpixel SP11 of the first region OA, and the 12th subpixel SP12 of the lower region NA2.

[0366] In the example in Figure 11, the third data line DL3 may be a red data line DL(R) for supplying data signals to the red subpixels located in the upper region NA1, the first region OA, and the lower region NA2, respectively. However, this is merely illustrative and not limited to it.

[0367] Referring to Figure 11, the emission colors of the 10th subpixel SP10, the 11th subpixel SP11, and the 12th subpixel SP12 may differ from the emission colors of the 1st subpixel SP1, the 2nd subpixel SP2, the 3rd subpixel SP3, the 4th subpixel SP4, the 5th subpixel SP5, and the 6th subpixel SP6.

[0368] For example, the emission colors of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5, and the sixth subpixel SP6 may be green light, and the emission colors of the tenth subpixel SP10, the eleventh subpixel SP11, and the twelfth subpixel SP12 may be red light. However, this is not limited to these examples.

[0369] Referring to Figure 11, the display panel 110 according to the embodiment of the present disclosure may further include a common electrode CE arranged on a plurality of pixel electrodes PE.

[0370] Referring to Figure 11, within the first region OA, the common electrode CE may have multiple common electrode holes CH. For example, within the first region OA, the common electrode CE may have a common electrode hole CH between the first data line DL1 and the third data line DL3.

[0371] The display panel 110 according to the embodiments of this disclosure may include a substrate SUB that includes a display area DA capable of displaying an image and a non-display area NDA surrounding the display area DA, a plurality of subpixels SP included in the display area DA and each containing a plurality of light-emitting elements ED, and a plurality of data lines DL for supplying data signals for image display to the plurality of subpixels SP.

[0372] The display area DA may include a first area OA, which is an optical area that can transmit light, and a second area NA, which is a general area located outside the first area OA.

[0373] The second region NA may include an upper region NA1 located above the first region OA and a lower region NA2 located below the first region OA.

[0374] Multiple light-emitting elements (EDs) may each include multiple pixel electrodes (PEs).

[0375] Multiple pixel electrodes PE may be arranged in a first region OA and include two pixel electrodes PE3, PE4 that are electrically connected to each other.

[0376] The display panel 110 according to the embodiments of the present disclosure may further include a connecting wire CW arranged in a first area OA and electrically connecting two pixel electrodes PE3 and PE4.

[0377] Multiple data lines DL may include a first data line DL1 connected to one of two subpixels containing two pixel electrodes PE3 and PE4 (e.g., the subpixel containing PE3). The other of the two subpixels containing two pixel electrodes PE3 and PE4 (e.g., the subpixel containing PE4) is not connected to a data line.

[0378] Figures 12 and 13 are plan views of a portion of a first region OA1, which is the optical region OA of the display panel 110 according to an embodiment of the present disclosure.

[0379] Referring to Figures 12 and 13, the first region OA1, which is the optical region OA of the display panel 110, can include a transparent region TA and an opaque region NTA.

[0380] Referring to Figures 12 and 13, the opaque region NTA may include a circuit region CA in which multiple subpixel circuits are located, each contained within a multiple subpixel. For example, the multiple subpixel circuits may include a red subpixel circuit contained within a red subpixel, a green subpixel circuit contained within a green subpixel, and a blue subpixel circuit contained within a blue subpixel.

[0381] Referring to Figures 12 and 13, the opaque region NTA can include multiple light-emitting regions, each corresponding to a multiple subpixel. This allows multiple pixel electrodes PE(R), PE(G), and PE(B) to be placed in the opaque region NTA.

[0382] Referring to Figures 12 and 13, multiple pixel electrodes PE(R), PE(G), and PE(B) can be arranged in the non-transparent region NTA, with multiple contact holes CNT(R), CNT(G), and CNT(B) connected to multiple sub-pixel circuits, respectively.

[0383] For example, multiple pixel electrodes PE(R), PE(G), and PE(B) may include a red pixel electrode PE(R) contained in a red subpixel, a green pixel electrode PE(G) contained in a green subpixel, and a blue pixel electrode PE(B) contained in a blue subpixel. For reference, the arrangement of the red pixel electrode PE(R), green pixel electrode PE(G), and blue pixel electrode PE(B) in Figures 12 and 13 differs from the arrangement of the red pixel electrode PE(R), green pixel electrode PE(G), and blue pixel electrode PE(B) in Figure 11.

[0384] For example, multiple contact hole CNTs (R), CNTs (G), and CNTs (B) may include a contact hole CNT (R) between a red pixel electrode PE(R) and a red subpixel circuit, a contact hole CNT (G) between a green pixel electrode PE(G) and a green subpixel circuit, and a contact hole CNT (B) between a blue pixel electrode PE(B) and a blue subpixel circuit.

[0385] Referring to Figures 12 and 13, two green pixel electrodes PE(G) can be connected by a connecting wire CW. The two green pixel electrodes PE(G) connected by the connecting wire CW can correspond to the third pixel electrode PE3 and the fourth pixel electrode PE4 in Figure 11.

[0386] Referring to Figures 12 and 13, the blue pixel electrode PE(B) can correspond to the eighth pixel electrode PE8 in Figure 11.

[0387] Referring to Figure 11, in the second region NA, which is a general region NA, four data lines (red data line, green data line, blue data line, green data line) can be arranged repeatedly.

[0388] In the upper region NA1 of the second region NA, which is a general region NA, the red data line DL(R), the upper data line green data line DL(G)_U, the blue data line DL(B), and the green data line DL(G) can be arranged in that order.

[0389] Referring to Figure 11, in the lower region NA2 of the second region NA, which is the general region NA, the red data line DL(R), the lower data line green data line DL(G)_D, the blue data line DL(B), and the green data line DL(G) can be arranged in that order.

[0390] Referring to Figures 12 and 13, in the first region OA, which is the optical region OA, three data lines (red data line DL(R), blue data line DL(B), and green data line DL(G)) can be arranged repeatedly.

[0391] Referring to Figures 12 and 13, in the first region OA, the green data line is omitted in region 1200 between the red data line DL(R) and the blue data line DL(B). Therefore, the amount of metal can be reduced within the first region OA, which is the optical region OA. This lowers the metal ratio in the first region OA, which is the optical region OA, and increases the transmittance.

[0392] In Figures 12 and 13, the green data line DL(G) corresponds to the first data line DL1 in Figure 11; in Figures 12 and 13, the blue data line DL(B) corresponds to the second data line DL2 in Figure 11; and in Figures 12 and 13, the red data line DL(R) corresponds to the third data line DL3 in Figure 11.

[0393] Referring to Figures 12 and 13, the third data line DL3, which is the red data line DL(R), can be superimposed on the red pixel electrode PE(R).

[0394] The region 1200, where the green data line is omitted, is directly adjacent to the third data line DL3, which is the red data line DL(R), and can be superimposed on the red pixel electrode PE(R).

[0395] In the upper region NA1 of the second region NA, which is a general region NA, the red pixel electrode PE(R) overlaps with the two data lines DL(R) and DL(G)_U, and in the lower region NA2 of the second region NA, which is a general region NA, the red pixel electrode PE(R) can also overlap with the two data lines DL(R) and DL(G)_D.

[0396] However, as mentioned above, in the first region OA, which is the optical region OA, the red pixel electrode PE(R) overlaps with only one data line DL(R). As a result, the emission characteristics of the red subpixel in the first region OA may differ from those of the red subpixel in the second region NA.

[0397] To reduce such variations in luminescence characteristics, the third data line DL3, which is the red data line DL(R), may include a protrusion 1210, as shown in Figures 12 and 13. The protrusion 1210 can be superimposed on the red pixel electrode PE(R) in the first region OA.

[0398] That is, referring to Figures 12 and 13, the third data line DL3, which is the red data line DL(R), can overlap with the 11th subpixel PE11, which is the red subpixel PE(R), in Figure 11. The third data line DL3, which is the red data line DL(R), may include a protrusion 1210 that extends into the region 1200 where the green data line is omitted.

[0399] The protrusion 1210 can overlap with the red subpixel PE(R), which is the 11th subpixel PE11 in Figure 11, in the direction of the data line length (column direction, data line extension direction).

[0400] Referring to Figures 12 and 13, the third pixel electrode PE3, the connecting wiring CW, and the fourth pixel electrode PE4 can be constructed integrally. That is, the connecting wiring CW can be made of the pixel electrode material.

[0401] Referring to Figure 12, in the first region OA, the first data line DL1 and the second data line DL2 may be located within the same metal layer (second metal layer) and spaced apart on the same plane. Similarly, in the second region NA, the first data line DL1 and the second data line DL2 may be located within the same metal layer (second metal layer) and spaced apart on the same plane.

[0402] Referring to Figure 13, in at least a portion of the first region OA, the first data line DL1 and the second data line DL2 may be located in different metal layers (first metal layer, second metal layer). Alternatively, in the second region NA, the first data line DL1 and the second data line DL2 may be located within the same metal layer (second metal layer).

[0403] In other words, in the second region NA, the first data line DL1 and the second data line DL2 may be located within the same metal layer and spaced apart from each other on the same plane. Of the transparent region TA and the opaque region NTA included in the first region OA, in the transparent region TA, the first data line DL1 and the second data line DL2 may be located within different metal layers (first metal layer, second metal layer) and overlap vertically. Of the transparent region TA and the opaque region NTA included in the first region OA, in the opaque region NTA, the first data line DL1 and the second data line DL2 may be located within the same metal layer (second metal layer) and spaced apart from each other on the same plane.

[0404] Referring to Figure 13, for example, the first metal layer is the metal layer between the second interlayer insulating layer 823 and the first planarization layer 831, and may be the first source-drain metal layer. The second metal layer is the metal layer between the first planarization layer 831 and the second planarization layer 832, and may be the second source-drain metal layer. For example, the blue data line DL(B), which is the second data line DL2, may be located within the first metal layer, and the green data line DL(G), which is the first data line DL1, may be located within the second metal layer.

[0405] Figures 14 to 18 are cross-sectional views of a display panel 110 having a transmittance improvement structure according to an embodiment of the present disclosure. However, the laminated structure in the cross-sectional views of Figures 14 to 18 is the same as that in Figures 8 and 9. Therefore, a description of the laminated structure is omitted. In the following description, Figures 11 to 13 will also be referred to.

[0406] Figure 14 is a cross-sectional view taken along the line X1-X2 in Figures 12 and 13, Figure 15 is a cross-sectional view taken along the line X3-X4 in Figures 12 and 13, Figure 16 is a cross-sectional view taken along the line X5-X6 in Figure 13, Figure 17 is a cross-sectional view taken along the line X7-X8 in Figure 13, and Figure 18 is a cross-sectional view taken along the line X9-X10 in Figure 13.

[0407] Referring to Figure 14, the region where the X1-X2 line is displayed in Figures 12 and 13 contains a blue light-emitting region EA_B of a blue subpixel and a red light-emitting region EA_R of a red subpixel. In other words, a blue pixel electrode PE(B) and a red pixel electrode PE(R) can be placed in the region where the X1-X2 line is displayed in Figures 12 and 13.

[0408] Referring to Figure 14, the region where the X1-X2 line is shown in Figures 12 and 13 can be used to place the transistor TFTs included in the green subpixel circuit SPC(G), the transistor TFTs included in the blue subpixel circuit SPC(B), and the transistor TFTs included in the red subpixel circuit SPC(R).

[0409] These transistor TFTs may include a first active layer ACT1 and a first gate electrode GE1 on the first active layer ACT1. The first active layer ACT1 may include a silicon-based semiconductor material as the active layer of the lower transistor. For example, the silicon-based semiconductor material may include low-temperature polycrystalline silicon (LTPS).

[0410] A shielding metal SM may be placed below the transistor TFT, superimposed on the first active layer ACT1. The shielding metal SM can be placed between the multi-buffer layer 811a and the active buffer layer 811b.

[0411] A first upper metal TM1 may be placed on top of the transistor TFT, overlapping with the first gate electrode GE1. The first upper metal TM1 may be placed between the first interlayer insulating layer 813 and the second buffer layer 821.

[0412] Referring to Figure 14, the metal layer between the second interlayer insulating layer 823 and the first planarization layer 831 is called the first metal layer, and the metal layer between the first planarization layer 831 and the second planarization layer 832 is called the second metal layer. As shown in Figure 14, the second metal layer may be a metal layer located above the first metal layer.

[0413] Various horizontal wirings extending in the horizontal direction may be arranged within the first metal layer, and various vertical wirings extending in the vertical direction may be arranged within the second metal layer.

[0414] Referring to Figure 14, data lines DL(R), DL(G), and DL(B), which are a type of vertical wiring, can be placed within the second metal layer. Power wiring PWL, another type of vertical wiring, can also be placed within the second metal layer.

[0415] Referring to Figure 14, the power supply wiring PWL, unlike the data lines DL(R), DL(G), and DL(B), may be wiring to which a power supply voltage is applied that does not change in voltage level due to frame changes. For example, the power supply wiring PWL may include at least one of the drive voltage line VDDL and the base voltage line VSSL.

[0416] As mentioned above, the power supply wiring PWL can be placed within the same metal layer (second metal layer) as the longitudinal bypass wiring V_BW.

[0417] Referring to Figure 14, one of the two red data lines DL(R) that overlap with the red pixel electrode PE(R) corresponds to the protrusion 1210 that protrudes from the red data line DL(R), which is the third data line DL3 in Figures 12 and 13.

[0418] Referring to Figure 15, the two green pixel electrodes PE(G), the third pixel electrode PE3 and the fourth pixel electrode PE4, can be connected to each other via a connecting wire CW.

[0419] Referring to Figure 15, the third pixel electrode PE3 and the fourth pixel electrode PE4 can be configured integrally with the connecting wiring CW.

[0420] Referring to Figure 15, below the fourth pixel electrode PE4, a second active layer ACT2 on the second buffer layer 821 and a second gate metal GM2 corresponding to the second gate electrode GE2 on the second active layer ACT2 can be placed.

[0421] Referring to Figure 15, the first upper metal TM1 can be placed between the first interlayer insulating layer 813 and the second buffer layer 821, and the first gate metal GM1 can be placed between the first gate insulating layer 812 and the first interlayer insulating layer 813.

[0422] Referring to Figure 16, the area where the X5-X6 line is displayed is the boundary region between the transparent region TA and the opaque region NTA.

[0423] Referring to Figure 16, in the region where the X5-X6 line is shown, the second data line DL2 may include an upper portion located in the same second metal layer as the first data line DL1, a lower portion located in the first metal layer lower than the second metal layer, a connecting portion connecting the upper and lower portions, and an extension portion extending below the first data line DL1.

[0424] Referring to Figure 16, in the region where the X5-X6 line is displayed, the second data line DL2 descends vertically and shifts horizontally so as to overlap with the first data line DL1. Here, the first data line DL1 may be the green data line DL(G), and the second data line DL2 may be the blue data line DL(B).

[0425] Referring to Figure 16, in the region where the X5-X6 line is shown, the first data line DL1 may be the first upper data line DL(G)_ML2 located in the second metal layer. The second data line DL2 may include the second lower data line DL(B)_ML1 located in the first metal layer and the second upper data line DL(B)_ML2 located in the second metal layer.

[0426] Referring to Figure 16, the upper blue data line DL(B)_ML2 can be connected to the lower blue data line DL(B)_ML1 through a hole in the first planarization layer 831. The lower blue data line DL(B)_ML1 can extend slightly horizontally and overlap with the upper green data line DL(G)_ML2.

[0427] Referring to Figure 17, the region where the X7-X8 line is displayed is the region included in the transmission region TA. In the region where the X7-X8 line is displayed, the first data line DL1 and the second data line DL2 can be superimposed in the vertical direction.

[0428] Referring to Figure 17, in the region where the X7-X8 line is shown, the first data line DL1 may be the first upper data line DL(G)_ML2 located in the second metal layer, and the second data line DL2 may be the second lower data line DL(B)_ML1 located in the first metal layer.

[0429] Referring to Figure 17, the area where the X7-X8 line is displayed is the area included in the transmission region TA. In the area where the X7-X8 line is displayed, the first data line DL1 and the second data line DL2 overlap vertically, which significantly improves the transmittance of the transmission region TA.

[0430] Referring to Figure 18, the region where the X9-X10 line is displayed is a region included in the opaque region NTA, and may also be a subpixel circuit region.

[0431] Referring to Figure 18, in the opaque region NTA, the first data line DL1 may include a first lower data line DL(G)_ML1 located within the first metal layer and a first upper data line DL(G)_ML2 located within a second metal layer different from the first metal layer.

[0432] The first lower data line DL(G)_ML1 and the first upper data line DL(G)_ML2 can be electrically connected to each other through holes in the first planarization layer 831, which is an insulating layer between the first metal layer and the second metal layer.

[0433] Referring to Figure 18, in the opaque region NTA, the second data line DL2 may include a second lower data line DL(B)_ML1 located within the first metal layer and a second upper data line DL(B)_ML2 located within the second metal layer.

[0434] The second lower data line DL(B)_ML1 and the second upper data line DL(B)_ML2 can be electrically connected to each other through other holes in the first planarization layer 831, which is an insulating layer.

[0435] Figure 19 is a cross-sectional view of the connection area between the vertical bypass wiring V_BW and the horizontal bypass wiring H_BW in the display panel 110 according to an embodiment of the present disclosure. However, the laminated structure in the cross-sectional view of Figure 19 is the same as that in Figures 8 and 9. Therefore, a description of the laminated structure is omitted. In the following description, Figures 11 to 13 will also be referred to.

[0436] Referring to Figure 19, the lateral bypass wiring H_BW can be placed in the first metal layer, and the longitudinal bypass wiring V_BW can be placed in a second metal layer different from the first metal layer.

[0437] Referring to Figure 19, the longitudinal bypass wiring V_BW can be connected to the transverse bypass wiring H_BW through holes in the first planarization layer 831, which is an insulating layer placed between the first metal layer and the second metal layer.

[0438] Referring to Figure 19, the region where the lateral bypass wiring H_BW and the longitudinal bypass wiring V_BW are located may be a second region NA, which is a general region NA.

[0439] Referring to Figure 19, the second region NA contains the light-emitting region EA of a subpixel, and a pixel electrode PE can be placed therefor. Furthermore, a transistor TFT included in the subpixel circuit of the subpixel may be placed in the second region NA.

[0440] For example, each of the first subpixel SP1, second subpixel SP2, third subpixel SP3, fifth subpixel SP5, and sixth subpixel SP6 shown in Figure 11 includes a light-emitting element ED and a subpixel circuit SPC(G), and the subpixel circuit SPC(G) may include two or more transistors (TFTs; DT, ST).

[0441] The fourth subpixel SP4 includes the light-emitting element ED but does not include the subpixel circuit SPC(G). The source and drain electrodes of two or more transistor TFTs can be placed in the same first metal layer as the lateral bypass wiring H_BW.

[0442] The first data line DL1, the upper data line DL(G)_U, and the lower data line DL(G)_D can be placed within the same second metal layer as the longitudinal bypass wiring V_BW.

[0443] Referring to Figures 14 to 19, the display device 100 according to the embodiment of the present disclosure may further include an electronic device 800 located below the substrate SUB, overlapping with the first region OA, and performing a predetermined operation using light transmitted through the first region OA.

[0444] The embodiments of this disclosure described above can be briefly described as follows.

[0445] A display device according to an embodiment of the present disclosure may include a substrate comprising a display area capable of displaying an image and a non-display area outside the display area, a plurality of subpixels included in the display area, each comprising a plurality of light-emitting elements, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels.

[0446] The display area may include a first area that can transmit light and a second area located outside the first area. The second area may include an upper area located above the first area and a lower area located below the first area.

[0447] Multiple data lines may include a first data line that passes through the upper region, the first region, and the lower region, an upper data line located in the upper region, a lower data line located in the lower region, and bypass wiring that electrically connects the upper and lower data lines and bypasses the first region.

[0448] The bypass wiring may include a first bypass wiring connected to the upper data line, a second bypass wiring connected to the lower data line, and a third bypass wiring connecting the first and second bypass wirings.

[0449] Bypass wiring can include lateral bypass wiring extending laterally and vertical bypass wiring extending vertically. The first and second bypass wiring may be lateral bypass wiring, and the third bypass wiring may be vertical bypass wiring.

[0450] Lateral bypass wiring may be arranged on a first metal layer, while longitudinal bypass wiring may be arranged on a second metal layer different from the first metal layer.

[0451] The display device according to the embodiments of the present disclosure may further include power wiring to which a power supply voltage is applied that does not change in voltage level with respect to changes in the frame. The power wiring may be located within a second metal layer.

[0452] Power wiring can be placed within the same metal layer as longitudinal bypass wiring.

[0453] Multiple light-emitting elements may each contain multiple pixel electrodes.

[0454] The multiple pixel electrodes may include a first pixel electrode located in the upper region and contained within a first subpixel, a second pixel electrode located in the upper region and contained within a second subpixel, a third pixel electrode located in the first region and contained within a third subpixel, a fourth pixel electrode located in the first region and contained within a fourth subpixel, a fifth pixel electrode located in the lower region and contained within a fifth subpixel, and a sixth pixel electrode located in the lower region and contained within a sixth subpixel.

[0455] The first data line can be connected to the first subpixel, the third subpixel, and the fifth subpixel.

[0456] The upper data line can be connected to the second subpixel.

[0457] The lower data line can be connected to the sixth subpixel.

[0458] In the display device according to the embodiment of this disclosure, the third pixel electrode and the fourth pixel electrode can be electrically connected.

[0459] The emission colors of the first, second, third, fourth, fifth, and sixth subpixels may be the same.

[0460] The first, second, third, fifth, and sixth subpixels may each include a light-emitting element and a subpixel circuit that drives the light-emitting element. The subpixel circuit may include two or more transistors.

[0461] The fourth subpixel includes an light-emitting element, but does not necessarily include a subpixel circuit. In this case, the light-emitting element of the fourth subpixel can be driven by the subpixel circuit of the third subpixel.

[0462] The drive current output from the subpixel circuit of the third subpixel can be supplied to the third pixel electrode and the fourth pixel electrode.

[0463] The display device according to the embodiments of the present disclosure may further include connecting wiring arranged in a first region and electrically connecting a third pixel electrode and a fourth pixel electrode.

[0464] The third pixel electrode, the connecting wiring, and the fourth pixel electrode may be configured as a single unit.

[0465] The multiple pixel electrodes may further include a seventh pixel electrode located in the upper region and contained within a seventh subpixel, an eighth pixel electrode located in the second region and contained within an eighth subpixel, and a ninth pixel electrode located in the lower region and contained within a ninth subpixel.

[0466] Multiple data lines may further include second data lines connected to the seventh, eighth, and ninth subpixels.

[0467] The emission colors of the seventh, eighth, and ninth subpixels may differ from the emission colors of the first, second, third, fourth, fifth, and sixth subpixels.

[0468] The second data line may intersect and overlap with the portion where the third and fourth pixel electrodes are connected (i.e., the connection wiring).

[0469] In one example, in the first and second regions, the first data line and the second data line may be located within the same metal layer and spaced apart on the same plane.

[0470] In another example, in the second region, the first data line and the second data line may be located within the same metal layer. In at least a portion of the first region, the first data line and the second data line may be located within different metal layers.

[0471] For example, in the second region, the first data line and the second data line may be located within the same metal layer and spaced apart from each other on the same plane. The first region may include a transparent region and an opaque region. In the transparent region, the first data line and the second data line may be located within different metal layers and overlap vertically. In the opaque region, the first data line and the second data line may be located within the same metal layer and spaced apart from each other on the same plane.

[0472] The multiple pixel electrodes may further include a 10th pixel electrode located in the upper region and contained within a 10th subpixel, an 11th pixel electrode located in the first region and contained within an 11th subpixel, and a 12th pixel electrode located in the lower region and contained within a 12th subpixel.

[0473] The data lines may further include a third data line connected to the 10th subpixel, the 11th subpixel, and the 12th subpixel.

[0474] The third data line can overlap with the tenth pixel electrode.

[0475] The third data line includes a protruding portion, which may overlap the 11th pixel electrode in the direction of the data line length. The emission colors of the 10th subpixel, the 11th subpixel, and the 12th subpixel may differ from the emission colors of the 1st subpixel, the 2nd subpixel, the 3rd subpixel, the 4th subpixel, the 5th subpixel, and the 6th subpixel.

[0476] The display device according to the embodiments of this disclosure may further include a common electrode arranged on a plurality of pixel electrodes.

[0477] Within the first region, the common electrode may have multiple common electrode holes.

[0478] The display device according to the embodiments of the present disclosure may further include an electronic device located below the substrate, overlapping with the first region, and performing a predetermined operation using light transmitted through the first region.

[0479] A display device according to an embodiment of the present disclosure may include a second interlayer insulating layer on a substrate; a first planarizing layer on the second interlayer insulating layer; and a second planarizing layer on the first planarizing layer. The first metal layer may be located between the second interlayer insulating layer and the first planarizing layer, and the second metal layer may be located between the first planarizing layer and the second planarizing layer.

[0480] A display device according to an embodiment of the present disclosure may include a substrate having a display area capable of displaying an image and a non-display area outside the display area, a plurality of subpixels included in the display area and each having a plurality of pixel electrodes, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels.

[0481] The display area may include a first area that can transmit light and a second area located outside the first area.

[0482] The second region may include an upper region located above the first region and a lower region located below the first region.

[0483] The multiple pixel electrodes may include a first pixel electrode located in the upper region and contained within a first subpixel, a second pixel electrode located in the upper region and contained within a second subpixel, a third pixel electrode located in the first region and contained within a third subpixel, a fourth pixel electrode located in the first region and contained within a fourth subpixel, a fifth pixel electrode located in the lower region and contained within a fifth subpixel, and a sixth pixel electrode located in the lower region and contained within a sixth subpixel.

[0484] Multiple data lines may include a first data line that extends from the upper region through the first region to the lower region and connects to the first, third, and fifth subpixels; an upper data line located in the upper region and connected to the second subpixel; and a lower data line located in the lower region and connected to the sixth subpixel.

[0485] The third pixel electrode and the fourth pixel electrode may be electrically connected.

[0486] The display device according to the embodiments of the present disclosure may further include connecting wiring arranged in a first region and electrically connecting a third pixel electrode and a fourth pixel electrode.

[0487] A display device according to an embodiment of the present invention may include a substrate including a display area capable of displaying an image and a non-display area outside the display area, a plurality of subpixels included in the display area, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels. The display area may include a first area that can transmit light and a second area located outside the first area. Some of the plurality of data lines may pass through the first area, while other parts of the plurality of data lines may bypass the first area.

[0488] According to the embodiments of the present disclosure described above, it is possible to provide a display device having a light-transmitting structure that allows an electronic device to receive light (for example, visible light, infrared light, or ultraviolet light) to be received normally without the electronic device being exposed to the front.

[0489] According to embodiments of this disclosure, a display device can be provided that can improve the transmittance of an optical region (first region) through which light can pass.

[0490] According to embodiments of this disclosure, it is possible to provide a display device having a structure that reduces the metal ratio in an optical region (first region) through which light can pass.

[0491] According to embodiments of this disclosure, it is possible to provide a display device having a panel structure that can improve the sensing performance of a sensing sensor that uses light transmitted through an optical region (first region).

[0492] According to embodiments of this disclosure, it is possible to provide a display device having a panel structure that can improve the camera performance of a camera that uses light transmitted through an optical region (first region).

[0493] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only, and not to limit the technical concept of this disclosure, and the scope of the technical concept of this disclosure is not limited by such embodiments.

Claims

1. A substrate including a display area capable of displaying an image and a non-display area outside the display area, The display area includes a plurality of subpixels, each containing a plurality of light-emitting elements, and The plurality of subpixels include a plurality of data lines for supplying data signals for image display, The display area includes a first area that can transmit light and a second area located outside the first area, and the second area includes an upper area located above the first area and a lower area located below the first area. The aforementioned multiple data lines are, The upper data line arranged in the upper region, The lower data line arranged in the lower region, and The upper data line and the lower data line are electrically connected, and the wiring includes bypass wiring that bypasses the first region, The aforementioned bypass wiring is Lateral bypass wiring, and Including vertical bypass wiring extending in the vertical direction, The aforementioned lateral bypass wiring is arranged in the first metal layer. The longitudinal bypass wiring is arranged on a second metal layer different from the first metal layer, in a display device.

2. The display device according to claim 1, wherein the plurality of data lines further include a first data line extending from the upper region to the lower region.

3. The aforementioned lateral bypass wiring is, The first bypass wiring connected to the upper data line, and This includes a second bypass wiring connected to the lower data line, The display device according to claim 1, wherein the longitudinal bypass wiring includes a third bypass wiring connecting the first bypass wiring and the second bypass wiring.

4. The display device according to claim 1, wherein the intersection of the bypass wiring and the upper data line and the intersection of the bypass wiring and the lower data line have connection points.

5. A first connection point is formed at the intersection of the upper data line and the first bypass wiring. A second connection point is formed at the intersection of the lower data line and the second bypass wiring. A third connection point is formed at the intersection of the first bypass wiring and the third bypass wiring. The display device according to claim 3, wherein a fourth connection point is formed at the intersection of the second bypass wiring and the third bypass wiring.

6. A first connection point is formed at the intersection of the upper data line and the lateral bypass wiring. A second connection point is formed at the intersection of the lower data line and the lateral bypass wiring. The display device according to claim 1, wherein a third connection point and a fourth connection point are formed at the intersection of the lateral bypass wiring and the longitudinal bypass wiring, respectively.

7. The display device according to claim 1, wherein the second metal layer is located above the first metal layer.

8. The display device according to claim 1, wherein the lateral bypass wiring, the upper data line, and the lower data line form a mesh configuration.

9. The power supply wiring further includes a power supply voltage to which the voltage level does not change due to frame changes, The display device according to claim 1, wherein the power supply wiring is arranged within the second metal layer.

10. Each of the plurality of light-emitting elements includes a plurality of pixel electrodes, The aforementioned plurality of pixel electrodes are The first pixel electrode, which is located in the upper region and is included in the first subpixel, The upper region is arranged and includes a second pixel electrode within the second subpixel, A third pixel electrode, located in the first region and included in the third subpixel, A fourth pixel electrode, located in the first region and included in the fourth subpixel, The lower region is located and includes a fifth pixel electrode within the fifth subpixel, and The lower region is located and includes a sixth pixel electrode that is part of the sixth subpixel, The upper data line is connected to the second subpixel, The lower data line is connected to the sixth subpixel, The display device according to claim 1, wherein the third pixel electrode and the fourth pixel electrode are electrically connected to each other.

11. The plurality of data lines further include a first data line extending from the upper region to the lower region, The display device according to claim 10, wherein the first data line is connected to the first subpixel, the third subpixel, and the fifth subpixel.

12. The display device according to claim 11, wherein the emission colors of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel, and the sixth subpixel are the same.

13. Each of the first subpixel, second subpixel, third subpixel, fifth subpixel, and sixth subpixel includes a light-emitting element and a subpixel circuit for driving the light-emitting element, and the subpixel circuit includes two or more transistors. The display device according to claim 11, wherein the fourth subpixel includes an light-emitting element but does not include a subpixel circuit, and the light-emitting element of the fourth subpixel is driven by the subpixel circuit of the third subpixel.

14. The display device according to claim 13, wherein the drive current output from the subpixel circuit of the third subpixel is supplied to the third pixel electrode and the fourth pixel electrode.

15. The display device according to claim 10, further comprising connecting wiring arranged in the first region and electrically connecting the third pixel electrode and the fourth pixel electrode.

16. The aforementioned plurality of pixel electrodes are The seventh pixel electrode, located in the upper region and included in the seventh subpixel, An eighth pixel electrode, which is located in the first region and is included in the eighth subpixel, and The lower region is further comprising a ninth pixel electrode located within the ninth subpixel, The display device according to claim 10, wherein the emission colors of the seventh subpixel, the eighth subpixel, and the ninth subpixel are different from the emission colors of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel, and the sixth subpixel, respectively.

17. The aforementioned multiple data lines are, The display device according to claim 16, further comprising a second data line connected to the seventh subpixel, the eighth subpixel, and the ninth subpixel.

18. The display device according to claim 17, wherein the second data line intersects and overlaps with the portion where the third pixel electrode and the fourth pixel electrode are connected.

19. The plurality of data lines further include a first data line extending from the upper region to the lower region, The display device according to claim 17, wherein in the first region and the second region, the first data line and the second data line are arranged within the same metal layer and spaced apart on the same plane.

20. The plurality of data lines further include a first data line extending from the upper region to the lower region, In the second region, the first data line and the second data line are arranged within the same metal layer. The display device according to claim 17, wherein in at least a portion of the first region, the first data line and the second data line are arranged on different metal layers.

21. In the second region, the first data line and the second data line are arranged within the same metal layer and spaced apart from each other on the same plane. The first region includes a transparent region and an opaque region, In the transparent region, the first data line and the second data line are arranged in different metal layers and are superimposed vertically. The display device according to claim 20, wherein in the non-transparent region, the first data line and the second data line are arranged within the same metal layer and spaced apart from each other on the same plane.

22. The aforementioned plurality of pixel electrodes are The 10th pixel electrode, which is located in the upper region and is included in the 10th subpixel, An eleventh pixel electrode, which is located in the first region and is included in the eleventh subpixel, and The lower region is further comprising a 12th pixel electrode located within the 12th subpixel, The display device according to claim 10, wherein the emission colors of the 10th subpixel, the 11th subpixel, and the 12th subpixel are different from the emission colors of the 1st subpixel, the 2nd subpixel, the 3rd subpixel, the 4th subpixel, the 5th subpixel, and the 6th subpixel, respectively.

23. The aforementioned multiple data lines are, The system further includes a third data line connected to the tenth subpixel, the eleventh subpixel, and the twelfth subpixel, The third data line is superimposed on the tenth pixel electrode, The display device according to claim 22, wherein the third data line includes a projection, the projection superimposed on the eleventh pixel electrode in the longitudinal direction of the data line.

24. It further includes a common electrode placed on multiple pixel electrodes, The display device according to claim 1, wherein the common electrode has a plurality of common electrode holes within the first region.

25. The display device according to claim 1, further comprising an electronic device located below the substrate and overlapping with the first region, which performs a predetermined operation using light transmitted through the first region.

26. The second interlayer insulating layer on the substrate, The first planarization layer on the second interlayer insulating layer, and The present invention further includes a second planarization layer on the first planarization layer, The display device according to any one of claims 1 to 25, wherein the first metal layer is located between the second interlayer insulating layer and the first planarization layer, and the second metal layer is located between the first planarization layer and the second planarization layer.

27. A substrate including a display area capable of displaying an image and a non-display area outside the display area, The display area includes a plurality of subpixels, each containing a plurality of pixel electrodes, and The plurality of subpixels include a plurality of data lines for supplying data signals for image display, The display area includes a first area that can transmit light and a second area located outside the first area. The second region includes an upper region located above the first region and a lower region located below the first region. The aforementioned plurality of pixel electrodes are The first pixel electrode, which is located in the upper region and is included in the first subpixel, The upper region is arranged and includes a second pixel electrode within the second subpixel, A third pixel electrode, located in the first region and included in the third subpixel, A fourth pixel electrode, located in the first region and included in the fourth subpixel, The lower region is located and includes a fifth pixel electrode within the fifth subpixel, and The lower region is located and includes a sixth pixel electrode that is part of the sixth subpixel, The aforementioned multiple data lines are, An upper data line located in the upper region and connected to the second subpixel, and The lower region includes a lower data line that is located in the lower region and connected to the sixth subpixel, A display device in which the third pixel electrode and the fourth pixel electrode are electrically connected to each other.

28. The aforementioned multiple data lines are, The display device according to claim 27, further comprising a first data line extending from the upper region to the lower region and connected to the first subpixel, the third subpixel, and the fifth subpixel.

29. The display device according to claim 27 or 28, further comprising connecting wiring arranged in the first region and electrically connecting the third pixel electrode and the fourth pixel electrode.

30. A substrate including a display area capable of displaying an image and a non-display area outside the display area, Multiple subpixels included in the display area, and The plurality of data lines include a plurality of data lines for supplying data signals for image display to the plurality of subpixels, The display area includes a first area that can transmit light and a second area located outside the first area. The plurality of data lines include upper and lower data lines positioned above and below the first region, respectively, and at least one bypass wiring that electrically connects the upper data line and the lower data line and bypasses the first region. The at least one bypass wiring includes a lateral bypass wiring extending laterally and a longitudinal bypass wiring extending vertically, The lateral bypass wiring is arranged in a first metal layer, and the longitudinal bypass wiring is arranged in a second metal layer different from the first metal layer. A display device in which at least one of the plurality of data lines includes a portion arranged in an upper layer and a portion arranged in a lower layer on the substrate.

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