Semiconductor equipment

Abstract

To solve the problem in which conventional semiconductor devices cannot sufficiently reduce power consumption by bus clock stopping.SOLUTION: A semiconductor device according to an embodiment has: a level detection unit 17 that validates a level detection signal LD when a value indicated by stream data exceeds a threshold condition value; a ring buffer 18 that cyclically and sequentially stores internal data generated from the stream data in a storage area that is set within a predetermined address range; a data processing unit 12 that operates with a bus clock and performs data processing using the internal data acquired from the ring buffer 18; and an address adjustment unit 44 that adjusts a read address indicating a read start position of the ring buffer 18 to a position that becomes a predetermined difference from a write address of the ring buffer at that time in accordance with a start of generation of the bus clock, wherein a bus clock is generated during a period in which the level detection signal LD is valid.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005] , ,

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device having a ring buffer that updates data cyclically accumulated within a predetermined address range.

Background Art

[0002] In a semiconductor device that performs information processing on stream data transmitted continuously in time, the core clock used for capturing the stream data and the bus clock or system clock that operates a system including an information processing unit that performs specific processing within the semiconductor device often have different frequencies. Therefore, in such a semiconductor device, in order to absorb the speed difference between the stream data capture unit and the information processing unit, it has a speed difference absorption function such as a ring buffer. Thus, an example of a ring buffer is disclosed in Patent Document 1.

[0003] The ring buffer circuit described in Patent Document 1 includes a read / write memory having an address specified by N bits, a write address counter pointer and a read address counter pointer for counting an N + 1-bit Gray code of the read / write memory, and a write / read address conversion circuit that converts the N + 1-bit Gray code output by the write and read address counter pointers into an N-bit address that can be directly specified as the write and read addresses of the read / write memory.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a level detection unit that activates a level detection signal when the value indicated by stream data exceeds a threshold condition value, a ring buffer that cyclically stores internal data generated from stream data sequentially in a storage area set within a predetermined address range, a data processing unit that operates on a bus clock and processes data using the internal data acquired from the ring buffer, and an address adjustment unit that adjusts the read address indicating the start position of reading from the ring buffer to a position that is a predetermined difference from the write address of the ring buffer at that time, in conjunction with the start of bus clock generation, and generates a bus clock during the period in which the level detection signal is active. [Effects of the Invention]

[0008] In one embodiment of the semiconductor device, power consumption can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram of a semiconductor device according to Embodiment 1. [Figure 2] This diagram illustrates the processing of the address adjustment section of the ring buffer according to Embodiment 1. [Figure 3] This is a flowchart illustrating the operation of the semiconductor device according to Embodiment 1. [Figure 4] This is a timing chart illustrating the operation of the semiconductor device according to Embodiment 1. [Figure 5] This is a detailed timing chart illustrating the operation of the semiconductor device according to Embodiment 1. [Figure 6] This is a block diagram of a semiconductor device according to Embodiment 2. [Figure 7] This is a flowchart illustrating the operation of the semiconductor device according to Embodiment 2. [Figure 8] This is a timing chart illustrating the operation of the semiconductor device according to Embodiment 2. [Figure 9] This is a detailed timing chart illustrating the operation of the semiconductor device according to Embodiment 2. [Figure 10] This is a block diagram of a first example of the level detection unit according to Embodiment 3. [Figure 11] This is a block diagram of a second example of the level detection unit according to Embodiment 3. [Modes for carrying out the invention]

[0010] For clarity, the following descriptions and drawings have been omitted and simplified as appropriate. Furthermore, the same elements are denoted by the same reference numerals in each drawing, and redundant explanations have been omitted where necessary.

[0011] Embodiment 1 First, Figure 1 shows a block diagram of the semiconductor device 1 according to Embodiment 1. As shown in Figure 1, the semiconductor device 1 according to Embodiment 1 includes a data receiving unit 10, a system controller 11, an arithmetic unit (CPU (Central Processing Unit) in Figure 1) 12, a DMAC (Direct Memory Access Controller) 13, a memory 14, a bus clock generation unit 15, a register 16, a level detection unit 17, and a ring buffer 18. In Figure 1, SRAM (Static Random Access Memory) is shown as the memory, but other storage devices available in computers, such as DRAM (Dynamic Random Access Memory) and flash memory, can be used.

[0012] The data receiving unit 10 converts stream data supplied from an external source into internal data that can be processed internally (write data WDT in Figure 1). For example, if the stream data is a time-continuous analog signal, the data receiving unit 10 converts the analog signal into digital data that can be processed internally by analog-to-digital conversion to generate the write data WDT. Alternatively, if the digital values ​​of the stream data are transmitted sequentially as serial data, the data receiving unit 10 converts the serial data into parallel data to generate the write data WDT. The data receiving unit 10 also operates based on the core clock used to acquire the stream data when generating the write data WDT. This core clock may be generated within the semiconductor device 1 or generated outside the semiconductor device 1. The data receiving unit 10 also outputs a write enable WEN, which indicates the output timing of the write data WDT, synchronized with the write data WDT.

[0013] The system controller 11 operates the bus clock generation unit 15 during the period when the level detection signal LD indicates an active state. Also, the system controller 11 controls the switching of the operating state of the bus clock generation unit 15 according to the state of the level detection signal LD, and rewrites the values of a plurality of registers in the register 16 that controls the operations of the level detection unit 17 and the ring buffer 18. Also, it is assumed that the portion related to the reception processing of the level detection signal LD operates based on the core clock, and the other portions operate based on the bus clock.

[0014] The arithmetic unit 12 performs information processing using the read data RDT read from the ring buffer 18 using the DMAC 13. The information processing performed by the arithmetic unit 12 differs according to the type of the read data RDT but is processing defined based on the specifications of the semiconductor device 1. The DMAC 13 is a memory interface circuit and is controlled by the arithmetic unit 12. The DMAC 13 performs specific processing of data transmission and reception between the arithmetic unit 12 and the memory 14, and between the arithmetic unit 12 and the ring buffer 18. The memory 14 is a storage device used in the information processing of the arithmetic unit 12. The bus clock generation unit 15 generates a bus clock used within the semiconductor device 1. Whether the bus clock generation unit 15 generates a bus clock is controlled by the system controller 11.

[0015] The register 16 includes a plurality of registers in which setting values that define the operations of the semiconductor device 1 are stored. In the example shown in FIG. 1, at least a threshold setting register, a level detection clear register, a data accumulation amount register, and a bus clock supply signal register are included.

[0016] Note that the threshold setting value Th, the level detection clear signal LDC, the data accumulation amount DS, and the bus clock supply signal CB_EN may be signals directly output by the system controller 11 without using registers.

[0017] The threshold setting register stores a threshold setting value Th that is used by the level detection unit 17 to determine the validity of the stream data. This threshold setting value Th is a value written by the system controller 11 or another external device.

[0018] The level detection clear register generates a level detection clear signal LDC for clearing the level detection signal LD to 0 by a write access from the arithmetic unit 12. The value stored in the level detection clear register is determined by the system controller 11 based on the operation sequence and the value of the level detection signal LD, and the arithmetic unit 12 rewrites it upon receiving the determination of the system controller 11.

[0019] The data accumulation amount register stores a data accumulation amount DS indicating the amount of data accumulated in the ring buffer 18. The data accumulation amount DS is rewritten by the ring buffer 18 and referred to by the arithmetic unit 12. The arithmetic unit 12 changes the number of data readouts or changes the content of information processing according to the data accumulation amount DS.

[0020] The bus clock supply signal register stores the logical value of a bus clock supply signal CB_EN that notifies the operating state of the bus clock generation unit 15. The value stored in the bus clock supply signal register is updated by the system controller 11. The system controller 11 rewrites the value of the bus clock supply signal register to a state where bus clock supply is valid (for example, high level) in response to the bus clock generation unit 15 starting to generate the bus clock, and rewrites the value of the bus clock supply signal register to a state where bus clock supply is stopped (for example, low level) in response to the bus clock generation unit 15 stopping the generation of the bus clock.

[0021] The level detection unit 17 activates the level detection signal LD ​​when the value indicated by the internal data (e.g., the written data WDT) exceeds the threshold condition value. In the example shown in Figure 1, a threshold setting value Th is given as the threshold condition. For example, if the stream data is an analog signal, the level detection unit 17 activates the level detection signal LD ​​when the level of the analog signal exceeds the value indicated by the threshold setting value Th.

[0022] In the example shown in Figure 1, the level detection unit 17 includes an upper threshold comparison unit 20 and a detection control unit 21. The upper threshold comparison unit 20 determines whether the value indicated by the write data WDT exceeds the threshold setting value Th and outputs the determination result to the detection control unit 21. The upper threshold comparison unit 20 also performs a comparison of the magnitude of the write data WDT and the threshold setting value Th during the period when the write enable WEN is in an active state. The detection control unit 21 activates the level detection signal LD ​​(for example, to a high level) in response to the upper threshold comparison unit 20 determining that the write data WDT is greater than or equal to the threshold setting value Th. In addition, in the semiconductor device 1, if it is determined that processing should be stopped during data processing performed by the CPU 12, the level detection clear signal LDC disables the level detection signal LD ​​output by the detection control unit 21 (for example, by setting it to a low level).

[0023] The ring buffer 18 cyclically and sequentially stores internal data (e.g., write data WDT) in a storage area set within a predetermined address range. The ring buffer 18 also includes a storage unit 31, and this storage unit 31 and the circuit blocks related to writing to the storage unit 31 are operated by the core clock, while other parts are operated by the bus clock. Details of the ring buffer 18 will be described later.

[0024] In the semiconductor device 1 according to Embodiment 1, a data receiving unit 10 receives temporally continuous stream data from an external source and transmits the received stream data to the arithmetic unit 12, which acts as a data processing unit, via a ring buffer 18. Furthermore, in the semiconductor device 1 according to Embodiment 1, the arithmetic unit 12 uses a DMAC 13 and a memory 14 when processing the stream data.

[0025] Furthermore, in the semiconductor device 1 according to Embodiment 1, the data receiving unit 10 and the level detection unit 17 are operated with a core clock used for receiving stream data, the arithmetic unit 12, DMAC 13, memory 14, and level detection unit 17 are operated with a bus clock used for internal processing of the semiconductor device, and the system controller 11 and ring buffer 18 are operated using both the core clock and the bus clock. In the semiconductor device 1 according to Embodiment 1, the bus clock is generated by selecting a period during which the level detection unit 17 determines that the stream data is valid data. As a result, the semiconductor device 1 according to Embodiment 1 reduces the operating time of the internal circuitry and thus reduces power consumption.

[0026] In the semiconductor device 1 according to Embodiment 1, the ring buffer 18 is equipped with a configuration to prevent the loss of data stored in the ring buffer 18 when the supply of the bus clock to the internal circuit is restored. The configuration of the ring buffer 18 will be described in detail below, but the features of the semiconductor device 1 are not limited to this. The core clock is a clock signal used for receiving stream data, and whether or not it is synchronized with the bus clock depends on the specifications of the semiconductor device 1. In the following description, the case in which the core clock and the bus clock are asynchronous clock signals will be described, but the core clock and the bus clock may be synchronized.

[0027] As shown in Figure 1, the ring buffer 18 includes a write selection unit 30, a storage unit 31, a read selection unit 32, a write address generation unit 33, a read address generation unit 36, a write address encoder 40, a write address synchronization unit 41, a write address decoder 42, a read synchronization comparison calculation unit 43, and a counter adjustment unit 44. The storage unit 31 is the data storage area in the ring buffer 18. The write selection unit 30, read selection unit 32, write address generation unit 33, read address generation unit 36, write address encoder 40, write address synchronization unit 41, write address decoder 42, read synchronization comparison calculation unit 43, and counter adjustment unit 44 are peripheral circuits for writing data to and reading data from the storage unit 31.

[0028] In the ring buffer 18, the write selection unit 30, storage unit 31, write address generation unit 33, and write address encoder 40 are set to operate using the core clock as the operating clock. In addition, the read selection unit 32, read address generation unit 36, write address synchronization unit 41, write address decoder 42, read synchronization comparison calculation unit 43, and counter adjustment unit 44 are set to operate using the bus clock as the operating clock.

[0029] The write address generation unit 33 operates with the core clock used for acquiring stream data and generates a cyclically changing write address WADD. More specifically, the write address generation unit 33 includes a write address counter pointer (e.g., a write pointer generation unit) 34 and a write address translation unit 35.

[0030] The write address counter pointer 34 generates a write pointer WPTR that repeats cyclically within a certain range. The write address counter pointer 34 also increments the write pointer WPTR by one each time the write enable WEN is enabled (e.g., high level). The write address counter pointer 34 sequentially increments the value of the write pointer WPTR so that its value repeats cyclically between the minimum and maximum values. The write address conversion unit 35 converts the write pointer WPTR to the write address WADD, which is the actual address of the storage unit 31. The write selection unit 30 selects the storage area specified by the write address WADD and writes the write data WDT to the selected storage area. The write selection unit 30 also performs the write data WDT to the storage unit 31 each time the write enable WEN is enabled.

[0031] The read address generation unit 36 ​​operates on the bus clock and generates a cyclically changing read address RADD. More specifically, the read address generation unit 36 ​​includes a read address counter pointer (e.g., a read pointer generation unit) 37 and a read address translation unit 38.

[0032] The read address counter pointer 37 generates a read pointer RPTR that repeats cyclically within a certain range. The read address counter pointer 37 also increments the read pointer RPTR by one each time the read enable signal REN output by the DMAC 13 becomes enabled (for example, high level). The read address counter pointer 37 sequentially increments the value of the read pointer RPTR so that its value repeats cyclically between the minimum and maximum values. The read address conversion unit 38 converts the read pointer RPTR into the read address RADD, which is the actual address of the storage unit 31. The read selection unit 32 selects the storage area specified by the read address RADD and reads the read data RDT from the selected storage area. The read selection unit 32 also performs the read data RDT reading process each time the read enable REN becomes enabled and sends the read data RDT to the DMAC 13.

[0033] The write address counter pointer 34 outputs the write pointer WPTR as binary data. The write address encoder 40 converts the write pointer WPTR output by the write address counter pointer 34 into Gray code. Gray code is a code that limits the difference between consecutive values ​​to only one bit for a multi-bit value. For example, if the write pointer WPTR is 0, 1, 2, 3 in decimal, and the corresponding binary data changes to 00, 01, 10, 11, then the Gray code will be 00, 01, 11, 10.

[0034] The write address synchronization unit 41 transfers the value of the write pointer WPTR, indicated in Gray code, from the core clock to the bus clock. The write address decoder 42 converts the write pointer WPTR output by the write address synchronization unit 41 from Gray code to binary code.

[0035] In this case, when data is transferred using an asynchronous clock system, metastables can occur where data is not transmitted correctly if the timing of the clock change and the timing of the data change coincide. Therefore, when the core clock and bus clock are asynchronous, data corruption of the write pointer WPTR, which is indicated by Gray code, can be reduced. In other words, when the core clock and bus clock are synchronized clocks, the write address encoder 40, write address synchronization unit 41, and write address decoder 42 can be omitted.

[0036] The read-synchronous comparison unit 43 calculates the difference between the write pointer WPTR and the read pointer RPTR as the data storage amount DS, which is the amount of data stored in the storage unit 31. In Embodiment 1, the read-synchronous comparison unit 43 receives the bus clock supply signal CB_EN, and when the bus clock supply signal CB_EN is enabled, the read-synchronous comparison unit 43 calculates the data storage amount DS based on the difference between the read pointer RPTR after adjustment by the counter adjustment unit 44 (described later) and the write pointer WPTR. The read-synchronous comparison unit 43 stores the calculated data storage amount DS in the data storage amount register of register 16. The calculation unit 12 also performs processing such as changing the number of data read from the storage unit 31 by referring to the data storage amount DS in register 16.

[0037] The counter adjustment unit 44 adjusts the difference between the read address and the write address to less than the size of a predetermined address range at the timing of the start of bus clock generation. More specifically, the counter adjustment unit 44 instructs the read address counter pointer 37 to adjust the value of the read pointer RPTR so that the difference between the write pointer WPTR and the read pointer RPTR immediately after the bus clock supply signal CB_EN changes to the enabled state is a predetermined value set in advance. Here, an example of a predetermined value is a value one less than the maximum value of the data storage amount DS of the storage unit 31. If the maximum value of the data storage amount DS is N, then N-1 can be set as the predetermined value.

[0038] Here, the operation of the counter adjustment unit 44 will be explained using specific values. Figure 2 shows a diagram illustrating the processing of the address adjustment unit of the ring buffer according to Embodiment 1. Figure 2 shows two examples where the maximum value N of the data storage amount DS is 4.

[0039] In the first example shown in the upper part of Figure 2, the write pointer WPTR is 3 just before the bus clock supply signal CB_EN changes from a disabled state (e.g., low level) to an enabled state (e.g., high level). In this first example, when the bus clock supply signal CB_EN switches to the enabled state, the counter adjustment unit 44 instructs the read address counter pointer 37 to set the read pointer RPTR to 0 so that the difference between the read pointer RPTR and the write pointer WPTR is N-1 (=3).

[0040] Furthermore, in the second example shown in the lower part of Figure 2, the write pointer WPTR is 1 just before the bus clock supply signal CB_EN changes from a disabled state (e.g., low level) to an enabled state (e.g., high level). In this second example, when the bus clock supply signal CB_EN switches to the enabled state, the counter adjustment unit 44 instructs the read address counter pointer 37 to set the read pointer RPTR to 2 so that the difference between the read pointer RPTR and the write pointer WPTR is N-1 (=3).

[0041] In other words, the counter adjustment unit 44 instructs the read address counter pointer 37 to adjust the pointer value so that it becomes the value of the read pointer RPTR derived based on equation (1), given that the maximum value of the data storage amount DS is N and a predetermined value is N-1. PRTR=((N+WPRT)-(N-1)) mod N ···(1)

[0042] In the semiconductor device 1 according to Embodiment 1, data writing to the storage unit 31 continues based on the core clock even when the bus clock is stopped, and the counter adjustment unit 44 adjusts the data reading start position after the bus clock supply is resumed, thereby reading data including that accumulated in the storage unit 31 before the bus clock supply was resumed. The operation of the semiconductor device 1 according to Embodiment 1 will be described below.

[0043] Figure 3 shows a flowchart illustrating the operation of the semiconductor device according to Embodiment 1. In the semiconductor device 1 according to Embodiment 1, the operation according to the flowchart in Figure 3 is repeatedly performed each time the bus clock is stopped. Furthermore, the flowchart in Figure 3 assumes that invalid data is supplied to the semiconductor device 1 as stream data and that operation begins from the period when the bus clock supply is stopped.

[0044] In the semiconductor device 1 according to Embodiment 1, during the period when invalid data is received as stream data, the level detection unit 17 sets the level detection signal LD ​​to a low level. As a result, in the semiconductor device 1 according to Embodiment 1, during the period when invalid data is input as stream data, the system controller 11 maintains a state in which the bus clock generation unit 15 is stopped.

[0045] As shown in Figure 3, in the semiconductor device 1 according to Embodiment 1, when the level detection unit 17 recognizes that valid data has been input as stream data, the level detection unit 17 switches the level detection signal LD ​​from a low level to a high level (step S1). Then, in response to the level detection signal LD ​​switching to a high level, the system controller 11 instructs the bus clock generation unit 15 to generate a bus clock, and the bus clock generation unit 15 starts supplying the bus clock (step S2). As a result, the semiconductor device 1 transitions from a low power consumption state to a normal state.

[0046] Furthermore, the system controller 11 rewrites the value of the bus clock supply signal register in register 16 from a low level to a high level. As a result, the bus clock supply signal CB_EN in the semiconductor device 1 switches from a disabled state (e.g., low level) to an enabled state (e.g., high level) (step S3). Then, in response to the bus clock supply signal CB_EN becoming enabled, the counter adjustment unit 44 adjusts the value of the read pointer RPTR for the read address counter pointer 37 (step S4). In step S4, the read pointer RPTR is adjusted based on equation (1) described above.

[0047] Subsequently, the semiconductor device 1 refers to the data storage amount DS, and if there is data stored in the storage unit 31, the arithmetic unit 12 and DMAC 13 read the data from the storage unit 31 (steps S5 and S6). Furthermore, the data reading in steps S5 and S6 continues until a decision is made in the data processing performed by the CUP 12 to stop processing (the NO branch of step S7). In other words, in the semiconductor device 1 according to Embodiment 1, after valid data is input as stream data, the bus clock is continuously supplied and data reading from the storage unit 31 continues until a decision is made in the data processing to stop processing.

[0048] In the semiconductor device 1 according to Embodiment 1, if the CPU 12 determines during data processing that invalid data has been input as stream data (the YES branch in step S7), the CPU 12 operates register 16 to raise the level detection clear signal LDC (step S8). This rewriting of the register value in step S8 causes the level detection clear signal LDC to become high, and the detection control unit 21 of the level detection unit 17 sets the value of the level detection signal LD ​​to low. In response to the level detection signal LD ​​becoming low, the system controller 11 rewrites the bus clock supply signal register to switch the bus clock supply signal CB_EN from high to low (step S9). Subsequently, the system controller 11 instructs the bus clock generation unit 15 to stop supplying the bus clock (step S10). As a result, the semiconductor device 1 transitions to a low-power state in which the bus clock supply is stopped.

[0049] Next, the operation of the semiconductor device 1 according to Embodiment 1 will be explained using specific signals. Figure 4 shows a timing chart illustrating the operation of the semiconductor device according to Embodiment 1. Figure 4 shows an example where an analog audio signal with varying amplitude is input as stream data.

[0050] In the example shown in Figure 4, at timing T1 the audio signal changes from silent to audible, but because it does not have sufficient amplitude (e.g., noise level), it is not considered valid data at the start of input, and the level detection unit 17 maintains the level detection signal LD ​​at a low level. Subsequently, as the amplitude of the stream data gradually increases, at timing T2 the level detection unit 17 determines that the amplitude has exceeded the threshold setting value Th, and switches the level detection signal LD ​​from a low level to a high level. Then, in response to the rising edge of the level detection signal LD ​​at timing T2, the system controller 11 rewrites the value of the bus clock supply signal register in register 16 from 0 to 1, so that the bus clock supply signal CB_EN becomes high level at timing T3.

[0051] Now, considering the clock signal, the core clock is continuously supplied to the semiconductor device 1 as long as stream data is being input, regardless of whether the stream data is audible or silent. On the other hand, the bus clock is generated in response to the level detection signal LD ​​becoming high, and its generation stops when the CPU 12 determines that it is no longer necessary to acquire new data during data processing.

[0052] In semiconductor device 1, even before the bus clock is generated (for example, before timing T3), the storage of stream data to the storage unit 31 continues based on the core clock. Then, when the bus clock is supplied at timing T3, the reading of read data RDT from the storage unit 31 begins based on the bus clock. In the example shown in Figure 4, the data is read intermittently. In addition, the number of data items read continuously changes with each reading cycle according to the amount of data stored in the storage unit 31 DS.

[0053] Then, at timing T5, the CPU 12 determines that it is safe to stop data processing, and based on this, the level detection unit 17 switches the level detection signal LD ​​from high to low. In response to the level detection signal LD ​​becoming low, the system controller 11 rewrites the value of the bus clock supply signal register from 1 to 0, thereby switching the bus clock supply signal CB_EN from high to low. Also, at timing T6, the bus clock supply is stopped.

[0054] Here, the signal flow within the semiconductor device 1 during the period from timing T1 to timing T4 will be explained in more detail. Timing T4 is after timing T3 and is the timing when the data readout from the storage unit 31 has been completed twice. Figure 5 shows a detailed timing chart illustrating the operation of the semiconductor device 1 according to Embodiment 1. Note that the example shown in Figure 5 is an example where the maximum value N of the data storage amount DS is 4.

[0055] As shown in Figure 5, in semiconductor device 1, the core clock is continuously supplied while stream data is being input, as explained in Figure 4. In the example shown in Figure 5, at timing T1, the write pointer WPTR is 00, and the write address WADD corresponding to the write pointer WPTR is 0. Furthermore, the write pointer WPTR after conversion to Gray code is 01. In addition, at timing T1, the read pointer RPTR becomes 10, which is the point when the bus clock supply is stopped at a timing not shown, and the read address RADD corresponding to the read pointer RPTR is 2.

[0056] Then, from timing T1 onward, the data receiving unit 10 sets the write enable WEN to a high level in synchronization with the output of data D0 to D5. Also, each time the data receiving unit 10 sends data to the ring buffer 18, the write address counter pointer 34 cyclically advances the write pointer WPTR from 01, 10, 11, 00, ... in synchronization with the rising edge of the write enable WEN. The timing at which the write address counter pointer 34 advances the write pointer WPTR is the timing at which the rising edge of the write enable WEN is input. Furthermore, the change in the write pointer WPTR is reflected in the write address WADD in synchronization with the rising edge of the core clock that is input in synchronization with the rising edge of the write enable WEN. As a result, in the ring buffer 18, data D0 to D3, which will be the write data WDT, are stored in the region where the write address WADD is 0 to 3, and data D4 and D5 are stored in the region where the write address WADD is 0 to 1.

[0057] Furthermore, in the semiconductor device 1 according to Embodiment 1, the write address encoder 40 generates a Gray code corresponding to the value of the write pointer WPTR generated by the write address counter pointer 34 at a timing synchronized with the write address conversion unit 35. In the example shown in Figure 5, for the write pointer WPTR which changes from 00, 01, 10, 11, 00..., the Gray code changes in the order of 00, 01, 11, 10, 00....

[0058] In the example shown in Figure 5, data D0, D1, and D2 are invalid data that do not reach a sufficient value, while data D3, D4, and D5 are valid data. Therefore, at timing T2 when data D3 is input, the level detection signal LD ​​is switched to a high level. As a result, at timing T2, the system controller 11 instructs the bus clock generation unit 15 to start generating the bus clock. However, since it takes time for the bus clock frequency to stabilize, the system controller 11 switches the bus clock supply signal CB_EN from a low level to a high level at timing T3, which is after timing T2. As a result, the supply of the bus clock starts at timing T3, and data reading from the storage unit 31 begins.

[0059] At timing T31, when the first rising edge of the bus clock after timing T3 is input, the write address synchronization unit 41 switches the write pointer WPTR, which is represented by Gray code, from the core clock to the bus clock. The write address decoder 42 converts the write pointer WPTR output by the write address synchronization unit 41 into a write pointer WPTR represented by binary code. In semiconductor device 1, the write address synchronization unit 41 and the write address decoder 42 update the write pointer WPTR in synchronization with the rising edge of the bus clock immediately after the write pointer WPTR changes. In the example shown in Figure 5, timings T33 and T37 are the update timings for the write pointer WPTR in the write address synchronization unit 41 and the write address decoder 42.

[0060] Furthermore, as shown in Figure 5, in the semiconductor device 1 according to Embodiment 1, when the bus clock supply signal CB_EN becomes high level at timing T3, the counter adjustment unit 44 instructs the read address counter pointer 37 to output a pointer value so that the difference between it and the write pointer WPTR output by the write address decoder 42 becomes a predetermined value. The predetermined value can be, for example, a value that is N-1 when the maximum value of the data storage amount DS is N. Specifically, when the maximum value N is 4, the predetermined value is 3. As a result, at timing T31, the data storage amount DS becomes 3. Also, the read pointer RPTR output by the read address counter pointer 37 becomes 01, which is 3 different from the write pointer WPTR.

[0061] Then, at timing T32, which is the rising edge timing of the bus clock after timing T31, the following processing is performed. At timing T32, the read address RADD becomes 01, indicating an address value of 1, according to the value of the read pointer RPTR. Then, in response to the data storage amount DS becoming 3 at timing T31, the arithmetic unit 12 enables the read enable REN for the storage unit 31 (for example, to high level). As a result, data D1 is read from the storage area where the address value is 1. Also, because the read enable REN is enabled, the read address counter pointer 37 is advanced by one to 10, corresponding to the read pointer RPTR. Furthermore, in response to the reading of data D1, the data storage amount DS is updated from 3 to 2. Note that in the example shown in Figure 5, data D0 will be discarded by being overwritten with data D4, which will be described later, but data D0 is invalid data and its invalidation does not cause any problems.

[0062] Next, at timing T33, which is the rising edge timing of the bus clock after timing T32, the following processing takes place. At timing T33, the read address RADD becomes 10, indicating an address value of 2, according to the value of the read pointer RPTR. Then, in accordance with the data storage amount DS being 2 at timing T32, the arithmetic unit 12 enables the read enable REN for the storage unit 31 (for example, to a high level). As a result, data D2 is read from the storage area with an address value of 2. Also, because the read enable REN is enabled, the read address counter pointer 37 advances the read pointer RPTR by one to 11. Note that at timing T33, the write pointer WPTR output by the write address decoder 42 advances by one to 01 (address value becomes 1), so even though data D2 is read, the data storage amount DS remains at 2.

[0063] Next, at timing T34, which is the rising edge timing of the bus clock after timing T33, the following processing takes place. At timing T34, the read address RADD becomes 11, which indicates address value 3, according to the value of the read pointer RPTR. Then, in accordance with the data storage amount DS being 2 at timing T33, the arithmetic unit 12 enables the read enable REN for the storage unit 31 (for example, to high level). As a result, data D3 is read from the storage area with address value 3. Also, because the read enable REN is enabled, the read address counter pointer 37 is set to 00 by advancing the read pointer RPTR by one. Furthermore, in accordance with the reading of data D3, the data storage amount DS is updated from 2 to 1.

[0064] Next, at timing T35, which is the rising edge timing of the bus clock after timing T34, the following processing takes place. At timing T35, the read address RADD becomes 00, indicating an address value of 0, according to the value of the read pointer RPTR. Then, in accordance with the data storage amount DS being 1 at timing T34, the arithmetic unit 12 enables the read enable REN for the storage unit 31 (for example, to a high level). As a result, data D4 is read from the storage area whose address value is 0. Also, because the read enable REN is enabled, the read address counter pointer 37 is advanced by one from the read pointer RPTR to 01. Furthermore, in accordance with the reading of data D4, the data storage amount DS is updated from 1 to 0.

[0065] Next, at timing T36, which is the rising edge timing of the bus clock after timing T35, the following processing is performed. At timing T36, the read address RADD becomes 01, indicating an address value of 1, according to the value of the read pointer RPTR. Since the data storage amount DS at timing T35 is 0, the arithmetic unit 12 disables the read enable REN (for example, to a low level). As a result, no data is read from the storage unit 31. Also, because the read enable REN is disabled, the read address counter pointer 37 maintains the read pointer RPTR at 01. Furthermore, since no data is stored in the storage unit 31 at this point, the data storage amount DS remains 0.

[0066] Next, at timing T37, which is the rising edge of the bus clock immediately after the value of the write pointer WPTR output by the write address decoder 42 is updated in response to the update of the write pointer WPTR after timing T35, the following processing takes place. At timing T37, the read pointer RPTR and read address RADD maintain the values ​​they had at timing T36. On the other hand, the data storage amount DS becomes 1 because the write pointer WPTR has advanced by one.

[0067] Next, at timing T38, which is the rising edge timing of the bus clock after timing T37, the following processing is performed. At timing T38, in accordance with the data storage amount DS being 1 at timing T37, the arithmetic unit 12 enables the read enable REN for the storage unit 31 (for example, to a high level). As a result, data D5 is read from the storage area whose address value is 1. Also, because the read enable REN is enabled, the read address counter pointer 37 is set to 10 by advancing the read pointer RPTR by one. Furthermore, in accordance with the reading of data D5, the data storage amount DS is updated from 1 to 0.

[0068] Next, at timing T39, which is the rising edge timing of the bus clock after timing T38, the following processing takes place. At timing T39, the read address RADD becomes 10, which indicates address value 2, according to the value of the read pointer RPTR. Since the data storage amount DS at timing T38 is 0, the arithmetic unit 12 disables the read enable REN (for example, to a low level). As a result, no data is read from the storage unit 31. Also, because the read enable REN is disabled, the read address counter pointer 37 maintains the read pointer RPTR at 01. Furthermore, since no data is stored in the storage unit 31 at this point, the data storage amount DS remains at 0.

[0069] As described above, in the semiconductor device 1 according to Embodiment 1, the power consumed by the internal circuit can be reduced by stopping the bus clock during periods when invalid data that does not require processing is input as stream data. At this time, the semiconductor device 1 according to Embodiment 1 continues to accumulate data in the storage unit 31 using the core clock even during the bus clock stop period. Then, after the bus clock supply is resumed, the semiconductor device 1 according to Embodiment 1 sets the read pointer RPTR so that the difference between it and the write pointer WPTR at that time is a predetermined value, and then performs the read processing after the bus clock supply is resumed. As a result, the semiconductor device 1 according to Embodiment 1 can prevent data loss caused by the bus clock stoppage without processing such as delays in operation. In other words, the semiconductor device 1 according to Embodiment 1 can achieve a high power consumption reduction effect while preventing a decrease in processing speed.

[0070] Furthermore, in the semiconductor device 1 according to Embodiment 1, the write address encoder 40, the write address synchronization unit 41, and the write address decoder 42 are used to transmit the write pointer WPTR to the read address counter pointer 37 side using Gray code. As a result, the semiconductor device 1 according to Embodiment 1 can reduce the rate of data errors caused by metastable data that occurs when transmitting data from a circuit system operating on a core clock to a circuit system operating on a bus clock.

[0071] Furthermore, in the semiconductor device 1 according to Embodiment 1, the ring buffer 18 outputs a data storage amount DS indicating the amount of data stored in the storage unit 31. This allows the arithmetic unit 12, which is the data processing unit, to switch between read processing and other data processing. Also, since the data storage amount DS immediately after the bus clock supply is restarted is known, there is no need to perform processing to reconfirm the data storage amount in the read processing immediately after the bus clock supply is restarted in the arithmetic unit 12.

[0072] Embodiment 2 Embodiment 2 describes a semiconductor device 2, which is another form of the semiconductor device 1 according to Embodiment 1. In the description of Embodiment 2, components that are the same as those described in Embodiment 1 are denoted by the same reference numerals as in Embodiment 1 and their descriptions are omitted. Figure 6 shows a block diagram of the semiconductor device according to Embodiment 2.

[0073] As shown in Figure 6, the semiconductor device 2 according to Embodiment 2 replaces the ring buffer 18 with a ring buffer 58 and adds a clock switching unit 51. The clock switching unit 51 switches the clock supplied to the ring buffer 18 between the bus clock and the core clock based on whether or not a bus clock is supplied. More specifically, the clock switching unit 51 supplies the core clock to at least the read synchronous comparison calculation unit 63, the address adjustment unit (e.g., the counter adjustment unit 64), and the read address generation unit (e.g., the read address counter pointer 77) when the bus clock generation unit 15 is stopped, and supplies the bus clock to the read synchronous comparison calculation unit 63, the counter adjustment unit 64, and the read address counter pointer 77 when the bus clock generation unit 15 is operating. The clock signal output by the clock switching unit 51 will be referred to as the select clock in the following description. The clock switching unit 51 recognizes the supply status of the bus clock by the bus clock supply signal CB_EN and switches whether to output the core clock or the bus clock as the select clock. Furthermore, in the example shown in Figure 6, since the core clock and bus clock are asynchronous, the select clock is also supplied to the write address synchronization unit 61 and the write address decoder 62.

[0074] The ring buffer 58 has a write address synchronization unit 61, a write address decoder 62, a read synchronization comparison unit 63, a counter adjustment unit 64, and a read address generation unit 76, instead of the write address synchronization unit 41, write address decoder 42, read synchronization comparison unit 43, counter adjustment unit 44, and read address generation unit 36 ​​of the ring buffer 18 in Embodiment 1. Furthermore, the read address generation unit 76 replaces the read address counter pointer 37 of the read address generation unit 36 ​​with a read address counter pointer 77.

[0075] The write address synchronization unit 61, write address decoder 62, read synchronization comparison unit 63, and read address counter pointer 77 are circuit blocks that operate on a select clock. Furthermore, the write address synchronization unit 61, write address decoder 62, read synchronization comparison unit 63, and read address counter pointer 77 are assumed to operate in the same manner as the write address synchronization unit 41, write address decoder 42, read synchronization comparison unit 43, and read address counter pointer 37.

[0076] The counter adjustment unit 64 monitors the data storage amount DS and instructs the read address counter pointer 77 to adjust the generated read pointer RPTR so that the data storage amount DS is within a range less than or equal to a predetermined value. Although the calculation method of the counter adjustment unit 64 differs from that of the counter adjustment unit 44, it has the same function as the counter adjustment unit 44 in that it adjusts the value of the read pointer RPTR so that the difference between the write pointer WPTR and the read pointer RPTR is less than or equal to a predetermined value. Furthermore, the counter adjustment unit 64 operates based on the select clock.

[0077] Next, the operation of the semiconductor device 2 according to Embodiment 2 will be described. Figure 7 shows a flowchart illustrating the operation of the semiconductor device according to Embodiment 2. As shown in Figure 7, the operation of the semiconductor device 2 according to Embodiment 2 is the same as the operation of Embodiment 1, with steps S11, S12, and S14 added, and step S4 changed to step S13.

[0078] In the semiconductor device 2 according to Embodiment 2, the read address counter pointer 77 and the read synchronization comparison unit 43 are operating even when the bus clock is stopped, so the value of the data storage amount DS in the storage unit 31 is updated each time a write operation to the storage unit 31 progresses. Therefore, as shown in Figure 7, in the semiconductor device 2 according to Embodiment 2, if the level detection signal LD ​​is at a low level in step S1 (the NO branch of step S1), the counter adjustment unit 64 compares the data storage amount DS with an upper limit setting value (for example, a predetermined value) (step S11). In step S11, if the data storage amount DS is greater than the predetermined value (the YES branch of step S11), the counter adjustment unit 64 adjusts the read pointer RPTR so that the data storage amount DS is less than or equal to the predetermined value (step S12). On the other hand, in step S11, if the data storage amount DS is less than or equal to the predetermined value (the NO branch of step S11), the counter adjustment unit 64 does not adjust the read pointer RPTR and the process ends.

[0079] Furthermore, in the semiconductor device 2 according to Embodiment 2, instead of adjusting the read pointer RPTR shown in Figure 3 (step S4), a process is performed to switch the clock output as the select clock from the core clock to the bus clock (step S13).

[0080] In the semiconductor device 2 according to Embodiment 2, after setting the bus clock supply signal CB_EN to a low level and before stopping the supply of the bus clock (between step S9 and step S10), a process is performed to switch the clock output as the select clock from the bus clock to the core clock (step S14).

[0081] The operation of the semiconductor device 2 according to Embodiment 2, following the flowchart above, will be explained using a timing chart. Figure 8 shows a timing chart illustrating the operation of the semiconductor device according to Embodiment 2. As shown in Figure 8, the data writing and reading operations of the semiconductor device 2 according to Embodiment 2 are the same as those of the semiconductor device 1 according to Embodiment 1, except for the presence or absence of a select clock. The select clock acts as the bus clock only during the period when the bus clock is supplied, and as the core clock during other periods. Furthermore, the difference in operation between the semiconductor device 2 according to Embodiment 1 and the semiconductor device 1 according to Embodiment 1 lies in the period when the level detection signal LD ​​is at a low level and the bus clock supply is stopped. Therefore, the detailed operation of the semiconductor device 2 between timings T2 to T4 in Figure 8 will be explained below.

[0082] Figure 9 shows a detailed timing chart illustrating the operation of the semiconductor device 2 according to Embodiment 2. The example shown in Figure 9 shows the case where the semiconductor device 2 according to Embodiment 2 operates for the same period as the semiconductor device 1 according to Embodiment 1 shown in Figure 5. In the semiconductor device 2 according to Embodiment 2, when the maximum value N of the data storage amount DS is set to 4, the value of the data storage amount changes within the range of 0 to 4. Therefore, in the example shown in Figure 9, in order to avoid overflow in the calculation of the data storage amount DS, the write pointer WPTR (both binary code and Gray code), the output value of the write address synchronization unit 61, the output value of the write address decoder 62, and the read pointer RPTR (binary code) are each shown as 3-bit values. Note that it is also possible to process the values ​​shown as 3 bits in Figure 9 with 2 bits by using a configuration such as an overflow flag.

[0083] As shown in Figure 9, in the semiconductor device 2 according to Embodiment 2, the operation after the bus clock supply starts and after data reading starts is the same as in the semiconductor device 1 according to Embodiment 1. Below, the operation from timing T1 to T31, in which the operation differs between the semiconductor device 1 according to Embodiment 1 and the semiconductor device 2 according to Embodiment 2, will be described in detail.

[0084] In the example shown in Figure 9, at timing T1, the write pointer WPTR is 000, and the write address WADD corresponding to the write pointer WPTR is 0. Furthermore, the write pointer WPTR after conversion to Gray code is 000. In addition, the write pointer WPTR output by the write address synchronization unit 41 and the write address decoder 42 at timing T1 both show 000. The read pointer RPTR shows 010, and the read address RADD shows 2. As a result, the data storage amount DS at timing T1 is 2.

[0085] Then, at timing T11, which is the rising edge of the core clock after timing T1, the following processing is performed. At timing T11, the data receiving unit 10 enables write enable WEN and outputs data D0. In addition, in response to write enable WEN being enabled, the write address counter pointer 34 advances the write pointer WPTR by one to 001. At this time, the write address WADD is not updated and maintains 000, which indicates an address value of 0, so data D0 is stored in the memory area where the address value is 0. Also, at timing T11, the write address encoder 40 does not reflect the update of the write pointer WPTR, so the values ​​output by the write address synchronization unit 61 and the write address decoder 62 maintain the values ​​from timing T1. Also, since the bus clock is stopped, read enable REN remains disabled, and the read pointer RPTR, read address RADD, and data storage amount DS output by the read address counter pointer 77 maintain the values ​​from timing T1.

[0086] Next, at timing T12, which is the rising edge timing of the core clock after timing T11, the following processing is performed. At timing T12, the data receiving unit 10 disables the write enable WEN, resulting in a state where no data is being transferred. Also, in response to the rising edge of the core clock, the write address translation unit 35 updates the write address WADD to 001, which corresponds to the write pointer WPTR. The write address encoder 40 also updates the Gray code corresponding to the value of the write pointer WPTR to 001. Here, at timing T12, the value of the write pointer WPTR in the Gray code updated by the write address encoder 40 is not reflected in the values ​​output by the write address synchronization unit 61 and the write address decoder 62. Also, because the bus clock is stopped, the read enable REN remains disabled, and the read pointer RPTR, read address RADD, and data storage amount DS output by the read address counter pointer 77 maintain the values ​​from timing T1.

[0087] Next, at timing T13, which is the rising edge timing of the core clock after timing T12, the following processing is performed. At timing T13, the data receiving unit 10 maintains the write enable WEN in a disabled state, so the write pointer WPTR and write address WADD maintain their values ​​from timing T12. On the other hand, at timing T13, the write address encoder 40 sets its output value to 001, reflecting the updated value of the write pointer WPTR represented by the Gray code. Then, in response to the update of the output value of the write address synchronization unit 61, the write address decoder 62 updates the write pointer WPTR it outputs to 001. At this time, since the bus clock is stopped, the read enable REN is also maintained in a disabled state, so the read pointer RPTR and read address RADD output by the read address counter pointer 77 maintain their values ​​from timing T1. Then, at timing T13, the data storage amount DS is updated from 2 to 3 because the write pointer WPTR output by the write address decoder 62 has been updated.

[0088] Next, at timing T14, which is the rising edge timing of the core clock after timing T13, the following processing is performed. At timing T14, the data receiving unit 10 enables write enable WEN and outputs data D1. In addition, in response to write enable WEN being enabled, the write address counter pointer 34 advances the write pointer WPTR by one to 010. At this time, the write address WADD is not updated and maintains 001, which indicates an address value of 1, so data D1 is stored in the memory area where the address value is 1. Also, at timing T14, the write address encoder 40 does not reflect the update of the write pointer WPTR, so the values ​​output by the write address synchronization unit 61 and the write address decoder 62 maintain the values ​​from timing T13. Furthermore, since the bus clock is stopped, read enable REN also remains disabled, and the read pointer RPTR, read address RADD, and data storage amount DS output by the read address counter pointer 77 maintain the values ​​from timing T13.

[0089] Next, at timing T15, which is the rising edge timing of the core clock after timing T14, the following processing is performed. At timing T15, the data receiving unit 10 disables the write enable WEN, resulting in a state where no data is being transferred. Also, in response to the rising edge of the core clock, the write address translation unit 35 updates the write address WADD to 010, which corresponds to the write pointer WPTR. In addition, the write address encoder 40 updates the Gray code corresponding to the value of the write pointer WPTR to 011. Here, at timing T15, the value of the write pointer WPTR in the Gray code updated by the write address encoder 40 is not reflected in the values ​​output by the write address synchronization unit 61 and the write address decoder 62. Also, since the bus clock is stopped, the read enable REN remains disabled, and the read pointer RPTR, read address RADD, and data storage amount DS output by the read address counter pointer 77 maintain the values ​​from timing T13.

[0090] Next, at timing T16, which is the rising edge timing of the core clock after timing T15, the following processing is performed. At timing T16, the data receiving unit 10 maintains the write enable WEN in a disabled state, so the write pointer WPTR and write address WADD maintain their values ​​from timing T15. On the other hand, at timing T16, the write address encoder 40 sets its output value to 011, reflecting the updated Gray code value of the write pointer WPTR. Then, in response to the update of the output value of the write address synchronization unit 61, the write address decoder 62 updates the write pointer WPTR it outputs to 010. At this time, since the bus clock is stopped, the read enable REN is also maintained in a disabled state, so the read pointer RPTR and read address RADD output by the read address counter pointer 77 maintain their values ​​from timing T13. Then, at timing T16, the data storage amount DS is updated from 3 to 4 because the write pointer WPTR output by the write address decoder 62 has been updated.

[0091] Next, at timing T17, which is the rising edge of the core clock after timing T16, the following processing is performed. At timing T17, the data receiving unit 10 enables write enable WEN and outputs data D2. In response to write enable WEN being enabled, the write address counter pointer 34 advances the write pointer WPTR by one to 011. At this time, the write address WADD is not updated and maintains 010, which indicates an address value of 2, so data D2 is stored in the memory area where the address value is 2. Also, at timing T17, the write address encoder 40 does not reflect the update of the write pointer WPTR, so the values ​​output by the write address synchronization unit 61 and the write address decoder 62 maintain the values ​​from timing T16. Also, since the bus clock is stopped, read enable REN remains disabled, and the read address RADD maintains the value from timing T16. On the other hand, at timing T16, the data storage amount DS becomes 4, which is larger than a predetermined value, so the counter adjustment unit 64 instructs the read address counter pointer 77 to advance the read pointer RPTR by one. As a result, at timing T17, the data storage amount DS is updated to 3.

[0092] Next, at timing T18, which is the rising edge timing of the core clock after timing T17, the following processing is performed. At timing T18, the data receiving unit 10 disables the write enable WEN, resulting in a state where no data is being transferred. Also, in response to the rising edge of the core clock, the write address translation unit 35 updates the write address WADD to 011, which corresponds to the write pointer WPTR. In addition, the write address encoder 40 updates the Gray code corresponding to the value of the write pointer WPTR to 010. Here, at timing T18, the value of the write pointer WPTR in the Gray code updated by the write address encoder 40 is not reflected in the values ​​output by the write address synchronization unit 61 and the write address decoder 62. Also, since the bus clock is stopped, the read enable REN remains disabled, and the read pointer RPTR and data storage amount DS output by the read address counter pointer 77 maintain the values ​​from timing T17. On the other hand, at timing T18, due to the read pointer RPTR becoming 011 at timing T17, the read address RADD is updated from 2 to 3.

[0093] Next, at timing T19, which is the rising edge timing of the core clock after timing T18, the following processing is performed. At timing T19, the data receiving unit 10 maintains the write enable WEN in a disabled state, so the write pointer WPTR and write address WADD maintain the values ​​they had at timing T18. On the other hand, at timing T19, the write address encoder 40 sets its output value to 010, reflecting the updated Gray code value of the write pointer WPTR. Then, in response to the update of the output value of the write address synchronization unit 61, the write address decoder 62 updates the write pointer WPTR it outputs to 011. At this time, since the bus clock is stopped, the read enable REN is also maintained in a disabled state, so the read pointer RPTR and read address RADD output by the read address counter pointer 77 maintain the values ​​they had at timing T17. Then, at timing T19, the data storage amount DS is updated from 3 to 4 because the write pointer WPTR output by the write address decoder 62 has been updated.

[0094] Next, at timing T2, which is the rising edge timing of the core clock after timing T18, the following processing is performed. At timing T2, the data receiving unit 10 enables write enable WEN and outputs data D3. In response to write enable WEN being enabled, the write address counter pointer 34 advances the write pointer WPTR by one to 000. At this time, the write address WADD is not updated and maintains 011, which indicates the address value 3, so data D3 is stored in the memory area where the address value is 3. Also, at timing T2, the write address encoder 40 does not reflect the update of the write pointer WPTR, so the values ​​output by the write address synchronization unit 61 and the write address decoder 62 maintain the values ​​from timing T16. Also, since the bus clock is stopped, read enable REN remains disabled, and the read address RADD maintains the value from timing T19. On the other hand, at timing T19, the data storage amount DS becomes 4, which is larger than a predetermined value, so the counter adjustment unit 64 instructs the read address counter pointer 77 to advance the read pointer RPTR by one. As a result, at timing T2, the data storage amount DS is updated to 3. Since data D3 is valid data, the level detection unit 17 switches the level detection signal LD ​​from low level to high level. Then, the system controller 11 instructs the bus clock generation unit 15 to start generating the bus clock, and the bus clock generation unit 15 starts generating the bus clock.

[0095] Next, at timing T21, which is the rising edge timing of the core clock after timing T2, the following processing is performed. At timing T21, the bus clock is not yet active, so the select clock is the core clock. At timing T21, the data receiving unit 10 disables the write enable WEN, resulting in a data not being transferred. In addition, in response to the rising edge of the core clock, the write address translation unit 35 updates the write address WADD to 000, which corresponds to the write pointer WPTR. The write address encoder 40 also updates the Gray code corresponding to the value of the write pointer WPTR to 000. At timing T21, the value of the write pointer WPTR in the Gray code updated by the write address encoder 40 is not reflected in the values ​​output by the write address synchronization unit 61 and the write address decoder 62. Also, since the bus clock is stopped, the read enable REN remains disabled, and the read pointer RPTR output by the read address counter pointer 37, and the data storage amount DS, maintain the values ​​from timing T2. On the other hand, at timing T21, the read address RADD is updated from 3 to 0 because the read pointer RPTR became 000 at timing T2.

[0096] Next, at timing T3, which is the rising edge timing of the core clock after timing T21, the following processing is performed. At timing T3, since the bus clock is not yet enabled, the select clock is in the state of the core clock. In the example shown in Figure 5, the bus clock supply signal CB_EN is enabled between timing T3 and timing T31, so operations using the bus clock are performed from timing T31 onwards. At timing T3, the data receiving unit 10 maintains the write enable WEN in a disabled state, so the write pointer WPTR and write address WADD maintain the values ​​they had at timing T21. On the other hand, at timing T3, the write address encoder 40 sets its output value to 000, reflecting the updated Gray code value of the write pointer WPTR. Then, upon receiving the update of the output value of the write address synchronization unit 61, the write address decoder 62 updates the write pointer WPTR it outputs to 000. At this time, since the bus clock is not yet enabled, the read enable REN also remains disabled, and the read pointer RPTR and read address RADD output by the read address counter pointer 77 maintain the values ​​they had at timing T2. Then, at timing T3, the write pointer WPTR output by the write address decoder 62 is updated, causing the data storage amount DS to be updated from 3 to 4.

[0097] Next, at timing T31, which is the rising edge timing of the bus clock after timing T3, the following processing is performed. At timing T31, the bus clock supply signal CB_EN is enabled, so the write address synchronization unit 61, write address decoder 62, read synchronization comparison calculation unit 63, counter adjustment unit 64, read address counter pointer 77, read address conversion unit 38, and read selection unit 32 start operating based on the bus clock. In addition, the system controller 11, calculation unit 12, DMAC 13, and memory 14 also start operating based on the bus clock.

[0098] At timing T31, since there is no change in the write pointer WPTR output by the write address encoder 40, the values ​​output by the write address decoder 62 and the read synchronization comparison calculation unit 63 remain the same as at timing T3. On the other hand, at timing T31, the counter adjustment unit 64 instructs the read address counter pointer 77 to advance the read pointer RPTR by one in response to the data storage amount DS exceeding a predetermined value at timing T3, which has become 4. As a result, at timing T31, the read pointer RPTR becomes 001, and the data storage amount DS is updated from 4 to 3. The operation from timing T32 onward is the same as that of the semiconductor device 1 according to Embodiment 1, so the explanation is omitted.

[0099] As described above, in the semiconductor device 2 according to Embodiment 2, by using a select clock, the read pointer RPTR is adjusted so that the difference between the read pointer RPTR and the write pointer WPTR does not exceed a predetermined value even when the bus clock is stopped. As a result, in the semiconductor device 2 according to Embodiment 2, the probability of malfunctions caused by data transfer errors in the write address synchronization unit 61 can be reduced.

[0100] Embodiment 3 Embodiment 3 describes level detection units 17a and 17b, which are different forms of the level detection unit 17. In the description of Embodiment 3, the same reference numerals as those used in Embodiment 1 are used for components that were described in Embodiment 1, and their descriptions are omitted.

[0101] First, Figure 10 shows a block diagram of a first example of the level detection unit according to Embodiment 3. In Figure 10, the level detection unit is labeled 17a. The level detection unit 17a corresponds to the case where the write data WDT is signed data. The lower threshold setting value ThL and the upper threshold setting value ThH input to the level detection unit 17a are provided from register 16.

[0102] The level detection unit 17a is a modified version of the level detection unit 17 in Embodiment 1, in which the upper threshold comparison unit 20 is replaced with a lower threshold comparison unit 22, an upper threshold comparison unit 23, and an OR circuit 24. Both the lower threshold comparison unit 22 and the upper threshold comparison unit 23 receive the write enable WEN and the write data WDT as inputs. The lower threshold comparison unit 22 determines the relationship between the value of the write data WDT and the lower threshold setting value ThL during the period when the write enable WEN is enabled (e.g., high level). More specifically, the lower threshold comparison unit 22 outputs a high-level signal if the value of the write data WDT is smaller than the lower threshold setting value ThL. The upper threshold comparison unit 23 determines the relationship between the value of the write data WDT and the upper threshold setting value ThH during the period when the write enable WEN is enabled (e.g., high level). More specifically, the upper threshold comparison unit 23 outputs a high-level signal if the value of the write data WDT is larger than the upper threshold setting value ThH. The OR circuit 24 sets the output signal to a high level during the period when at least one of the lower threshold comparison unit 22 and the upper threshold comparison unit 23 is outputting a high level.

[0103] According to the level detection unit 17a, even when the written data WDT is signed data, it is possible to detect positive and negative levels for data that has an amplitude above a certain level.

[0104] Figure 11 shows a block diagram of a second example of the level detection unit according to Embodiment 3. In Figure 11, the level detection unit is denoted as 17b. The level detection unit 17b is a level detection unit 17a with a moving average processing unit 25 added and the detection control unit 21 replaced by a detection control unit 26. Furthermore, the detection control unit 26 is a detection control unit 21 with a continuous detection counter 27 added.

[0105] The moving average processing unit 25 outputs the average value of the write data WDT over a certain period. This prevents the level detection signal LD ​​from becoming high for suddenly large or suddenly small write data WDTs. The continuous detection counter 27 counts the period during which the output signal of the OR circuit 24 is high. The continuous detection counter 27 then restricts the detection control unit 26 from raising the level detection signal LD ​​to high until the count value reaches the number of consecutive detections set by the continuous detection count setting value Cset provided by the register 16.

[0106] The level detection unit 17b can perform detection processing with high noise immunity by suppressing sensitivity to sudden signal fluctuations in the written data WDT. Note that the moving average processing unit 25 and the detection control unit 26 may also be applied to the level detection unit 17, which only has an upper limit threshold comparison unit 20.

[0107] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention. [Explanation of Symbols]

[0108] 1, 2 Semiconductor equipment 2 Semiconductor devices 10 Data receiving unit 11 System Controllers 12 Arithmetic section 13 DMAC 14 memory 15. Bus clock generation unit 16 registers 17, 17a, 17b Level detection unit 18, 58 Ring Buffer 20, 23 Upper threshold comparison section 21, 26 Detection and Control Unit 22 Lower threshold comparison section 24 OR circuits 25 Moving Average Processing Unit 27 Continuous detection counter 30 Writing Selection Section 31 Storage section 32 Readout Selection Section 33. Write address generation unit 34 Write address counter pointer 35. Write address conversion unit 36, 76 Read address generation unit 37, 77 Read address counter pointer 38 Read Address Translation Unit 40. Write address encoder 41, 61 Write address synchronization section 42, 62 write address decoder 43, 63 Read-Synchronized Comparison Calculation Unit 44, 64 Counter adjustment section 51 Clock switching section LD level detection signal LDC Level Detection Clear Signal DS data storage volume CB_EN Bus clock supply signal WDT written data WEN (Write Enable) WPTR write pointer WADD writing address RDT read data REN Read Enable RPTR read pointer RADD read address

Claims

1. A data receiving unit that converts stream data provided from an external source into internal data that can be processed internally, A level detection unit that activates a level detection signal when the value indicated by the internal data exceeds a threshold condition value, A ring buffer that cyclically stores the aforementioned internal data sequentially in a storage area set within a predetermined address range, A bus clock generation unit that generates a bus clock, A data processing unit that operates on the bus clock and processes data using the internal data acquired from the ring buffer, The system controller includes a system controller that selectively operates the bus clock generation unit during the period in which the level detection signal is in an active state, The aforementioned ring buffer is A write address generation unit that operates with the core clock used for acquiring the stream data and generates a cyclically changing write address, A storage unit that operates at the aforementioned core clock and stores the internal data in the area specified by the write address, A read address generation unit that operates with the aforementioned bus clock and generates a cyclically changing read address, A semiconductor device having an address adjustment unit that adjusts the difference between the read address and the write address to less than the size of the predetermined address range at the timing of the start of the bus clock generation.

2. The aforementioned write address generation unit, A write pointer generation unit that generates write pointers that are repeated cyclically within a certain range, The system includes a write address conversion unit that converts the write pointer into the write address which is the actual address of the storage unit, The aforementioned read address generation unit, A read pointer generation unit that generates read pointers that are repeated cyclically within a certain range, The semiconductor device according to claim 1, further comprising: a read address translation unit that converts the read pointer into the read address which is the actual address of the storage unit.

3. The semiconductor device according to claim 2, wherein the address adjustment unit causes the read pointer generation unit to output the read pointer having a pointer value obtained by subtracting a predetermined value less than the size of the predetermined address range from the write pointer.

4. The semiconductor device according to claim 2, further comprising a read synchronization comparison calculation unit that calculates the difference between the write pointer and the read pointer as a data storage amount which is the amount of internal data stored in the storage unit.

5. It has a data storage amount register that records the amount of data to be stored, The semiconductor device according to claim 4, wherein the data processing unit changes the number of data items read from the storage unit by referring to the value of the data storage amount register.

6. The semiconductor device according to claim 2, wherein the core clock is a clock signal that is asynchronous with the bus clock.

7. A write address encoder that converts the value of an adjacent write pointer into Gray code in which the change is limited to one bit, A write address synchronization unit that transfers the value of the write pointer indicated by the Gray code from the core clock to the bus clock, The semiconductor device according to claim 6, further comprising: a write address decoder that converts the write pointer output by the write address synchronization unit from Gray code to binary code.

8. A clock switching unit that supplies a core clock to at least the address adjustment unit and the write pointer generation unit during the period when the bus clock generation unit is stopped, and supplies the bus clock to the address adjustment unit and the write pointer generation unit during the period when the bus clock generation unit is operating, The system further includes a read synchronization comparison calculation unit that obtains the difference between the write pointer and the read pointer as a data storage amount which is the amount of internal data stored in the storage unit, The semiconductor device according to claim 6, wherein the address adjustment unit adjusts the value of the read pointer so that the difference between the write pointer and the read pointer is less than or equal to the predetermined value when the amount of data stored becomes greater than a predetermined value less than the size of the predetermined address range.

9. The semiconductor device according to claim 1, wherein the system controller rewrites the value of a bus clock supply status notification register, which indicates the logical state of a bus clock supply signal that notifies that the bus clock generation unit is operating, depending on whether the level detection signal is in an enabled state or an disabled state.

10. The semiconductor device according to claim 9, wherein the address adjustment unit adjusts the read address during a period in which the bus clock supply signal indicates that the bus clock is being supplied.

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