Power converter

Abstract

Each of the multiple unit converters comprises a main circuit (30), a control circuit (32) configured to control multiple switching elements (11-14) according to a control signal received from a control device, a power supply (50) that generates a power supply voltage by stepping down the voltage of a first capacitor (15) and supplies the power supply voltage to the control circuit (32), and a current limiting resistor circuit (80) with a variable resistance value, placed between the main circuit (30) and the power supply (50). The power supply (50) comprises a second capacitor (51), an overcharge suppression circuit (54), a power supply circuit (56), and a control unit (500). The control unit (500) includes an overcharge suppression control circuit (53) that controls an overcharge suppression circuit (54) according to the magnitude of the voltage of the second capacitor (51), a current limiting resistor switching circuit (83) that switches the resistance value of the current limiting resistor circuit (80) according to the magnitude of the voltage of the first capacitor (15), and a short-circuit fault detection circuit (200) that detects a short-circuit fault in at least one switch of the current limiting resistor circuit (80) based on the duty cycle of the switching signal and the magnitude of the DC voltage of the first capacitor (15).

Description

Technical Field

[0001] The present disclosure relates to a power conversion device, and more particularly to a power conversion device configured by connecting in series at least one unit converter of a main circuit power supply method.

Background Art

[0002] In recent years, in self-excited reactive power compensation devices such as STATCOM (Static Synchronous Compensator), DC power transmission systems such as BTB (Back to Back) systems, and motor drive inverters, the application of a modular multilevel converter (MMC: Modular Multilevel Converter) has been considered (see, for example, International Publication No. 2007 / 025828 (Patent Document 1)).

[0003] The MMC is configured by connecting a plurality of unit converters in series. The unit converter includes a main circuit having a switching element and a DC capacitor. By the switching operation of the switching element in the unit converter, the voltage of the DC capacitor is output to the output terminal. As the switching element, generally, a semiconductor switching element capable of controlling conduction / non-conduction such as an IGBT (Insulated Gate Bipolar Transistor) is used.

[0004] In addition to the main circuit, the unit converter includes a control circuit and a power supply for controlling the conduction / non-conduction of the switching element of the main circuit in cooperation with an upper control device that controls the entire MMC. The power supply supplies a power supply voltage to the control circuit based on the power generated in the main circuit. This is called the main circuit power supply method.

[0005] Generally, in an MMC having such a configuration, the DC voltage of the DC capacitor of the main circuit is stepped down by a current limiting resistor to generate an input voltage to the power supply. Power corresponding to this input voltage is temporarily stored in a capacitor provided inside the power supply. The power supply supplies a power supply voltage obtained by further stepping down this input voltage to the control circuit. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] International Publication No. 2007 / 025828 [Overview of the project] [Problems that the invention aims to solve]

[0007] In power conversion devices like the one described in Patent Document 1, it is not possible to detect a short-circuit failure in the current-limiting resistor switching circuit. As a result, there is a problem in that the operation of the power conversion device continues even as the surplus power increases.

[0008] Therefore, the object of this disclosure is to provide a power converter capable of detecting a short-circuit fault in a current-limiting resistor switching circuit. [Means for solving the problem]

[0009] The power converter of this disclosure comprises a power converter having an arm configured by connecting a plurality of unit converters in series, and a control device for controlling the power converter. Each of the plurality of unit converters includes a main circuit including a plurality of switching elements and a first capacitor electrically connected between a first DC line and a second DC line, a control circuit configured to control the plurality of switching elements according to a control signal received from the control device, a power supply that generates a power supply voltage by stepping down the voltage of the first capacitor and supplies the power supply voltage to the control circuit, and a current limiting resistor circuit disposed between the main circuit and the power supply, the resistance value of which is switched by at least one switch. The power supply comprises a second capacitor electrically connected between a first DC line and a second DC line, an overcharge suppression circuit electrically connected between the first DC line and the second DC line, a power supply circuit electrically connected between the first DC line and the second DC line and configured to convert the voltage of the second capacitor into a power supply voltage, and a control unit. The control unit includes an overcharge suppression control circuit that outputs a switching signal to the overcharge suppression circuit for controlling the overcharge suppression circuit according to the magnitude of the voltage of the second capacitor, a current limiting resistor switching circuit that switches the resistance value of the current limiting resistor circuit according to the magnitude of the DC voltage of the first capacitor, and a short-circuit fault detection circuit that detects a short-circuit fault in at least one switch of the current limiting resistor circuit based on the duty cycle of the switching signal and the magnitude of the DC voltage of the first capacitor. [Effects of the Invention]

[0010] According to this disclosure, a short-circuit fault in the current-limiting resistor switching circuit can be detected. [Brief explanation of the drawing]

[0011] [Figure 1] This is a diagram showing the configuration of the power converter 100 according to the embodiment. [Figure 2] This is a circuit block diagram showing the configuration of the unit converter 5. [Figure 3] This is a circuit block diagram of the unit converter according to the embodiment. [Figure 4]This diagram shows the configuration of the short-circuit fault detection circuit 200. [Figure 5] This figure shows the time variation of the input voltage Vin and the switching signal ST when the DC voltage Vdc of the first capacitor 15 is relatively low. [Figure 6] This figure shows the time variation of the input voltage Vin and the switching signal ST when the DC voltage Vdc of the first capacitor 15 is relatively high. [Figure 7] This diagram shows the time variation of the input voltage Vin and the switching signal ST when at least one of the switches SW1 and SW2 of the current-limiting resistor circuit 80 is short-circuited. [Figure 8] This diagram shows the changes in the duty cycle of the switching signal ST and the supplied power PIN in response to a partial change in the DC voltage Vdc of the first capacitor 15, both under normal conditions and during a short circuit. [Figure 9] This diagram illustrates the short-circuit detection of at least one of the switches SW1 and SW2 of the current-limiting resistor circuit 80 using Method A. [Figure 10] This diagram illustrates a method for detecting a short-circuit fault in a current-limiting resistor circuit 80 according to an embodiment. [Figure 11] This diagram illustrates the magnitudes of the lower voltage limit VdcL, the upper voltage limit VdcH, and the reference value Ref. [Modes for carrying out the invention]

[0012] The embodiments will be described in detail below with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals, and their descriptions will not be repeated.

[0013] Embodiment. Figure 1 is a diagram showing the configuration of the power converter 100 according to the embodiment.

[0014] The power conversion device 100 is used as a reactive power compensation device that compensates for the reactive power of the power system 1. Referring to FIG. 1, the power conversion device 100 includes arms A1 to A3 configured by connecting at least one unit converter 5 of the main circuit power supply method in series, and a control device 4 that controls at least one unit converter 5. More specifically, the power conversion device 100 includes switches S1 to S6, transformers 2 and 3, current limiting resistors R1 to R3, AC lines UL, VL, WL, converters C1 to C3, reactors L1 to L3, arms A1 to A3, and a control device 4.

[0015] One terminal of each of the switches S1, S2, and S3 is connected to the three-phase transmission lines 1u, 1v, and 1w of the power system 1, respectively, and the other terminal is connected to the three primary windings of the transformer 2, respectively. The switches S1, S2, and S3 are normally in the conductive state, and are made non-conductive, for example, during maintenance of the power conversion device 100. The transformer 2 includes three primary windings and three secondary windings, and exchanges three-phase AC power.

[0016] One terminal of each of the current limiting resistors R1 to R3 is connected to the three secondary windings of the transformer 2, respectively, and the other terminal is connected to the AC lines UL, VL, WL, respectively. The current limiting resistors R1 to R3 limit the current flowing from the power system 1 to the arms A1 to A3, respectively, when the power conversion device 100 is started up.

[0017] The switches S4, S5, and S6 are connected in parallel to the current limiting resistors R1 to R3, respectively. The switches S4, S5, and S6 are made conductive after the current flowing through the arms A1 to A3 stabilizes when the power conversion device 100 is started up. The transformer 3 outputs three-phase AC voltages Vu, Vv, and Vw having values corresponding to the AC voltages of the AC lines UL, VL, WL to the control device 4.

[0018] Reactor L1 and arm A1 are connected in series between AC line UL and AC line VL. Reactor L2 and arm A2 are connected in series between AC line VL and AC line WL. Reactor L3 and arm A3 are connected in series between AC line WL and AC line UL. In other words, arms A1 to A3 are delta connected. Arms A1 to A3 are controlled by control device 4 to generate three-phase AC power.

[0019] Each of the arms A1 to A3 includes a cascaded set of unit converters 5. Each of the unit converters 5 generates AC power according to a control signal from the control device 4.

[0020] The first terminal 5a of the first-stage unit converter 5 of arm A1 is connected to one terminal of reactor L1. In arm A1, the second terminal 5b of the unit converter 5, except for the final stage, is connected to the first terminal 5a of the subsequent unit converter 5. The second terminal 5b of the final-stage unit converter 5 of arm A1 is connected to one terminal of reactor L2.

[0021] The first terminal 5a of the first-stage unit converter 5 of arm A2 is connected to one terminal of reactor L2. In arm A2, the second terminal 5b of the unit converter 5, except for the final stage, is connected to the first terminal 5a of the subsequent unit converter 5. The second terminal 5b of the final-stage unit converter 5 of arm A2 is connected to one terminal of reactor L3.

[0022] The first terminal 5a of the unit converter 5 in the first stage of arm A3 is connected to one terminal of reactor L3. In arm A3, the second terminal 5b of the unit converter 5 in all stages except the final stage is connected to the first terminal 5a of the subsequent unit converter 5. The second terminal 5b of the unit converter 5 in the final stage of arm A3 is connected to one terminal of reactor L1.

[0023] Reactors L1 to L3 suppress the circulating currents flowing through arms A1 to A3, respectively. Reactors L1 to L3 may be provided separately from arms A1 to A3, or they may be the inductance components of arms A1 to A3. Current transformers C1 to C3 detect the alternating currents Iuv, Ivw, and Iwu flowing through arms A1 to A3, respectively, and output them to the control device 4.

[0024] The control device 4 receives inputs such as the reactive power command value Qr, three-phase AC voltages Vu, Vv, Vw, AC currents Iuv, Ivw, Iwu, and the DC voltage Vdc of the first capacitor 15 (described later), and controls each of the three arms A1 to A3 (i.e., each of the multiple unit converters 5) by outputting control signals GC, gate block signal GB, gate deblock signal DEB, conduction command Son, etc. (described later). The reactive power command value Qr is provided, for example, from the central control room (not shown) of the power system 1. The power converter 100 supplies reactive power to the power system 1 with a value corresponding to the reactive power command value Qr.

[0025] Figure 2 is a circuit block diagram showing the configuration of the unit converter 5. Referring to Figure 2, the unit converter 5 includes a main circuit 30, a control circuit 32, a current-limiting resistor circuit 80, and a power supply 50.

[0026] The main circuit 30 is composed of a full-bridge circuit equipped with a capacitor. Specifically, the main circuit 30 has a first terminal 5a and a second terminal 5b. The main circuit 30 includes switching elements 11 to 14, diodes D1 to D4, and a first capacitor 15. The main circuit 30 performs power conversion by controlling the conduction / non-conductivity of the switching elements 11 to 14 to output a voltage pulse with an amplitude corresponding to the voltage of the first capacitor 15 between the first terminal 5a and the second terminal 5b.

[0027] Switching elements 11-14 are self-extinguishing power semiconductor elements, such as IGBTs. Switching elements 11 and 13 are connected in series between the first DC line PL and the second DC line NL. Switching elements 12 and 14 are connected in series between the first DC line PL and the second DC line NL. The collectors of switching elements 11 and 12 are both connected to the first DC line PL, and the emitters of switching elements 13 and 14 are both connected to the second DC line NL. The connection point between the emitter of switching element 11 and the collector of switching element 13 is connected to the first terminal 5a. The connection point between the emitter of switching element 12 and the collector of switching element 14 is connected to the second terminal 5b.

[0028] Diodes D1 to D4 are connected in antiparallel to switching elements 11 to 14, respectively. The first capacitor 15 is electrically connected between the first DC line PL and the second DC line NL, and stores DC power.

[0029] In the unit converter 5, the conduction / non-conductivity of switching elements 11-14 is controlled by the control circuit 32. Switching elements 11 and 13 are each in a complementary conduction state. Switching elements 12 and 14 are each in a complementary conduction state. As shown in Figure 2, if the voltage from the second terminal 5b to the first terminal 5a is defined as the cell voltage Vcell, the cell voltage Vcell is controlled by the conduction / non-conductivity of switching elements 11-14.

[0030] Specifically, when switching elements 11 and 14 are both conducting and switching elements 12 and 13 are both non-conducting, the cell voltage Vcell is approximately equal to the DC voltage Vdc of the first capacitor 15. When switching elements 11 and 12 are both conducting and switching elements 13 and 14 are both non-conducting, the cell voltage Vcell is approximately zero. When switching elements 11 and 12 are both non-conducting and switching elements 13 and 14 are both conducting, the cell voltage Vcell is approximately zero. When switching elements 11 and 14 are both non-conducting and switching elements 12 and 13 are both conducting, the cell voltage Vcell is approximately equal to the voltage obtained by reversing the polarity of the DC voltage Vdc of the first capacitor 15.

[0031] The total voltage of each arm A1 to A3 is expressed as the sum of the cell voltages Vcell of each unit converter 5 included in the corresponding arm A1 to A3. Therefore, the total voltage of each arm A1 to A3 can be controlled by the conduction / non-conductivity of the switching elements 11 to 14 that constitute each unit converter 5.

[0032] The main circuit 30 further includes a switch S7. The switch S7 is connected between the first terminal 5a and the second terminal 5b. The switch S7 is configured to short-circuit the first terminal 5a and the second terminal 5b by closing in response to a conduction command Son from the control circuit 32.

[0033] The control circuit 32 includes drive circuits 40 and 42, a switch operation circuit 44, and an I / F (interface) circuit 48. The control circuit 32 is configured to control the conduction / non-conductivity of the switching elements 11 to 14 according to the control signals received from the control device 4.

[0034] The I / F circuit 48 communicates with the control device 4 by wire or wireless (not shown). The I / F circuit 48 receives a control signal GC from the control device 4 to control the full-bridge circuit of the main circuit 30. The I / F circuit 48 also receives a gate block signal GB from the control device 4 to fix all switching elements 11-14 constituting the full-bridge circuit in a non-conductive state. More specifically, when all switching elements 11-14 are fixed in a non-conductive state, the gate block signal GB is activated to a high level. In response to the activation of the gate block signal GB to a high level, the gate deblock signal DEB is deactivated to a low level. The I / F circuit 48 receives a gate deblock signal DEB from the control device 4 to release the non-conductive fixation of the switching elements 11-14 constituting the full-bridge circuit. More specifically, when the non-conductive fixation of the switching elements 11-14 is released, the gate deblock signal DEB is activated to a high level. In response to the activation of the gate deblock signal DEB to a high level, the gate block signal GB is deactivated to a low level. The I / F circuit 48 outputs the received control signal GC, gate block signal GB, and gate deblock signal DEB to the drive circuits 40 and 42.

[0035] The drive circuit 40 controls the conduction / non-conductivity of the switching elements 11 and 13 in response to the control signal GC. In response to the gate block signal GB, the drive circuit 40 fixes the switching elements 11 and 13 in a non-conductive state (stopped state or gate-blocked state). In response to the gate deblock signal DEB, the drive circuit 40 releases the non-conductive state of the switching elements 11 and 13 (not in a gate-blocked state or gate-deblocked state).

[0036] The drive circuit 42 controls the conduction / non-conductivity of the switching elements 12 and 14 in response to the control signal GC. In response to the gate block signal GB, the drive circuit 42 fixes the switching elements 12 and 14 in a non-conductive state (stopped state or gate block state). In response to the gate deblock signal DEB, the drive circuit 42 releases the non-conductive state of the switching elements 12 and 14 (not in a gate block state or gate deblock state).

[0037] In other words, when the gate block signal GB is at a high level and the gate deblock signal DEB is at a low level, the switching elements 11 to 14 are in a gate-blocked state. When the gate block signal GB is at a low level and the gate deblock signal DEB is at a high level, the switching elements 11 to 14 are not in a gate-blocked state.

[0038] The control device 4 may simultaneously control the level of the gate block signal GB and the gate deblock signal DEB for all unit converters 5 in arm A1. As a result, the switching elements 11-14 of all unit converters 5 in arm A1 become non-conductive at the same time, and their non-conductive lock is released at the same time. The same applies to arms A2 and A3.

[0039] The switch operation circuit 44 is a circuit for operating the switch S7. The switch operation circuit 44 controls the energization of the excitation coil 18 according to a command from the control device 4. During normal operation, the supply of current to the excitation coil 18 is stopped, so the switch S7 is in a non-conducting state. On the other hand, if the control device 4 detects an abnormality such as a short-circuit failure of the switching elements 11 to 14 in any of the unit converters 5, it outputs a conduction command Son for the switch S7 to the faulty unit converter 5. In the faulty unit converter 5, the I / F circuit 48 receives the conduction command Son and outputs it to the switch operation circuit 44. In response to the conduction command Son, the switch operation circuit 44 supplies current to the excitation coil 18, causing the switch S7 to become conductive. As a result, the output of the faulty unit converter 5 is short-circuited.

[0040] The current-limiting resistor circuit 80 is inserted in the first DC line PL between the main circuit 30 and the power supply 50. The current-limiting resistor circuit 80 steps down the DC voltage Vdc of the first capacitor 15.

[0041] The power supply 50 includes input terminals 501 and 502. Input terminal 501 is connected to the first DC line PL. Input terminal 502 is connected to the second DC line NL. The power supply 50 is electrically connected in parallel to the first capacitor 15. The power supply 50 steps down the voltage across the first capacitor 15 to generate a power supply voltage and supplies this power supply voltage to the control circuit 32. As a result, the unit converter 5 forms a self-sufficient cell that can supply power from the main circuit 30 to the control circuit 32.

[0042] Next, we will describe the normal operation of the power converter 100. The control device 4 determines the levels of the three-phase AC currents Iu, Iv, and Iw corresponding to the AC currents flowing through the AC lines UL, VL, and WL, based on the AC currents Iuv, Ivw, and Iwu from the current transformers C1 to C3. Here, Iu = Iuv - Iwu, Iv = Ivw - Iuv, and Iw = Iwu - Ivw.

[0043] The control device 4 calculates the reactive power Q0 based on the three-phase AC voltages Vu, Vv, Vw from the transformer 3 and the three-phase AC currents Iu, Iv, Iw from the calculator 31. The control device 4 calculates the deviation ΔQ = Qr - Q0 between the reactive power command value Qr and the reactive power Q0.

[0044] The control device 4 generates multiple voltage command values ​​Vdcr corresponding to multiple unit converters 5, based on the AC currents Iuv, Ivw, Iwu from current transformers C1 to C3 and the three-phase AC voltages Vu, Vv, Vw from transformer 3.

[0045] The control device 4 calculates the deviation ΔVdc between the voltage command value Vdcr and the DC voltage Vdc of the first capacitor 15. The control device 4 generates three-phase AC voltage command values ​​Vuvr, Vvwr, and Vwur by performing control calculations to set the voltage deviation ΔVdc to 0 and the reactive power deviation ΔQ to 0.

[0046] In other words, the control device 4 controls the active current of each unit converter 5 so that the voltage deviation ΔVdc becomes 0, and also controls the reactive current of each unit converter 5 so that the reactive power deviation ΔQ becomes 0.

[0047] Based on the three-phase AC voltage command values ​​Vuvr, Vvwr, and Vwur, each unit converter 5 of arms A1 to A3 is operated so that the DC voltage Vdc of the first capacitor 15 matches the voltage command value Vdcr, and the reactive power Q0 matches the reactive power command value Qr. Specifically, the control device 4 generates a control signal GC, for example, according to PWM (Pulse Width Modulation) control, for the power converter to output voltages corresponding to the three-phase AC voltage command values ​​Vuvr, Vvwr, and Vwur. The control device 4 outputs the control signal GC to the control circuits 32 of each unit converter 5 of arms A1 to A3. Each control circuit 32 converts the DC voltage to an AC voltage by making each of the switching elements 11 to 14 conduct at a predetermined timing according to the control signal GC.

[0048] FIG. 3 is a circuit block diagram of the unit converter according to the embodiment. Referring to FIG. 3, the current limiting resistance circuit 80 includes resistors Ra, Rb, Rc and switches SW1, SW2. The power supply 50 includes a second capacitor 51, voltage sensors 46, 52, an overcharge suppression circuit 54, a control unit 500, and a power supply circuit 56. The overcharge suppression circuit 54 includes a switch S8 and a resistor R5.

[0049] The second capacitor 51 is connected between the first DC line PL and the second DC line NL. The overcharge suppression circuit 54 includes a resistor R5 and a switch S8 connected in series between the first DC line PL and the second DC line NL. The second capacitor 51 is supplied with the charge from the first capacitor 15 through the current limiting resistance circuit 80. Power is supplied from the power supply 50 to the control circuit 32.

[0050] Here, let Po be defined as the sum of the load power of the control circuit 32 and the loss power generated in the power supply 50. Po is the required power. Let the resistance value of the current limiting resistance circuit 80 be R, the DC voltage of the first capacitor 15 be Vdc, and the input voltage of the second capacitor 51 be Vin. Then, the supply power PIN from the main circuit 30 to the power supply 50 is expressed by the following equation.

[0051] PIN = (Vdc - Vin) / R * Vin ··· (1) [[ID=十三]] In order to maintain the power supply to the control circuit 32, the relationship PIN ≥ Po must hold. When PIN = Po, the input voltage Vin is maintained at a constant value. When PIN > Po, the second capacitor 51 is overcharged by the excess power (PIN - Po). The input voltage Vin is restricted by the internal circuit specifications of the power supply 50, and its average value needs to be kept substantially constant. Therefore, the resistor R5 in the overcharge suppression circuit 54 provided in parallel with the second capacitor 51 consumes the excess power, thereby maintaining the input voltage Vin at a substantially constant value. When PIN < Po, the control circuit 32 is not supplied with the power required by the control circuit 32.

[0052] Resistors Ra, Rb, and Rc are connected in series on the first DC line PL. Resistor Rb is connected in parallel to switch SW1. Switch SW1 is controlled by control unit 500. Resistor Rc is connected in parallel to switch SW2. Switch SW2 is controlled by control unit 500. Let Ra be the resistance value of resistor Ra, Rb be the resistance value of resistor Rb, and Rc be the resistance value of resistor Rc. When switches SW1 and SW2 are ON, the resistance of the current-limiting resistor circuit 80 is Ra. When switch SW1 is OFF and switch SW2 is ON, the resistance of the current-limiting resistor circuit 80 is (Ra + Rb). When switches SW1 and SW2 are OFF, the resistance of the current-limiting resistor circuit 80 is (Ra + Rb + Rc).

[0053] The second capacitor 51 is connected between the input terminal 501 on the first DC line PL and the input terminal 502 on the second DC line NL. The second capacitor 51 is configured to generate an input voltage Vin by power supplied from the first capacitor 15 via the current-limiting resistor circuit 80.

[0054] The power supply circuit 56 is electrically connected between the first DC line PL and the second DC line NL, and is configured to convert the voltage across the second capacitor 51 into a power supply voltage.

[0055] The voltage sensor 46 detects the DC voltage Vdc across the terminals of the first capacitor 15 and outputs the detected value to the control unit 500. The voltage sensor 52 detects the voltage Vin across the terminals of the second capacitor 51 (hereinafter referred to as the input voltage) and outputs the detected value to the control unit 500.

[0056] Switch S8 and resistor R5 are electrically connected in series between the first DC line PL and the second DC line NL. The conduction / non-conductivity of switch S8 is controlled by the control unit 500. When switch S8 is conducting, the discharge current of the second capacitor 51 flows through resistor R5, and the input voltage Vin of the second capacitor 51 decreases. In other words, resistor R5 is an overcharge suppression resistor for the second capacitor 51. Switch S8 is composed of a transistor, relay, etc.

[0057] The control unit 500 controls the conduction / non-conductivity of switch S8 and the starting / stopping of power supply circuit 56 based on the input voltage Vin detected by voltage sensor 52. The control unit 500 controls switches SW1 and SW2 of current limiting resistor circuit 80 based on the DC voltage Vdc of the first capacitor detected by voltage sensor 46. The control unit 500 includes an overcharge suppression control circuit 53, a start / stop circuit 55, and a resistance switching circuit 88. The resistance switching circuit 88 includes a voltage detection circuit 83 and an AND circuit 82.

[0058] The start / stop circuit 55 controls the start / stop of the power supply circuit 56 based on the detected value of the input voltage Vin. The signal output from the start / stop circuit 55 to the power supply circuit 56 transitions from an L level to an H level when the detected value of the input voltage Vin rises and becomes greater than or equal to the threshold VC. The signal output from the start / stop circuit 55 to the power supply circuit 56 transitions from an H level to an L level when the detected value of the input voltage Vin falls below the threshold VD when the input voltage Vin falls. However, VC > VD.

[0059] The power supply circuit 56 is activated when the output signal of the start / stop circuit 55 transitions from a low level to a high level, supplying power voltage to the control circuit 32. This activates the control circuit 32. The power supply circuit 56 is deactivated when the output signal of the start / stop circuit 55 transitions from a high level to a low level. This stops the supply of power voltage from the power supply circuit 56 to the control circuit 32, and thus deactivates the control circuit 32.

[0060] The resistance switching circuit 83 switches the resistance value of the current limiting resistor circuit 80 based on the DC voltage Vdc of the first capacitor 15 detected by the voltage sensor 46. The AND circuit 82 outputs a signal representing the logical AND of the output signal of the voltage detection circuit 83 and the control power supply activation signal UC to switches SW1 and SW2.

[0061] Switches SW1 and SW2 are normally off, so they are off at startup. Therefore, at startup, the resistance value of the current-limiting resistor circuit 80 is Ra + Rb + Rc.

[0062] The control power supply 90 is activated to power supply 50 when the input voltage Vin rises to a certain value. Upon activation of the control power supply 90, the control power supply activation signal UC becomes high.

[0063] The voltage detection circuit 83 outputs a signal PX to switch SW1 to turn off switch SW1 when the DC voltage Vdc of the first capacitor 15 rises and the detected value of the DC voltage Vdc of the first capacitor 15 becomes equal to or greater than the switching voltage Vdc3. As a result, the resistance value of the current limiting resistor circuit 80 becomes Ra + Rb.

[0064] The voltage detection circuit 83 outputs a signal PX to switch SW2 to turn off switch SW2 when the DC voltage Vdc of the first capacitor 15 rises further and the detected value of the DC voltage Vdc of the first capacitor 15 becomes equal to or greater than the first switching voltage Vdc1. As a result, the resistance value of the current limiting resistor circuit 80 becomes Ra + Rb + Rc.

[0065] The voltage detection circuit 83 outputs a signal PX to switch SW2 to turn off switch SW2 when the DC voltage Vdc across the first capacitor 15 decreases and the detected value of the DC voltage Vdc across the first capacitor 15 becomes less than or equal to the switching voltage Vdc2. As a result, the resistance value of the current limiting resistor circuit 80 becomes Ra + Rb.

[0066] The voltage detection circuit 83 outputs a signal PX to switch SW1 to turn off switch SW1 when the DC voltage Vdc of the first capacitor 15 drops further and the detected value of the DC voltage Vdc of the first capacitor 15 becomes less than or equal to the switching voltage Vdc4. As a result, the resistance value of the current limiting resistor circuit 80 becomes Ra.

[0067] The overcharge suppression control circuit 53 suppresses overcharging of the second capacitor 51 by conducting / deconducting the switch S8 based on the input voltage Vin detected by the voltage sensor 52. When the input voltage Vin rises and the detected value of the input voltage Vin exceeds the threshold VA, the overcharge suppression control circuit 53 transitions the switching signal ST output to the switch S8 from L (logic low) level to H (logic high) level. When the input voltage Vin falls and the detected value of the input voltage Vin falls below the threshold VB, the overcharge suppression control circuit 53 transitions the switching signal ST output to the switch S8 from H level to L level. However, VA > VB.

[0068] The short-circuit fault detection circuit 200 detects a short-circuit fault in at least one of the switches SW1 and SW2 of the current-limiting resistor circuit 80 based on the duty cycle of the switching signal ST and the magnitude of the DC voltage Vdc of the first capacitor 15. The duty cycle of the switching signal ST represents the ratio of the on time (the time it is at a high level) to the switching period of the switching signal ST. More specifically, the short-circuit fault detection circuit 200 detects that at least one of the switches SW1 and SW2 of the current-limiting resistor circuit 80 is short-circuited if the duty cycle of the switching signal ST is greater than or equal to a reference value Ref, and the DC voltage Vdc of the first capacitor 15 is within a range of greater than or equal to a predetermined lower limit voltage VdcL and less than or equal to a predetermined upper limit voltage VdcH.

[0069] Figure 4 shows the configuration of the short-circuit fault detection circuit 200. The short-circuit fault detection circuit 200 includes an LPF 201, comparators 202 and 203, an AND circuit 204, an inverter 205, an on-time calculation circuit 206, a comparator 207, and an AND circuit 208.

[0070] LPF201 allows the low-frequency components of the DC voltage Vdc across the first capacitor 15 to pass through in order to remove noise.

[0071] The comparator 202 outputs an H-level signal when the DC voltage Vdc across the first capacitor 15 output from the LPF 201 is equal to or greater than the lower limit voltage VdcL, and outputs an L-level signal when the DC voltage Vdc across the first capacitor 15 is less than the lower limit voltage VdcL.

[0072] The comparator 203 outputs an H-level signal when the DC voltage Vdc across the first capacitor 15 output from the LPF 201 is less than or equal to the upper limit voltage VdcH, and outputs an L-level signal when the DC voltage Vdc across the first capacitor 15 exceeds the upper limit voltage VdcH.

[0073] The AND gate 204 outputs the logical AND of the output of comparator 202 and the output of comparator 203.

[0074] Inverter 205 inverts the output of AND circuit 204. The on-time calculation circuit 206 calculates the length of the on-time of the switching signal ST, i.e., the duty cycle D. The on-time calculation circuit 206 receives the output of the inverter 205 and resets the duty cycle D when the output of the AND circuit 204 is at a low level.

[0075] The comparator 207 outputs an H-level signal when the duty cycle D, which is the output of the on-time calculation circuit 206, is greater than or equal to the reference value Ref, and outputs an L-level signal when the duty cycle D, which is the output of the on-time calculation circuit 206, is less than the reference value Ref.

[0076] The AND gate 208 outputs a detection signal DT as the logical AND of the output of the AND gate 204 and the output of the comparator 207. When the detection signal DT is at a high level, it indicates that at least one of the switches SW1 and SW2 of the current-limiting resistor circuit 80 is short-circuited.

[0077] Figure 5 shows the time variation of the input voltage Vin and the switching signal ST when the DC voltage Vdc of the first capacitor 15 is relatively low. Figure 6 shows the time variation of the input voltage Vin and the switching signal ST when the DC voltage Vdc of the first capacitor 15 is relatively high.

[0078] As shown in Figures 5 and 6, when the input voltage Vin rises and the detected value of the input voltage Vin exceeds the threshold VA, the switching signal ST output to switch S8 changes from L level to H level. As a result, switch S8 conducts, overcharging of the second capacitor 51 is suppressed, and the input voltage Vin decreases. When the input voltage Vin falls and the detected value of the input voltage Vin falls below the threshold VB, the switching signal ST output to switch S8 changes from H level to L level. As a result, switch S8 becomes non-conductive, charging of the second capacitor 51 progresses, and the input voltage Vin increases.

[0079] Figure 6 shows the changes in the input voltage Vin and the switching signal ST when the DC voltage Vdc is greater than or equal to the first switching voltage Vdc1 and the resistance value of the current-limiting resistor circuit 80 is Ra + Rb + Rc.

[0080] As shown in Figure 6, when the DC voltage Vdc of the first capacitor 15 is high, the rate at which the input voltage Vin rises (the charging rate of the second capacitor 51) is faster than when the DC voltage Vdc of the first capacitor 15 is low. The rate at which the input voltage Vin falls (the discharge rate of the second capacitor 51) does not change depending on the magnitude of the DC voltage Vdc of the first capacitor 15. Therefore, as the DC voltage Vdc of the first capacitor 15 increases, the duty cycle of the switching signal ST increases.

[0081] Figure 7 shows the time variation of the input voltage Vin and the switching signal ST when at least one of the switches SW1 and SW2 of the current-limiting resistor circuit 80 is short-circuited. As shown in Figure 7, when at least one of the switches SW1 and SW2 is short-circuited, the charging rate of the second capacitor 51, i.e., the rate at which the input voltage Vin rises, becomes faster, and the duty cycle of the switching signal ST becomes larger.

[0082] Figure 8 shows the changes in the duty cycle of the switching signal ST and the supplied power PIN in response to a partial change in the DC voltage Vdc of the first capacitor 15, under normal and short-circuit conditions.

[0083] When the current-limiting resistor is short-circuited, the supplied power PIN increases, so the duty cycle of the switching signal ST increases in order to consume the excess power. Therefore, a method (hereinafter referred to as Method A) can be considered to detect a short circuit in switches SW1 and SW2 of the current-limiting resistor circuit 80 by monitoring the duty cycle of the switching signal ST (for example, by comparing it with a reference value Ref).

[0084] Figure 9 illustrates the short-circuit detection of at least one of the switches SW1 and SW2 of the current-limiting resistor circuit 80 by Method A. Figure 9 shows the changes in the resistance value of the current-limiting resistor circuit 80, the duty cycle of the switching signal ST, and the supplied power PIN in response to a change in the DC voltage Vdc of the first capacitor 15. Figure 9 shows only the waveform when the DC voltage Vdc of the first capacitor 15 is rising.

[0085] When the DC voltage Vdc of the first capacitor 15 is less than the first voltage V1, the power converter performs a start-up or stop-down process. When the DC voltage Vdc of the first capacitor 15 is greater than or equal to the first voltage V1 and less than or equal to the second voltage V2, the power converter operates normally. When the DC voltage Vdc of the first capacitor 15 exceeds the second voltage V2, the power converter enters an overvoltage state.

[0086] As shown in Figure 9, as the DC voltage Vdc of the first capacitor 15 increases, the duty cycle of the switching signal ST and the supplied power PIN increase.

[0087] When the DC voltage Vdc across the first capacitor 15 is at the switching voltage Vdc3, switch SW1 turns off, the supplied power PIN decreases, and the duty cycle of the switching signal ST also decreases. At this time, the resistance of the current-limiting resistor circuit 80 becomes Ra + Rb. When the DC voltage Vdc across the first capacitor 15 is at the first switching voltage Vdc1, switch SW2 turns off, the supplied power PIN decreases, and the duty cycle of the switching signal ST also decreases. At this time, all switches SW1 and SW2 included in the current-limiting resistor circuit 80 turn off, and the resistance value of the current-limiting resistor circuit 80 becomes the maximum value Ra + Rb + Rc. If switches SW1 and SW2 are short-circuited, the duty cycle of the supplied power PIN and the switching signal ST will be greater than under normal conditions.

[0088] Because the resistance value of the current-limiting resistor circuit 80 changes due to the DC voltage Vdc of the first capacitor 15, the duty cycle of the switching signal ST temporarily exceeds the reference value Ref even during the startup or shutdown process of the power converter. Therefore, in method A, even under normal circumstances, the switches SW1 and SW2 of the current-limiting resistor circuit 80 are incorrectly detected as having a short-circuit fault.

[0089] When the DC voltage Vdc of the first capacitor 15 is overvoltage, the duty cycle of the switching signal ST increases and becomes larger than the reference value Ref. Therefore, in method A, even under normal conditions, the switches SW1 and SW2 of the current-limiting resistor circuit 80 are incorrectly detected as having a short-circuit fault.

[0090] Figure 10 is a diagram illustrating a method for detecting a short-circuit fault in the current-limiting resistor circuit 80 according to an embodiment. Similar to Figure 9, Figure 10 shows the changes in the resistance value of the current-limiting resistor circuit 80, the duty cycle of the switching signal ST, and the supplied power PIN in normal and short-circuit conditions in response to a change in the DC voltage Vdc of the first capacitor 15, and only the waveform when the DC voltage Vdc of the first capacitor 15 is rising is shown.

[0091] In this embodiment, the detection range for short-circuit faults in switches SW1 and SW2 of the current-limiting resistor circuit 80 is limited when the DC voltage Vdc of the first capacitor 15 is within a predetermined range (lower limit voltage VdcL or higher and upper limit voltage VdcH or lower). This prevents false detections due to overvoltage of the DC voltage Vdc of the first capacitor 15 and temporary exceedance of reference values ​​during the startup or shutdown process of the power converter.

[0092] Figure 11 is a diagram illustrating the magnitudes of the lower voltage limit VdcL, the upper voltage limit VdcH, and the reference value Ref.

[0093] The lower limit voltage VdcL is set to a value greater than the first switching voltage Vdc1 and less than the first voltage V1, which is the lower limit of the normal operating range. Within this range, the lower limit voltage VdcL can be set to any value.

[0094] The reference value Ref and the upper limit voltage VdcH can be determined by the following procedure. To enable detection of short-circuit faults during normal operation, the reference value Ref is set to a value less than or equal to the duty cycle (point a) of the switching signal ST of the switch SW1 of the current-limiting resistor circuit 80 during a short-circuit fault, when the DC voltage Vdc of the first capacitor 15 is equal to the first voltage V1. For example, the reference value Ref should be set to a value slightly smaller than point a.

[0095] When the power converter is in an overvoltage state, even if switches SW1 and SW2 of the current-limiting resistor circuit 80 are functioning normally, the duty cycle of the switching signal ST exceeds the set reference value Ref. To prevent detection of this, the upper limit voltage VdcH is set to a value less than or equal to the value of the DC voltage Vdc of the first capacitor 15 (point b) when the duty cycle of the switching signal ST is at the reference value Ref, while the power converter is in an overvoltage state (Vdc>V2) and switches SW1 and SW2 of the current-limiting resistor circuit 80 are functioning normally. For example, the upper limit voltage VdcH should be set to a value slightly smaller than point b.

[0096] Although Figure 10 only shows the waveform when the DC voltage Vdc of the first capacitor 15 is rising, the short-circuit fault detection method for switches SW1 and SW2 of the current-limiting resistor circuit 80 in this embodiment can also be applied when the DC voltage Vdc of the first capacitor 15 is falling. Figure 10 shows the case when either switch SW1 or switch SW2 is short-circuited, but when both switch SW1 and switch SW2 are short-circuited, the duty cycle of the supplied power PIN and switching signal ST becomes larger than when either switch SW1 or SW2 is short-circuited, so detection is possible even in that case.

[0097] As described above, according to this embodiment, by limiting the DC voltage range for detecting short-circuit faults in switches SW1 and SW2 of the current-limiting resistor circuit 80, it is possible to prevent false detections due to temporary exceedance of a reference value during overvoltage of the DC voltage Vdc of the first capacitor 15 and during the startup or shutdown process of the power converter.

[0098] In the above embodiment, the current-limiting resistor circuit 80 comprises three resistor elements and two switches, but it is not limited to this. The current-limiting resistor circuit 80 may also comprise N resistor elements connected in series and (N-1) switches, each connected in parallel with one of the (N-1) resistor elements out of the N resistor elements.

[0099] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended. [Explanation of Symbols]

[0100] 1 Power system, 1u, 1v, 1w Transmission line, 2,3 Transformer, 4 Control device, 5 Unit converter, 5a First terminal, 5b Second terminal, 11~14 Switching element, 15, 51 Capacitor, 18 Excitation coil, 30 Main circuit, 32 Control circuit, 40, 42 Drive circuit, 44 Switch operation circuit, 46, 52 Voltage sensor, 48 I / F circuit, 50 Power supply, 53 Overcharge suppression control circuit, 54 Overcharge suppression circuit, 55 Start / stop circuit, 56 Power supply circuit, 80 Current limiting resistor circuit, 82 AND circuit, 83 Voltage detection circuit, 88 Resistance switching circuit, 90 Control power supply, 200 Short circuit fault detection circuit, 201 LPF, 202, 203, 207 Comparator, 204, 208 AND circuit, 205 Inverter, 206 On-time calculation circuit, 500 Control unit, 501, 502 input terminals, A1~A3 arms, C1~C3 current transformers, D1~D4 diodes, Iuv, Ivw, Iwu AC current, L1~L3 reactors, NL, PL DC lines, R1~R3 ​​current limiting resistors, R5, Ra, Rb, Rc resistors, S1~S8, SW1, SW2 switches, UL, VL, WL AC lines.

Claims

1. A power converter having an arm configured by connecting multiple unit converters in series, The system includes a control device for controlling the power converter, Each of the aforementioned plurality of unit converters is A main circuit including multiple switching elements and a first capacitor electrically connected between a first DC line and a second DC line, A control circuit configured to control the plurality of switching elements in accordance with a control signal received from the control device, A power supply that generates a power supply voltage by stepping down the voltage of the first capacitor described above, and supplies the power supply voltage to the control circuit, The system includes a current-limiting resistor circuit positioned between the main circuit and the power supply, the resistance value of which can be switched by at least one switch, The aforementioned power supply is A second capacitor electrically connected between the first DC line and the second DC line, An overcharge suppression circuit electrically connected between the first DC line and the second DC line, A power supply circuit is electrically connected between the first DC line and the second DC line and configured to convert the voltage of the second capacitor into the power supply voltage, It includes a control unit, The control unit, An overcharge suppression control circuit outputs a switching signal to the overcharge suppression circuit for controlling the overcharge suppression circuit according to the magnitude of the voltage of the second capacitor, A current-limiting resistor switching circuit that switches the resistance value of the current-limiting resistor circuit according to the magnitude of the DC voltage of the first capacitor, A power converter comprising a short-circuit fault detection circuit that detects a short-circuit fault in at least one switch of the current-limiting resistor circuit based on the duty cycle of the switching signal and the magnitude of the DC voltage of the first capacitor.

2. The power conversion device according to claim 1, wherein the short-circuit fault detection circuit detects that the switch of the current-limiting resistor circuit is short-circuit faulted when the duty cycle of the switching signal is greater than or equal to a reference value, and the DC voltage of the first capacitor is within a range of greater than or equal to a predetermined lower limit voltage and less than or equal to a predetermined upper limit voltage.

3. When the voltage of the first capacitor is less than the first voltage, the power converter performs a start-up process and a stop-down process. When the voltage of the first capacitor is greater than or equal to the first voltage and less than or equal to the second voltage, the power converter operates normally. When the voltage across the first capacitor exceeds the voltage across the second capacitor, the power converter enters an overvoltage state. The power conversion device according to claim 2, wherein the current-limiting resistor switching circuit, when the voltage of the first capacitor rises, increases the resistance value of the current-limiting resistor circuit in steps by turning off each switch included in the current-limiting resistor circuit at each switching voltage of the voltage of the first capacitor, and at a first switching voltage below the first voltage, all switches included in the current-limiting resistor circuit are turned off, and the resistance value of the current-limiting resistor circuit becomes maximum.

4. The power conversion device according to claim 3, wherein the lower limit voltage is smaller than the first voltage and the upper limit voltage is larger than the second voltage.

5. The power conversion device according to claim 4, wherein the lower limit voltage is greater than the first switching voltage.

6. The power conversion device according to claim 4, wherein the reference value is a value less than or equal to the duty cycle of the switching signal during a short-circuit failure of at least one switch of the current-limiting resistor circuit when the DC voltage of the first capacitor is the first voltage.

7. The power converter according to claim 6, wherein the upper limit voltage is a value less than or equal to the DC voltage of the first capacitor when the duty cycle of the switching signal becomes the reference value, when the power converter is in an overvoltage state and the switch of the current limiting resistor circuit is functioning normally.

8. The current-limiting resistor circuit is N resistors connected in series, The power conversion device according to any one of claims 1 to 7, each comprising (N-1) switches connected in parallel to one of the (N-1) resistive elements among the N resistive elements.

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