Semiconductor equipment

Abstract

To simplify a manufacturing step of a semiconductor device.SOLUTION: A semiconductor device 100 comprises: a connection terminal P2 and a connection terminal N2; a driving circuit that contains one or more power conductor elements; a control circuit that controls one or more power semiconductor elements; a wiring board 60; a capacitative element 15 installed in the wiring board 60; and a high-potential bus bar and a low-potential bus bar. The high-potential bus bar includes: a main body part 71 constructing a path for electrically connecting the connection terminal P2 with the driving circuit; and a projection part 732 projected toward the wiring board 60 with respect to the main body part 71. The low-potential bus bar includes: a main body part 81 constructing a path for electrically connecting the connection terminal N2 and the driving circuit; and a projection part 832 projected toward the wiring board 60 with respect to the main body part 81. The capacitative element 15 is electrically connected to the projection part 732 and the projection part 832.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This disclosure relates to a semiconductor device using a power semiconductor device.

Background Art

[0002] For example, semiconductor devices using power semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor) have been proposed conventionally. For example, Patent Document 1 discloses a power conversion device including a first substrate on which a switching element is mounted and a second substrate on which a capacitive element is mounted. The switching element and the capacitive element are electrically connected by dedicated wiring extending over the first substrate and the second substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the configuration of Patent Document 1, it is necessary to join a linear wiring, which is configured separately from an element installed on the first substrate or an element installed on the second substrate, to both the first substrate and the second substrate. Therefore, it is difficult to simplify the manufacturing process of the device. In view of the above circumstances, one aspect of this disclosure aims to simplify the manufacturing process of the semiconductor device.

Means for Solving the Problems

[0005] To solve the above problems, the semiconductor device according to this disclosure comprises a first connection terminal and a second connection terminal, a drive circuit including one or more power semiconductor elements, a control circuit for controlling the one or more power semiconductor elements, a wiring board, a passive element mounted on the wiring board, a first bus bar and a second bus bar, wherein the first bus bar includes a first main body that constitutes a path for electrically connecting the first connection terminal and the drive circuit, and a first projection that protrudes toward the wiring board relative to the first main body, and the second bus bar includes a second main body that constitutes a path for electrically connecting the second connection terminal and the drive circuit, and a second projection that protrudes toward the wiring board relative to the second main body, and the passive element is electrically connected to the first projection and the second projection. [Brief explanation of the drawing]

[0006] [Figure 1] This is a circuit diagram illustrating the electrical configuration of a semiconductor device according to the first embodiment. [Figure 2] This is a plan view illustrating the configuration of a semiconductor device. [Figure 3] This is a cross-sectional view along line III-III in Figure 2. [Figure 4] This is a plan view illustrating the configuration of the semiconductor unit and its housing. [Figure 5] This is a plan view illustrating the configuration of a semiconductor device that focuses on connecting conductors. [Figure 6] This is a plan view from Figure 5 with the semiconductor unit omitted. [Figure 7] This is a perspective view of the relationship between the connection point and the mounted circuit board. [Figure 8] This is a partially magnified perspective view of the high-potential and low-potential busbars. [Figure 9] This is a magnified plan view of the vicinity of a capacitive element. [Figure 10] Figure 9 is a cross-sectional view of the XX line. [Figure 11] This is a process diagram illustrating the manufacturing process of semiconductor devices. [Figure 12]This is a circuit diagram illustrating the electrical configuration of a semiconductor device in a second embodiment. [Figure 13] This is a block diagram illustrating the configuration of the detection circuit. [Figure 14] This is a plan view illustrating the configuration of a semiconductor device in the second embodiment. [Figure 15] This is an enlarged plan view of the resistor array in the second embodiment. [Figure 16] This is a perspective view of the high-potential busbar and low-potential busbar in modified example (1). [Figure 17] This is a perspective view of the high-potential busbar and low-potential busbar in modified example (2). [Figure 18] This is a perspective view of the high-potential busbar and low-potential busbar in modified example (3). [Modes for carrying out the invention]

[0007] The embodiments for implementing this disclosure will be described with reference to the drawings. Note that the dimensions and scale of the elements in each drawing may differ from those of the actual product. Furthermore, the embodiments described below are illustrative examples of embodiments that may be envisioned when implementing this disclosure. Therefore, the scope of this disclosure is not limited to the embodiments exemplified below.

[0008] A: First Embodiment Figure 1 is a circuit diagram illustrating the electrical configuration of the semiconductor device 100. The semiconductor device 100 is a power semiconductor module used as a three-phase inverter circuit to drive an electric motor such as a three-phase motor. As illustrated in Figure 1, the semiconductor device 100 comprises connection terminals P (P1, P2), connection terminals N (N1, N2), three output terminals O[1] to O[3], three drive circuits 11[1] to 11[3], a control circuit 13, and a capacitive element 15.

[0009] The connection terminals P (P1, P2) are positive input terminals (P terminals) for electrically connecting each drive circuit 11[k] (k = 1 to 3) to an external device (not shown). The connection terminals N (N1, N2) are negative input terminals (N terminals) for electrically connecting each drive circuit 11[k] to an external device. A higher voltage is applied to each connection terminal P compared to each connection terminal N. The connection terminal P is an example of a "first connection terminal", and the connection terminal N is an example of a "second connection terminal".

[0010] Each output terminal O[k] is a terminal electrically connected to different input terminals of the motor to be driven. The power required to drive the motor is supplied from each output terminal O[k] to the motor. The three output terminals O[1] to O[3] correspond to the output terminals of the U phase, V phase, and W phase that constitute a three-phase inverter circuit.

[0011] Each drive circuit 11[k] is a circuit for controlling the current supplied from the output terminal O[k] to the motor. The three drive circuits 11[1] to 11[3] correspond to the drive circuits of the U phase, V phase, and W phase that constitute a three-phase inverter circuit. Each drive circuit 11[k] is electrically connected to each connection terminal P via the high-potential bus bar 70 and electrically connected to each connection terminal N via the low-potential bus bar 80. The high-potential bus bar 70 is a wiring for electrically connecting each connection terminal P and each drive circuit 11[k]. The low-potential bus bar 80 is a wiring for electrically connecting each connection terminal N and each drive circuit 11[k]. The high-potential bus bar 70 is set to a higher potential than the low-potential bus bar 80. The high-potential bus bar 70 is an example of a "first bus bar", and the low-potential bus bar 80 is an example of a "second bus bar". Note that the number of drive circuits 11[k] mounted on the semiconductor device 100 is arbitrary and is not limited to the three exemplified in the first embodiment.

[0012] The semiconductor device 100 includes six switching elements S (SH[1] to SH[3], SL[1] to SL[3]) and six diode elements D (DH[1] to DH[3], DL[1] to DL[3]). Each switching element S is a transistor including a main electrode E, a main electrode C, and a control electrode G. Each diode element D is a rectifying element including an anode (A) and a cathode (K). The switching element S and the diode element D are an example of a "power semiconductor element". Note that the number or type of power semiconductor elements included in the drive circuit 11[k] is not limited to the example of the first embodiment.

[0013] Each drive circuit 11[k] is a half-bridge circuit including two switching elements S (SH[k], SL[k]) and two diode elements D (DH[k], DL[k]). The main electrode C of the high-potential-side switching element SH[k] is electrically connected to the high-potential bus bar 70, and the main electrode E of the low-potential-side switching element SL[k] is electrically connected to the low-potential bus bar 80. The main electrode E of the switching element SH[k] and the main electrode C of the switching element SL[k] are electrically connected to the output-side bus bar 54[k]. The output-side bus bar 54[k] is a wiring for electrically connecting the drive circuit 11[k] and the output terminal O[k]. Also, the diode element DH[k] is connected in parallel with the switching element SH[k], and the diode element DL[k] is connected in parallel with the switching element SL[k].

[0014] The control circuit 13 is a circuit that controls each switching element S (SH[1] to SH[3], SL[1] to SL[3]). The control circuit 13 includes six control chips 14 (14H[1] to 14H[3], 14L[1] to 14L[3]) corresponding to different switching elements S. Each control chip 14H[k] is a HVIC (High Voltage IC) that controls the high-potential-side switching element SH[k]. Each control chip 14L[k] is a LVIC (Low Voltage IC) that controls the low-potential-side switching element SL[k].

[0015] The capacitive element 15 is a passive element electrically connected to the high-potential busbar 70 and the low-potential busbar 80. Specifically, the capacitive element 15 includes a first electrode 151 and a second electrode 152. The first electrode 151 is electrically connected to the high-potential busbar 70, and the second electrode 152 is electrically connected to the low-potential busbar 80. With this configuration in which the capacitive element 15 is connected between the high-potential busbar 70 and the low-potential busbar 80, the frequency characteristics of the noise caused by the switching of the switching element S can be changed. Specifically, the frequency at which a peak exists in the noise frequency characteristics can be changed. The capacitive element 15 may also be used as a snubber capacitor to reduce surge voltages that instantaneously occur in the semiconductor device 100. However, a large capacitive element 15 is required to sufficiently reduce surge voltages. Therefore, from the viewpoint of miniaturizing the semiconductor device 100, a configuration in which a large snubber capacitor separate from the capacitive element 15 is externally attached to the semiconductor device 100 is preferable.

[0016] Figure 2 is a plan view illustrating the configuration of the semiconductor device 100. Figure 3 is a cross-sectional view taken along line III-III in Figure 2. Note that Figures 4 and 5, shown later, also illustrate the cutting lines corresponding to the cross-section in Figure 3, similar to Figure 2.

[0017] In the following explanation, we assume that the X, Y, and Z axes are mutually orthogonal, as illustrated in Figures 2 and 3. One direction along the X axis is denoted as the X1 direction, and the opposite direction is denoted as the X2 direction. The direction of the X axis can also be described as the longitudinal direction of the semiconductor device 100 (i.e., the direction of the longer side in its external shape). Similarly, one direction along the Y axis is denoted as the Y1 direction, and the opposite direction is denoted as the Y2 direction. Likewise, one direction along the Z axis is denoted as the Z1 direction, and the opposite direction is denoted as the Z2 direction. Furthermore, viewing any element of the semiconductor device 100 along the Z axis (Z1 or Z2 direction) will be referred to as "planar view" below.

[0018] In actual use, the semiconductor device 100 can be installed in any direction, but for convenience, in the following explanation, we will assume that the Z1 direction is downward and the Z2 direction is upward. Therefore, any surface of the semiconductor device 100 facing the Z1 direction will be referred to as the "bottom surface," and any surface of the same element facing the Z2 direction will be referred to as the "top surface." Also, as illustrated in Figure 2, in the following explanation, we will assume a hypothetical plane (hereinafter referred to as the "reference plane") R parallel to the XZ plane. The reference plane R is located in the center of the semiconductor device 100 in the direction of the Y axis. That is, the reference plane R is a plane that bisects the semiconductor device 100 in the direction of the Y axis.

[0019] As illustrated in Figure 3, the semiconductor device 100 of the first embodiment comprises a base portion 21, a cover portion 22, a housing portion 30, a semiconductor unit 40, a connecting conductor 50, and a wiring board 60. The connecting conductor 50 is located between the semiconductor unit 40 and the wiring board 60. The wiring board 60 is located between the connecting conductor 50 and the cover portion 22. Note that the cover portion 22 is omitted in Figure 2 for convenience.

[0020] The base portion 21 in Figure 3 is a rectangular plate-like member that supports the semiconductor unit 40, and is made of a conductive material such as aluminum or copper. The base portion 21 is also used as a heat sink that radiates the heat generated in the semiconductor unit 40. Alternatively, a cooler such as fins or a water-cooled jacket that cools the semiconductor unit 40 may be used as the base portion 21. Furthermore, the base portion 21 may be used as a grounding element set to ground potential.

[0021] The housing 30 houses the semiconductor unit 40, the connecting conductor 50, and the wiring board 60. The housing 30 is formed from various resin materials, such as PPS (polyphenylene sulfide) resin, PBT (polybutylene terephthalate) resin, PBS (poly butylene succinate) resin, PA (polyamide) resin, or ABS (acrylonitrile-butadiene-styrene) resin.

[0022] Figure 4 is a plan view illustrating the configuration of the semiconductor unit 40 and the housing portion 30. That is, Figure 4 shows the state with the connecting conductor 50 and the wiring board 60 removed from Figure 2. As illustrated in Figure 4, the housing portion 30 comprises side wall portions 31, 32, 33, 34, and protruding portions 35 and 36. The side wall portions 31, 32, 33, and 34 are connected to each other to form a rectangular frame-shaped structure. The side wall portions 31 and 33 are wall-like portions that extend in the direction of the Y axis with a gap in the direction of the X axis. On the other hand, the side wall portions 32 and 34 are wall-like portions that extend in the direction of the X axis with a gap in the direction of the Y axis. The side wall portions 32 and 34 are shaped to connect the ends of the side wall portions 31 and 33 to each other.

[0023] The protruding portion 35 is a flat plate-shaped portion that protrudes in the Y1 direction from the inner wall surface of the side wall portion 32. The protruding portion 36 is a flat plate-shaped portion that protrudes in the Y2 direction from the inner wall surface of the side wall portion 34. Each of the protruding portions 35 and 36 extends in the X-axis direction across the inner circumferential surface of the side wall portion 31 and the inner circumferential surface of the side wall portion 33. As illustrated in Figure 3, the base portion 21 is fixed in the space surrounded by the side wall portions 31, 32, 33 and 34 in the Z1 direction relative to the protruding portions 35 and 36. The semiconductor unit 40, the connecting conductor 50 and the wiring board 60 are housed in the space surrounded by the side wall portions 31, 32 and 33 and 34, with the top surface of the base portion 21 as the bottom surface. As illustrated in Figure 3, the semiconductor unit 40 is located between the protruding portion 35 and the protruding portion 36. The lid portion 22 in Figure 3 is fixed to the housing portion 30 so as to close the space (opening) surrounded by the side walls 31, 32, 33, and 34. That is, the base portion 21 and the lid portion 22 face each other with a gap between them. The semiconductor unit 40, the connecting conductor 50, and the wiring board 60 are housed in the space between the base portion 21 and the lid portion 22.

[0024] A sealing member (not shown) may be formed in the space surrounded by the housing portion 30. The sealing member seals the semiconductor unit 40, the connecting conductor 50, and the wiring board 60. The sealing member is formed from various resin materials, such as silicone gel or epoxy resin. In addition to the resin material, the sealing member may also contain various insulating fillers, such as silicon oxide or aluminum oxide.

[0025] As illustrated in Figure 4, the housing portion 30 is equipped with a plurality of support members 37 (37H[1] to 37H[3], 37L[1] to 37L[3]) corresponding to different switching elements S. Three support members 37H[1] to 37H[3] corresponding to different switching elements SH[k] are formed on the upper surface of the protruding portion 36. Each support member 37H[k] is a prismatic portion that protrudes from the upper surface of the protruding portion 36 in the Z2 direction and is formed integrally with the protruding portion 36. On the other hand, three support members 37L[1] to 37L[3] corresponding to different switching elements SL[k] are formed on the upper surface of the protruding portion 35. Each support member 37L[k] is a prismatic portion that protrudes from the upper surface of the protruding portion 35 in the Z2 direction and is formed integrally with the protruding portion 35.

[0026] As illustrated in Figures 3 and 4, each support 37 is provided with a plurality of control terminals 38. The plurality of control terminals 38 on each support 37 are conductors with a circular cross-section that supply control signals to the control chip 14 for controlling each switching element S. As illustrated in Figure 3, each control terminal 38 includes a lower end portion 381 that protrudes from the side of the support 37 and an upper end portion 382 that protrudes in the Z2 direction from the top surface of the support 37.

[0027] Furthermore, multiple external terminals 39 are installed on the side wall portion 34 of the housing portion 30. Each external terminal 39 is a conductor with a circular cross-section for supplying control signals from an external device to the semiconductor device 100 for controlling the switching element S. The control signals supplied to each external terminal 39 are transmitted to each control terminal 38 via the wiring board 60, and from each control terminal 38 to each control chip 14 via the wiring board 60. Each external terminal 39 includes a lower end portion 391 that protrudes from the inner wall surface of the housing portion 30 (side wall portions 32, 34) and an upper end portion 392 that protrudes in the Z2 direction from the upper surface of the side wall portion 34. Each control terminal 38 and each external terminal 39 are formed integrally with the housing portion 30, for example by insert molding.

[0028] As illustrated in Figures 3 and 4, the semiconductor unit 40 comprises a mounting substrate 41, six switching elements S (SH[1]~SH[3], SL[1]~SL[3]), and six diode elements D (DH[1]~DH[3], DL[1]~DL[3]). Each switching element S and each diode element D is mounted on the mounting substrate 41.

[0029] The mounting substrate 41 is a rectangular plate-shaped member that supports each drive circuit 11[k]. For example, a multilayer ceramic substrate such as a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate, or a metal base substrate including a resin insulating layer, can be used as the mounting substrate 41.

[0030] The mounting substrate 41 is a laminated substrate composed of an insulating substrate 42, a metal layer 43, and a plurality of conductor patterns 44 (44H[k]_a, 44H[k]_b, 44L[k]_a, 44L[k]_b). The insulating substrate 42 is a rectangular plate-like member formed of an insulating material. The material of the insulating substrate 42 is arbitrary, but for example, ceramic materials such as alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4), or resin materials such as epoxy resin can be used.

[0031] The metal layer 43 is a conductive film formed on the lower surface of the insulating substrate 42 that faces the base portion 21. The metal layer 43 is formed on part or all of the lower surface of the insulating substrate 42. The lower surface of the metal layer 43 is in contact with the upper surface of the base portion 21. The metal layer 43 is made of a highly thermally conductive metal material such as copper or aluminum.

[0032] As illustrated in Figure 4, the upper surface of the insulating substrate 42 is divided into six mounting regions 45 (45H[1]~45H[3], 45L[1]~45L[3]) corresponding to different switching elements S. Three mounting regions 45H[1]~45H[3] are arranged in the direction of the X axis in a plan view. Similarly, three mounting regions 45L[1]~45L[3] are arranged in the direction of the X axis in a plan view. Three mounting regions 45H[1]~45H[3] are located in the Y1 direction when viewed from the reference plane R, and three mounting regions 45L[1]~L[3] are located in the Y2 direction when viewed from the reference plane R. The boundary between the three high-potential mounting regions 45H[1]~45H[3] and the three low-potential mounting regions 45L[1]~45L[3] may be expressed as the reference plane R.

[0033] Each conductor pattern 44 is a conductive film formed on the upper surface of the insulating substrate 42. For example, the conductor patterns 44 are formed from a low-resistance conductive material such as copper or a copper alloy. As illustrated in Figure 4, in each mounting region 45H[k], conductor patterns 44H[k]_a and conductor patterns 44H[k]_b are formed spaced apart from each other. Similarly, in each mounting region 45L[k], conductor patterns 44L[k]_a and conductor patterns 44L[k]_b are formed spaced apart from each other.

[0034] Each switching element S (SH[1]~SH[3], SL[1]~SL[3]) is a power semiconductor element capable of switching between current conduction and interruption, and is bonded to the mounting substrate 41 via a bonding material such as solder (not shown). In the first embodiment, each switching element S is an IGBT (Insulated Gate Bipolar Transistor). Each switching element S is a semiconductor chip comprising a main electrode E, a main electrode C, and a control electrode G. The main electrode E and the main electrode C are electrodes to which the current to be controlled is input or output. Specifically, the main electrode E is an emitter electrode formed on the upper surface of the switching element S, and the main electrode C is a collector electrode formed on the lower surface of the switching element S. On the other hand, the control electrode G is a gate electrode to which a voltage for controlling the on / off state of the switching element S is applied, and is formed on the upper surface of the switching element S. The control electrode G may also include a detection electrode used for current detection or temperature detection, etc.

[0035] Each switching element SH[k] is joined to the conductor pattern 44H[k]_a within the mounting area 45H[k]. That is, the main electrode C of the switching element SH[k] is joined to the conductor pattern 44H[k]_a. Similarly, each switching element SL[k] is joined to the conductor pattern 44L[k]_a within the mounting area 45L[k]. That is, the main electrode C of the switching element SL[k] is joined to the conductor pattern 44L[k]_a.

[0036] Each diode element D (DH[1]~DH[3], DL[1]~DL[3]) is a power semiconductor element that rectifies current and is joined to the mounting substrate 41 via a bonding material such as solder. Each diode element D is a semiconductor chip comprising an anode A and a cathode K. The anode A is formed on the upper surface of the diode element D, and the cathode K is formed on the lower surface of the diode element D.

[0037] Each diode element DH[k] is joined to the conductor pattern 44H[k]_a in the mounting region 45H[k]. That is, the cathode K of the diode element DH[k] is joined to the conductor pattern 44H[k]_a. Similarly, each diode element DL[k] is joined to the conductor pattern 44L[k]_a in the mounting region 45L[k]. That is, the cathode K of the diode element DL[k] is joined to the conductor pattern 44L[k]_a.

[0038] In the above configuration, the main electrode E of each switching element SH[k] is electrically connected to the conductor pattern 44H[k]_b within the mounting area 45H[k] by multiple wires. The control electrode G of each switching element SH[k] is electrically connected to each control terminal 38 of the support 37H[k] by multiple wires. Specifically, the control electrode G and the lower end 381 of each control terminal 38 are electrically connected by wires. In addition, the anode A of each diode element DH[k] is electrically connected to the conductor pattern 44H[k]_b by multiple wires. Similarly, the main electrode E of each switching element SL[k] is electrically connected to the conductor pattern 44L[k]_b within the mounting area 45L[k] by multiple wires. The control electrode G of each switching element SL[k] is electrically connected to each control terminal 38 (lower end 381) of the support 37L[k] by multiple wires. In addition, the anode A of each diode element DL[k] is electrically connected to the conductor pattern 44L[k]_b by multiple wires.

[0039] As illustrated in Figures 2 to 4, connection terminals P1 and N1 are installed on the side wall portion 31 of the housing portion 30. Specifically, connection terminal P1 is installed in the Y1 direction when viewed from the reference plane R, and connection terminal N1 is installed in the Y2 direction when viewed from the reference plane R. In addition, connection terminals P2 and N2 are installed on the side wall portion 33 of the housing portion 30. Specifically, connection terminal P2 is installed in the Y1 direction when viewed from the reference plane R, and connection terminal N2 is installed in the Y2 direction when viewed from the reference plane R.

[0040] Figure 5 is a plan view illustrating the configuration of the semiconductor device 100, focusing on the connecting conductor 50. Figure 5 shows the device with the wiring board 60 omitted from Figure 2. Figure 6 is a plan view of Figure 5 with the semiconductor unit 40 omitted. As illustrated in Figures 5 and 6, the connecting conductor 50 in Figure 2 consists of a high-potential busbar 70, a low-potential busbar 80, and three output-side busbars 54[1] to 54[3]. Each busbar is a plate-shaped or rod-shaped conductor for conducting large currents, and is made of a conductive material such as copper or aluminum. The high-potential busbar 70 is a conductor for electrically connecting the three drive circuits 11[1] to 11[3] to connection terminals P1 and P2, as described above with reference to Figure 1. On the other hand, the low-potential busbar 80 is a conductor for electrically connecting the three drive circuits 11[1] to 11[3] to connection terminals N1 and N2.

[0041] As illustrated in Figure 6, the high-potential busbar 70 is a structure that includes a main body 71, three connecting parts 72 (72[1] to 72[3]), and one connecting part 73. The main body 71 and each of the connecting parts 72 and 73 are integrally formed. For example, the high-potential busbar 70 is formed by bending a metal plate that has been formed into a predetermined planar shape by press working. The high-potential busbar 70 is located between the mounting substrate 41 and the wiring substrate 60.

[0042] The main body portion 71 extends in the direction of the X axis. Specifically, the main body portion 71 extends linearly in the direction of the X axis across the opposing side walls 31 and 33. One end of the main body portion 71 is connected to connection terminal P1, and the other end of the main body portion 71 is connected to connection terminal P2. Specifically, the end of the main body portion 71 located in the X1 direction is connected to connection terminal P1, and the end located in the X2 direction is connected to connection terminal P2.

[0043] Each connection portion 72 is a part for electrically connecting the mounting substrate 41 (conductor pattern 44) and the main body portion 71. Each connection portion 72 branches off from the main body portion 71 in the Y1 direction. Specifically, each connection portion 72[k] branches off from the part of the main body portion 71 corresponding to the mounting area 45H[k] in a plan view in the Y1 direction and is electrically connected to the conductor pattern 44H[k]_a within the said mounting area 45H[k].

[0044] Figure 7 is a perspective view showing the relationship between each connection portion 72 (72[1] to 72[3]) and the mounting substrate 41. As illustrated in Figure 7, the connection portion 72 consists of an extension portion 55 and a terminal portion 56. The extension portion 55 is a portion that branches laterally from the side surface of the main body portion 71 and extends in a direction parallel to the XY plane. The terminal portion 56 is a portion that protrudes in the Z1 direction toward the mounting substrate 41 from the tip of the extension portion 55. The tip of the terminal portion 56 is joined to the conductor pattern 44 using a bonding material such as solder. As can be understood from the above explanation, the connection portion 72 protrudes toward the mounting substrate 41 relative to the main body portion 71 and is electrically connected to the drive circuit 11[k]. The main body portion 71 is an example of the "first main body portion", and the connection portion 72 is an example of the "first connection portion".

[0045] The connection portion 73 in Figure 6 is a part for electrically connecting the wiring board 60 and the main body 71. The connection portion 73 branches off from the main body 71. Specifically, the connection portion 73 is a part of the main body 71 that branches off in the Y2 direction from near the center in the X-axis direction.

[0046] Figure 8 is a partially enlarged perspective view of the high-potential busbar 70 and the low-potential busbar 80. As illustrated in Figure 8, the connection portion 73 is composed of an extended portion 731 and a projection portion 732. The extended portion 731 is the part that branches off from the main body portion 71 and extends in a direction parallel to the XY plane. Specifically, the extended portion 731 extends linearly from the main body portion 71 in the Y2 direction. The projection portion 732 is the part that protrudes from the tip of the extended portion 731 toward the wiring board 60 in the Z2 direction. Specifically, the projection portion 732 is the part that is bent relative to the extended portion 731. That is, the projection portion 732 is formed by bending a linear portion that branches laterally from the main body portion 71 in the Z2 direction, for example by press working. Therefore, the cross-sectional shape of the projection portion 732 is rectangular. With the above configuration, for example, the projection 732 can be easily formed compared to a configuration in which a projection 732 separate from the extension 731 is joined to the extension 731. As can be understood from the above description, the high-potential busbar 70 includes a projection 732 that protrudes toward the wiring board 60 relative to the main body 71. The extension 731 is an example of the "first extension," and the projection 732 is an example of the "first projection."

[0047] As illustrated in Figure 6, the low-potential busbar 80 is a structure that includes a main body 81, three connection parts 82 (82[1] to 82[3]), one connection part 83, a connecting part 84, and a connecting part 85. The main body 81 and each of the connection parts 82, connection part 83, connecting part 84, and connecting part 85 are integrally formed. For example, similar to the high-potential busbar 70, the low-potential busbar 80 is formed by bending a metal plate that has been formed into a predetermined planar shape by press working. The low-potential busbar 80 is located between the mounting substrate 41 and the wiring substrate 60.

[0048] The main body portion 81 is a part that extends linearly in the direction of the X axis. The connecting portion 84 is a part that is bent or curved in a plan view relative to the main body portion 81 so as to connect the end of the main body portion 81 in the X1 direction to the connection terminal N1. Similarly, the connecting portion 85 is a part that is bent or curved in a plan view relative to the main body portion 81 so as to connect the end of the main body portion 81 in the X2 direction to the connection terminal N2. That is, the elongated portion composed of the connecting portion 84, the main body portion 81, and the connecting portion 85 extends across the opposing side walls 31 and 33. One end of this portion is connected to the connection terminal N1, and the other end of this portion is connected to the connection terminal N2.

[0049] The main body portion 71 and the main body portion 81 extend in the direction of the X axis at a position spaced apart from the reference plane R in the Y1 direction. That is, as can be understood from Figures 4 and 5, the main body portion 71 and the main body portion 81 overlap in a plan view in each mounting area 45H[k], but do not overlap in a plan view in each mounting area 45L[k]. Also, the main body portion 71 and the main body portion 81 overlap each other in a plan view. That is, the main body portion 71 and the main body portion 81 face each other with a certain distance between them in the Z axis direction. Specifically, the main body portion 71 is located between the main body portion 81 and the mounting substrate 41. That is, the main body portion 81 is located in the Z2 direction relative to the main body portion 71. With the above configuration, the inductive component associated with the current path of the semiconductor device 100 can be reduced compared to a configuration in which the main body portion 71 and the main body portion 81 do not overlap each other in a plan view. Two spacers 58 are installed on the main body portion 81 of the low-potential busbar 80. For example, spacers 58 are installed at each position that sandwiches the connection portion 73 in a plan view in the direction of the X axis. The spacers 58 are rectangular tubular structures that surround the main body portion 71. By interposing a part of the spacers 58 between the main body portion 71 and the main body portion 81, a gap equal to the thickness of the spacers 58 is secured between the main body portion 71 and the main body portion 81. An insulating sheet (not shown) may also be interposed between the main body portion 71 and the main body portion 81. The insulating sheet is a layered or plate-shaped member having electrical insulating properties. For example, insulating paper or insulating resin film is suitable as an insulating sheet. By interposing an insulating sheet between the main body portion 71 and the main body portion 81, electrical insulation between the main body portion 71 and the main body portion 81 is ensured.

[0050] Each connection portion 82 of the low-potential busbar 80 is a portion for electrically connecting the mounting substrate 41 (conductor pattern 44) and the main body 81. Each connection portion 82 branches off from the main body 81 in the Y2 direction. Specifically, each connection portion 82[k] branches off from the part of the main body 81 corresponding to the mounting area 45L[k] in a plan view in the Y2 direction and is electrically connected to the conductor pattern 44L[k]_b within the said mounting area 45L[k]. As can be understood from the above explanation, each connection portion 72 of the high-potential busbar 70 protrudes from the main body 71 in the Y1 direction, and each connection portion 82 of the low-potential busbar 80 protrudes from the main body 81 in the Y2 direction. That is, each connection portion 72 and each connection portion 82 protrude in opposite directions relative to the main body 71 or the main body 81 in a plan view.

[0051] As illustrated in Figure 7, the connection portion 82, like the connection portion 72 described above, is composed of an extension portion 55 and a terminal portion 56. The extension portion 55 is a part that branches laterally from the side surface of the main body portion 81 and extends in a direction parallel to the XY plane. The terminal portion 56 is a part that protrudes in the Z1 direction toward the mounting substrate 41 from the tip of the extension portion 55. The tip of the terminal portion 56 is joined to the conductor pattern 44 using a bonding material such as solder. As can be understood from the above explanation, the connection portion 82[k] protrudes toward the mounting substrate 41 relative to the main body portion 81 and is electrically connected to the drive substrate[k]. The main body portion 81 is an example of a "second main body portion", and the connection portion 82[k] is an example of a "second connection portion".

[0052] The connection portion 83 in Figure 6 is a part for electrically connecting the wiring board 60 and the main body 81. The connection portion 83 branches off from the main body 81. Specifically, the connection portion 83 is a part of the main body 81 that branches off in the Y2 direction from near the center in the X-axis direction.

[0053] As illustrated in Figure 8, the connecting portion 83 is composed of an extended portion 831 and a projection portion 832. The extended portion 831 is a part that branches off from the main body portion 81 and extends in a direction parallel to the XY plane. Specifically, the extended portion 831 is an L-shaped portion that includes a portion 831a extending from the main body portion 81 in the Y2 direction and a portion 831b extending from the tip of portion 831a in the X2 direction. The projection portion 832 is a part that protrudes from the tip of the extended portion 831 toward the wiring board 60 in the Z2 direction. Specifically, the projection portion 832 is a portion that is bent relative to the extended portion 831. That is, the projection portion 832 is formed by bending a portion that branches laterally from the main body portion 81 in the Z2 direction, for example by press working. Therefore, similar to the projection portion 732, the cross-sectional shape of the projection portion 832 is rectangular. With the above configuration, for example, the projection 832 can be easily formed compared to a configuration in which a projection 832 separate from the extension 831 is joined to the extension 831. As can be understood from the above description, the low-potential busbar 80 includes a projection 832 that protrudes toward the wiring board 60 relative to the main body 81. The extension 831 is an example of a "second extension," and the projection 832 is an example of a "second projection."

[0054] As can be seen from Figure 8, projections 732 and 832 are arranged in parallel with a predetermined distance between them in the Y-axis direction. Specifically, projection 832 is located at a distance from projection 732 in the Y2 direction. The central axes of projection 732 and projection 832 are parallel to each other. Note that "parallel" means that the central axes of projection 732 and projection 832 are not only strictly parallel, but also substantially parallel. Therefore, if the central axes of projection 732 and projection 832 intersect within a manufacturing tolerance (±10%), for example, it can be interpreted that the central axes are substantially parallel. Also, the cross-sections of projection 732 and projection 832 are the same shape. Similarly, the identity of the cross-sectional shapes includes not only cases where the cross-sectional shapes of both are perfectly identical, but also cases where the cross-sectional shapes are substantially identical. Therefore, differences in shape within the manufacturing tolerance can be interpreted as substantially the same shape.

[0055] As can be seen from Figure 3, the main body 71 and the main body 81 are located between the mounting board 41 and the wiring board 60. The terminal portion 56 of the connection portion 72 protrudes from the main body 71 toward the mounting board 41 in the Z1 direction, and the projection 732 of the connection portion 73 protrudes from the main body 71 toward the wiring board 60 in the Z2 direction. In other words, the terminal portion 56 and the projection 732 protrude in opposite directions relative to the main body 71. Similarly, the terminal portion 56 of the connection portion 82 protrudes from the main body 81 toward the mounting board 41 in the Z1 direction, and the projection 832 of the connection portion 83 protrudes from the main body 81 toward the wiring board 60 in the Z2 direction. In other words, the terminal portion 56 and the projection 832 protrude in opposite directions relative to the main body 81.

[0056] As illustrated in Figures 2 to 4, the three output terminals O[1] to O[3] are installed on the side wall 32 of the housing 30. Specifically, output terminal O[1] is installed in the X1 direction relative to output terminal O[2], and output terminal O[3] is installed in the X2 direction relative to output terminal O[2]. As illustrated in Figures 5 and 6, each output busbar 54[k] electrically connects output terminal O[k] to the drive circuit 11[k]. Specifically, the output busbar 54[k] extends from output terminal O[k] in the Y1 direction so as to span the mounting area 45H[k] and mounting area 45L[k] in a plan view.

[0057] Specifically, the output busbar 54[k] comprises a main body 541[k], a connecting portion 542[k], and a connecting portion 543[k], as illustrated in Figure 6. The main body 541[k] is the portion that extends linearly in the Y1 direction from the output terminal O[k]. Specifically, the main body 541[k] extends in the Y1 direction, starting from the output terminal O[k] and traversing the reference plane R. That is, the tip of the main body 541[k] protrudes from the reference plane R in the Y1 direction. The main body 71 and the main body 81 are installed at positions spaced apart in the Y1 direction from the reference plane R so as not to overlap with the output busbar 54[k] in a plan view.

[0058] The connection portion 542[k] branches off in the X-axis direction from the end of the main body portion 541[k] corresponding to the mounting area 45H[k], and is electrically connected to the conductor pattern 44H[k]_b within the said mounting area 45H[k]. Similarly, the connection portion 543[k] branches off in the X-axis direction from the part of the main body portion 541[k] corresponding to the mounting area 45L[k], and is electrically connected to the conductor pattern 44L[k]_a within the said mounting area 45L[k]. The specific structure of the connection portions 542[k] and 543[k] and their connection to the conductor pattern 44 are the same as those of the connection portion 72 or 82 illustrated in Figure 7.

[0059] As can be understood from the above explanation, the drive circuit 11[k] is formed by electrically connecting the elements in the mounting area 45H[k] and the elements in the mounting area 45L[k] by the output busbar 54[k]. The high-potential busbar 70 and the low-potential busbar 80 are electrically connected to each drive circuit 11[k] as described above with reference to Figure 1. As can be understood from the above explanation, the main body 71 of the high-potential busbar 70 constitutes a path that electrically connects each connection terminal P(P1, P2) to each drive circuit 11[k]. Similarly, the main body 81 of the low-potential busbar 80 constitutes a path that electrically connects each connection terminal N(N1, N2) to each drive circuit 11[k].

[0060] The wiring board 60 in Figure 2 is a rigid printed circuit board with multiple wiring patterns formed on its surface. The wiring board 60 is a plate-like member including a first surface F1 and a second surface F2, as illustrated in Figure 3. The first surface F1 and the second surface F2 are opposite surfaces to each other. The wiring board 60 is fixed to the housing 30 with the first surface F1 facing each drive circuit 11[k] (or mounting board 41). That is, the first surface F1 faces in the Z1 direction, and the second surface F2 faces in the Z2 direction. The first surface F1 and the second surface F2 are planes parallel to the XY plane. Therefore, the X-axis direction (X1, X2) and the Y-axis direction (Y1, Y2) can also be described as the direction parallel to the first surface F1 or the second surface F2. The Z-axis direction is the direction of the thickness of the wiring board 60. The reference plane R may also be described as a plane that bisects the wiring board 60 in the direction of the Y axis.

[0061] As illustrated in Figure 3, the wiring board 60 is fixed to the housing 30 with its first surface F1 in contact with the upper surface of each of the multiple support members 37 (37H[1]~37H[3], 37L[1]~37L[3]). As illustrated in Figure 2, the wiring board 60 has multiple through holes Ha and multiple through holes Hb. The multiple through holes Ha are arranged linearly along the outer edge of the wiring board 60. The multiple through holes Hb are formed in positions that overlap each support member 37 in a plan view.

[0062] As illustrated in Figure 3, when the wiring board 60 is housed in the housing 30, the upper end portion 382 of each control terminal 38 protrudes from the second surface F2 in the Z2 direction by being inserted through the through hole Ha. The upper end portion 382 of each control terminal 38 is electrically connected to the wiring pattern on the second surface F2 by a bonding material such as solder. Also, when the wiring board 60 is housed in the housing 30, the lower end portion 391 of each external terminal 39 protrudes from the second surface F2 in the Z2 direction by being inserted through the through hole Hb. The lower end portion 391 of each external terminal 39 is electrically connected to the wiring pattern on the second surface F2 by a bonding material such as solder.

[0063] As illustrated in Figure 2, the wiring board 60 is composed of a first section 61, a second section 62, a connecting section 63, a connecting section 64, and a connecting section 65. Each of the first section 61 and the second section 62 is an elongated section in the direction of the X axis. The first section 61 and the second section 62 are spaced apart from each other in the direction of the Y axis. Each connecting section (63, 64, 65) connects the first section 61 and the second section 62. Connecting section 63 connects the ends of each of the first section 61 and the second section 62 in the X1 direction. Connecting section 64 connects the ends of each of the first section 61 and the second section 62 in the X2 direction. Connecting section 65 connects the central parts of each of the first section 61 and the second section 62 in the direction of the X axis. Connecting section 65 is located approximately in the center of the wiring board 60 in a plan view. Specifically, the connecting portion 65 intersects the reference plane R at the center of the wiring board 60 in the direction of the X axis. For example, the connecting portion 65 is the part that contains the centroid of the outer shape of the wiring board 60 (i.e., the figure defined by the outer edge).

[0064] As can be understood from the above explanation, openings 66 and 67 are formed in the wiring board 60. Openings 66 and 67 are through holes formed between the first portion 61 and the second portion 62. Specifically, opening 66 is the space surrounded by the first portion 61, the connecting portion 63, the second portion 62, and the connecting portion 65 in a plan view. Opening 67 is the space surrounded by the first portion 61, the connecting portion 65, the second portion 62, and the connecting portion 64 in a plan view. Therefore, the connecting portion 65 is located between opening 66 and opening 67 in a plan view. In other words, a long space along the X-axis formed in the wiring board 60 is divided into opening 66 and opening 67 by the connecting portion 65. Opening 66 is an example of a "first opening," and opening 67 is an example of a "second opening."

[0065] A sealing member (not shown) is supplied to the space inside the housing portion 30 through an opening 66 or an opening 67. The sealing member is an insulating mold for sealing the drive circuit 11[k]. For example, a resin material such as epoxy resin is used as the sealing member. As can be understood from the above description, the openings 66 and 67 are used as supply ports for the sealing member. In addition, the formation of a connecting portion 65 between the openings 66 and 67 has the advantage of making it easier to maintain the mechanical strength of the wiring board 60 compared to a configuration in which the connecting portion 65 is omitted.

[0066] As illustrated in Figure 2, the control circuit 13 and capacitive element 15 illustrated in Figure 1 are mounted on the wiring board 60. Specifically, the control circuit 13 and capacitive element 15 are mounted on the second surface F2 of the wiring board 60. As mentioned above, the control circuit 13 consists of six control chips 14 (14H[1]~14H[3], 14L[1]~14L[3]) corresponding to different switching elements S. The six control chips 14 of the control circuit 13 are mounted on the second surface F2. Three control chips 14H[1]~14H[3] corresponding to the high-potential switching element SH[k] are mounted on the first part 61 of the wiring board 60. Specifically, the three control chips 14H[1]~14H[3] are arranged on the second surface F2 of the first part 61 with spacing between them in the X-axis direction. Specifically, the three control chips 14H[1] to 14H[3] are arranged along the outer edge of the wiring board 60 that extends in the direction of the X axis in the Y1 direction. In addition, the three control chips 14L[1] to 14L[3] corresponding to the low-potential switching element SL[k] are mounted on the second part 62 of the wiring board 60. Specifically, the three control chips 14L[1] to 14L[3] are arranged on the second surface F2 of the second part 62 with spacing between them in the direction of the X axis. That is, the three control chips 14L[1] to 14L[3] are arranged along the outer edge of the wiring board 60 that extends in the direction of the X axis in the Y2 direction.

[0067] The capacitive element 15 is a passive element mounted on the wiring board 60. Specifically, the capacitive element 15 is a chip capacitor including a first electrode 151 and a second electrode 152. As illustrated in Figures 2 and 3, the capacitive element 15 is mounted on the connecting portion 65 of the wiring board 60. Therefore, the capacitive element 15 is located in the center of the wiring board 60. Specifically, it intersects the reference plane R at the center of the wiring board 60 in the direction of the X axis.

[0068] As described above, in the first embodiment, the capacitive element 15 is mounted on the connecting portion 65 that connects the first portion 61 and the second portion 62 of the wiring board 60. In other words, the portion of the wiring board 60 that connects the first portion 61 and the second portion 62 can be effectively used for the placement of the capacitive element 15.

[0069] As described above, the three control chips 14H[1] to 14H[3] of the control circuit 13 are mounted on the first part 61, and the three control chips 14L[1] to 14L[3] of the control circuit 13 are mounted on the second part 62. In other words, the multiple control chips 14 are arranged in the region surrounding the capacitive element 15. That is, the multiple control chips 14 are arranged so as to surround the capacitive element 15 in a plan view. Specifically, the capacitive element 15 is placed between the array of the three control chips 14H[1] to 14H[3] and the array of the three control chips 14L[1] to 14L[3].

[0070] As described above, in the first embodiment, the main body 71 of the high-potential busbar 70 and the main body 81 of the low-potential busbar 80 are installed at positions spaced apart from the reference plane R in the Y1 direction. On the other hand, the capacitive element 15 is located on the reference plane R. Therefore, as can be seen from Figure 2, the capacitive element 15 does not overlap with the main body 71 and the main body 81 in a plan view. Similarly, in the first embodiment, each control chip 14 does not overlap with the main body 71 and the main body 81 in a plan view.

[0071] The heat generated by the operation of each drive circuit 11[k] can be propagated to the high-potential busbar 70 or the low-potential busbar 80. In a configuration where the capacitive element 15 overlaps the main body 71 or the main body 81 in a plan view, the capacitive element 15 may be heated by the heat of the high-potential busbar 70 or the low-potential busbar 80. In the first embodiment, since the capacitive element 15 does not overlap the main body 71 and the main body 81 in a plan view, the heat of the high-potential busbar 70 or the low-potential busbar 80 is less likely to reach the capacitive element 15. Therefore, changes in the electrical characteristics of the capacitive element 15 due to heating are suppressed. Consequently, malfunctions of the semiconductor device 100 due to changes in the electrical characteristics of the capacitive element 15 are suppressed. Also, in the first embodiment, each control chip 14 does not overlap the main body 71 and the main body 81 in a plan view. Therefore, similarly, malfunctions due to heating are suppressed for each control chip 14. Furthermore, if heat transfer to the capacitive elements 15 or each control chip 14 does not pose a particular problem, a configuration in which the capacitive elements 15 or each control chip 14 overlap the main body 71 or the main body 81 in a plan view is also conceivable.

[0072] Incidentally, a configuration in which the capacitive element 15 is mounted on the mounting substrate 41 (hereinafter referred to as "proportional arrangement") is also conceivable. However, in the proportional arrangement, in addition to the multiple mounting areas 45 corresponding to different switching elements S, it is necessary to secure an area for mounting the capacitive element 15. Therefore, the mounting substrate 41 needs to be made larger, which consequently limits the miniaturization of the semiconductor device 100. In contrast to the proportional arrangement described above, according to the first embodiment, since the capacitive element 15 is mounted on the wiring substrate 60, it is not necessary to make the mounting substrate 41 larger. Therefore, there is an advantage in that the semiconductor device 100 can be made smaller compared to the proportional arrangement.

[0073] Furthermore, soldering is used to mount each switching element S to the mounting substrate 41. From the viewpoint of ensuring the reliability of the mechanical and electrical connections between the mounting substrate 41 and each switching element S, it is necessary to use high-melting-point solder. In the proportional case, if we assume that the capacitive element 15 is soldered to the mounting substrate 41 in the same process as the switching element S, then, due to the circumstances exemplified above, high-melting-point solder is also used for joining the capacitive element 15. That is, the capacitive element 15 may be heated to a high temperature during the soldering process. Therefore, there is a possibility that the capacitive element 15 may be damaged by heating, or that the electrical characteristics of the capacitive element 15 may change from the target characteristics due to heating. In contrast to the proportional case, in the first embodiment, the capacitive element 15 is mounted on the wiring board 60. In soldering for mounting various electrical components, including the capacitive element 15, to the wiring board 60, low-melting-point solder is used. Therefore, even when high-melting-point solder is used to mount the switching element S onto the mounting substrate 41, low-melting-point solder can be used to mount the capacitive element 15 onto the wiring substrate 60. In other words, it is possible to suppress the capacitive element 15 from being heated to excessively high temperatures. Accordingly, according to the first embodiment, it is possible to reduce the possibility of the capacitive element 15 being damaged or the electrical characteristics of the capacitive element 15 changing due to heating during the manufacturing process of the semiconductor device 100.

[0074] Figure 9 is an enlarged plan view of the vicinity of the capacitive element 15. Figure 10 is a cross-sectional view of line XX in Figure 9. As illustrated in Figures 9 and 10, wiring patterns 681 and 682 are formed on the second surface F2 of the wiring board 60. The first electrode 151 of the capacitive element 15 is electrically connected to the wiring pattern 681 by a bonding material such as solder. The second electrode 152 is electrically connected to the wiring pattern 682 by a similar bonding material.

[0075] Through holes H1 and H2 are formed in the wiring board 60. Each of the through holes H1 and H2 is a circular opening that penetrates the wiring board 60. Through holes H1 and H2 are formed in the connecting portion 65 of the wiring board 60. In a plan view, through hole H1 overlaps with the wiring pattern 681, and through hole H2 overlaps with the wiring pattern 682 in a plan view. The diameter of each of the through holes H1 and H2 is greater than or equal to the maximum diagonal length in the respective cross-sections of the aforementioned projections 732 and 832.

[0076] As can be seen from Figures 9 and 10, with the wiring board 60 fixed to the housing 30, the projection 732 of the high-potential busbar 70 is inserted through the through hole H1. Similarly, the projection 832 of the low-potential busbar 80 is inserted through the through hole H2. The respective tips of projections 732 and 832 protrude in the Z2 direction from the second surface F2 of the wiring board 60. The respective tips of projections 732 and 832 are joined to the wiring board 60 by a bonding material 69, such as solder. Specifically, the tip of projection 732 is electrically connected to the wiring pattern 681 while joined to the second surface F2 of the wiring board 60. Similarly, the tip of projection 832 is electrically connected to the wiring pattern 682 while joined to the second surface F2 of the wiring board 60.

[0077] As can be understood from the above explanation, the capacitive element 15 is electrically connected to the protrusions 732 and 832. Specifically, the first electrode 151 of the capacitive element 15 is electrically connected to the protrusion 732 via the wiring pattern 681. In addition, the second electrode 152 of the capacitive element 15 is electrically connected to the protrusion 832 via the wiring pattern 682.

[0078] [Manufacturing method for semiconductor device 100] Figure 11 is a process diagram illustrating the manufacturing process of a semiconductor device 100. First, in process Q1, the housing portion 30 is prepared. Each connection terminal P, each connection terminal N, each output terminal O[k], each control terminal 38, each external terminal 39, and the connecting conductor 50 are integrally formed with the housing portion 30, for example, by insert molding.

[0079] In step Q2, following step Q1, the base portion 21 and the semiconductor unit 40 are fixed to the housing portion 30. For example, the base portion 21, with the semiconductor unit 40 bonded to its upper surface, is bonded to the housing portion 30. In step Q3, following step Q2, multiple wires are formed. For example, wires are formed to electrically connect each control terminal 38 to the control electrode G of the switching element S.

[0080] In step Q4, following the execution of step Q3, the wiring board 60 is placed in the space inside the housing 30. Specifically, the wiring board 60 is lowered in the Z1 direction until its first surface F1 contacts the upper surface of each support 37 of the housing 30. During the process of lowering the wiring board 60, the projection 732 is inserted into the through hole H1, the projection 832 is inserted into the through hole H2, the upper end 382 of each control terminal 38 is inserted into the through hole Ha, and the lower end 391 of each external terminal 39 is inserted into the through hole Hb.

[0081] In step Q5, following the execution of step Q4, the protrusions 732 and 832, the control terminals 38 and external terminals 39 are soldered to the second surface F2 of the wiring board 60. Step Q5 fixes the wiring board 60 to the housing 30. In step Q6, following the execution of step Q5, a sealing member is supplied to the space inside the housing 30 through the openings 66 and 67 of the wiring board 60. In step Q7, after the sealing member has hardened, the lid 22 is fixed to the housing 30, thereby manufacturing the semiconductor device 100.

[0082] As described above, in the first embodiment, the projection 732 constituting the high-potential busbar 70 and the projection 832 constituting the low-potential busbar 80 are electrically connected to the capacitive element 15 on the wiring board 60. Therefore, separate elements for electrically connecting each of the connection terminals P and N to the capacitive element 15 are unnecessary. Consequently, the number of parts is reduced compared to a configuration in which, for example, the connection terminals P and N are electrically connected to the capacitive element 15 by dedicated wiring, and as a result, the manufacturing of the semiconductor device 100 is simplified. For example, as described above with reference to Figure 11, in the process of placing the wiring board 60 in the housing 30 (step Q4), the projection 732 is inserted into the through hole H1 and the projection 832 is inserted into the through hole H2. Therefore, separate steps for installing elements for connecting each of the connection terminals P and N to the capacitive element 15 are unnecessary, and the projections 732 and 832 can be easily fixed to the wiring board 60.

[0083] Furthermore, in the first embodiment, the main body 71 of the high-potential busbar 70 and the main body 81 of the low-potential busbar 80 are located between the mounting substrate 41 and the wiring substrate 60. That is, the mounting substrate 41 and the main body 71 and the main body 81 and the wiring substrate 60 are stacked in the Z-axis direction. Therefore, the planar size of the semiconductor device 100 can be reduced compared to a configuration in which the main body 71 and the main body 81 do not overlap with the mounting substrate 41 or the wiring substrate 60 in a plan view.

[0084] Furthermore, in the first embodiment, a plurality of control chips 14 are arranged around the capacitive element 15 along the periphery of the wiring board 60. With this configuration, it is possible to bring the distance (electrical path length) between each control chip 14 and the capacitive element 15 closer to each other (ideally matching) for a plurality of control chips 14. Therefore, compared to a configuration in which the capacitive element 15 is unevenly distributed near the periphery of the wiring board 60, the effects utilizing the capacitive element 15 (for example, the modification of the noise frequency characteristics mentioned above) can be effectively realized.

[0085] B: Second Embodiment Figure 12 is a circuit diagram illustrating the electrical configuration of the semiconductor device 100 in the second embodiment. As illustrated in Figure 12, the second embodiment is a configuration in which the capacitive element 15 in the first embodiment is replaced with a resistor train L. The other configurations of the semiconductor device 100 are the same as in the first embodiment.

[0086] A resistor train L (ladder resistor) is a passive element consisting of five resistor elements 16 (16[1] to 16[5]) connected in series. The resistor train L has a first end e1 and a second end e2. The first end e1 and the second end e2 are opposite ends to each other. Specifically, the first end e1 is the terminal of resistor element 16[1] that is opposite to resistor element 16[2]. The second end e2 is the terminal of resistor element 16[5] that is opposite to resistor element 16[4]. The first end e1 is electrically connected to a high-potential busbar 70. The second end e2 is electrically connected to a low-potential busbar 80.

[0087] A detection line 17 is electrically connected between two adjacent resistors 16[4] and 16[5] in the resistor train L. Therefore, a voltage V obtained by dividing the voltage between connection terminal P and connection terminal N by the resistor train L (hereinafter referred to as the "detection voltage") is output to the detection line 17. Resistor 16[4] is an example of a "first resistor," and resistor 16[5] is an example of a "second resistor." The number of resistors 16 constituting the resistor train L can be changed arbitrarily. The position of the detection line 17 relative to the resistor train L is also arbitrary.

[0088] As illustrated in Figure 12, a detection circuit 18 is electrically connected to the detection line 17. The detection circuit 18 is a circuit for detecting abnormalities in the detection voltage V supplied via the detection line 17. The detection circuit 18 may be mounted on any of the multiple control chips 14, or it may be mounted separately on the wiring board 60 from the multiple control chips 14. Alternatively, the detection circuit 18 may be configured separately from the semiconductor device 100 and attached externally to the semiconductor device 100.

[0089] Figure 13 is a block diagram illustrating the configuration of the detection circuit 18. As illustrated in Figure 13, the detection circuit 18 comprises a reference voltage source 181 and a comparison circuit 182. The reference voltage source 181 is a power supply that generates a predetermined voltage (hereinafter referred to as "reference voltage") Vref, which serves as a reference for the detection voltage V. The reference voltage Vref is set to the upper limit of the range in which fluctuations are permitted for the detection voltage V. The comparison circuit 182 compares the detection voltage V with the reference voltage Vref. Specifically, the comparison circuit 182 outputs a warning signal α when the detection voltage V exceeds the reference voltage Vref. That is, when the detection voltage V rises to a voltage that exceeds the upper limit of the permissible range, the detection circuit 18 outputs a warning signal α. On the other hand, if the detection voltage V is equal to the reference voltage Vref, or if the detection voltage V is lower than the reference voltage Vref, the warning signal α is not output.

[0090] An external control device 200 is connected to the output terminal of the detection circuit 18. The control device 200 is externally connected to the semiconductor device 100 and controls the semiconductor device 100. The control device 200 detects an abnormality in the semiconductor device 100 when a warning signal α is supplied from the detection circuit 18, and can stop the operation of the semiconductor device 100 upon detection of the abnormality.

[0091] As described above, in the second embodiment, the detected voltage V obtained by dividing the voltage between connection terminal P and connection terminal N by a plurality of resistors 16[1] to 16[5] is detected by the detection line 17. Therefore, an abnormality in the voltage between connection terminal P and connection terminal N can be detected.

[0092] Figure 14 is a plan view illustrating the configuration of the semiconductor device 100 in the second embodiment. Figure 15 is an enlarged plan view of the resistor train L. Similar to the first embodiment, through holes H1 and H2 are formed in the connecting portion 65 of the wiring board 60. Through holes H1 and H2 are spaced apart in the direction of the Y axis. The projection 732 of the high-potential busbar 70 is inserted through through hole H1, and the projection 832 of the low-potential busbar 80 is inserted through through hole H2.

[0093] Each of the five resistive elements 16[1] to 16[5] constituting the resistor train L is a chip resistor mounted on the second surface F2 of the wiring board 60. Each resistive element 16 is mounted on the connecting portion 65 of the wiring board 60. Specifically, the five resistive elements 16[1] to 16[5] are arranged linearly in the direction of the X-axis within the region between the through holes H1 and H2. That is, the direction in which the through holes H1 and H2 are arranged (Y-axis) and the direction in which the multiple resistive elements 16 are arranged (X-axis) are mutually orthogonal. In the direction of the X-axis, the through holes H1 and H2 are located approximately in the center of the resistor train L (specifically, the midpoint between the first end e1 and the second end e2). Also, as can be seen from Figure 14, the five resistive elements 16[1] to 16[5] are arranged linearly between the opening 66 and the opening 67. Two adjacent resistive elements 16 are electrically connected by a wiring pattern 683 formed on the second surface F2.

[0094] A wiring pattern 684 and a wiring pattern 685 are formed on the second surface F2 of the wiring board 60. The through hole H1 overlaps with the wiring pattern 684 in a plan view, and the through hole H2 overlaps with the wiring pattern 685 in a plan view. The projection 732 inserted through the through hole H1 is electrically connected to the wiring pattern 684 by a bonding material such as solder. The projection 832 inserted through the through hole H2 is electrically connected to the wiring pattern 685 by a bonding material such as solder.

[0095] The wiring pattern 684 is an L-shaped conductor pattern including wiring portion 684a and wiring portion 684b. Wiring portion 684a is the portion that extends linearly in the X1 direction from the through hole H1. Wiring portion 684b is the portion of wiring portion 684a that extends in the Y2 direction from the X1 direction end to the first end e1. The first end e1 of the resistor train L is electrically connected to wiring portion 684b. That is, the first end e1 is electrically connected to the projection 732 of the high-potential busbar 70, as illustrated in Figure 12.

[0096] On the other hand, the wiring pattern 685 is an L-shaped conductor pattern including wiring portion 685a and wiring portion 685b. Wiring portion 685a is the portion that extends linearly in the X2 direction from the through hole H2. Wiring portion 685b is the portion of wiring portion 685a that extends in the Y1 direction from the X2 end to the second end e2. The second end e2 of the resistor train L is electrically connected to the wiring portion 685b. That is, the second end e2 is electrically connected to the projection 832 of the low-potential busbar 80, as illustrated in Figure 12. As can be understood from the above description, the resistor train L and wiring patterns (683-685) of the second embodiment are arranged point-symmetrically with respect to the midpoint or centroid of the wiring board 60.

[0097] The detection line 17 is composed of a wire electrically connected between the resistive elements 16[4] and 16[5]. Alternatively, a wiring pattern formed on the second surface F2 of the wiring board 60 may be used as the detection line 17.

[0098] The configuration of the semiconductor device 100, excluding the part related to the resistor array L, is the same as in the first embodiment. For example, the configuration described for the capacitive element 15 in the first embodiment is similarly applied to the resistor array L in the second embodiment. For example, the resistor array L is located in the center of the wiring board 60, and a plurality of control chips 14 are arranged around the resistor array L. Also, the resistor array L does not overlap the main body portion 71 and the main body portion 81 in a plan view.

[0099] As described above, in the second embodiment, the projection 732 constituting the high-potential busbar 70 and the projection 832 constituting the low-potential busbar 80 are electrically connected to the resistor train L on the wiring board 60. Therefore, separate elements for electrically connecting each of the connection terminals P and N to the resistor train L are unnecessary. Accordingly, compared to a configuration in which, for example, the connection terminals P and N are electrically connected to the resistor train L by dedicated wiring, as in the first embodiment, the manufacturing of the semiconductor device 100 is simplified. As described above, the second embodiment achieves the same effects as the first embodiment.

[0100] C: Variant Specific modifications added to each of the embodiments exemplified above are exemplified below. Two or more embodiments arbitrarily selected from the following examples may be merged as appropriate, provided they do not contradict each other. In the following description, the capacitive element 15 exemplified in the first embodiment and the resistor train L exemplified in the second embodiment will be collectively referred to as "passive elements".

[0101] (1) The structure of the connection portion 73 in the high-potential busbar 70 and the structure of the connection portion 83 in the low-potential busbar 80 are not limited to the examples in each of the embodiments described above. For example, in each of the embodiments described above, as illustrated in Figure 8, the connection portion 73 of the high-potential busbar 70 is illustrated in a form that includes a linear extension portion 731, but as illustrated in Figure 16, an L-shaped extension portion 731 composed of portion 731a and portion 731b may be formed on the high-potential busbar 70. Portion 731a extends from the main body portion 71 of the high-potential busbar 70 in the Y2 direction. Portion 731b extends from the tip of portion 731a in the X2 direction. Also, in each of the embodiments described above, as illustrated in Figure 8, the connection portion 83 of the low-potential busbar 80 is illustrated in a form that includes an L-shaped extension portion 831, but as illustrated in Figure 16, the extension portion 831 may be a portion that extends linearly from the main body portion 81 in the Y2 direction.

[0102] (2) In the above-described embodiments, examples were given in which the projections 732 and 832 are arranged in the direction of the Y axis, but the positional relationship between the projections 732 and 832 is not limited to the above examples. For example, as illustrated in Figure 17, an embodiment in which the projections 732 and 832 are spaced apart in the direction of the X axis is also conceivable. The connecting portion 73 in Figure 17 is the same as in the first embodiment. On the other hand, the connecting portion 83 is formed in the same shape as the connecting portion 73. That is, the extended portion 831 of the connecting portion 83 illustrated in Figure 17 extends linearly from the main body portion 81 in the Y2 direction. Therefore, the projections 732 and 832 are spaced apart in the direction of the X axis. In the configuration of Figure 17, the through holes H1 and H2 of the wiring board 60 are also arranged in the direction of the X axis.

[0103] (3) In the above-described embodiments, the connection portion 73 of the high-potential busbar 70 is shown to consist of an extended portion 731 and a projection portion 732, but the extended portion 731 may be omitted. For example, as illustrated in Figure 18, an embodiment in which the projection portion 732 is directly connected to the main body portion 71 of the high-potential busbar 70 can be assumed. Similarly, for the low-potential busbar 80, the extended portion 831 may be omitted from the connection portion 83. For example, as illustrated in Figure 18, an embodiment in which the projection portion 832 is directly connected to the main body portion 81 of the low-potential busbar 80 can be assumed. Note that in the configuration of Figure 18, it is necessary that the projection portion 732 of the high-potential busbar 70 does not come into contact with the low-potential busbar 80. For example, by forming a notch in the periphery of the main body portion 81 of the low-potential busbar 80 near the projection portion 732 of the high-potential busbar 70, contact of the projection portion 832 with the main body portion 81 can be avoided. In each of the above-described configurations, the main body 71 and the projection 732 are connected via the extension 731. Compared to the configuration in Figure 18, where the projection 732 is directly connected to the main body 71, it is easier to ensure greater freedom in the planar position of the projection 732. For example, the projection 732 can be installed at any position spaced apart from the main body 71. The same applies to the low-potential busbar 80.

[0104] (4) In the above-described embodiments, the passive elements are shown mounted on the second surface F2 of the wiring board 60, which is opposite to the mounting board 41. However, the passive elements may also be mounted on the first surface F1 of the wiring board 60, which faces the mounting board 41. However, in the configuration where the passive elements are mounted on the first surface F1, it is necessary to ensure sufficient space between the mounting board 41 and the wiring board 60, or between the connecting conductor 50 and the wiring board 60, for the placement of the passive elements. In the above-described embodiments, the passive elements are mounted on the second surface F2 of the wiring board 60, which is opposite to the drive circuit 11[k] (mounting board 41). Therefore, compared to the embodiment in which the passive elements are mounted on the first surface F1, the space that needs to be secured between the mounting board 41 and the wiring board 60, or between the connecting conductor 50 and the wiring board 60 can be reduced, and consequently, the semiconductor device 100 can be made thinner.

[0105] Furthermore, although the above-described embodiments illustrate a configuration in which the control circuit 13 is mounted on the second surface F2, the control circuit 13 may also be mounted on the first surface F1 of the wiring board 60. In each of the above-described embodiments, both the passive element and the control circuit 13 are mounted on the second surface F2. Therefore, the above-described embodiments have a particularly significant effect in that they reduce the spacing that needs to be maintained between the mounting board 41 and the wiring board 60, or between the connecting conductor 50 and the wiring board 60, compared to a configuration in which the passive element and the control circuit 13 are implemented on the first surface F1.

[0106] (5) In the embodiments described above, an example was given in which the projection 732 of the high-potential busbar 70 is inserted through the through-hole H1 and the projection 832 of the low-potential busbar 80 is inserted through the through-hole H2. However, the configuration in which the projection 732 is inserted through the through-hole H1 or the configuration in which the projection 832 is inserted through the through-hole H2 is not essential in this disclosure. For example, an embodiment is also conceivable in which the projection 732 of the high-potential busbar 70 is joined to the first surface F1 of the wiring board 60, thereby electrically connecting the projection 732 to the wiring pattern on the first surface F1. Similarly, an embodiment is also conceivable in which the projection 832 of the low-potential busbar 80 is joined to the first surface F1 of the wiring board 60, thereby electrically connecting the projection 832 to the wiring pattern on the first surface F1.

[0107] (6) In the first embodiment, a capacitive element 15 was exemplified, and in the second embodiment, a resistor train L was exemplified, but both the capacitive element 15 and the resistor train L may be mounted on the wiring board 60. Multiple capacitive elements 15 may be connected in parallel between the protrusions 732 and 832. Furthermore, the passive elements mounted on the wiring board 60 are not limited to the capacitive element 15 and the resistor train L. Examples of passive elements mounted on the wiring board 60 include inductive elements (coils) or individual resistors.

[0108] (7) In the above-described embodiments, the control circuit 13 is shown as being composed of multiple control chips 14 corresponding to different switching elements S, but the control circuit 13 may be composed of a single IC chip. Two or more of the multiple control chips 14 (14H[1]~14H[3], 14L[1]~14L[3]) in the above-described embodiments may be composed of single IC chips. In other words, the number of control chips 14 and the number of switching elements S may differ.

[0109] (8) In the embodiments described above, embodiments using IGBTs as switching elements S have been given as examples, but the configuration of the switching element S is not limited to the above examples. For example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) may be used as the switching element S. In the embodiment where the switching element S is a MOSFET, the main electrode C is one of the source electrode and the drain electrode, and the main electrode E is the other of the source electrode and the drain electrode. In addition, an RC-IGBT (Reverse Conducting IGBT) including an IBGT and an FWD (Free Wheeling Diode) may be used as the switching element S. In the embodiment using an RC-IGBT, the diode elements D (DH[1]~DH[3], DL[1]~DL[3]) in the embodiments described above may be omitted.

[0110] D: Addendum From the various forms exemplified above, the following configurations can be identified, for example.

[0111] A semiconductor device according to one aspect of the present disclosure (Aspect 1) comprises a first connection terminal and a second connection terminal, a drive circuit including one or more power semiconductor elements, a control circuit for controlling the one or more power semiconductor elements, a wiring board, a passive element installed on the wiring board, a first bus bar and a second bus bar, wherein the first bus bar includes a first main body portion that constitutes a path for electrically connecting the first connection terminal and the drive circuit, and a first projection portion that protrudes toward the wiring board relative to the first main body portion, and the second bus bar includes a second main body portion that constitutes a path for electrically connecting the second connection terminal and the drive circuit, and a second projection portion that protrudes toward the wiring board relative to the second main body portion, and the passive element is electrically connected to the first projection portion and the second projection portion.

[0112] In the above embodiment, the first projection constituting the first busbar and the second projection constituting the second busbar are electrically connected to the passive element on the wiring board. Therefore, no separate elements are required to electrically connect the first and second connection terminals to the passive element. According to the above embodiment, the manufacturing of the semiconductor device is simplified compared to a configuration in which, for example, the first or second connection terminal is electrically connected to the passive element by a dedicated element (e.g., a linear connecting conductor).

[0113] A "busbar (first busbar / second busbar)" is a plate-shaped or rod-shaped conductor for conducting large currents. For example, a lead frame (lead) formed from a metal plate is also included in the concept of a "busbar" in this disclosure.

[0114] The forms in which element A and element B are "electrically connected" include not only forms in which element A and element B are directly connected, but also forms in which element A and element B are indirectly connected via a conductor.

[0115] With respect to the first projection, "projecting toward the wiring board relative to the first main body" means that the first projection protrudes in a direction toward the wiring board from a plane including the surface of the first main body. Whether the first projection and the first main body are directly connected or indirectly connected via other elements (for example, the first extension described later) is irrelevant in this disclosure. In the above explanation, we have focused on the first busbar, but the second busbar is interpreted similarly.

[0116] In a specific example of Embodiment 1 (Embodiment 2), the semiconductor device comprises a mounting substrate on which the drive circuit is installed, the first main body and the second main body are located between the mounting substrate and the wiring substrate, the first busbar includes a first connection portion that protrudes toward the mounting substrate relative to the first main body and is electrically connected to the drive circuit, the second busbar includes a second connection portion that protrudes toward the mounting substrate relative to the second main body and is electrically connected to the drive circuit, and each of the first projection and the second projection is electrically connected to the passive element while fixed to the wiring substrate. In the above embodiment, the first main body of the first busbar and the second main body of the second busbar are located between the mounting substrate and the wiring substrate. That is, the mounting substrate, the first / second main body and the wiring substrate are stacked. Therefore, the planar size of the semiconductor device can be reduced compared to a configuration in which the first main body and the second main body do not overlap with the mounting substrate or wiring substrate in a plan view.

[0117] In a specific example of Embodiment 1 or Embodiment 2 (Embodiment 3), at least a portion of the first main body and at least a portion of the second main body overlap each other in a plan view. In the above embodiments, since at least a portion of the first main body and at least a portion of the second main body overlap in a plan view, the inductive component associated with the current path of the semiconductor device is reduced compared to a configuration in which the first main body and the second main body do not overlap each other in a plan view. Note that "plan view" means observing the object from a direction perpendicular to the board surface (top or bottom surface) of the wiring board.

[0118] The first main body and the second main body overlap in a plan view, either entirely or partially. For example, a configuration is envisioned in which the first main body and the second main body overlap in a plan view at their respective central portions in the direction in which they extend.

[0119] In any specific example of Embodiments 1 to 3 (Embodiment 4), the wiring board has a first through hole and a second through hole, the first projection is inserted through the first through hole, and the second projection is inserted through the second through hole. In the above embodiment, the first projection is inserted through the first through hole, and the second projection is inserted through the second through hole. Therefore, the first projection and the second projection can be easily fixed to the wiring board.

[0120] In any specific example of Embodiments 1 to 4, the wiring board includes a first surface facing the drive circuit and a second surface opposite to the first surface, and the passive element is installed on the second surface. In the above embodiments, the passive element is installed on the second surface of the wiring board opposite to the drive circuit. Therefore, compared to the configuration in which the passive element is installed on the first surface, the distance that must be maintained between the drive circuit and the wiring board can be reduced.

[0121] In a specific example of Embodiment 5 (Embodiment 6), the control circuit is installed on the second surface. In the above embodiments, both the passive element and the control circuit are installed on the second surface of the wiring board, which is opposite to the drive circuit. Therefore, compared to the configuration in which the control circuit is installed on the first surface, the effect of reducing the distance between the drive circuit and the wiring board is significant.

[0122] In any specific example of Embodiments 1 to 6 (Embodiment 7), the control circuit includes a plurality of control chips installed on the wiring board, the passive element is located in the center of the wiring board, and the plurality of control chips are arranged along the periphery of the wiring board in the region surrounding the passive element. According to the above embodiment, since the plurality of control chips are arranged along the periphery of the wiring board in the region surrounding the passive element, it is possible to bring the distance (electrical path length) between each control chip and the passive element closer to each other for the plurality of control chips. Therefore, compared to an embodiment in which the passive element is concentrated near the periphery of the wiring board, it is possible to effectively realize the function of utilizing the passive element (noise reduction or detection of voltage anomalies).

[0123] In any specific example of Embodiments 1 to 7 (Embodiment 8), the passive element does not overlap the first main body and the second main body in a plan view. Heat generated in the power semiconductor element by the operation of the semiconductor device can be propagated to the first busbar or the second busbar. In a configuration in which the passive element overlaps the first main body or the second main body in a plan view, there is a possibility that heat from the first busbar or the second busbar will reach the passive element. On the other hand, according to the above embodiment in which the passive element does not overlap the first main body and the second main body in a plan view, heat from the first busbar or the second busbar is less likely to be propagated to the passive element. Therefore, changes in the electrical characteristics of the passive element due to heating are suppressed, and consequently, malfunctions of the semiconductor device due to changes in the electrical characteristics of the passive element are suppressed.

[0124] In any specific example of Embodiments 1 to 8 (Embodiment 9), the first busbar includes a first extension portion extending from the first main body in a direction along the surface of the wiring board, and the first projection protrudes toward the wiring board from the tip of the first extension portion. The second busbar includes a second extension portion extending from the second main body in a direction along the surface of the wiring board, and the second projection protrudes toward the wiring board from the tip of the second extension portion. In the above embodiments, since the first main body and the first projection are connected via the first extension portion, a high degree of freedom in the planar position of the first projection can be maintained. For example, the first projection can be installed at a position spaced apart from the first main body. The same applies to the second busbar.

[0125] In any specific example of Embodiments 1 to 9 (Embodiment 10), the first projection is a portion bent relative to the first extension, and the second projection is a portion bent relative to the second extension. In the above embodiments, the first projection is formed by bending a portion continuous with the first extension. Therefore, compared to a configuration in which, for example, a separate first projection is connected to the first extension, the first projection can be formed more easily. The same applies to the second projection.

[0126] In any specific example of Embodiments 1 to 10 (Embodiment 11), the wiring board includes a first portion and a second portion that are spaced apart from each other, and a connecting portion that connects the first portion and the second portion, and the passive element is installed in the connecting portion. In the above embodiment, the passive element is installed in the connecting portion that connects the first portion and the second portion of the wiring board. That is, the portion that connects the first portion and the second portion can be effectively utilized for the arrangement of the passive element.

[0127] In a specific example of Embodiment 11 (Embodiment 12), a first opening and a second opening are formed between the first and second parts, and the connecting portion is located between the first and second openings. According to the above embodiment, a resin material for sealing the drive circuit can be injected through the first or second opening. Furthermore, the formation of a connecting portion between the first and second openings makes it easier to maintain the mechanical strength of the wiring board.

[0128] In any specific example of Embodiments 1 to 12 (Embodiment 13), the passive element includes a capacitive element having a first electrode electrically connected to the first projection and a second electrode electrically connected to the second projection. According to the above embodiment, the frequency characteristics of noise caused by switching of the power semiconductor element can be changed (for example, noise can be reduced).

[0129] In any specific example of Embodiments 1 to 13 (Embodiment 14), the passive element includes a resistor array in which a plurality of resistive elements are connected in series, the first end of the resistor array is electrically connected to the first projection, the second end of the resistor array opposite to the first end is electrically connected to the second projection, and the passive element includes a detection line connected between a first resistive element and a second resistive element that are adjacent to each other among the plurality of resistive elements. According to the above embodiment, the voltage obtained by dividing the voltage between the first connection terminal and the second connection terminal by the plurality of resistive elements is detected by the detection line. Therefore, an abnormality in the voltage between the first connection terminal and the second connection terminal (and furthermore, the occurrence of a voltage abnormality) can be detected. [Explanation of symbols]

[0130] 100...Semiconductor device, 11...Drive circuit, 13...Control circuit, 14...Control chip, 15...Capacitive element, 151...First electrode, 152...Second electrode, 16...Resistor element, 17...Detection line, 18...Detection circuit, 181...Reference voltage source, 182...Comparison circuit, 21...Base part, 22...Lid part, 30...Housing part, 31~34...Side wall part, 35,36...Protruding part, 37...Support, 38...Control terminal, 39...External terminal, 40...Semiconductor unit, 41...Mounting board, 42...Insulating board, 43...Metal layer, 44...Conductor pattern, 45...Mounting area, 50...Connecting conductor, 54...Output side busbar, 55...Extending part, 56...Terminal part, 58...Spacer, 60...Wiring board, 61 ...Part 1, 62...Part 2, 63-65...Connecting part, 66,67...Opening, F1...First surface, F2...Second surface, H1,H2,Ha,Hb...Through hole, 70...High potential busbar, 71...Main body, 72...Connection part, 73...Connection part, 731...Extending part, 732...Protrusion, 80...Low potential busbar, 81...Main body, 82...Connection part, 83...Connection part, 831...Extending part, 832...Protrusion, 84,85...Connecting part, 85...Connecting part, 200...Control device, 681-685...Wiring pattern, P,N...Connection terminal, D...Diode element, S...Switching element, V...Detected voltage, Vref...Reference voltage, e1...First end, e2...Second end, α...Warning signal.

Claims

1. First connection terminal and second connection terminal, A drive circuit including one or more power semiconductor elements, A control circuit for controlling the one or more power semiconductor elements, Wiring board and A passive element installed on the aforementioned wiring board, First busbar and second busbar It is equipped with, The first busbar is, A first main body portion that constitutes a path for electrically connecting the first connection terminal and the drive circuit, It includes a first projection that protrudes toward the wiring board from the first main body and whose tip is joined to the wiring board, The aforementioned second busbar is, A second main body that constitutes a path for electrically connecting the second connection terminal and the drive circuit, It includes a second projection that protrudes toward the wiring board from the second main body and whose tip is joined to the wiring board, The passive element is electrically connected to the first projection and the second projection. Semiconductor equipment.

2. First connection terminal and second connection terminal, A drive circuit including one or more power semiconductor elements, A control circuit for controlling the one or more power semiconductor elements, A wiring board having a first through hole and a second through hole formed therein, A passive element installed on the aforementioned wiring board, First busbar and second busbar It is equipped with, The first busbar is, A first main body portion that constitutes a path for electrically connecting the first connection terminal and the drive circuit, The first main body portion includes a first projection that protrudes toward the wiring board and is inserted through the first through hole, The second busbar is, A second main body that constitutes a path for electrically connecting the second connection terminal and the drive circuit, The second main body portion includes a second projection that protrudes toward the wiring board and is inserted into the second through hole, The passive element is electrically connected to the first projection and the second projection. Semiconductor equipment.

3. First connection terminal and second connection terminal, A drive circuit including one or more power semiconductor elements, Wiring board and The circuit includes a plurality of control chips installed on the wiring board, and a control circuit for controlling the one or more power semiconductor elements, A passive element is installed in the center of the aforementioned wiring board, First busbar and second busbar It is equipped with, The plurality of control chips are arranged in the region surrounding the passive element, along the periphery of the wiring board. The first busbar is, A first main body portion that constitutes a path for electrically connecting the first connection terminal and the drive circuit, It includes a first projection that protrudes toward the wiring board relative to the first main body, The second busbar is, A second main body that constitutes a path for electrically connecting the second connection terminal and the drive circuit, It includes a second projection that protrudes toward the wiring board relative to the second main body, The passive element is electrically connected to the first projection and the second projection. Semiconductor equipment.

4. First connection terminal and second connection terminal, A drive circuit including one or more power semiconductor elements, A control circuit for controlling the one or more power semiconductor elements, Wiring board and A passive element installed on the aforementioned wiring board, First busbar and second busbar It is equipped with, The first busbar is, A first main body portion that constitutes a path for electrically connecting the first connection terminal and the drive circuit, A first extending portion extending from the first main body portion in a direction along the surface of the wiring board, It includes a first projection that protrudes from the tip of the first extension toward the wiring board, The second busbar is, A second main body that constitutes a path for electrically connecting the second connection terminal and the drive circuit, The second main body portion includes a second extending portion that extends in a direction along the surface of the wiring board, The second extension portion includes a second projection that protrudes toward the wiring board from the tip of the second extension portion, The passive element is electrically connected to the first projection and the second projection. Semiconductor equipment.

5. The first projection is a portion bent relative to the first extension, The second projection is a portion bent relative to the second extension. The semiconductor device according to claim 4.

6. First connection terminal and second connection terminal, A drive circuit including one or more power semiconductor elements, A control circuit for controlling the one or more power semiconductor elements, A wiring board including a first part and a second part that are spaced apart from each other, and a connecting part that connects the first part and the second part, A passive element installed in the aforementioned connecting portion, First busbar and second busbar It is equipped with, The first busbar is, A first main body portion that constitutes a path for electrically connecting the first connection terminal and the drive circuit, It includes a first projection that protrudes toward the wiring board relative to the first main body, The second busbar is, A second main body that constitutes a path for electrically connecting the second connection terminal and the drive circuit, It includes a second projection that protrudes toward the wiring board relative to the second main body, The passive element is electrically connected to the first projection and the second projection. Semiconductor equipment.

7. A first opening and a second opening are formed between the first portion and the second portion. The connecting portion is located between the first opening and the second opening. The semiconductor device according to claim 6.

8. The device comprises a mounting board on which the aforementioned drive circuit is installed, The first main body and the second main body are located between the mounting board and the wiring board, The first busbar is, The first main body includes a first connection portion that protrudes toward the mounting substrate and is electrically connected to the drive circuit, The second busbar is, The second main body includes a second connection portion that protrudes toward the mounting substrate and is electrically connected to the drive circuit, Each of the first and second protrusions is electrically connected to the passive element while fixed to the wiring board. A semiconductor device according to any one of claims 1 to 7.

9. At least a portion of the first main body and at least a portion of the second main body overlap each other in a plan view. A semiconductor device according to any one of claims 1 to 8.

10. The aforementioned wiring board is The first surface facing the drive circuit, Including a second surface opposite to the first surface, The passive element is installed on the second surface. A semiconductor device according to any one of claims 1 to 9.

11. The control circuit is installed on the second surface. The semiconductor device according to claim 10.

12. The passive element does not overlap the first main body and the second main body in a plan view. A semiconductor device according to any one of claims 1 to 11.

13. The passive element is, A first electrode electrically connected to the first projection, The second electrode electrically connected to the second projection and Includes a capacitive element having A semiconductor device according to any one of claims 1 to 12.

14. The passive element includes a resistor array in which a plurality of resistive elements are connected in series. The first end of the resistor array is electrically connected to the first projection, The second end of the resistor array, opposite to the first end, is electrically connected to the second projection. A detection wire connected between a first resistor and a second resistor that are adjacent to each other among the plurality of resistors. A semiconductor device according to any one of claims 1 to 13, comprising the above.

Images