Image inspection of semiconductor devices

Abstract

To accurately detect a defect even when there is no characteristic point in an inspection range.SOLUTION: An image inspecting method for a semiconductor element includes the steps of: placing a semiconductor element on a stage with an upper surface having a plurality of alignment marks; photographing an upper surface inspection mage and a first alignment image corresponding to an image of the upper surface of the stage with respect to each inspection range on an upper surface of the semiconductor element; and performing image inspection. An image inspection device stores an upper surface normal image and a second alignment image for each inspection range. In the image inspection, the image inspection device compares the upper surface inspection image with the upper surface normal image on the basis of the position of the alignment mark included in the first alignment image and the position of the alignment mark included in the second alignment image for each inspection range, thereby determining whether the upper surface inspection image contains a defect.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The technology disclosed in this specification relates to the image inspection of semiconductor elements.

[0002] Patent Document 1 discloses a method for inspecting a mask pattern provided on the surface of a wafer. In this inspection method, by providing a dummy pattern on the surface of the wafer, the recognition of pseudo defects is prevented.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] There is a technology for detecting defects on the surface of a semiconductor element by partitioning the surface of the semiconductor element into a plurality of inspection ranges, taking images of each inspection range, and comparing the images of each inspected range with a normal image. In this type of technology, in an inspection range where no feature points exist, it becomes difficult to specify the relative positional relationship between the image of the inspection range and the normal image, and defects cannot be accurately detected. For example, when a corner of an element pattern exists in the inspection range, defects can be accurately detected by comparing these images in a state where the corners of the element pattern are aligned between the image of the inspection range and the normal image. On the other hand, when no feature points (for example, corners of an element pattern, etc.) exist in the inspection range, alignment cannot be performed between the image of the inspection range and the normal image, and defects cannot be accurately detected. In this specification, an image inspection method capable of accurately detecting defects even when no feature points exist in the inspection range is proposed.

Means for Solving the Problems

[0005] The image inspection method for a semiconductor device disclosed herein comprises a semiconductor device placement step, an image capture step, and an image inspection step. In the semiconductor device placement step, a semiconductor device is placed on a stage having a plurality of alignment marks on its upper surface. In the image capture step, a plurality of inspection areas are set on the upper surface of the semiconductor device such that at least one of the alignment marks is positioned below each inspection area, and for each inspection area, an upper surface inspection image, which is an image of the upper surface of the semiconductor device, and a first alignment image, which is an image of the upper surface of the stage, are captured. In the image inspection step, image inspection is performed using an image inspection device. The image inspection device stores, for each inspection area, an upper surface normal image, which is a normal image of the upper surface of the semiconductor device, and a second alignment image, which is a normal image of the upper surface of the stage. In the image inspection described above, the image inspection device determines whether or not a defect is present in the top surface inspection image by comparing the top surface inspection image with the top surface normal image, using the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image as references for each inspection range.

[0006] Alignment marks are provided on the top surface of the stage used in this image inspection method. The alignment marks can be any marks that can identify the position (e.g., x and y coordinates) within the inspection range. In this image inspection method, a top surface inspection image and a first alignment image are taken for each inspection range of the semiconductor device. The first alignment image is an image of the top surface of the stage and includes an image of the alignment marks provided on the stage. In the image inspection, the top surface inspection image and the top surface normal image are compared based on the positions of the alignment marks included in the first alignment image and the alignment marks included in the second alignment image. That is, the relative positions of the top surface inspection image and the top surface normal image are determined using the alignment marks included in the first alignment image and the alignment marks included in the second alignment image, and the top surface inspection image and the top surface normal image are compared based on that relative position. Therefore, even if there are no feature points within the inspection range, alignment can be performed between the top surface inspection image and the top surface normal image. For this reason, this inspection method can accurately detect defects even when there are no feature points within the inspection range. [Brief explanation of the drawing]

[0007] [Figure 1] Plan view of semiconductor wafer 10. [Figure 2] Plan view of semiconductor element 14. [Figure 3] A floor plan showing the inspection area of ​​50. [Figure 4] Floor plan of Stage 40. [Figure 5] A plan view of the stage 40 with a semiconductor wafer 10 placed on it. [Figure 6] Diagram showing the configuration of an image inspection system. [Figure 7] A diagram showing grooves 42x and 42y visible through the semiconductor element 14. [Figure 8] Diagram illustrating the coordinates (x1, y1) and (x2, y2). [Figure 9] A diagram illustrating the method for calculating the difference (Δxc, Δyc). [Figure 10]A diagram illustrating the method for calculating the difference (Δxc, Δyc). [Figure 11] A diagram illustrating how to overlay a top view inspection image and a top view normal image. [Figure 12] An explanatory diagram illustrating false detection of defects due to misalignment. [Figure 13] Configuration diagram of the image inspection apparatus in Example 2. [Figure 14] A diagram showing an example of the placement of alignment marks on the upper surface of stage 40. [Modes for carrying out the invention]

[0008] In one example of an image inspection method disclosed herein, the semiconductor element may be provided on a light-transmitting semiconductor wafer. In capturing the top surface inspection image, the top surface of the semiconductor wafer may be photographed from above by a camera. In capturing the first alignment image, the top surface of the stage, visible through the semiconductor wafer, may be photographed from above by the camera.

[0009] This configuration allows for accurate acquisition of top-view inspection images and first alignment images.

[0010] In an example image inspection method disclosed herein, the semiconductor element may be provided on a semiconductor wafer. The stage may be light-transmitting. In capturing the top surface inspection image, the top surface of the semiconductor wafer may be photographed from above by a first camera. In capturing the first alignment image, the top surface of the stage, visible through the stage, may be photographed from below by a second camera provided coaxially with the first camera.

[0011] This configuration allows for accurate acquisition of top-view inspection images and first alignment images.

[0012] In an example of the image inspection method disclosed in this specification, the upper surface of the semiconductor element may have feature points having a shape capable of specifying a position. The upper surface inspection image including the feature points may be a feature point upper surface inspection image. The first alignment image corresponding to the feature point upper surface inspection image may be a specified first alignment image. In the image inspection, the image inspection apparatus may specify a specific positional relationship between the feature points included in the feature point upper surface inspection image and the alignment marks included in the specified first alignment image. In the image inspection, for each inspection range, the image inspection apparatus compares the upper surface inspection image and the upper surface normal image based on the position of the alignment marks included in the first alignment image, the position of the alignment marks included in the second alignment image, and the specific positional relationship, thereby determining whether the upper surface inspection image includes a defect.

[0013] According to this configuration, misalignment when placing the semiconductor element on the stage can be corrected, and defects can be detected more accurately.

[0014] In an example of the image inspection method disclosed in this specification, before the step of placing the semiconductor element on the stage, a pattern provided on the upper surface of the wafer on which the semiconductor element is provided may be photographed, and a step of adjusting an angle around the central axis of the wafer based on the photographed pattern may be included. In the step of placing the semiconductor element on the stage, the wafer in the state where the angle is adjusted may be placed on the stage.

[0015] According to this configuration, angular misalignment between the semiconductor element and the stage can be suppressed.

Example

[0016] The manufacturing method of the semiconductor element of Example 1 will be described. The manufacturing method of Example 1 includes an image inspection method for the semiconductor element.

[0017] (Semiconductor element structure formation step) First, a semiconductor device formation process is carried out. In the semiconductor device formation process, as shown in Figure 1, a plurality of semiconductor devices 14 are formed on a semiconductor wafer 10. The semiconductor wafer 10 has a disc shape. In Example 1, the semiconductor wafer 10 is made of a light-transmitting semiconductor material such as SiC or GaN. For example, in the semiconductor device formation process, a plurality of semiconductor devices 14 are formed on the upper surface 10a of the semiconductor wafer 10 by performing ion implantation, epitaxial growth, etching, etc. In each figure, the x-direction of the semiconductor wafer 10 is a single direction parallel to the upper surface 10a, the y-direction of the semiconductor wafer 10 is parallel to the upper surface 10a and perpendicular to the x-direction, and the z-direction of the semiconductor wafer 10 is the thickness direction of the semiconductor wafer 10. The plurality of semiconductor devices 14 are arranged in a matrix along the x and y directions on the upper surface 10a. Figure 2 illustrates an enlarged plan view of the upper surface 10a of one semiconductor device 14 (i.e., the upper surface 10a of the semiconductor wafer 10 within the range of one semiconductor device 14). The semiconductor element 14 has two element regions 15 on its upper surface 10a. A trench-type FET is formed in each element region 15. As a result, a striped pattern formed by trenches is visible within each element region 15. Note that, in figures other than Figure 2, the striped pattern within each element region 15 is omitted for clarity. As will be described in detail later, image inspection is performed on the upper surface 10a of the semiconductor element 14. In the image inspection, as shown in Figure 3, the upper surface 10a of the semiconductor element 14 is divided into multiple inspection areas 50, and inspection is performed on each inspection area 50. The inspection area 50n shown in Figure 3 does not include characteristic points such as the outer edge of the element region 15. The image inspection method of Example 1 can appropriately inspect even inspection areas 50n that do not include characteristic points.

[0018] Next, the semiconductor wafer 10 is image-inspected using an image inspection device. The image inspection device has a handling tool and a stage. First, the wafer transport process is carried out.

[0019] (Wafer transport process) In the wafer placement process, the semiconductor wafer 10 is transported onto the stage by a handling tool. Figure 4 shows the top surface 40a of the stage 40 of the image inspection apparatus. In each figure, the x-direction of the stage 40 is parallel to the top surface 40a, the y-direction of the stage 40 is parallel to the top surface 40a and perpendicular to the x-direction, and the z-direction of the stage 40 is the thickness direction of the stage 40. As shown in Figure 4, the top surface 40a of the stage 40 is provided with a plurality of grooves 42x extending along the x-direction and a plurality of grooves 42y extending along the y-direction. Therefore, the intersections 44 of the grooves 42x and grooves 42y are arranged in a matrix along the x and y directions. The intersections 44 of the grooves 42x extending in the x-direction and grooves 42y extending in the y-direction have a shape that allows the position in the x and y directions to be identified when the top surface 40a is image-recognized. Each intersection 44 is used as an alignment mark for position measurement. In the wafer transfer process, the handling tool adjusts its angle so that the x and y directions of the semiconductor wafer 10 coincide with the x and y directions of the stage 40, and then places the semiconductor wafer 10 on the stage 40. Specifically, first, the handling tool captures images of patterns (i.e., feature points) on the upper surface 10a of the semiconductor wafer 10 using a camera or the like, and identifies the location of these patterns. Here, the locations of multiple patterns are identified. The patterns may be, for example, the corners 15a of the element region 15 shown in Figure 2, or position detection marks provided outside the element region 15 (i.e., the outer periphery of the semiconductor wafer 10). Once the locations of multiple patterns are identified, the angle of the semiconductor wafer 10 around the z axis is calculated based on the identified locations. Next, the handling tool adjusts the angle of the semiconductor wafer 10 around the z axis so that the angle of the semiconductor wafer 10 around the z axis matches the design value. Then, with the angle around the z axis adjusted, the handling tool places the semiconductor wafer 10 on the stage 40. As a result, the semiconductor wafer 10 is placed on the stage 40 with its x and y directions aligned with the x and y directions of the stage 40.

[0020] Figure 5 shows a semiconductor wafer 10 placed on a stage 40. As shown in Figure 5, since the semiconductor wafer 10 is light-transmitting, the grooves 42x and 42y provided in the stage 40 can be seen through the semiconductor wafer 10. The spacing between the grooves 42x and 42y is sufficiently smaller than the width of the semiconductor element 14 in the x and y directions. Therefore, as shown in Figure 5, multiple intersections 44 are arranged below each semiconductor element 14.

[0021] (Image inspection process) Next, an image inspection process is performed using an image inspection device. In the image inspection process, the top surface 10a of each semiconductor element 14 is photographed for each inspection range 50, and the presence or absence of defects on the top surface 10a is inspected. As shown in Figure 6, the image inspection device has a camera 62, a storage device 66, and a control device 68. The camera 62 is positioned above the stage 40. The camera 62 is installed facing vertically downwards. The camera 62 can photograph the top surface 10a of the semiconductor wafer 10 placed on the stage 40. The camera 62 can move relative to the stage 40 in the x and y directions. By moving the camera 62 relative to the stage 40, the shooting range of the camera 62 can be changed. The control device 68 controls the camera 62. The control device 68 can also read data from the storage device 66. In the image inspection process, the image inspection device sequentially performs image acquisition, displacement calculation, and defect detection.

[0022] (Photo taken) In image capture, the control device 68 first sets multiple inspection areas 50 on the upper surface 10a of one semiconductor element 14, as shown in Figure 7. The control device 68 sets multiple inspection areas 50 so that rectangular inspection areas 50 are arranged in a matrix along the x and y directions. In Figure 7, the dashed lines indicate grooves 42x and 42y visible through the semiconductor element 14. The control device 68 sets the inspection areas 50 so that one intersection 44 is located at the bottom of each inspection area 50.

[0023] Next, the control device 68 selects one inspection range 50 and moves the camera 62 to the coordinates corresponding to the selected inspection range 50. Then, the control device 68 takes an image with the camera 62's focus aligned to the top surface 10a. This captures an image of the top surface 10a within the selected inspection range 50 (hereinafter referred to as the top surface inspection image). Next, without moving the camera 62's shooting range, the control device 68 takes an image with the camera 62's focus aligned to the top surface 40a of the stage 40. Since the semiconductor wafer 10 is light-transmitting, the camera 62 can capture the top surface 40a. This captures an image of the top surface 40a within the selected inspection range 50 (hereinafter referred to as the first alignment image). In this way, the control device 68 captures the top surface inspection image and the first alignment image of the selected inspection range 50. By changing the focus, the top surface inspection image and the first alignment image can be captured coaxially. Therefore, the discrepancy in the imaging range between the top inspection image and the first alignment image can be suppressed. Since the intersection 44 is within the inspection range 50, the first alignment image includes the intersection 44. The control device 68 sequentially performs the same imaging for each inspection range 50. Therefore, a top inspection image and a first alignment image are captured for each inspection range 50.

[0024] (Calculation of deviation) Next, the control device 68 reads out the top inspection image and the first alignment image of the inspection range 50a shown in Figure 7. The inspection range 50a includes the corner 15a of the element region 15. Figure 8 shows the top inspection image and the first alignment image of the inspection range 50a superimposed. The control device 68 identifies the x and y coordinates of the corner 15a within the top inspection image of the inspection range 50a. Since the corner 15a is the connection point between the edge extending in the x direction and the edge extending in the y direction of the element region 15, the control device 68 can identify the x and y coordinates of the corner 15a. The control device 68 also identifies the x and y coordinates of the intersection 44 within the first alignment image of the inspection range 50a. Since the intersection 44 is the intersection of the groove 42x extending in the x direction and the groove 42y extending in the y direction, the control device 68 can identify the x and y coordinates of the intersection 44. Next, the control device 68 calculates the relative position (x1, y1) of the corner 15a with respect to the intersection 44 between the top surface inspection image and the first alignment image. When the semiconductor wafer 10 is placed on the stage 40, errors occur in the placement position in the x and y directions, so the relative position (x1, y1) changes according to the errors.

[0025] Next, the control device 68 accesses the storage device 66 to read out the normal top image and the second alignment image. First, the normal top image and the second alignment image will be explained. The normal top image and the second alignment image are images taken by the camera 62 of the top surface 10a of the semiconductor element 14 without defects and the top surface 40a of the stage 40, with the semiconductor element 14 without defects placed on the stage 40. The normal top image and the second alignment image are taken for all inspection areas 50. The normal top image and the second alignment image were previously taken by the image inspection device. The normal top image and the second alignment image for all inspection areas 50 are stored in the storage device 66.

[0026] The control device 68 reads out a normal top image and a second alignment image of the inspection range 50a, which includes the corner 15a of the element region 15. The control device 68 identifies the x and y coordinates of the corner 15a within the normal top image of the inspection range 50a. The control device 68 also identifies the x and y coordinates of the intersection 44 within the second alignment image of the inspection range 50a. Next, the control device 68 calculates the relative position (x2, y2) of the corner 15a with respect to the intersection 44 between the normal top image and the second alignment image. The relative coordinates (x2, y2) are the design position of the corner 15a with respect to the intersection 44. Note that the relative coordinates (x2, y2) may be values ​​that have been stored in the storage device 66 beforehand.

[0027] The control device 68 calculates the relative coordinates (x1, y1) and (x2, y2), and then calculates the difference between them (Δxref, Δyref) (i.e., Δxref = x2 - x1, Δyref = y2 - y1). Since the relative coordinates (x1, y1) are the relative positions of the corner 15a of the top surface inspection image with respect to the intersection point 44, and the relative coordinates (x2, y2) are the relative positions of the corner 15a of the top surface normal image with respect to the intersection point 44, the difference (Δxref, Δyref) represents the relative position of the corner 15a of the top surface inspection image with respect to the corner 15a of the top surface normal image. Since angle adjustment is performed when the semiconductor wafer 10 is placed on the stage 40, there is almost no angular difference between the top surface inspection image and the top surface normal image. Therefore, the difference (Δxref, Δyref) indicates the positional shift of the shooting range of the top surface inspection image relative to the shooting range of the top surface normal image. Furthermore, although the difference (Δxref, Δyref) is a value calculated in the inspection range 50a, the positional displacement when the semiconductor wafer 10 is placed on the stage 40 occurs similarly in all inspection ranges 50. Therefore, the difference (Δxref, Δyref) indicates the difference between the acquisition range of the normal top surface image and the acquisition range of the top surface inspection image in all inspection ranges 50.

[0028] (Defect detection) After calculating the difference (Δxref, Δyref), the control device 68 selects one inspection range 50 from multiple inspection ranges 50 and performs defect detection on the selected inspection range 50. In defect detection, the control device 68 reads out the first alignment image and the second alignment image of the selected inspection range 50. Next, it calculates the difference (Δxc, Δyc) in the position of the intersection point 44 between the first alignment image and the second alignment image. For example, as shown in Figure 9, the control device 68 identifies the coordinates (xc1, yc1) of the intersection point 44 within the shooting range of the first alignment image. Similarly, the control device 68 identifies the coordinates (xc2, yc2) of the intersection point 44 within the shooting range of the second alignment image. Then, using the formulas Δx=xc2-xc1 and Δy=yc2-yc1, it calculates the difference (Δxc, Δyc) in the position of the intersection point 44 between the first alignment image and the second alignment image. In another example, the control device 68 may superimpose the first alignment image and the second alignment image so that the intersection points 44 coincide, as shown in Figure 10, and calculate the difference in position (Δxc, Δyc) between the first alignment image and the second alignment image in the x and y directions. The difference (Δxc, Δyc) can be calculated using either method shown in Figures 9 and 10.

[0029] Next, as shown in Figure 11, the control device 68 superimposes the normal top image onto the top inspection image. At this time, the control device 68 calculates the difference (Δxd, Δyd) by adding the difference (Δxref, Δyref) and the difference (Δxc, Δyc). That is, Δxd = Δxref + Δxc and Δyd = Δyref + Δyc. Next, the control device 68 superimposes the normal top image onto the top inspection image with a position shift of the same amount as the difference (Δxd, Δyd). By superimposing the normal top image onto the top inspection image in this way, the control device 68 can accurately superimpose an image of a normal semiconductor element 14 in substantially the same portion as the top inspection image onto the top inspection image. By superimposing the normal top image onto the top inspection image in this way, the control device 68 detects the differences between the top inspection image and the normal top image as defects.

[0030] The control device 68 performs image inspection on all inspection ranges 50 of all semiconductor elements 14. Through this, the control device 68 detects the presence or absence of defects in each inspection range 50 of each semiconductor element 14. Semiconductor elements 14 in which defects are detected during image inspection are marked.

[0031] Figure 12 shows the top inspection image, the top normal image, and the pixels of each image. The width of the pixels in the image captured by camera 62 is approximately 0.5 μm. In Figure 12, the area enclosed by the thick line indicates a trench. In Figure 12, the top inspection image and the top normal image are positioned with a 0.5 μm (i.e., 1 pixel) offset in the y direction. Therefore, if the top inspection image and the top normal image are superimposed in this state, the pixels with the offset (i.e., the hatched pixels in Figure 12) will be falsely detected as defects. In contrast, the above defect detection method can reduce the positional offset between the top inspection image and the top normal image to less than 0.25 μm (i.e., less than 0.5 pixels). Therefore, there is no shift in the position of the trench between the top inspection image and the top normal image for each pixel. Thus, false detection of defects caused by positional offset can be suppressed. For this reason, defects can be detected accurately.

[0032] Furthermore, this defect inspection method allows for the superimposition of the top surface inspection image onto the normal top surface image with high positional accuracy, even in inspection range 50 that does not contain feature points (for example, inspection range 50n in Figure 3). Therefore, defects can be accurately detected even in inspection range 50 that does not contain feature points.

[0033] After the image inspection process is completed, electrodes (e.g., source electrodes for FETs, signal electrode pads, etc.) are formed on the upper surface 10a of each semiconductor element 14. Next, electrodes (e.g., drain electrodes for FETs) are formed over the entire lower surface 10b of the semiconductor wafer 10. Then, the semiconductor wafer 10 is divided into multiple semiconductor element 14 chips. After that, semiconductor elements 14 with detected defects are removed, and normal semiconductor elements 14 are shipped. In this way, semiconductor elements 14 without defects on the upper surface can be manufactured using this manufacturing method. [Examples]

[0034] The method for manufacturing a semiconductor device in Example 2 will now be described. The semiconductor wafer 10 used in Example 2 may or may not be light-transmitting. The image inspection apparatus used in Example 2 is different from the image inspection apparatus used in Example 1. Figure 13 shows the image inspection apparatus used for image inspection in Example 2. This image inspection apparatus has a camera 64 in addition to a camera 62. The camera 64 is positioned below the stage 40. The relative positions of the cameras 62 and 64 are fixed. The camera 64 is coaxial with the camera 62 and positioned upward. In this image inspection apparatus, the stage 40 is light-transmitting. The camera 64 captures an image of the upper surface 40a of the stage 40, which is visible through the stage 40. That is, the camera 64 captures a first alignment image. With the camera 64, the first alignment image can be captured coaxially with the camera 62. Except for the fact that the camera 64 captures the first alignment image, the method for manufacturing a semiconductor device in Example 2 is the same as the method for manufacturing a semiconductor device in Example 1. Therefore, defects can be accurately detected even with the manufacturing method of Example 2.

[0035] In the above-described embodiments 1 and 2, the top inspection image and the first alignment image were captured coaxially. However, the shooting range of the top inspection image and the shooting range of the first alignment image may be misaligned due to errors, etc. Even in this case, as long as the relative positional relationship between the shooting range of the top inspection image and the shooting range of the first alignment image is fixed, image inspection can be performed appropriately.

[0036] Furthermore, in Examples 1 and 2 described above, the top surface inspection image and the top surface normal image were superimposed and compared, but defects may be detected by comparing them using other methods.

[0037] Furthermore, in the above-described embodiments 1 and 2, alignment marks (i.e., intersection points 44) for position detection were formed by grooves 42x and 42y formed on the upper surface 40a of the stage 40. However, alignment marks may be formed by something other than grooves, as long as they are optically detectable. Also, in embodiments 1 and 2, the intersection point 44 of a groove 42x extending linearly in the x direction and a groove 42y extending linearly in the y direction was used as the alignment mark, but as shown in Figure 14, alignment marks 44a may be discretely provided on the upper surface 40a of the stage 40. Thus, any shape is acceptable for the alignment marks as long as the coordinates in the x and y directions can be identified.

[0038] Furthermore, in the above-described examples 1 and 2, the difference (Δxref, Δyref) was calculated based on each image in the inspection range 50a, and the overlapping position was corrected by the difference (Δxref, Δyref) when the top surface inspection image and the top surface normal image were superimposed in each inspection range 50. However, if the positional accuracy when placing the semiconductor wafer 10 on the stage 40 is sufficiently high, correction by the difference (Δxref, Δyref) may not be necessary.

[0039] Furthermore, in the above-described embodiments 1 and 2, the angle of the semiconductor wafer 10 was adjusted before placing it on the stage 40. However, if the angle of the semiconductor wafer 10 can be precisely controlled, it is not necessary to adjust the angle of the semiconductor wafer 10 before placing it on the stage 40.

[0040] Furthermore, in the above-described embodiments 1 and 2, one alignment mark (i.e., intersection point 44) of the stage 40 was placed within the inspection range 50, but two or more alignment marks may be placed within the inspection range 50.

[0041] The components of the technology disclosed herein are listed below. (Composition 1) A method for image inspection of semiconductor devices, A process of placing a semiconductor element on a stage having multiple alignment marks on its upper surface, The process involves setting a plurality of inspection areas on the upper surface of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area, and capturing a top surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, for each inspection area. The process of performing image inspection using an image inspection device, It has, The image inspection device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the aforementioned image inspection, the image inspection device determines whether or not a defect is present in the top surface inspection image by comparing the top surface inspection image with the top surface normal image, using the positions of the alignment marks in the first alignment image and the positions of the alignment marks in the second alignment image as references for each inspection range. Image inspection methods. (Configuration 2) The semiconductor element is provided on a light-transmitting semiconductor wafer. In capturing the top surface inspection image, the top surface of the semiconductor wafer is photographed from above by a camera. In capturing the first alignment image, the camera captures the upper surface of the stage visible through the semiconductor wafer from above the semiconductor wafer. The image inspection method described in Configuration 1. (Composition 3) The aforementioned semiconductor element is provided on a semiconductor wafer, The aforementioned stage has light transmittance, In capturing the top surface inspection image, the top surface of the semiconductor wafer is photographed from above by the first camera. In capturing the first alignment image, a second camera, which is mounted coaxially with the first camera, captures the upper surface of the stage, visible through the stage, from below the stage. The image inspection method described in Configuration 1. (Composition 4) The upper surface of the semiconductor element has a characteristic point with a shape that allows its position to be identified. The top surface inspection image containing the aforementioned feature points is a feature point top surface inspection image. The first alignment image corresponding to the feature point top surface inspection image is a specific first alignment image. In the aforementioned image inspection, the image inspection device identifies a specific positional relationship between the feature point included in the feature point top surface inspection image and the alignment mark included in the specific first alignment image. In the aforementioned image inspection, the image inspection device determines whether or not a defect is present in the top surface inspection image by comparing the top surface inspection image and the top surface normal image based on the position of the alignment marks included in the first alignment image and the position of the alignment marks included in the second alignment image and the specific positional relationship for each inspection range. An image inspection method described in any one of items 1 to 3 of the configuration. (Composition 5) Prior to the step of placing the semiconductor element on the stage, the process includes a step of photographing a pattern provided on the upper surface of the wafer on which the semiconductor element is located, and adjusting the angle around the central axis of the wafer based on the photographed pattern. In the step of placing the semiconductor element on the stage, the wafer with the adjusted angle is placed on the stage. An image inspection method described in any one of items 1 to 4 of the configuration. (Composition 6) A method for manufacturing a semiconductor device having an image inspection method described in any one of items 1 to 5. (Composition 7) A semiconductor device image inspection apparatus, A stage with multiple alignment marks on its top surface, Camera and, Memory device and control device, It has, The control device, with respect to the semiconductor element placed on the stage, A step of placing a semiconductor element on the aforementioned stage, The process involves setting a plurality of inspection areas on the upper surface of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area, and capturing a top surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, for each inspection area. The process of performing image inspection, It is configured to perform the following actions: The memory device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the image inspection, the control device determines whether or not a defect is present in the top surface inspection image by comparing the top surface inspection image and the top surface normal image based on the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image for each inspection range. Image inspection device.

[0042] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0043] 10: Semiconductor wafer, 14: Semiconductor element, 40: Stage, 44: Intersection

Claims

1. A method for image inspection of a semiconductor device (14), A step of placing a semiconductor element on a stage (40) having a plurality of alignment marks (44) on its upper surface (40a), The process involves setting a plurality of inspection areas on the upper surface (10a) of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area (50), and capturing an upper surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, for each inspection area. The process of performing image inspection using an image inspection device, It has, The image inspection device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the aforementioned image inspection, the image inspection device compares the top surface inspection image and the top surface normal image with respect to the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image for each inspection range, thereby determining whether or not the top surface inspection image contains defects. The semiconductor element is provided on a light-transmitting semiconductor wafer (10), In capturing the top surface inspection image, the top surface of the semiconductor wafer is photographed from above by the camera (62). In capturing the first alignment image, the camera captures the upper surface of the stage visible through the semiconductor wafer from above the semiconductor wafer. Image inspection methods.

2. A method for image inspection of a semiconductor element (14), A step of placing a semiconductor element on a stage (40) having a plurality of alignment marks (44) on its upper surface (40a), The process involves setting a plurality of inspection areas on the upper surface (10a) of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area (50), and capturing an upper surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, for each inspection area. The process of performing image inspection using an image inspection device, It has, The image inspection device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the aforementioned image inspection, the image inspection device compares the top surface inspection image and the top surface normal image with respect to the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image for each inspection range, thereby determining whether or not the top surface inspection image contains defects. The aforementioned semiconductor element is provided on a semiconductor wafer, The aforementioned stage has light transmittance, In capturing the top surface inspection image, the top surface of the semiconductor wafer is photographed from above by the first camera (62). In capturing the first alignment image, a second camera (64) mounted coaxially with the first camera captures the upper surface of the stage, visible from below the stage and through the stage. Image inspection methods.

3. A method for image inspection of a semiconductor element (14), A step of placing a semiconductor element on a stage (40) having a plurality of alignment marks (44) on its upper surface (40a), The process involves setting a plurality of inspection areas on the upper surface (10a) of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area (50), and capturing an upper surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, for each inspection area. The process of performing image inspection using an image inspection device, It has, The image inspection device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the aforementioned image inspection, the image inspection device compares the top surface inspection image and the top surface normal image with respect to the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image for each inspection range, thereby determining whether or not the top surface inspection image contains defects. The upper surface of the semiconductor element has a characteristic point (15a) with a shape that allows its position to be identified. The top surface inspection image containing the aforementioned feature points is a feature point top surface inspection image. The first alignment image corresponding to the feature point surface inspection image is a specific first alignment image. In the aforementioned image inspection, the image inspection device identifies a specific positional relationship (x1, x2) between the feature point included in the feature point top surface inspection image and the alignment mark included in the specific first alignment image. In the aforementioned image inspection, the image inspection device determines whether or not a defect is present in the top surface inspection image by comparing the top surface inspection image and the top surface normal image based on the position of the alignment marks included in the first alignment image and the position of the alignment marks included in the second alignment image and the specific positional relationship for each inspection range. Image inspection methods.

4. Prior to the step of placing the semiconductor element on the stage, the process includes a step of photographing a pattern provided on the upper surface of the wafer on which the semiconductor element is located, and adjusting the angle around the central axis of the wafer based on the photographed pattern. In the step of placing the semiconductor element on the stage, the wafer with the adjusted angle is placed on the stage. The image inspection method according to any one of claims 1 to 3.

5. A method for manufacturing a semiconductor element having the image inspection method described in any one of claims 1 to 3.

6. An image inspection apparatus for a semiconductor element provided on a light-transmitting semiconductor wafer (10), A stage with multiple alignment marks on its top surface, Camera and, Memory device and control device, It has, The control device, with respect to the semiconductor element placed on the stage, The process involves setting a plurality of inspection areas on the upper surface of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area, and capturing a top surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, for each inspection area. The process of performing image inspection, It is configured to perform the following actions: The memory device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the image inspection, the control device compares the top surface inspection image and the top surface normal image with respect to the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image for each inspection range, thereby determining whether or not the top surface inspection image contains defects. In capturing the top surface inspection image, the camera captures the top surface of the semiconductor wafer from above. In capturing the first alignment image, the camera captures the upper surface of the stage visible through the semiconductor wafer from above the semiconductor wafer. Image inspection device.

7. An image inspection apparatus for semiconductor elements provided on a semiconductor wafer, A stage with multiple alignment marks on its top surface, First camera and, The second camera and Memory device and control device, It has, The control device, with respect to the semiconductor element placed on the stage, The process involves setting a plurality of inspection areas on the upper surface of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area, and capturing a top surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, for each inspection area. The process of performing image inspection, It is configured to perform the following actions: The memory device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the image inspection, the control device compares the top surface inspection image and the top surface normal image with respect to the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image for each inspection range, thereby determining whether or not the top surface inspection image contains defects. The aforementioned stage has light transmittance, In capturing the top surface inspection image, the first camera captures the top surface of the semiconductor wafer from above the semiconductor wafer. In capturing the first alignment image, the upper surface of the stage, which is visible through the stage, is captured by the second camera, which is mounted coaxially with the first camera, from below the stage. Image inspection device.

8. An image inspection apparatus for semiconductor elements, A stage with multiple alignment marks on its top surface, Camera and, Memory device and control device, It has, The control device, with respect to the semiconductor element placed on the stage, The process involves setting a plurality of inspection areas on the upper surface of the semiconductor element such that at least one of the alignment marks is positioned at the bottom of each inspection area, and capturing a top surface inspection image, which is an image of the upper surface of the semiconductor element, and a first alignment image, which is an image of the upper surface of the stage, with the camera for each inspection area. The process of performing image inspection, It is configured to perform the following actions: The memory device stores, for each inspection range, a normal top surface image, which is a normal top surface image of the semiconductor element, and a second alignment image, which is a normal top surface image of the stage. In the image inspection, the control device compares the top surface inspection image and the top surface normal image with respect to the positions of the alignment marks included in the first alignment image and the positions of the alignment marks included in the second alignment image for each inspection range, thereby determining whether or not the top surface inspection image contains defects. The upper surface of the semiconductor element has a characteristic point (15a) with a shape that allows its position to be identified. The top surface inspection image containing the aforementioned feature points is a feature point top surface inspection image. The first alignment image corresponding to the feature point surface inspection image is a specific first alignment image. In the aforementioned image inspection, the image inspection device identifies a specific positional relationship (x1, x2) between the feature point included in the feature point top surface inspection image and the alignment mark included in the specific first alignment image. In the aforementioned image inspection, the image inspection device determines whether or not a defect is present in the top surface inspection image by comparing the top surface inspection image and the top surface normal image based on the position of the alignment marks included in the first alignment image and the position of the alignment marks included in the second alignment image and the specific positional relationship for each inspection range. Image inspection device.

Images