Optical semiconductor integrated circuits

Abstract

An optical semiconductor integrated circuit according to the present disclosure comprises: electrical input / output terminals arranged in the peripheral part of a chip; and optical input / output terminals in the periphery where the electrical input / output terminals are not arranged, thereby achieving efficient inspection of the wafer level. The optical semiconductor integrated circuit chip comprises the plurality of electrical input / output terminals in at least one peripheral part of a chip region. The electrical input / output terminals may be arranged in a U-shape in the peripheral part including three sides. The optical semiconductor integrated circuit chip further comprises the optical input / output terminals on one side where the electrical input / output terminals are not arranged. The optical input / output terminals may be a grating coupler formed on a substrate.

Description

Technical Field

[0001] The present invention relates to an optoelectronic integrated circuit, and more specifically to a terminal arrangement that enables optical and electrical inspections.

Background Art

[0002] In recent years, the application range of optical communication modules and devices is not limited to long-distance communication, but is also used for links between data centers, between base stations of mobile phones, between edge routers, etc., and the demand is increasing. In an optoelectronic integrated circuit chip including an optical circuit used in an optical communication module, in order to exclude defective chips before the module assembly process and improve the yield, automatic inspection at the wafer level is required.

[0003] In a semiconductor integrated circuit that does not include an optical circuit, wafer-level automatic inspection is widely performed using a low-cost cantilever type probe card. In wafer-level automatic inspection of a semiconductor integrated circuit chip having several tens to several hundreds or more terminals, it is common to use a cantilever type probe card that can be manufactured at low cost (Non-Patent Document 1, Non-Patent Document 2).

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

[0005] In wafer-level automated inspection of optical semiconductor integrated circuits included in optical communication devices, optical inspection is required in addition to electrical inspection. For optical inspection, optical input / output terminals such as grating couplers are placed on the chip and used as optical input / output probes. Optical semiconductor integrated circuits require inspection using both optical input / output probes and electrical probes simultaneously. In the case of typical cantilever-type probe cards, due to their structure, it is not possible to provide an area for the optical input / output probes to contact the optical semiconductor integrated circuit wafer, making wafer-level automated inspection impossible. Even inspection methods that support optical probes do not have a corresponding chip terminal layout on electrical probe cards, so only DC probes and RF probes can be used, and the number of electrical terminals is limited to about 10-20 (Non-Patent Literature 3). [Means for solving the problem]

[0006] One aspect of the present invention is an optical semiconductor integrated circuit having a mixture of optical and electrical circuits, comprising a plurality of electrical input / output terminals arranged around at least one periphery of a chip area, and one or more optical input / output terminals arranged around one periphery where the plurality of electrical input / output terminals are not arranged. [Effects of the Invention]

[0007] This invention enables efficient wafer-level inspection of optical semiconductor integrated circuits. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram illustrates the terminal arrangement for automated testing in semiconductor integrated circuits. [Figure 2] This diagram shows how a semiconductor integrated circuit is measured using a probe card. [Figure 3] This figure shows the terminal arrangement configuration of the optical semiconductor integrated circuit in Embodiment 1 of this disclosure. [Figure 4] This diagram shows the configuration of a probe card suitable for an optical semiconductor integrated circuit. [Figure 5] This figure shows the terminal arrangement configuration of the optical semiconductor integrated circuit of Embodiment 2 of the present disclosure. [Figure 6] This figure shows the terminal arrangement configuration of the optical semiconductor integrated circuit of Embodiment 3 of the present disclosure. [Figure 7] This figure shows the terminal arrangement configuration of the optical semiconductor integrated circuit of Embodiment 4 of the present disclosure. [Figure 8] This diagram illustrates optical measurements using an array-type optical input / output probe. [Modes for carrying out the invention]

[0009] The optical semiconductor integrated circuit disclosed herein enables efficient wafer-level inspection by providing electrical input / output terminals located on the periphery of the chip and optical input / output terminals on the periphery where no electrical input / output terminals are located. We propose a terminal arrangement in the optical semiconductor integrated circuit that enables efficient automated wafer-level inspection. In the following description, we will first describe the arrangement configuration of electrical terminals for automated inspection in a semiconductor integrated circuit, and then describe the arrangement configuration of electrical input / output terminals and optical input / output terminals in the optical semiconductor integrated circuit disclosed herein.

[0010] Figure 1 illustrates the terminal arrangement for automated testing in a semiconductor integrated circuit. To accommodate automated testing, the semiconductor integrated circuit chip 100 has multiple electrical input / output terminals 101 arranged around the periphery of the chip area. These terminals 101 are also called pads, and a corresponding cantilever, described later, contacts each pad. The cantilever enters from outside the chip area in four directions 10a to 10d corresponding to the four sides of the chip area and contacts the electrical input / output terminals.

[0011] Figure 2 shows how a semiconductor integrated circuit is measured using a probe card. A probe card is an instrument used for electrical testing of LSI chips and functions as an interface that electrically connects the LSI tester (a measuring instrument) to the electrical input / output terminals, i.e., pads 101, located within the chip area of ​​the wafer. Figure 2 shows the top surface of probe card 1 inspecting the chip area 10 of a semiconductor integrated circuit on the left, and a cross-section of the vicinity of the chip area of ​​probe card 1 during inspection on the right. In Figure 2, only a single semiconductor integrated circuit on the wafer is depicted as the chip area 10. Note that probe cards perform wafer-level inspections, meaning the inspection takes place before the chip is cut out.

[0012] The probe card 1 has numerous probes (probes), and electrical contact is achieved by pressing the probes against the pads. As shown in Figure 2, cantilever-type probes are widely used, and a stable electrical connection with the electrical circuits within the chip is obtained by pressing multiple cantilevers 2 against the pads with a predetermined pressure. The entire wafer is moved by a transport unit (not shown) that holds the wafer, and different chip regions are inspected sequentially.

[0013] The configuration for inspecting the chip region 10 of a semiconductor integrated circuit with the terminal arrangement shown in Figure 1 using the cantilever-type probe card 1 shown in Figure 2 does not allow for simultaneous measurement of the optical input / output terminals of the optical semiconductor integrated circuit. For the optical input / output terminals, it is necessary to use a tip-sphere fiber, lensed fiber, single-mode fiber, polarization-maintaining fiber, or a fiber array combining these as the optical input / output probe.

[0014] The optical semiconductor integrated circuit disclosed herein provides a terminal configuration that enables simultaneous electrical measurement using widely used probe cards and optical measurement using optical input / output terminals and optical input / output probes. [Embodiment 1] Figure 3 shows the terminal arrangement configuration of an optical semiconductor integrated circuit according to Embodiment 1 of this disclosure. The optical semiconductor integrated circuit chip 200 is an integrated circuit that includes both optical circuit elements and electrical circuit elements, and is fabricated, for example, on a Si substrate wafer. The optical semiconductor integrated circuit chip 200 shown in Figure 3 shows the top surface of a single chip region, which is a single region on the wafer before it is cut into individual chips during wafer-level inspection. There are no limitations on the functions realized by the optical semiconductor integrated circuit chip 200, and all subsequent drawings show terminals necessary for wafer-level inspection.

[0015] The optical semiconductor integrated circuit chip 200 includes a plurality of electrical input / output terminals 201 at at least one periphery of the chip region. The electrical input / output terminals may be arranged in a U-shape at the peripheral portions of three sides as shown in FIG. 3. The optical semiconductor integrated circuit chip 200 further includes an optical input / output terminal 202 on one side where the electrical input / output terminals are not arranged. The optical input / output terminal can be a grating coupler formed on the substrate. The grating coupler is connected to a waveguide having a width of about 350 - 600 nm through a tapered waveguide expansion region from a portion where a rectangular grating is formed. This waveguide is connected to optical circuit elements such as an optical modulator and a photodiode in the chip, and light can be input and output by an external optical input / output probe in the grating. In each figure after FIG. 3, the grating region and the waveguide expansion region are schematically shown as triangles.

[0016] In the probe card 1 shown in FIG. 2, the cantilevers were inserted from the four directions of up, down, left, and right. In contrast, with the terminal arrangement as shown in FIG. 3, the cantilevers can be inserted from three directions 10a to 10c with respect to the electrical input / output terminals arranged in a U-shape. At the same time, an optical input / output probe can be inserted in the direction 20 from outside the chip region toward one periphery of the optical semiconductor integrated circuit 200 and optically coupled with the optical input / output terminal 202 to perform an optical inspection.

[0017] Therefore, the optical semiconductor integrated circuit of the present disclosure can be implemented as an optical semiconductor integrated circuit 200 in which an optical circuit and an electrical circuit are mixed, and includes a plurality of electrical input / output terminals 201 arranged at at least one periphery of the chip region, and one or more optical input / output terminals 202 arranged at one periphery where the plurality of electrical input / output terminals are not arranged.

[0018] Figure 4 shows the configuration of a probe card adapted to an optical semiconductor integrated circuit. By cutting off one side of the probe card 1 for the semiconductor integrated circuit shown in Figure 2, the optical probe 3 can penetrate the chip area through the cut-off region. By adjusting the probe card to a U-shape that can accommodate three sides of the optical semiconductor integrated circuit, inspection using the optical input / output probe 3 becomes possible. As shown in Figure 3, by providing electrical input / output terminals on up to three sides and optical input / output terminals 202 on the side without electrical input / output terminals, wafer-level automated inspection of large-scale optical semiconductor integrated circuits with more than 100 electrical terminals becomes possible. For example, it is suitable for optical semiconductor integrated circuits equipped with numerous optical transceiver circuits, such as those incorporated into optical communication modules.

[0019] Figure 3 shows an example where electrical input / output terminals are located around three peripheries, and an optical input / output probe 202 is located around the remaining periphery. The location of the optical input / output probe is not limited to this; if electrical input / output terminals are located around two peripheries corresponding to directions 10a and 10b, an optical input / output terminal can also be located on the side corresponding to direction 10c. In this case, the optical input / output probe would penetrate direction 10c in Figure 3. As yet another example, if electrical input / output terminals are located around only one periphery corresponding to direction 10b, an optical input / output terminal can also be located on the side corresponding to direction 10a. In this case, the optical input / output probe would penetrate direction 10a.

[0020] Therefore, the electrical input / output terminals 201 do not need to be located on all three sides of the chip periphery as shown in Figure 3. Furthermore, the electrical input / output terminals may be located not only on the chip periphery as shown in Figure 3, but also inside the chip area. The electrical input / output terminals include those necessary for testing and those necessary for modularization when mounted on a device board or the like. Terminals used only during mounting may be placed in any position. [Embodiment 2] Figure 5 shows the terminal arrangement configuration of an optical semiconductor integrated circuit of Embodiment 2 of the present disclosure. Embodiment 2 shows a case in which the optical semiconductor integrated circuit 300 includes a plurality of Mach-Zehnder interferometer (MZI) type modulators as an optical circuit. Figure 5 schematically shows an example including four MZI type modulators 303. The MZI type modulator includes a modulation electrode formed between a high-frequency electrical signal input terminal 304 and a high-frequency electrical signal output terminal 305.

[0021] The optical semiconductor integrated circuit 300 has multiple electrical input / output terminals on at least one periphery, and in the example shown in Figure 5, it has multiple electrical input / output terminals 301 on three sides. Of the electrical input / output terminals, one periphery has a high-frequency electrical signal input terminal 304 for an MZI type modulator. Another periphery that does not have electrical input / output terminals has an additional optical input / output terminal 302. The optical input / output terminal 302 may be a grating coupler formed on the substrate.

[0022] By positioning the high-frequency signal input terminal 304 of the MZI type modulator's electrodes near the chip, the physical distance between the MZI type modulator and the drive circuit can be shortened when the chip is mounted on a module board or the like. Shortening the connection distance reduces high-frequency losses due to the connection between the drive circuit and the MZI type modulator, thereby improving the high-frequency performance of the modulator.

[0023] In the optical semiconductor integrated circuit 300, a cantilever can be inserted from three directions 10a to 10c into the U-shaped arrangement of electrical input / output terminals. An optical input / output probe can be inserted in a direction 20 toward one periphery of the optical semiconductor integrated circuit 300 from outside the chip area and optically coupled with the optical input / output terminal 302 to perform optical inspection. Similar to the optical semiconductor integrated circuit of Embodiment 1, since the optical input / output terminal 302 is provided in one periphery where no electrical input / output terminals are located, wafer-level automated inspection of the optical semiconductor integrated circuit equipped with an MZI type modulator can be performed.

[0024] The electrical input / output terminals 301 and 304 do not need to be located on all three sides of the chip's periphery. The electrical input / output terminals may also be located inside the chip. In optical semiconductor integrated circuits, electrical input / output terminals include terminals necessary for testing and mounting terminals necessary for assembly when actually modularizing the chip. Terminals used only for mounting can be located in any position. The terminal on the high-frequency signal output side of the MZI type modulator is a mounting terminal that does not need to be probed during testing, so it may be located near the optical input / output terminal 302 of a grating coupler or similar. [Embodiment 3] Figure 6 shows the terminal arrangement configuration of an optical semiconductor integrated circuit of Embodiment 3 of the present disclosure. Embodiment 3 shows a case in which the optical semiconductor integrated circuit 400 includes a plurality of photodiodes as an optical circuit. Figure 6 schematically shows an example including four photodiodes 403. Each photodiode 403 includes a photodiode element 405 and a high-frequency electrical signal output terminal 404 for extracting a detection signal.

[0025] The optical semiconductor integrated circuit 400 has multiple electrical input / output terminals on at least one periphery, and in the example shown in Figure 6, it has multiple electrical input / output terminals 401 on three sides. Of these electrical input / output terminals, a high-frequency electrical signal output terminal 404 of a photodiode is located on the periphery of one side. On the side where no electrical input / output terminals are located, there is an additional optical input / output terminal 402. The optical input / output terminal 402 may be a grating coupler formed on the substrate.

[0026] By positioning the high-frequency signal output terminal 404 of the photodiode's electrode near the periphery of the chip, the physical distance from the photodiode to the amplification circuit for the electrical signal output can be shortened when the chip is mounted on a module or the like. Shortening the electrical wiring reduces high-frequency losses due to the connection between the amplification circuit and the photodiode, thereby improving high-frequency performance.

[0027] In the optical semiconductor integrated circuit 400, a cantilever can be inserted from three directions 10a to 10c into the U-shaped arrangement of electrical input / output terminals. An optical input / output probe can be inserted in a direction 20 toward the periphery of one of the optical semiconductor integrated circuits 400 from outside the chip area and optically coupled with the optical input / output terminal 402 to perform optical inspection. Similar to the optical semiconductor integrated circuits of Embodiments 1 and 2, the optical input / output terminal 402 is provided on one side where no electrical input / output terminals are located, making it possible to perform wafer-level automated inspection of optical semiconductor integrated circuits equipped with multiple photodiodes.

[0028] Electrical input / output terminals do not need to be located on all three sides of the chip's periphery. Electrical input / output terminals may also be located inside the chip. In optical semiconductor integrated circuits, electrical input / output terminals include terminals necessary for testing and mounting terminals necessary for actual module assembly. Terminals used only during mounting may be placed in any location. [Embodiment 4] Figure 7 shows the terminal arrangement configuration of the optical semiconductor integrated circuit of Embodiment 4 of this disclosure. Embodiment 4's optical semiconductor integrated circuit 500 shows an example configuration where the electrical input / output terminals and optical input / output terminals are in close proximity.

[0029] The optical semiconductor integrated circuit 500 has multiple electrical input / output terminals on at least one periphery, and in the example shown in Figure 7, it has multiple electrical input / output terminals 501 on three sides. Furthermore, it has electrical input / output terminals 504a arranged parallel to the electrical input / output terminals on the upper side and electrical input / output terminals 504 arranged parallel to the electrical input / output terminals on the lower side, located further inside the chip area. By maintaining a certain distance between the two rows of electrical input / output terminals, a cantilever can be inserted into the two rows simultaneously or separately from directions 10a and 10c. The optical semiconductor integrated circuit 500 also has optical input / output terminals 502 on the side where no electrical input / output terminals are located. The optical input / output terminals 502 may be grating couplers formed on the substrate.

[0030] In the optical semiconductor integrated circuit 500 of this embodiment, an optical input / output probe can be inserted from outside the chip area in direction 20 and optically coupled with the optical input / output terminal 502 to perform optical inspection. In the terminal arrangement of the optical semiconductor integrated circuit 500, the distance between the optical input / output terminal 502 and the adjacent electrical input / output terminals 503a and 504a becomes an issue.

[0031] Figure 8 illustrates optical measurement using an array-type optical input / output probe. Figure 8(a) shows the structure of the array-type optical input / output probe 510. The optical input / output probe 510 comprises a base member 513 with multiple grooves formed at intervals between the fiber arrays, and a lid member 512 that sandwiches and fixes the fiber array 511. The lid member 512 needs to be at least 200 μm thick.

[0032] Figure 8(b) shows how optical measurements are performed using an array-type optical input / output probe 510. It shows a cross-section perpendicular to the wafer substrate, including the optical input / output terminal 502 and the adjacent electrical input / output terminal 504a for inspection, as shown in Figure 7. Here, the optical input / output terminal 502 is considered to be a grating coupler fabricated using silicon photonics technology with a silicon substrate. The beam output from such a grating coupler 502 is in the communication wavelength band of 1550 μm, and with a surface height of 150 μm from the wafer, it has a spread of about 100 μm in the left-right direction in Figure 8(b). That is, if the adjacent electrical input / output terminal 504a is about 250 μm away from the optical input / output center point 505, which is on the extension of the core center of the optical input / output probe 510, the cantilever can penetrate without interference. This is because a spatial margin of about 50 μm is required in the direction where the electrical input / output terminal 504a is located when scanning the position of the optical input / output probe 510 to obtain maximum optical coupling with the beam output from the grating coupler.

[0033] Referring again to Figure 7, by positioning each terminal so that it is at least 250 μm away from the coupling center position 505 of the optical input / output terminal 502 to the nearest electrical input / output terminal, the cantilever-type probe and the optical output probe do not interfere with each other, and wafer-level automated inspection of optical semiconductor integrated circuits can be performed.

[0034] In this embodiment of the optical semiconductor integrated circuit, electrical input / output terminals do not need to be located on all three sides of the chip's periphery. Electrical input / output terminals may be located inside the chip. Electrical input / output terminals include those necessary for testing and those necessary for actual module assembly. Terminals used only during assembly may be placed in any position. [Industrial applicability]

[0035] This invention can be used in optical communications.

Claims

1. An optical semiconductor integrated circuit in which optical circuits and electrical circuits are mixed, Multiple electrical input / output terminals are arranged around the three peripheries of the rectangular chip area, One or more optical input / output terminals are located around one of the multiple electrical input / output terminals that are not arranged therein. In at least one of the three peripheries, there are other electrical input / output terminals arranged parallel to the plurality of electrical input / output terminals, and further inside the rectangle. An optical semiconductor integrated circuit equipped with [a specific feature].

2. The optical circuit includes a Mach-Zehnder interferometer type modulator. The chip region, which is not on the side where the high-frequency signal input terminals of the Mach-Zehnder interferometer type modulator are located, is provided with one or more optical input / output terminals. The optical semiconductor integrated circuit according to claim 1.

3. The optical circuit includes a photodiode, The chip region on the side other than the side where the high-frequency signal output terminal of the photodiode is located is provided with one or more optical input / output terminals. The optical semiconductor integrated circuit according to claim 1.

4. Among the electrical input / output terminals arranged along the side perpendicular to the side on which the one or more optical input / output terminals are located, the distance between the electrical input / output terminal closest to the one or more optical input / output terminals and the optical input / output point of the optical input / output terminal is 250 μm or more. The optical semiconductor integrated circuit according to claim 1.

5. The optical semiconductor integrated circuit according to any one of claims 1 to 4, wherein the optical input / output terminal is a grating coupler capable of inputting and outputting light toward the outside of the chip region.

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