Simulation program, simulation method, and information processing device

Abstract

The present invention improves the efficiency of calculating the probability of occurrence of logical errors.　An information processing device (10) generates error patterns (2-4) indicating a first data qubit that generates an error among a plurality of data qubits included in a two-dimensional lattice array in which the plurality of data qubits and a plurality of auxiliary qubits are arranged alternately in each of the row and column directions. The information processing device (10) determines whether or not the first data qubit indicated in the error patterns (2-4) meets predetermined determination criteria. If the determination criteria are met, the information processing device (10) determines that no logical error occurs in the error patterns (2-4). If the determination criteria are not met, the information processing device (10) determines whether or not a logical error has occurred on the basis of error detection information with flipped states of the auxiliary qubits adjacent to the first data qubit in the row or column direction as indicated in the error patterns (2-4).

Description

Technical Field

[0001] The present invention relates to a simulation program for quantum bit error correction, a simulation method, and an information processing apparatus.

Background Art

[0002] The calculation of a quantum computer is realized by performing initialization, gate operations, and measurement processing on a plurality of qubits. In a quantum computer, an error (physical error) occurs in a qubit due to environmental noise or the like during the process of operating on such qubits. Therefore, in a quantum computer, in order to identify an error qubit and the error content, redundancy of qubits is performed in the same manner as in a classical computer (also called a Neumann-type computer).

[0003] One method for identifying an error qubit and the error content using redundant qubits is a surface code. In a surface code, data qubits and auxiliary qubits are alternately arranged in a two-dimensional lattice. The state of the data qubits among the plurality of qubits (data qubits and auxiliary qubits) arranged in the lattice is encoded into one logical qubit. The auxiliary qubits are used either for X error detection or for Z error detection for each column. When performing a surface code, the quantum computer first appropriately initializes the logical quantum state, and during error detection, performs a gate operation between one auxiliary qubit and four surrounding data qubits, and measures the auxiliary qubit. The quantum computer detects an X error or a Z error based on the value of the auxiliary qubit. Then, the quantum computer performs a gate operation for error correction processing on the qubit using the information indicating the type of error and the position information of the data qubit identified as the error location.

[0004] Error correction techniques include, for example, quantum error correction methods that include a step of correcting the stream of syndrome measurements generated by quantum computers. Techniques for optimizing physical parameters in fault-tolerant quantum computing to reduce frequency congestion have also been proposed. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Special Publication No. 2020-535690 [Patent Document 2] Special Publication No. 2020-515970 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] When errors occur in a predetermined number of qubits among the multiple qubits that make up a single logical qubit, error correction may fail even with surface coding. Such a failure of error correction is called a logical error.

[0007] In surface coding, the probability of a logical error occurring changes depending on the number of qubits in the two-dimensional lattice array representing a single logical qubit. The probability of a logical error also changes depending on the rate of qubit errors caused by environmental noise, etc. Therefore, to evaluate the performance of quantum error correction using surface coding, it is conceivable to perform a simulation of error correction using surface coding with a classical computer. In a real quantum computer, it is not possible to determine whether a logical error has occurred without measuring the data qubit itself, but in a simulation, the location of the error can be known in advance. Therefore, by performing a simulation of error correction using surface coding under predetermined conditions, it is possible to determine whether or not a logical error occurs under those conditions.

[0008] In error correction simulations, the probability of a logical error occurring is used to evaluate the performance of the error correction code. For example, N error patterns (where N is a natural number) are generated, and each one is decoded (the process of identifying the location of the error), and a determination is made as to whether or not a logical error occurred based on the error pattern and the decoded result. If the total number of times a logical error occurs is m (where m is a non-negative integer), the probability of a logical error is calculated as m / N. To minimize the influence of statistical errors, N is generally a very large value, typically between 10,000 and 1,000,000. Because the calculation of the probability of a logical error involves numerous decodements, the computation time is prolonged.

[0009] In one aspect, this project aims to improve the efficiency of calculating the probability of logical errors occurring. [Means for solving the problem]

[0010] One proposal provides a simulation program that instructs a computer to perform the following processes: The computer generates an error pattern that indicates a first data qubit that generates an error among multiple data qubits contained in a two-dimensional lattice array in which multiple data qubits and multiple auxiliary qubits are alternately arranged in the row and column directions. The computer determines whether the first data qubit indicated in the error pattern satisfies predetermined criteria. If the criteria are met, the computer determines that no logical error has occurred in the error pattern. If the criteria are not met, the computer determines whether a logical error has occurred based on error detection information obtained by inverting the state of the auxiliary qubits adjacent to the first data qubit indicated in the error pattern in the row or column direction. [Effects of the Invention]

[0011] According to one embodiment, the calculation efficiency of the probability of logical error occurrence is improved. The above and other objects, features, and advantages of the present invention will become apparent from the following description in connection with the accompanying drawings that represent preferred embodiments of the present invention as examples.

Brief Description of the Drawings

[0012] [Figure 1] It is a diagram showing an example of a simulation method according to a first embodiment. [Figure 2] It is a diagram showing an example of the hardware of a computer that executes surface code simulation. [Figure 3] It is a diagram showing an example of the error occurrence situation in a qubit. [Figure 4] It is a diagram showing an example of the redundancy of qubits. [Figure 5] It is a diagram showing an example of the configuration of qubits for performing surface code. [Figure 6] It is a diagram showing an example of the measurement result of an auxiliary qubit when an error occurs. [Figure 7] It is a diagram showing an example of error correction by surface code. [Figure 8] It is a diagram showing an example when the error occurrence location cannot be uniquely specified. [Figure 9] It is a diagram showing an example of a logical error due to miscorrection. [Figure 10] It is a diagram showing an example of the relationship between the physical error probability and the logical error probability. [Figure 11] It is a diagram showing an example of an error pattern. [Figure 12] It is a block diagram showing the functions of a computer for performing surface code simulation. [Figure 13] It is a diagram showing an example of a determination example of the presence or absence of decoding omission. [Figure 14] It is a flowchart showing an example of the procedure of logical error (Z error) probability calculation processing. [Figure 15] It is a flowchart showing the details of the procedure of logical error (Z error) occurrence determination processing. [Figure 16]It is a flowchart showing an example of the procedure for calculating the logical error (X error) probability. [Figure 17] It is a flowchart showing the details of the procedure for determining the occurrence of a logical error (X error). [Figure 18] It is a diagram showing an example of the measurement result of the calculation time. [Figure 19] It is a diagram showing an example of the counting result of the number of decoding times. [Figure 20] It is a diagram showing an example of the calculation result of the logical error probability. [Figure 21] It is a diagram showing an example of the number of occurrences of a logical error when the judgment criterion is satisfied.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, the present embodiment will be described with reference to the drawings. Note that each embodiment can be implemented by combining a plurality of embodiments within a non - contradictory range. 〔First Embodiment〕 The first embodiment is a simulation method that enables efficient determination of the presence or absence of the occurrence of a logical error in quantum error correction.

[0014] FIG. 1 is a diagram showing an example of the simulation method according to the first embodiment. In FIG. 1, an information processing apparatus 10 for implementing the simulation method according to the first embodiment is shown. The information processing apparatus 10 can implement the simulation method according to the first embodiment by executing, for example, a simulation program.

[0015] The information processing apparatus 10 has a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or a storage device included in the information processing apparatus 10. The processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing apparatus 10.

[0016] The memory unit 11 stores the simulation condition 1. For example, the simulation condition 1 includes the probability of a physical error. The probability of a physical error is the probability that an error occurs in a data qubit.

[0017] The processing unit 12 performs a simulation of qubit error correction based on simulation condition 1. The processing unit 12 calculates the probability of a logical error occurring in a predetermined qubit error correction scheme through the simulation.

[0018] For example, the processing unit 12 determines the first data qubit that generates an error from among multiple data qubits included in a two-dimensional lattice array in which multiple data qubits and multiple auxiliary qubits are arranged alternately in the row and column directions. The processing unit 12 then generates error patterns 2 to 4 that represent the first data qubit in the two-dimensional lattice array.

[0019] For example, the processing unit 12 uses a random number to determine whether or not to generate an error for each data qubit, based on the physical error probability shown in simulation condition 1. Then, the processing unit 12 generates error patterns 2 to 4, which indicate the data qubits for which it was determined that an error should occur.

[0020] The processing unit 12 determines, for each of the generated error patterns 2 to 4, whether the first data qubits shown in the error patterns 2 to 4 satisfy a predetermined criterion. As a predetermined criterion, for example, a first criterion can be applied in which the number of first data qubits that generate an error is less than or equal to a predetermined value corresponding to the size of the two-dimensional lattice array. The predetermined value corresponding to the size of the two-dimensional lattice array in the first criterion is, for example, half of the value obtained by subtracting 1 from the code distance of the two-dimensional lattice array.

[0021] The code distance is the minimum number of data qubits contained on one side of a two-dimensional grid array. For example, error patterns 2-4 contain 3 data qubits on each vertical side and 4 data qubits on each horizontal side. Therefore, the code distance for error patterns 2-4 is "3". When the code distance is "3", half of the value obtained by subtracting 1 from the code distance is "1".

[0022] Furthermore, a second criterion can be applied as a predetermined criterion: that the maximum number of first data qubits contained in the same row or column of the two-dimensional lattice array is less than or equal to a predetermined value (e.g., "1").

[0023] The processing unit 12 determines that no logical error occurs in an error pattern if the error pattern satisfies the judgment criteria. For example, error pattern 2 has only one first data qubit that generates an error. In this case, the first judgment criterion is satisfied. Therefore, when the first judgment criterion is applied, it is determined that no logical error occurs in quantum error correction for error pattern 2.

[0024] Error pattern 3 has three first data qubits that generate an error. Therefore, the first criterion is not met. On the other hand, all of the first data qubits in error pattern 3 are in different rows and columns. Therefore, the maximum number of first data qubits in the same row or column is "1", and the second criterion is met. When the second criterion is applied, it is determined that no logical error occurs in quantum error correction for error pattern 3.

[0025] Error pattern 4 has two first data qubits that generate an error. Therefore, the first criterion is not met. Also, the first data qubits included in error pattern 4 are in the same row. Therefore, the maximum number of first data qubits in the same row or column is "2", and the second criterion is not met. Even if both the first and second criterions are applied, error pattern 4 does not satisfy the criteria. In this case, it is determined that there is a possibility of a logical error occurring in quantum error correction for error pattern 4.

[0026] If the judgment criteria are not met, the processing unit 12 determines whether a logical error has occurred based on error detection information obtained by inverting the state of an auxiliary qubit adjacent to the first data qubit in the row or column direction, as indicated by the corresponding error pattern. For example, the processing unit 12 searches for a data qubit error pattern that inverts the inverted auxiliary qubit according to a predetermined quantum error correction scheme and identifies the data qubit where the error occurred. The processing unit 12 determines whether a logical error has occurred based on the identified data qubit and the first data qubit. For example, the processing unit 12 determines that a logical error has occurred if the identified data qubit and the first data qubit are continuous from one edge to the opposite edge of a two-dimensional lattice array.

[0027] For example, when an auxiliary qubit is inverted based on error pattern 4, if the data qubit whose state was inverted as an error in error pattern 4 is identified as the error data qubit, then a logical error does not occur. However, if a different data qubit is identified as the one to be inverted based on error pattern 4, then a logical error may occur.

[0028] In this way, by determining whether or not a logical error has occurred for the generated error patterns 2 to 4, the probability of a logical error occurring using a predetermined quantum error correction method can be calculated. Moreover, if error patterns 2 to 4 satisfy the predetermined criteria, the process of identifying the error location based on the inverting auxiliary qubit is omitted for that error pattern. As a result, the number of executions of the error location identification process is reduced. Furthermore, the calculation efficiency of the probability of a logical error occurring when quantum error correction is performed using the predetermined method is improved.

[0029] [Second Embodiment] Next, a second embodiment will be described. The second embodiment is a computer that performs a simulation of error correction using surface codes for randomly occurring errors in a quantum computer (hereinafter referred to as surface code simulation) and efficiently determines whether or not a logical error has occurred.

[0030] Figure 2 shows an example of computer hardware for performing surface code simulation. The computer 100 is controlled by a processor 101. The processor 101 is connected to memory 102 and several peripheral devices via a bus 109. The processor 101 may be a multiprocessor. The processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or a DSP (Digital Signal Processor). At least some of the functions that the processor 101 implements by executing a program may be implemented by electronic circuits such as an ASIC (Application Specific Integrated Circuit) or a PLD (Programmable Logic Device).

[0031] Memory 102 is used as the main memory of the computer 100. Memory 102 temporarily stores at least a portion of the OS (Operating System) programs and application programs that are to be executed by the processor 101. Memory 102 also stores various data used for processing by the processor 101. As memory 102, a volatile semiconductor memory device such as RAM (Random Access Memory) is used.

[0032] Peripheral devices connected to bus 109 include a storage device 103, a GPU (Graphics Processing Unit) 104, an input interface 105, an optical drive device 106, a device connection interface 107, and a network interface 108.

[0033] The storage device 103 electrically or magnetically writes and reads data from its built-in recording medium. The storage device 103 is used as an auxiliary storage device for the computer 100. The storage device 103 stores the OS program, application programs, and various data. For example, the storage device 103 can be an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0034] The GPU104 is a processing unit that performs image processing and is also called a graphics controller. A monitor 21 is connected to the GPU104. The GPU104 displays images on the screen of the monitor 21 according to instructions from the processor 101. The monitor 21 can be a display device using organic EL (Electro Luminescence) or a liquid crystal display device.

[0035] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals from the keyboard 22 and mouse 23 to the processor 101. Note that the mouse 23 is just one example of a pointing device; other pointing devices can also be used. Other pointing devices include touch panels, tablets, touchpads, and trackballs.

[0036] The optical drive device 106 uses laser light or the like to read data recorded on the optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded in a way that makes it readable by the reflection of light. Examples of optical discs 24 include DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), and CD-R (Recordable) / RW (ReWritable).

[0037] The device connection interface 107 is a communication interface for connecting peripheral devices to the computer 100. For example, a memory device 25 and a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a communication function with the device connection interface 107. The memory reader / writer 26 is a device that writes data to or reads data from the memory card 27. The memory card 27 is a card-type recording medium.

[0038] The network interface 108 is connected to the network 20. The network interface 108 transmits and receives data to and from other computers or communication devices via the network 20. The network interface 108 is a wired communication interface, for example, connected by cable to a wired communication device such as a switch or router. Alternatively, the network interface 108 may be a wireless communication interface, connected by radio waves to a wireless communication device such as a base station or access point.

[0039] The computer 100 can implement the processing functions of the second embodiment using the hardware described above. The information processing device 10 shown in the first embodiment can also be implemented using hardware similar to that of the computer 100 shown in Figure 2.

[0040] Computer 100 implements the processing functions of the second embodiment by executing a program recorded on a computer-readable recording medium, for example. A program describing the processing content to be executed by computer 100 can be recorded on various recording media. For example, a program to be executed by computer 100 can be stored in storage device 103. Processor 101 loads at least a portion of the program in storage device 103 into memory 102 and executes the program. Alternatively, a program to be executed by computer 100 can be recorded on a portable recording medium such as an optical disc 24, memory device 25, or memory card 27. A program stored on a portable recording medium becomes executable after being installed in storage device 103, for example, under control from processor 101. Processor 101 can also directly read and execute a program from a portable recording medium.

[0041] Before explaining surface code simulations, we will refer to Figures 3 to 9 to explain error correction using surface codes in quantum computers and the causes of logical errors. Figure 3 shows an example of an error occurring in a qubit. Qubit 31 is affected by various types of noise. These noises include environmental noise, noise during qubit operations, and interference from other qubits. The state of qubit 31 may change unintentionally due to the influence of noise. Such unintentional changes in state are called qubit errors. Errors that occur in qubits include bit inversion errors (X errors) and phase inversion errors (Z errors).

[0042] Current quantum computers have a high probability of errors occurring in qubits due to environmental noise, making it difficult to accurately perform large-scale calculations as is. Therefore, for quantum computers to be practical, it is necessary to be able to perform calculations while correcting errors (quantum error correction). Quantum error correction is a process that maintains the correct state by, for example, making qubits redundant and detecting and correcting errors.

[0043] Figure 4 shows an example of qubit redundancy. When one qubit 31 is made redundant, the quantum state represented by qubit 31 is represented by a logical quantum state represented by logical qubit 32. Logical qubit 32 is composed of multiple qubits 32a to 32h, ...

[0044] Now, let's assume an error occurs in one of the qubits 32h that make up the logical qubit 32. In this case, the error qubit and the error content are identified through a process that identifies the error qubit and the error content.

[0045] If qubit 32h is correctly identified as an error qubit and the nature of the error is also correctly identified, an error correction gate operation is performed on qubit 32h. Error correction corrects the state of logical qubit 32 to the state it would be in if no error occurred.

[0046] In the example in Figure 4, the error qubit is assumed to have been correctly identified, but identifying the error qubit is not easy. Identifying the error qubit requires information about the states of qubits 32a~32h,... that constitute the logical qubit 32, but directly measuring the qubits would destroy their quantum states and prevent the computation from continuing. Therefore, an auxiliary qubit is introduced, and by measuring the state of the auxiliary qubit, information about the states of qubits 32a~32h,... that constitute the logical qubit 32 can be obtained.

[0047] Surface coding is a method for identifying error qubits based on the state of qubits obtained using auxiliary qubits. Surface coding is a representative coding (redundancy) method in quantum error correction.

[0048] Figure 5 shows an example of a qubit configuration for surface coding. In the example in Figure 5, the qubits are arranged in a two-dimensional lattice. The data qubit 40 and auxiliary qubits 41 and 42 are arranged alternately in both the row and column directions. The auxiliary qubits 41 and 42 are divided into auxiliary qubit 41 for X error detection and auxiliary qubit 42 for Z error detection. Then, in each column, the auxiliary qubit 41 for X error detection and the auxiliary qubit 42 for Z error detection are arranged alternately.

[0049] A single logical qubit is constructed using all 40 data qubits. The state of a logical qubit is called its logical quantum state. The number of data qubits on the shorter side of the two-dimensional grid array of qubits that make up a logical qubit is called the code distance.

[0050] The qubits shown in Figure 5 are a portion of the qubits used for error correction using surface codes. When error correction is performed using surface codes, the number of quantum bits on one side of the two-dimensional lattice array containing all the qubits used for error correction (the sum of data qubits and auxiliary qubits) is odd, and data qubits are placed at the four corners (see Figure 9, etc.).

[0051] First, the logical quantum state is properly initialized. During error detection, a gate operation (2-qubit operation) is performed between one auxiliary qubit and the four surrounding data qubits, and the presence or absence of an error can be detected by measuring the auxiliary qubit. Error detection is divided into X error detection using auxiliary qubit 41 for X error detection and Z error detection using auxiliary qubit 42 for Z error detection.

[0052] Figure 6 shows an example of the measurement results of the auxiliary qubits when an error occurs. In the error occurrence pattern 43 shown in Figure 6, a Z error occurs in the two data qubits 40a and 40b. The Z error is detected by the auxiliary qubit for Z error detection. In Figure 6, the auxiliary qubit for X error detection is omitted.

[0053] In quantum error correction using surface codes, a predetermined two-qubit operation is first performed between adjacent data qubits and auxiliary qubits. A two-qubit operation for Z-error detection is performed between the data qubit and the auxiliary qubit for Z-error detection, and a two-qubit operation for X-error detection is performed between the data qubit and the auxiliary qubit for X-error detection.

[0054] A two-qubit operation inverts the states of the auxiliary qubits 42a-42d, which are adjacent to the data qubits 40a and 40b where the Z error occurred, and are used for Z error detection. By measuring the state of all auxiliary qubits after the two-qubit operation, the inversion of auxiliary qubits 42a-42d can be detected. The data showing the measurement results of the auxiliary qubits is called syndrome 44. Syndrome 44 is an example of error detection information shown in the first embodiment.

[0055] In the error correction process, the location of the data qubit where the error occurred is identified based on Syndrome 44. Figure 7 shows an example of error correction using surface codes. When error correction is performed using surface codes, matching of inverted auxiliary qubits is first performed based on syndrome 44. In matching, pairs of inverted auxiliary qubits 42a to 42d are generated. In the example in Figure 7, a pair of auxiliary qubit 42a and auxiliary qubit 42b, and a pair of auxiliary qubit 42c and auxiliary qubit 42d are generated.

[0056] Then, based on the pairs of auxiliary qubits generated by the matching, the error location is identified. That is, for each inverted pair of auxiliary qubits, one or more data qubits are identified that will simultaneously invert the pair if an error occurs in the corresponding data qubit. In the example in Figure 7, based on the pair of auxiliary qubits 42a and 42b, data qubit 40a is identified as the error location. Based on the pair of auxiliary qubits 42c and 42d, data qubit 40b is identified as the error location.

[0057] In this way, the data qubit at the location of the error is identified based on Syndrome 44. This process of identifying the data qubit where such an error occurred is called decoding.

[0058] Furthermore, surface coding has the property that it is not possible to uniquely identify the location of an error. For example, a different error location is identified for each matching candidate of the inverted auxiliary qubit. Therefore, in decoding, for example, the solution with the fewest errors (candidate error location) is identified as the error location.

[0059] Figure 8 shows an example of a case where the location of the error cannot be uniquely identified. In syndrome 44, the states of the four auxiliary qubits 42a to 42d are inverted. Therefore, matching of the four inverted auxiliary qubits 42a to 42d is performed.

[0060] The first matching candidate 51 generates pairs of auxiliary qubits 42a and 42b, and pairs of auxiliary qubits 42c and 42d. If the error location is identified based on these pairs, for example, two data qubits may be identified as the error location.

[0061] The second matching candidate 52 generates pairs of auxiliary qubits 42a and 42c, and pairs of auxiliary qubits 42b and 42d. If the error locations are identified based on these pairs, for example, six data qubits may be identified as error locations.

[0062] The third matching candidate 53 generates pairs of auxiliary qubits 42a and 42d, and pairs of auxiliary qubits 42b and 42c. If the error locations are identified based on these pairs, for example, four data qubits may be identified as error locations.

[0063] In this case, the error locations identified based on the first matching candidate 51 have the fewest occurrences. In other words, it is judged that the error locations identified based on the first matching candidate 51 are most likely to indicate the correct error locations.

[0064] In this way, the error locations are identified in a manner that minimizes the number of error locations. Then, quantum error correction is performed by inverting the state of the data qubits at the identified error locations.

[0065] However, the error locations identified during decoding are only likely to occur, and there is no guarantee that an error actually occurred at those locations. Therefore, in quantum error correction, error correction processing (state inversion) may be performed on incorrect data qubits.

[0066] Figure 9 shows an example of a logical error due to erroneous correction. In the error pattern 61 shown in Figure 9, a Z error occurs in multiple data qubits 61a to 61c on the same row. In this case, the state of auxiliary qubits 61d to 61h adjacent to any of the data qubits 61a to 61c on the same row is inverted.

[0067] When a syndrome is obtained in which the auxiliary qubits 61d to 61h are inverted, two decoding methods are possible: the first decoding example 61-1 and the second decoding example 61-2.

[0068] In the first decoding example 61-1, the data qubits 61a to 61c where the error occurred are correctly identified. If quantum error correction is performed on the data qubits 61a to 61c identified in the first decoding example 61-1, the quantum error correction will be successful.

[0069] On the other hand, in the second decoding example 61-2, data qubits 61i to 61k are identified that are different from the data qubits 61a to 61c in which the error occurred. When error correction is performed on the data qubits 61i to 61k identified in the second decoding example 61-2, the data qubits 61a to 61c and 61i to 61k end up in an inverted state from the correct state. That is, in the second decoding example 61-2, the uncorrected data qubits 61a to 61c and the miscorrected data qubits 61i to 61k are connected from one boundary to the opposite boundary of the two-dimensional lattice array representing a single logical qubit. This state is called a logical error.

[0070] Logical errors alter the logical quantum state. Therefore, continuing the calculation in this state will not yield the correct result. In other words, quantum error correction fails when a logical error occurs. Thus, accurately evaluating logical errors is crucial in evaluating the performance of quantum error correction. For example, when a new quantum error correction method or a new decoding method is developed, the logical error probability is used as a performance evaluation value for that quantum error correction.

[0071] The probability of a logical error can be determined through computer simulation. In other words, with a physical quantum computer, it is impossible to determine whether a logical error has occurred without measuring the data qubit itself, and it is also impossible to determine its frequency. However, with a simulation of error correction using surface codes on a classical computer, the location of the error can be known in advance, making it possible to determine whether or not a logical error has occurred.

[0072] The logical error probability depends on factors such as the code distance and the frequency of errors occurring in the data qubits (physical error probability). Figure 10 shows an example of the relationship between physical error probability and logical error probability. In computer simulations of quantum error correction, a physical error can be generated with an arbitrary physical error probability, and the logical error probability at that time can be calculated.

[0073] For example, in computer simulations, N error patterns (where N is a natural number) are generated, and each one is decoded to obtain a logical error. of We determine the number of occurrences m (a non-negative integer). In this case, the logical error probability P. L P L It can be calculated using the formula "=m / N".

[0074] Graph 62 shows the probability of a physical error p on the horizontal axis and the probability of a logical error P on the vertical axis. L Graph 62 shows line graphs 62a, 62b, and 62c, which represent the logical error probability corresponding to the physical error probability for each code distance. Line graph 62a shows the logical error probability corresponding to the physical error probability when using a logic qubit with a code distance d of "11". Line graph 62b shows the logical error probability corresponding to the physical error probability when using a logic qubit with a code distance d of "21". Line graph 62c shows the logical error probability corresponding to the physical error probability when using a logic qubit with a code distance d of "31".

[0075] The dashed line 62d in Graph 62 indicates the position where the physical error probability and the logical error probability are equal. The further the logical error probability is below the dashed line 62d, the higher the performance of quantum error correction.

[0076] In certain quantum error correction methods, the higher the physical error probability, the higher the logical error probability. Also, the higher the code distance, the better the performance of quantum error correction. Different quantum error correction methods result in different line graphs showing the logical error probability in relation to the physical error probability. Therefore, computer simulations are used to calculate the logical error probability in relation to the physical error probability for each quantum error correction method and evaluate its performance. To accurately evaluate performance, it is necessary to generate a sufficiently large number of error patterns. For example, the number of error patterns N used in computer simulations to evaluate the performance of quantum error correction is generally between 10,000 and 1,000,000.

[0077] In computer simulations to calculate the probability of logical errors, decoding calculations are performed for each physical error pattern, resulting in a large number of decoding operations. In particular, when the probability of physical errors is small and the code distance is large, logical errors are rare events, so the number of error pattern samples required for accurate performance evaluation becomes enormous, and the time required to calculate the probability of logical errors becomes extremely long.

[0078] Therefore, techniques to reduce computational complexity are needed. In the calculation of the logical error probability for quantum error correction, decoding calculations account for a large proportion. In decoding, all matching candidates, as shown in Figure 8, are searched based on syndromes corresponding to the error pattern, and then the error location in each matching candidate is searched. As the code distance increases, the search space also expands, and the computational complexity increases.

[0079] Therefore, computer 100 omits decoding of error patterns that it estimates will not result in logical errors. For example, if the number of physical errors is very small compared to the code distance, logical errors will hardly occur.

[0080] Figure 11 shows an example of an error pattern. Error pattern 71 shows the positions on a two-dimensional array of physical qubits that have been inverted by a Z error, among the physical qubits that constitute a logical qubit with a code distance of 11 (d=11). In error pattern 71, there are two inverted data qubits. That is, the number of errors is "2". The auxiliary qubits adjacent to the inverted data qubits are also inverted. In cases like error pattern 71, the probability of a logical error occurring during decoding is extremely low.

[0081] Computer 100 improves the efficiency of calculating logical error probabilities by omitting decoding when it can be estimated that a logical error like the one shown in error pattern 71 will not occur. Specifically, computer 100 defines criteria for omitting decoding, and determines that error patterns that satisfy these criteria have an extremely low probability of logical error occurring, and omits the decoding calculation for those error patterns.

[0082] Figure 12 is a block diagram showing the functions of a computer for performing surface code simulation. The computer 100 includes a storage unit 110, a simulation management unit 120, an error pattern generation unit 130, a decoding omission determination unit 140, a decoding unit 150, and a logical error determination unit 160.

[0083] The memory unit 110 stores the simulation conditions 111 and the simulation results 112. The simulation conditions 111 are conditions such as the number of error patterns generated, the code distance, and the probability of physical errors. If a quantum error correction method (program) is provided, the specification of the method to be applied is included in the simulation conditions 111. The simulation results 112 are information that shows the results of the quantum error correction simulation. For example, the simulation results 112 include the probability of logical errors when quantum error correction is performed under the corresponding conditions, associated with information such as the quantum error correction method, the code distance, and the probability of physical errors.

[0084] The simulation management unit 120 manages the simulation of quantum error correction using surface codes. For example, the simulation management unit 120 instructs the error pattern generation unit 130 to generate error patterns according to the simulation conditions 111. The simulation management unit 120 also obtains the logic error determination result for each error pattern from the logic error determination unit 160 and calculates the logic error probability. The simulation management unit 120 then stores the calculated logic error probability as the simulation result 112 in the storage unit 110.

[0085] The error pattern generation unit 130 uses the simulation conditions 111 For data qubits with the code distance shown, the simulation conditions 111 An error pattern is generated by creating an error with the physical error probability shown. The error pattern generation unit 130 transmits the generated error pattern to the decoding omission determination unit 140.

[0086] The decoding omission determination unit 140 determines whether or not to omit decoding for the error pattern generated by the error pattern generation unit 130. For example, the decoding omission determination unit 140 compares the error pattern with predetermined criteria and determines to omit decoding if the criteria are met. If the decoding omission determination unit 140 determines to omit decoding, it notifies the logical error determination unit 160 that decoding has been omitted. If the decoding omission determination unit 140 determines not to omit decoding, it instructs the decoding unit 150 to decode.

[0087] The decoding unit 150 performs decoding based on a syndrome corresponding to the generated error pattern, in response to a decoding instruction. Decoding involves, for example, generating a syndrome, matching the inverted auxiliary qubits, generating a solution indicating the error location based on the matching result, and identifying the most likely solution. The finally identified solution becomes the decoding result, indicating the data qubit estimated to be the location of the error.

[0088] The logic error determination unit 160 determines whether or not a logic error has occurred based on the error pattern and the decoding result. The logic error determination unit 160 notifies the simulation management unit 120 of the result of determining whether or not a logic error has occurred.

[0089] Furthermore, the functions of each element shown in Figure 12 can be realized, for example, by having a computer execute the program module corresponding to that element. In this way, the decoding omission determination unit 140 determines whether or not to omit decoding, and performs decoding only if it determines that decoding should not be omitted, thereby streamlining the calculation of the quantum error probability. The following criteria can be considered as examples of criteria for determining whether or not to omit decoding. • First criterion: The number of errors n1 is less than or equal to (d-1) / 2. • Second criterion: The maximum number of errors n2 in the same row or column of the grid is 1 or less. The first criterion is based on the fact that for a logical error to occur due to incorrect decoding, there must be more physical errors than (d-1) / 2. For example, in the example shown in Figure 9, the number of data qubits in the row direction is "6". If the number of data qubits in the column direction is also "6", then the code distance d is "6". A logical error occurs when data qubits remain inverted even after quantum error correction, as in the second decoding example 61-2 shown in Figure 9 (error). Uncorrected This occurs when the data qubits (both the original data qubit and the data qubit that is incorrectly corrected) are continuous from one edge to the opposite edge. Therefore, for a logical error to occur, at least 6 data qubits must remain inverted even after quantum error correction. If the number of data qubits inverted due to the error is 2.5 (=(6-1) / 2) or less, the probability of 4 or more data qubits being identified as errors during decoding is extremely low. From this, it can be concluded that the possibility of a logical error is low if the first criterion is met.

[0090] The second criterion is based on the fact that even if the number of errors n1 exceeds (d-1) / 2, if the errors are distributed, the likelihood of a logical error is low. In other words, if there is one or fewer erroneous data qubits in each row or column of a two-dimensional lattice array, the likelihood of so many consecutive data qubits remaining inverted after quantum error correction resulting in a logical error is very low.

[0091] Figure 13 shows an example of determining whether or not decoding is omitted. In the example in Figure 13, the code distance d is "11". In this case, "(d-1) / 2" in the first criterion is "5".

[0092] The number of errors n1 in error pattern 72 is "2". Since the number of errors n1 is less than or equal to "(d-1) / 2", error pattern 72 satisfies the first criterion. Also, the maximum number of errors n2 in the same row or column of the data qubits where the errors occurred in error pattern 72 is "1". Therefore, error pattern 72 also satisfies the second criterion. Since error pattern 72 satisfies both the first and second criteria, the decoding process for error pattern 72 is omitted.

[0093] The number of errors n1 in error pattern 73 is "10". Since the number of errors n1 is greater than "(d-1) / 2", error pattern 73 does not satisfy the first criterion. Also, the maximum number of errors n2 in the same row or column of the data qubits where errors occurred in error pattern 73 is "1". Therefore, error pattern 73 satisfies the second criterion. Since error pattern 73 does not satisfy the first criterion but satisfies the second criterion, the decoding process for error pattern 73 is omitted.

[0094] The number of errors n1 in error pattern 74 is "6". Since the number of errors n1 is greater than "(d-1) / 2", error pattern 74 does not satisfy the first criterion. Also, the maximum number of errors n2 in the same row or column of the data qubits where the errors occurred in error pattern 74 is "6". Therefore, error pattern 74 also does not satisfy the second criterion. Since error pattern 74 does not satisfy either the first or second criterion, the decoding process for error pattern 74 is performed.

[0095] Next, we will explain the procedure for calculating the logical error probability of a Z error. Figure 14 is a flowchart showing an example of the procedure for calculating the probability of a logical error (Z error). The process shown in Figure 14 will be explained below according to the step numbers.

[0096] [Step S101] When the simulation management unit 120 receives an instruction to calculate the quantum error probability for a predetermined quantum error correction method, it initializes the number of logical errors m to "0" (m=0).

[0097] [Step S102] The simulation management unit 120 creates row number data R for the data qubits. The row number data R is an array of size Nd, where Nd is the number of data qubits. For example, the row number of the k-th data qubit (where k is an integer from 1 to Nd) is set as the value of the array index k in the row number data R.

[0098] [Step S103] The error pattern generation unit 130 repeats the process in steps S104 to S105 until the variable i, which indicates the loop count, becomes 1 to N. N is an integer indicating the number of error patterns generated.

[0099] [Step S104] The error pattern generation unit 130 creates error pattern data EZ for the Z error of the data qubit using random numbers. The error pattern data EZ is an array of size Nd. If a Z error occurs in the k-th data qubit, the value of the array with index k is set to "1". If no error occurs in the k-th data qubit (where k is an integer from 1 to Nd), the value of the array with index k is set to "0".

[0100] For example, the error pattern generation unit 130 generates a random number (a real number between 0 and 1) for each data qubit. If the physical error probability is "a" (where a is a real number between 0 and 1), the error pattern generation unit 130 decides to generate an error in the corresponding data qubit if the generated random number is less than or equal to a.

[0101] [Step S105] The decoding omission determination unit 140, the decoding unit 150, and the logical error determination unit 160 work in coordination to execute the logical error occurrence determination process. If a logical error occurs in the error pattern shown in the generated error pattern data EZ as a result of the logical error occurrence determination process, the number of logical errors m is incremented. Details of the logical error occurrence determination process will be described later (see Figure 15).

[0102] [Step S106] If the loop variable i reaches N, the error pattern generation unit 130 proceeds to step S107. [Step S107] The simulation management unit 120 calculates the logical error probability. The logical error probability is obtained by dividing the number of logical errors m by the number of error patterns generated N.

[0103] In this way, the probability of a logical error can be calculated. Next, Z error The logic error detection process will be explained in detail. Figure 15 is a flowchart detailing the procedure for determining the occurrence of a logical error (Z error). The process shown in Figure 15 will be explained below according to the step numbers.

[0104] [Step S121] The decoding omission determination unit 140 sums the values ​​of the error pattern data EZ. The decoding omission determination unit 140 sets the summed result as n1. [Step S122] The decoding omission determination unit 140 uses the row number data R to sum the values ​​of the error pattern data EZ for each row. For example, the decoding omission determination unit 140 counts the number of data qubits that have the same row number set in the row number data R and that have the error value "1" set in the error pattern data EZ. The decoding omission determination unit 140 sets the maximum number of data qubits counted for each row to n2.

[0105] [Step S123] The decoding omission determination unit 140 determines whether either the first or second determination criterion is met. For example, the decoding omission determination unit 140 determines that the first determination criterion is satisfied if "n1 ≤ (d-1) / 2". The decoding omission determination unit 140 also determines that the second determination criterion is satisfied if "n2 ≤ 1". If at least one of the determination criteria is satisfied, the decoding omission determination unit 140 determines that no logical error has occurred and terminates the logical error occurrence determination process. If neither of the determination criteria is satisfied, the decoding omission determination unit 140 proceeds to step S124.

[0106] [Step S124] The decoding unit 150 decodes the generated error pattern. For example, based on the error pattern data EZ, the decoding unit 150 inverts the state of the auxiliary qubit adjacent to the data qubit where the Z error occurred. Next, based on the arrangement (syndrome) of the inverted auxiliary qubits, the decoding unit 150 identifies the data qubit to be identified as an error based on a predetermined quantum error correction scheme.

[0107] [Step S125] The logic error determination unit 160 determines whether or not a logic error has occurred. For example, the logic error determination unit 160 identifies data qubits that have been reversed from their correct state when error correction (state inversion) is performed on data qubits identified as errors. Data qubits that have been reversed from their correct state are data qubits that have had an error but have not been corrected, and data qubits that have not had an error but have been corrected as if an error had occurred. The logic error determination unit 160 determines that a logic error has occurred if the data qubits that have been reversed from their correct state are continuous from one side to the opposite side of the two-dimensional array of qubits that constitute the logic qubit.

[0108] The logic error determination unit 160 proceeds to step S126 if a logic error occurs. If no logic error occurs, the logic error determination unit 160 terminates the logic error occurrence determination process.

[0109] [Step S126] The logic error determination unit 160 adds "1" to the number of logical errors m. In this way, the logical error probability for Z errors can be calculated. Similarly, the logical error probability for X errors can also be calculated.

[0110] Figure 16 is a flowchart showing an example of the procedure for calculating the probability of a logical error (X error). The process shown in Figure 16 will be explained below according to the step numbers. [Step S201] When the simulation management unit 120 receives an instruction to calculate the quantum error probability for a predetermined quantum error correction method, it initializes the number of logical errors m to "0" (m=0).

[0111] [Step S202] The simulation management unit 120 creates data qubit column number data C. The column number data C is an array of size Nd. For example, the column number of the k-th data qubit (where k is an integer from 1 to Nd) is set as the value of the array index k in the column number data C.

[0112] [Step S203] The error pattern generation unit 130 repeats the process in steps S204 to S205 until the variable i, which indicates the loop count, becomes 1 to N. [Step S204] The error pattern generation unit 130 uses random numbers to create error pattern data EX for X errors of data qubits. The error pattern data EX is an array of size Nd. When an X error is generated in the k-th data qubit, the value of the array with index k is set to "1".

[0113] [Step S205] The decoding omission determination unit 140, the decoding unit 150, and the logical error determination unit 160 work in coordination to execute the logical error occurrence determination process. If a logical error occurs in the error pattern shown in the generated error pattern data EX as a result of the logical error occurrence determination process, the number of logical errors m is incremented. Details of the logical error occurrence determination process will be described later (see Figure 17).

[0114] [Step S206] If the loop variable i reaches N, the error pattern generation unit 130 proceeds to step S207. [Step S207] The simulation management unit 120 calculates the logical error probability. The logical error probability is obtained by dividing the number of logical errors m by the number of error patterns generated N.

[0115] In this way, the probability of a logical error can be calculated. Next, we will explain in detail the logical error determination process for X errors. Figure 17 is a flowchart detailing the procedure for determining the occurrence of a logical error (X error). The process shown in Figure 17 will be explained below according to the step numbers.

[0116] [Step S221] The decoding omission determination unit 140 sums the values ​​of the error pattern data EX. The decoding omission determination unit 140 sets the summed result as n1. [Step S222] The decoding omission determination unit 140 uses the column number data C to sum the values ​​of the error pattern data EX for each column. For example, the decoding omission determination unit 140 counts the number of data qubits that have the same column number set in the column number data C and that have the error value "1" set in the error pattern data EX. The decoding omission determination unit 140 sets the maximum number of data qubits counted for each column to n2.

[0117] [Step S223] The decoding omission determination unit 140 determines whether either the first determination criterion or the second determination criterion is met. If at least one of the determination criteria is met, the decoding omission determination unit 140 determines that no logical error has occurred and terminates the logical error occurrence determination process. If neither of the determination criteria is met, the decoding omission determination unit 140 proceeds to step S224.

[0118] [Step S224] The decoding unit 150 decodes the generated error pattern. For example, based on the error pattern data EX, the decoding unit 150 inverts the state of the auxiliary qubit adjacent to the data qubit where the X error occurred. Next, based on the arrangement (syndrome) of the inverted auxiliary qubits, the decoding unit 150 identifies the data qubit to be identified as an error based on a predetermined quantum error correction scheme.

[0119] [Step S225] The logical error determination unit 160 determines whether or not a logical error has occurred. If a logical error occurs, the logical error determination unit 160 proceeds to step S226. If no logical error occurs, the logical error determination unit 160 terminates the logical error occurrence determination process.

[0120] [Step S226] The logical error determination unit 160 adds "1" to the number of logical errors m. In this way, the quantum error probability can also be calculated for X errors. By calculating the quantum error probabilities for Z errors and X errors, the accuracy of the quantum error correction scheme applied to decoding can be quantitatively evaluated. Moreover, since decoding is omitted for error patterns with a low probability of becoming quantum errors, the logical error probability can be calculated efficiently.

[0121] The following will specifically explain the difference in computation time between the quantum error probability calculation method that omits decoding based on the first and second criteria (partial decoding omission method) and other quantum error probability calculation methods.

[0122] The following three quantum error probability calculation methods are being compared: Brute Force (BF): Simple sampling Importance Sampling (ISA) Importance Splitting (ISP) BF generates a predetermined number of error patterns without considering processing efficiency, decodes all error patterns, and calculates the logical error probability based on the decoding results. ISA is a method that focuses on sampling rare events.

[0123] In ISA, rare error patterns are generated with particular emphasis. Details of ISA are described in "J. Geweke, "Bayesian Inference in Econometric Models Using Monte Carlo Integration", Econometrica, Vol. 57, No. 6, November 1989, pp. 1317-1339".

[0124] ISP is a method for extrapolating probabilities in ranges that are difficult to sample. Details of ISP are described in "M. Garvels and D. Kroese, "A comparison of RESTART implementations", WSC '98: Proceedings of the 30th conference on Winter simulation, December 1998, Pages 601-608".

[0125] Figures 18 and 19 show the results of measuring the computation time and number of decoding attempts required to calculate the logical error probability with a certain level of accuracy using each logical error probability calculation method. The accuracy standard is defined as being within the 95% confidence interval of the logical error probability calculated by BF. The least weighted perfect matching (MWPM) algorithm was used as the decoding method.

[0126] Other simulation conditions are a code distance d=11 and physical error probabilities p=1,2,4,6,8%. The BF sample size is 10 million. The sample size in the partially decoded omission method is the number required to meet the above accuracy criteria and varies depending on the physical error probability p.

[0127] Figure 18 shows an example of the measurement results for computation time. The computation time comparison table 81 shows the computation time for each physical error probability for the partially decrypted method, BF, and ISA. For ISA, the calculation time shown is for one set of calculations, as the logical error probability for any physical error probability can be calculated in a single set of calculations. Note that ISP was excluded from the computation time comparison because sufficient calculation accuracy could not be obtained under the condition of physical error probability p ≥ 1.

[0128] As shown in the calculation time comparison table 81, the calculation time for the partially decrypted method is reduced to 1 / 6 at p=1% and to 1 / 10 at p=2% compared to BF. Furthermore, the calculation time for the partially decrypted method is less than 1 / 4 compared to ISA.

[0129] Figure 19 shows an example of the counting results for the number of decryption attempts. The decryption attempt comparison table 82 shows the calculation time for each physical error probability for the partial decryption omission method, BF, and ISA. Since ISA can calculate the logical error probability for any physical error probability in one set of calculations, the number of decryption attempts shown is for that one set. Note that ISP was excluded from the comparison of decryption attempts because sufficient calculation accuracy could not be obtained under the condition that the physical error probability p ≥ 1.

[0130] According to the Decoding Count Comparison Table 82, the decoding count for the partially decoding omission method is less than 1 / 10 of that for all physical error probabilities p compared to BF. Furthermore, the decoding count for the partially decoding omission method is less than 1 / 3 of that for ISA.

[0131] By applying this partial decoding omission method, the computational complexity is reduced, resulting in shorter computation times. Furthermore, even if decoding is omitted for error patterns with a low probability of becoming quantum errors, the reduction in the accuracy of the logical error probability calculation is minimal.

[0132] Figure 20 shows an example of the calculation results for the logical error probability. The logical error probability comparison table 83 shows the logical error probability for each physical error probability for the partial decoding omission method and BF. The logical error probabilities shown in the logical error probability comparison table 83 are the average values ​​of the logical error probabilities when calculations for 10 million samples are performed three times. As shown in the logical error probability comparison table 83, the error in the logical error probability of the partial decoding omission method is minute when the logical error probability of BF is assumed to be correct.

[0133] In the partial decryption omission method, if the error pattern satisfies predetermined criteria, decryption is omitted. However, for some criteria, even if the criteria are satisfied, there remains a slight possibility that the decryption will result in a logical error.

[0134] Figure 21 shows the occurrence of a logical error when the judgment criteria are met. Number of times This figure shows an example. Table 84 of the number of logical errors shows the number of occurrences of error patterns that satisfy each criterion, and the number of logical errors m when the criterion is satisfied. The number of logical errors m when the criterion is satisfied is a value counted by determining whether or not a logical error has occurred without omitting decoding even when the criterion is satisfied.

[0135] If the first criterion is met, no logical error will occur even if decryption is performed. If the second criterion is met, a small logical error will occur if the probability of a physical error is 4% or higher. of The number of logical errors m when only one of the conditions is met will be the same as the value when the second criterion is met.

[0136] In the Logical Error Occurrence Count Table 84, the "total" occurrence count represents the total number of error patterns generated that are subject to quantum error correction. The "total" logical error occurrence count m represents the number of logical errors among all error patterns, including those that do not meet the judgment criteria.

[0137] Thus, even if the first criterion is applied to omit decoding, the occurrence of a logical error will not be overlooked. Furthermore, if the second criterion is applied to omit decoding, a logical error may be overlooked if the physical error probability p is 4% or higher, but this is an extremely small number compared to the total number of logical errors. Therefore, the reduction in the calculation accuracy of the logical error probability due to applying the second criterion is small.

[0138] [Other embodiments] In the second embodiment, the calculation of the logical error probability for Z errors and the calculation of the logical error probability for X errors are described separately, but these calculation processes may be performed consecutively.

[0139] Furthermore, depending on the required calculation precision for the logical error probability, it may be possible to relax either the first or second criterion. For example, if the code distance is sufficiently large and the required calculation precision is not strict, it may be possible to relax the upper limit of the maximum number of errors in the same row or column in the second criterion from "1" to "2". That is .

[0140] The above merely illustrates the principle of the present invention. Furthermore, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and applications shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and their equivalents. [Explanation of Symbols]

[0141] 1. Simulation conditions 2-4 Error Patterns 10 Information Processing Devices 11 Storage section 12 Processing Units

Claims

1. An error pattern is generated that indicates a first data qubit that generates an error among the multiple data qubits included in a two-dimensional lattice array in which multiple data qubits and multiple auxiliary qubits are alternately arranged in the row and column directions, respectively. Determine whether the first data qubit shown in the error pattern satisfies a predetermined criterion. If the above criteria are met, it is determined that no logical error occurs in the error pattern. If the above criteria are not met, the presence or absence of a logical error is determined based on error detection information obtained by inverting the state of an auxiliary qubit adjacent to the first data qubit shown in the error pattern in the row or column direction. A simulation program that causes a computer to perform a process.

2. In the process of determining whether the aforementioned criteria are met, it is determined whether the first criterion is met, namely that the number of the first data qubits is less than or equal to a value corresponding to the size of the two-dimensional lattice array. The simulation program according to claim 1.

3. In the process of determining whether the above criteria are met, half of the value obtained by subtracting 1 from the minimum number of data qubits contained in one side of the two-dimensional lattice array is set as a value corresponding to the size of the two-dimensional lattice array. The simulation program according to claim 2.

4. In the process of determining whether the aforementioned criteria are met, it is determined whether the second criterion is met, which is that the maximum number of the first data qubits included in the same row or column of the two-dimensional grid array is less than or equal to a predetermined value. A simulation program according to any one of claims 1 to 3.

5. An error pattern is generated that indicates a first data qubit that generates an error among the multiple data qubits included in a two-dimensional lattice array in which multiple data qubits and multiple auxiliary qubits are alternately arranged in the row and column directions, respectively. It is determined whether the first data qubit shown in the error pattern satisfies a predetermined criterion. If the above criteria are met, it is determined that no logical error occurs in the error pattern. If the above criteria are not met, the presence or absence of a logical error is determined based on error detection information obtained by inverting the state of an auxiliary qubit adjacent to the first data qubit shown in the error pattern in the row or column direction. A simulation method in which a computer performs a process.

6. A processing unit generates an error pattern indicating a first data qubit that generates an error among a plurality of data qubits included in a two-dimensional lattice array in which a plurality of data qubits and a plurality of auxiliary qubits are alternately arranged in the row and column directions, respectively; determines whether the first data qubit indicated in the error pattern satisfies a predetermined judgment criterion; if the judgment criterion is met, determines that no logical error occurs in the error pattern; if the judgment criterion is not met, determines whether or not a logical error has occurred based on error detection information obtained by inverting the state of an auxiliary qubit adjacent to the first data qubit indicated in the error pattern in the row or column direction. An information processing device having

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