Resistive random-access memory device with engineered electronic defects and method for manufacturing the same

Abstract

The present disclosure relates to a resistive random access memory (RRAM) device. A method for fabricating a resistive random access memory (RRAM) device can include fabricating a first interface layer on a first electrode of the RRAM device, the first interface layer including a first discontinuous film of a first material, fabricating a switching oxide layer on the first interface layer including at least one transition metal oxide, fabricating a second interface layer on the switching oxide layer, and fabricating a defect engineering layer on the second interface layer. The first material is more chemically stable than the at least one transition metal oxide. The defect engineering layer, in some embodiments, includes a layer of Ti.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefit of U.S. Patent Application No. 17 / 454,914, filed on November 15, 2021, titled "Resistive Random-Access Memory Devices with Multi-Component Electrodes and Discontinuous Interface Layers," and applies to U.S. Patent Application No. 17 / 658,641, filed on April 8, 2022, titled "Resistive Random-Access Memory Devices with Engineered Electronic Defects and Methods for Making the Same." U.S. Patent Application No. 17 / 319,057, filed on May 12, 2021, entitled "Resistive Random-Access Memory Devices with Multi-Component Electrodes,"This invention claims the interests of PCT application PCT / US21 / 40389, filed on July 3, 2021, entitled "Resistive Random-Access Memory Devices with Multi-Component Electrodes," and U.S. Patent Application 16 / 921,926, filed on July 6, 2020, entitled "Low Current RRAM-Based Crossbar Array Circuits Implemented with Interface Engineering Technologies," the entire disclosures of which are incorporated herein by reference.

[0002] The implementations of this disclosure generally relate to resistive random-access memory (RRAM) devices, and more specifically to RRAM devices with engineering electronic defects and methods for fabricating them. [Background technology]

[0003] A resistive random-access memory (RRAM) device is a two-terminal passive device with a tunable non-volatile resistor. The resistor in the RRAM device can be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS) by applying an appropriate programming signal to the RRAM device. RRAM devices can be used to form crossbar arrays, which can then be used to implement in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, and the like. [Overview of the project] [Means for solving the problem]

[0004] The following is a brief overview of the Disclosure to provide a basic understanding of some aspects of the Disclosure. This overview is not a comprehensive overview of the Disclosure. It is not intended to identify any key or important elements of the Disclosure, nor to delineate all aspects of any particular implementation of the Disclosure or all aspects of any claim. Its sole purpose is to provide some concepts of the Disclosure in a simplified form as an introduction to the more detailed explanations that will follow.

[0005] One or more aspects of the present disclosure provide a method for fabricating a resistive random-access memory (RRAM) device. The method includes: fabricating a first interface layer on a first electrode of the RRAM device, comprising a first discontinuous film of a first material; fabricating a switching oxide layer on the first interface layer, comprising at least one transition metal oxide; fabricating a second interface layer on the switching oxide layer, comprising a second discontinuous film of a second material; and fabricating a defect engineering layer on the second interface layer for generating electronic defects within the switching oxide layer. The first material and the second material are chemically more stable than the at least one transition metal oxide.

[0006] In some embodiments, the at least one transition metal oxide is HfO x or TaO y It includes at least one of the following, and x ≤ 2.0 and y ≤ 2.5.

[0007] In some embodiments, the first material comprises at least one of Al2O3, MgO, Y2O3, or La2O3.

[0008] In some embodiments, fabricating the first interface layer on the first electrode of the RRAM apparatus, which includes the first discontinuous film of the first material, involves depositing the first material on the first electrode to form the first discontinuous film.

[0009] In some embodiments, the thickness of the first interface layer is between 0.2 nm and 1 nm.

[0010] In some embodiments, the second material includes at least one of at least one of Al2O3, MgO, Y2O3, or La2O3.

[0011] In some embodiments, fabricating the defect engineering layer on the second interface layer includes fabricating a first layer of a first metal material and fabricating a second layer of a second metal material on the first layer of the first metal material.

[0012] In some embodiments, the first material is chemically more stable than the at least one transition metal oxide. The first material is chemically more stable than the oxide of the first metal material.

[0013] In some embodiments, the first metal material includes at least one of at least one of Ti, Hf, or Zr.

[0014] In some embodiments, the second metal material includes tantalum.

[0015] In some embodiments, fabricating the first layer of the first metal material includes depositing a layer of Ti on the second interface layer.

[0016] In some embodiments, the second layer of the second metal material includes one or more alloys containing tantalum.

[0017] In some embodiments, the defect engineering layer includes one or more alloys containing tantalum.

[0018] In some embodiments, the tantalum-containing alloy further comprises at least one of at least one of hafnium, molybdenum, tungsten, niobium, or zirconium.

[0019] In some embodiments, the one or more alloys containing tantalum include at least one of at least one of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a pentary alloy containing tantalum, a hexary alloy containing tantalum, or a higher-order alloy containing tantalum.

[0020] In some embodiments, the thickness of the first layer containing the first metal material is between 0.2 nm and 5 nm.

[0021] In some embodiments, the defect engineering layer is in contact with at least a portion of the switching oxide layer.

[0022] This disclosure will be better understood from the detailed description provided below and from the accompanying drawings of various embodiments of this disclosure. However, the drawings are for illustrative and illustrative purposes only and should not be construed as limiting this disclosure to any particular embodiment. [Brief explanation of the drawing]

[0023] [Figure 1] This is a schematic diagram illustrating an example of a crossbar circuit according to some implementations of the present disclosure. [Figure 2] This is a schematic diagram illustrating an example of a crosspoint device according to some implementations of this disclosure. [Figure 3A] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 3B] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 3C] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 4A] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 4B] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 4C] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 4D] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 4E] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 4F] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 5A] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 5B] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 5C] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 5D] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 6A] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 6B] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 6C] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 6D] A cross-sectional view of an example of an RRAM device according to some embodiments of this disclosure is described below. [Figure 7] This is a schematic diagram illustrating a cross-sectional view of the upper electrode of an RRAM device according to some embodiments of the present disclosure. [Figure 8] This graph illustrates the chemical stability of metal oxides according to some embodiments of the present disclosure. [Figure 9]This is a binary phase diagram of tantalum-titanium (Ta-Ti) according to some embodiments of the present disclosure. [Figure 10] This is a flowchart illustrating a method for fabricating an RRAM device according to some embodiments of the present disclosure. [Figure 11] This is a flowchart illustrating a method for fabricating an RRAM device according to some embodiments of the present disclosure. [Figure 12] This is a flowchart illustrating a method for fabricating an RRAM device according to some embodiments of the present disclosure. [Figure 13] This is a flowchart illustrating a method for fabricating a defect engineering layer to generate electronic defects in the switching oxide layer of an RRAM device according to some embodiments of the present disclosure. [Figure 14A] This is a binary phase diagram of tantalum hafnium (Ta-Hf) according to some embodiments of the present disclosure. [Figure 14B] This is a binary phase diagram of tantalum-tungsten (Ta-W) according to some embodiments of the present disclosure. [Figure 14C] This is a binary phase diagram of tantalum-molybdenum (Ta-Mo) according to some embodiments of the present disclosure. [Figure 14D] This is a binary state diagram of tantalumniobium (Ta-Nb) according to some embodiments of the present disclosure. [Figure 14E] This is a binary phase diagram of tantalum zirconium (Ta-Zr) according to some embodiments of the present disclosure. [Figure 15A] This graph illustrates the current-voltage characteristics of an example RRAM device according to some embodiments of the present disclosure. [Figure 15B] This graph illustrates the current-voltage characteristics of an example RRAM device according to some embodiments of the present disclosure. [Figure 15C] This graph illustrates the current-voltage characteristics of an example RRAM device according to some embodiments of the present disclosure. [Figure 15D]This graph illustrates the current-voltage characteristics of an example RRAM device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0024] Aspects of this disclosure provide resistive random-access memory (RRAM) devices and methods for manufacturing RRAM devices. The RRAM device is a two-terminal passive device with adjustable resistors. The RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first and second electrodes. The first electrode may include a non-reactive metal such as platinum (Pt) or palladium (Pd). The second electrode may include a reactive metal such as tantalum (Ta). Electrodes containing non-reactive metals may also be referred to here as "non-reactive electrodes." Electrodes containing reactive metals may also be referred to here as "reactive electrodes." The switching oxide layer may include hafnium oxide (HfO). x ) or tantalum oxide (TaO xThis may include transition metal oxides such as .RRAM devices can be in an initial or unused state before receiving appropriate electrical stimulation (e.g., a voltage or current signal applied to the RRAM device) and may have an initial high resistance. RRAM devices can be adjusted from an unused state to a low resistance state via a formation process, or from a high resistance state (HRS) to a low resistance state (LRS) via a setting process. The formation process can be described as programming the device to start from an unused state. The setting process can be described as programming the device to start from a high resistance state (HRS). After the reactive metal electrode is deposited on the transition oxide, the reactive metal can absorb oxygen from the transition oxide layer to create oxygen vacancies within the transition oxide layer, and oxygen ions can move into the transition oxide through a vacancy mechanism. During the formation process, appropriate programming signals (e.g., voltage or current signals) can be applied to the RRAM device, which can cause oxygen ions to drift from the transition oxide to the reactive electrode. As a result, conductive channels or filaments can be formed through the transition oxide layer (e.g., from the reactive electrode to the non-reactive electrode). Subsequently, the RRAM device can be reset to a high-resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device. Applying a reset signal to the RRAM device can move oxygen back to the switching oxide layer, thus interrupting the conductive filament. The RRAM device can be electrically switched between a high-resistance state and a low-resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device. In the case of a crossbar array circuit, a programming signal can be provided to a specified RRAM device via a selector such as a transistor.

[0025] When a conductive channel or filament is formed through the switching oxide (for example, from the reactive electrode to the non-reactive electrode), the RRAM device is considered to be operating in filament mode. When a suspended filament is formed within the switching oxide layer of the RRAM device, the RRAM device is considered to be operating in non-filament mode. A gap may exist between the suspended filament and the lower electrode of the RRAM device.

[0026] According to the concept of quantum conductance, the electrical conductivity of a material is observed to change at discrete or quantized levels. The unit of quantum conductance is Go = 2e 2 / h = 7.748E-5 Siemens (or 12.9 kΩ), where e is the electron charge and h is Planck's constant. The minimum quantum conductance occurs when two metal atoms form point contact, and this can be considered the minimum conductance (or maximum resistance) of a metal filament. In other words, the minimum conductance or maximum resistance in filament mode is limited to Go (7.74E-5 Siemens, or 12.9 kΩ). However, the implementation of certain applications (e.g., IMC applications) may require RRAM devices with high resistance, such as resistances higher than Go. This may require operating the RRAM device in non-filament mode to achieve such high resistances. Thus, the electron conduction properties in devices with high resistance are semiconducting rather than metallic. However, most RRAM devices only exhibit certain desired characteristics (e.g., analog resistance, multi-level resistance, linearity, etc.) when operating in filament mode. In filament mode, electrical conduction within an RRAM device can be dominated by conduction through the filament, while conduction through the switching oxide is negligible. This is because the conduction band and balance band of the metal overlap, allowing electrons to move easily between atoms. However, in semiconductors, an energy gap (or band gap) exists between the conduction band and the balance band. For electrons to move from the balance band to the conduction band in a semiconductor and enable interatomic movement, they must overcome this band gap. Electron defects in the switching oxide layer of an RRAM device can have energy between the balance band and the conduction band, trapping electrons that can be easily excited to the conduction band or hop from one trap site to another. Therefore, to implement the operation of a device using an RRAM device in non-filament mode with high resistance, electron defects in the switching oxide can be important, and electrical conduction within the switching oxide, where the filament can be interrupted, can be dominated by electron defects.Therefore, it may be desirable to perform electron defect engineering and control within the switching oxide of RRAM devices to achieve specific electronic behaviors crucial for IMC applications such as analog resistance, multi-level resistance, and IV (current-voltage) linearity.

[0027] Furthermore, it may be desirable to miniaturize RRAM devices to appropriate sizes (e.g., critical dimensions of 100 nm, 10 nm, or smaller) to implement certain in-memory computing (IMC) applications (e.g., high-density RRAM devices and / or IMC applications requiring low power consumption). However, conventional RRAM devices cannot be proportionally miniaturized when the critical dimension is reduced. For example, the size of the filaments formed in a miniaturized RRAM device cannot be reduced proportionally. Therefore, relatively high currents or voltages may still be required for the formation, setup, and / or reconfiguration of such conventional miniaturized RRAM devices. This can also hinder the effective miniaturization of selectors (e.g., transistors) and / or integrated circuits that supply current or voltage to the miniaturized RRAM device. Moreover, miniaturized RRAM devices may have upper electrodes with a relatively small area. Such upper electrodes may not be able to absorb oxygen to the same extent as those in larger RRAM devices. This can lead to device failure and / or failure of the RRAM device to function. For example, device failure may occur due to delamination between the reactive electrode and the switching oxide caused by the presence of oxygen molecules. Another example is when oxygen ions drift from the switching oxide to the upper electrode under an external voltage, and then return to the switching oxide after the external voltage is removed, resulting in volatile operation, which in the case of non-volatile memory would lead to a malfunction.

[0028] Therefore, the present disclosure provides a mechanism for manipulating defects within a RRAM device that can enhance the performance of the RRAM device and implement low-power IMC applications. In some embodiments, the RRAM device can include a bottom electrode, a first interface layer fabricated on the bottom electrode, a switching oxide layer fabricated on the first interface layer, and a top electrode. The bottom electrode can include Pt or any other suitable inert metal. The switching oxide layer can include a transition metal oxide such as HfO x , TaO x , TiO x , NbO x , ZrO x and the like. The first interface layer can include a discontinuous film of a first material that is more chemically stable than the transition metal oxide. The first material can include, for example, Al2O3, MgO, Y2O3, La2O3, and the like.

[0029] In some implementations, the RRAM device can further include a second interface layer fabricated on the switching oxide layer. In such an implementation, the top electrode can be fabricated on the second interface layer. The second interface layer can include a discontinuous film of a second material that is more chemically stable than the transition metal oxide and can further limit the electrical path through the switching oxide for lower current and lower power operation.

[0030] A defect engineering layer can be fabricated on the switching oxide layer and / or a second interface layer. The defect engineering layer may include a first layer of suitable metallic material for generating defects within the switching oxide layer. In some embodiments, the defect engineering layer may include a layer of titanium (Ti). The first layer of metallic material may be a thin layer having a thickness between approximately 0.2 nm and 5 nm. The defect engineering layer can trap and release oxygen during the operation of the device. Incorporation of a defect engineering layer into an RRAM device can generate a high density of electronic defects (e.g., oxygen-deficient defects) within the switching metal oxide. These electronic defects can assist in the transport of charge within the switching oxide layer under an electric field, at room temperature or below or above. In some embodiments, this charge is transported by an oxygen ion carrying a -2 charge (O₂). -2 , or oxygen-deficient Vo carrying a +2 charge +2 These can be ionic charges such as e -1 The electron charge can be such as e, where e represents an electron and -1 represents the charge carried by the electron. Trapped electrons can be excited to the conduction band (with lower excitation energy) under an electric field, or they can hop from one trap to another (also called tunneling) without excitation to the conduction band. Incorporating a thin defect engineering layer into the RRAM device can therefore change the unused resistance of the RRAM device, resulting in a less abrupt formation process, a lower formation voltage, a lower reset current, and lower voltage and / or current requirements in the subsequent operating process.

[0031] Furthermore, the defect engineering layer may include a second layer of Ta or any other suitable metallic material.

[0032] In some embodiments, the defect engineering layer may include one or more Ta alloys in a single implementation. The Ta alloy may be a Ta-containing binary alloy, a Ta-containing ternary alloy, a Ta-containing quaternary alloy, a Ta-containing pentary alloy, a Ta-containing hexary alloy, and / or a Ta-containing higher-order alloy (e.g., an alloy containing more than six metallic elements), and / or may include such alloys. Each of these alloys may contain Ta and one or more other metallic elements having the required thermodynamic and / or kinematic basic attributes, such as tungsten (W), hafnium (Hf), molybdenum (Mo), niobium (Nb), zirconium (Zr), etc. For example, using a Ta alloy instead of pure Ta metal to fabricate the upper electrode can reduce the migration of Ta into the transition oxide layer during the formation process and thus reduce the size of the filament formed in the transition oxide layer (e.g., by reducing the lateral dimension or diameter of the filament). This allows for an increase in the filament resistance of the RRAM device, and thus an increase in the resistance of the RRAM device in both low-resistance and high-resistance states, which in turn reduces the voltage and / or current required for the operation of the RRAM device, such as its formation, setup, resetting, and / or adjustment. RRAM devices incorporating a defect engineering layer can exhibit multidimensional dynamic memristor motion suitable for implementations of dynamic learning, edge processing, inference engine accelerators, and other IMC applications.

[0033] Accordingly, this disclosure provides defect engineering techniques within RRAM devices to achieve high filament resistance and reduced operating voltage and current. The RRAM devices described herein exhibit desirable behaviors such as linearity, analogity, coercivity, and durability for IMC applications in the high resistance range (e.g., from 10 kΩ to 10 MΩ). This technique enables efficient miniaturization of RRAM devices and low-power IMC applications utilizing RRAM devices.

[0034] Figure 1 is a schematic diagram illustrating an example of a crossbar circuit 100 according to some embodiments of the present disclosure. As shown in the figure, the crossbar circuit 100 may include one or more row wires 111a, 111b, ..., 111i, ..., 111n and a plurality of interconnecting conductive wires such as column wires 113a, 113b, ..., 113j, ..., 113m for an n-row m-column crossbar array. The crossbar circuit 100 may further include crosspoint devices 120a, 120b, ..., 120z, etc. Each of the crosspoint devices may be connected to row wires and column wires. For example, crosspoint device 120ij may be connected to row wire 111i and column wire 113j. In some embodiments, the crossbar circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and / or any other circuit components suitable for the implementation of a crossbar-based device. The number of column wires 113a-m and the number of row wires 111a-n may be the same or different.

[0035] The row wires 111 may include a first row wire 111a, a second row wire 111b, ..., 111i, and an nth row wire 111n. Each of the row wires 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row wire 111a-n may be a metal wire.

[0036] The row wire 113 may include a first row wire 113a, a second row wire 113b, ..., and an mth row wire 113m. Each of the row wires 113a-m may be and / or include any suitable conductive material. In some embodiments, each row wire 113a-m may be a metal wire.

[0037] Each crosspoint device 120 may be and / or include any suitable device with tunable resistors, such as a memristor, PCM device, floating gate, spintronics device, RRAM, or SRAM. In some embodiments, one or more of the crosspoint devices 120 may include an RRAM device as described in relation to Figures 3A-5B.

[0038] The crossbar circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows of the crossbar circuit 100 (e.g., one or more selected rows). The input signal can flow through the crosspoint devices of those rows of the crossbar circuit 100. The conductance of the crosspoint devices can be adjusted to a specific value (sometimes called "weighting"). By Ohm's law, multiplying the input voltage by the conductance of the crosspoint generates a current from the crosspoint device. By Kirchhoff's laws, the sum of the currents passing through the devices on each row generates a current as an output signal, which can be read out from the row (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of a crossbar array can be expressed as I=VG, where I is the output signal matrix expressed as current; V is the input signal matrix expressed as voltage; and G is the conductance matrix of the crosspoint devices. Therefore, the input signal is weighted in each crosspoint device according to Ohm's law based on its conductance. The weighted current is output through each column wire and can be accumulated according to Kirchhoff's current law. This enables in-memory computing (IMC) via parallel multiplication and addition performed within the crossbar array.

[0039] Figure 2 is a schematic diagram illustrating an example of a crosspoint device 200 according to some embodiments of the present disclosure. As shown in the figure, the crosspoint device 200 can connect bit lines (BL) 211, selection lines (SEL) 213, and word lines (WL) 215. The bit lines 211 and word lines 215 can be column wires and row wires, respectively, as described in relation to Figure 1.

[0040] The crosspoint device 200 may include an RRAM device 201 and a transistor 203. The transistor is a three-terminal device and can be marked as gate (G), source (S), and drain (D). Transistor 203 can be connected in series with the RRAM device 201. As shown in Figure 2, the first electrode of the RRAM device 201 can be connected to the drain of transistor 203. The second electrode of the RRAM device 201 can be connected to the bit line 211. The source of transistor 203 can be connected to the word line 215. The gate of transistor 203 can be connected to the selection line 213. The RRAM device 201 may include one or more RRAM devices as described below in relation to Figure 3A-7. The crosspoint device 200 is sometimes referred to as a one-transistor-one-resistor (1T1R) configuration. Transistor 203 can act as a selector for the RRAM device 201 during programming, as well as as a current controller that can set current compliance. The gate voltage of transistor 203 can be used to set the current compliance with respect to the crosspoint device 200 during programming, and thus control the conductance and analog behavior of the crosspoint device 200. For example, when setting the crosspoint device 200 from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) can be provided via the bit line (BL) 211. Another voltage, also called a selection voltage or gate voltage, can be applied to the gate of the transistor via the selection line (SEL) 213 to open the gate and set the current compliance, while the word line (WL) 215 can be set to ground. When resetting the crosspoint device 200 from a low-resistance state to a high-resistance state, a gate voltage can be applied to the gate of transistor 203 via the selection line 213 to open the gate of the transistor. Meanwhile, a reset signal can be sent to the RRAM device 201 via the word line 215, while the bit line 211 can be set to ground.

[0041] Figures 3A, 3B, and 3C illustrate cross-sectional views of examples of RRAM devices according to some embodiments of the present disclosure. RRAM devices 300a, 300b, and 300c can correspond to RRAM devices in an initial state, a low-resistance state, and a high-resistance state, respectively.

[0042] As shown in Figure 3A, the RRAM device 300a may include a substrate 310, a first electrode 320, a switching oxide layer 330, and a second electrode 340. Furthermore, the RRAM device 300a may include one or more other components for implementing an in-memory computing application.

[0043] The substrate 310 may include one or more layers of any suitable material that can serve as a substrate for an RRAM device, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or aluminum nitride (AlN). In some embodiments, the substrate 310 may include diodes, transistors, interconnects, integrated circuits, etc. In some embodiments, the substrate may include a drive circuit that includes one or more electrical circuits (e.g., an array of electrical circuits) that can be individually controlled. In some embodiments, the drive circuit may include one or more complementary metal-oxide-semiconductor (CMOS) drivers.

[0044] The first electrode 320 is and / or can be any suitable material that is electronically conductive and nonreactive to the switching oxide. For example, the first electrode 320 can be platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), etc.

[0045] The switching oxide layer 330 is TaO in the form of binary oxide, ternary oxide, and higher-order oxide. x , HfO x , TiO x NbO x ZrO xIt may contain one or more transition metal oxides. In some embodiments, the chemical stability of the nonreactive material in the first electrode 320 can be higher than that of the transition metal oxide in the switching oxide layer 330.

[0046] The second electrode 340 can include any suitable, electronically conductive, and reactive metallic material. For example, the metallic material in the second electrode 340 can include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 can be reactive to the switching oxide and have suitable oxygen solubility to adsorb some oxygen from the switching oxide layer 330, thereby creating oxygen vacancies within the switching oxide layer 330. In other words, the reactive metallic material in the second electrode 340 can have suitable oxygen solubility and / or oxygen mobility. In some embodiments, the second electrode 340 can not only create oxygen vacancies within the switching oxide layer 330 (e.g., by scavenging (removing) oxygen) but can also function as an oxygen reservoir or source for the switching oxide layer 330 during cell programming.

[0047] The RRAM device 300a may have an initial resistance (sometimes referred to here as "unused resistance") after it has been fabricated. The initial resistance of the RRAM device 300a can be changed, and the RRAM device 300a can be switched to a low-resistance state through the formation process. For example, an appropriate voltage or current can be applied to the RRAM device 300a. The application of voltage to the RRAM device 300a induces the absorption of oxygen from the switching oxide layer 330 by the metallic material in the second electrode, creating oxygen vacancies within the switching oxide layer 330. As a result, a conductive channel (e.g., a filament) rich in oxygen vacancies can be formed within the switching oxide layer 330. For example, a conductive channel 335a can be formed within the switching oxide layer 330, as illustrated in Figure 3B. As shown in the figure, the conductive channel 335a can be formed across the switching oxide layer 330 from the second electrode 340 to the first electrode 320. The RRAM device 300b can be considered to be operating in filament mode, where electrical conduction is dominated by conduction through the metal filament, while electrical conduction due to electron defects in the switching oxide can be ignored. The RRAM device 300b can be reset to a high-resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 300b during the reset process. In some embodiments, the set signal and the reset signal can have opposite polarity, i.e., a positive signal and a negative signal, respectively. The application of the reset signal can cause a drift of oxygen back to the switching oxide layer 330, allowing it to recombine with one or more oxygen vacancies. For example, as shown in Figure 3C, a partially interrupted conductive channel 335b can be formed in the switching oxide layer 330 during the reset process. As shown there, the conductive channel can be interrupted using an oxide gap between the partially interrupted conductive channel 335b and the first electrode 320. The lateral dimension of the conductive channel 335b can be smaller than that of the conductive channel 335a.In some embodiments, the conductive channel 335b does not continuously connect the first electrode 320 and the second electrode 340. An oxide gap 335c is located between the interrupted filament 335b and the first electrode 320. The RRAM device 300c can be considered to be operating in non-filament mode, and electrical conduction can be dominated by electron defects in the switching oxide gap 335c, which can have a much higher resistance than the interrupted filament 335b. RRAM devices 300a-c can be electrically switched between a high-resistance state and a low-resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

[0048] As described above, it may be necessary to operate the RRAM device in non-filament mode to achieve a desired high resistance (e.g., a resistance higher than Go). For example, as shown in Figure 3C, a circuit is formed that includes a suspended filament 335b and an oxide gap 335c located between the suspended filament 335b and the first electrode. Therefore, defect engineering and electronic defect control within the switching oxide are important for applications requiring high-resistance RRAM with a resistance higher than Go.

[0049] Figures 4A-4F are schematic diagrams illustrating cross-sectional views of examples 400a, 400b, 400c, 400d, 400e, and 400f of the structure of an RRAM device according to some embodiments of the present disclosure.

[0050] As illustrated in Figure 4A, the first electrode 420 can be fabricated on the substrate 410. The first electrode 420 and the substrate 410 can correspond to the first electrode 320 and the substrate 310, respectively, as described in relation to Figures 3A, 3B, and 3C.

[0051] As illustrated in Figure 4B, the interface layer 422 can be fabricated on the first electrode 420. The interface layer 422 (sometimes referred to here as the "first interface layer") may be a discontinuous film 422a and / or contain one. For example, the discontinuous film 422a may contain one or more pores 424. The pores 424 (sometimes referred to here as the "first pore") may have any suitable size and / or dimensions and may be randomly dispersed on the interface layer 422. A specific number of pores is illustrated in Figure 4B, but this is merely illustrative. The discontinuous film 422a may contain any suitable number of pores. In some embodiments, the thickness of the interface layer 422 and / or the discontinuous film 422a may be between approximately 0.2 nm and approximately 0.5 nm. In some embodiments, the discontinuous film 422a may be an Al2O3 film having a thickness of 0.5 nm or less. In some embodiments, the discontinuous film 422a may be an Al2O3 film having a thickness of less than 1 nm, and / or may include such a film.

[0052] As explained in Figure 4C, the switching oxide layer 430 can be fabricated on the interface layer 422. The switching oxide layer 430 is TaO x , HfO x , TiO x NbO x ZrO x The following transition metal oxides may be included, one or more in the form of binary oxides, ternary oxides, and higher-order oxides, where x can be used to indicate oxygen deficiency compared to the complete (or final) oxide, and the value of x is HfO x For x ≤ 2.0 (where the perfect oxide is HfO2), and TaO x The oxygen-to-metal atom ratio in the stoichiometry of a perfect oxide can be varied, such as x ≤ 2.5 (where the perfect oxide is Ta2O5). For example, the switching oxide layer 430 can contain Ta2O5. Another example is that the switching oxide layer 430 can contain HfO2.

[0053] In some embodiments, one or more portions of a transition metal oxide can be placed on the first electrode 420 through one or more pores 424 while the transition oxide layer 430 is being fabricated. Thus, the transition oxide layer 430 can come into contact with one or more portions of the first electrode 420.

[0054] In some embodiments, the interface layer 422 may contain a first material that is chemically more stable than the transition metal oxide in the transition oxide layer 430. As a result, the first material cannot react with the transition metal oxide in the transition oxide layer 430. As an example, the transition oxide in the transition oxide layer may be HfO x or TaO y (In this case, at least one of x ≤ 2.0, y ≤ 2.5) is a transition metal oxide, and / or may include such a first material, which may include Al2O3, MgO, Y2O3, La2O3, etc.

[0055] Referring to Figure 8, materials that are more chemically stable than the transition metal oxide in the transition oxide layer 430 can be identified using an Ellingham diagram. As illustrated in the figure, the Ellingham diagram plots the change in Gibbs free energy for an oxidation reaction as a function of temperature. The chemical stability of a material can be determined based on the Gibbs formation energy value of the material. The Gibbs free energy shown on the vertical axis in Figure 8 can represent the oxide formation energy. The curve of the material in the interface layer 422 may be lower than the curve corresponding to the transition metal oxide in the transition oxide layer 430. As an example, in some embodiments, Al2O3 can be used as the first material, and the transition metal oxide in the transition oxide layer 430 contains HfO2 or Ta2O5. During the setting and resetting processes, the first material containing Al2O3 does not react with the transition metal oxide containing HfO2 or Ta2O5.

[0056] As shown in Figure 4D, a second electrode 440 can be fabricated on the switching oxide layer 430. The second electrode 440 can function as a defect engineering layer for generating defects within the switching oxide layer 430. In some embodiments, the second electrode 440 may include one or more upper electrodes 700, as described in relation to Figure 7. In some embodiments, the second electrode 440 fabricated on the switching oxide layer 430 may include one or more alloys. Each of these alloys may contain two or more metallic elements. Each of these alloys may include a binary alloy (e.g., an alloy containing two metallic elements), a ternary alloy (e.g., an alloy containing three metallic elements), a quaternary alloy (e.g., an alloy containing four metallic elements), a pentary alloy (e.g., an alloy containing five metallic elements), a hexary alloy (e.g., an alloy containing six metallic elements), and / or a higher-order alloy (e.g., an alloy containing more than six metallic elements). In some embodiments, the second electrode 440 may include one or more alloys containing a first metallic element and one or more second metallic elements. Each of the second metal elements may have a lower or higher reactivity with respect to the transition metal oxide in the transition oxide layer than the first metal element. In some embodiments, the first metal element can be Ta. The second metal element may include one or more of W, Hf, Mo, Nb, Zr, etc. In some embodiments, the ratio of the first metal element to the second metal element in the alloy within the second electrode 340 can be about 50 atomic percent. In some embodiments, the appropriate ratio of the first metal element to the second metal element in the alloy can be optimized from the overall composition range. During the formation process, the second metal element can create fewer oxygen vacancies in the transition oxide layer than the first metal element. Therefore, the lateral size of the filament formed in the RRAM apparatus containing the second electrode containing the alloy can be made smaller than that of the filament formed in the RRAM apparatus containing the second electrode made of only the first metal.The implementation of a Ta-containing alloy within the second electrode 440 in the RRAM device results in a less abrupt formation process, lowering the formation voltage, lowering the reset current, and lowering the voltage and / or current requirements in the subsequent operation process. Furthermore, the incorporation of a Ta-containing alloy within the second electrode 440 can also generate electronic defects within the switching oxide that are suitable for performing RRAM operations requiring high resistance. The incorporation of Ta within the second electrode 440 can also generate defects within the switching oxide. These defects are generally considered as oxygen deficiencies, which are structural defects that can enhance the movement of oxygen ions within the switching oxide layer. Since electrical conduction in filament mode is governed by the metal filament rather than by electronic defects within the switching oxide layer, oxygen deficiencies as electronic defects do not affect the operation of the RRAM device in filament mode. However, in non-filament mode, these oxygen deficiencies can act as electronic defects (trapping and detrapping electrons) and (moving oxygen ions) rather than structural defects. The alloy incorporating Ta can provide electron defects for electrical conduction with high resistance in non-filamental mode within the switching oxide layer 430. RRAM devices with electron defects can exhibit specific electronic behaviors crucial for IMC applications, such as low current, analog resistance, multi-level resistance, and IV (current-voltage) linearity.

[0057] As an example, the second electrode 440 may contain one or more alloys containing Ta (sometimes called "Ta alloys"). Each Ta alloy may contain Ta and one or more other metallic elements (e.g., Hf, W, Mo, Nb, Zr, etc.). As an example, the second electrode 440 may contain one or more binary alloys containing Ta. Examples of binary alloys containing Ta include Ta-Hf alloy, Ta-W alloy, Ta-Mo alloy, Ta-Nb alloy, Ta-Zr alloy, etc. As another example, the second electrode 440 may contain one or more ternary alloys containing Ta. Examples of ternary alloys containing Ta include Ta-Hf-Mo alloy, Ta-Hf-Nb alloy, Ta-Hf-W alloy, Ta-Hf-Zr alloy, Ta-Mo-Nb alloy, Ta-Mo-W alloy, Ta-Mo-Zr alloy, Ta-Nb-W alloy, Ta-Nb-Zr alloy, Ta-W-Zr alloy, etc. As yet another example, the second electrode 440 may contain one or more quaternary alloys containing Ta. Examples of quaternary alloys containing Ta include Ta-Hf-Mo-Nb alloy, Ta-Hf-Mo-W alloy, Ta-Hf-Mo-Zr alloy, Ta-Hf-Nb-W alloy, Ta-Hf-Nb-Zr alloy, Ta-Mo-Nb-W alloy, Ta-Mo-Nb-Zr alloy, Ta-Nb-W-Zr alloy, etc. As yet another example, the second electrode 440 may contain one or more pentary alloys containing Ta. Examples of pentary alloys containing Ta include Ta-Hf-Mo-Nb-W alloy, Ta-Mo-Nb-W-Zr alloy, Ta-Hf-Nb-W-Zr alloy, Ta-Hf-Mo-W-Zr alloy, Ta-Hf-Mo-Nb-Zr alloy, etc. As yet another example, the second electrode 440 may include a hexa-alloy containing Ta, such as a Ta-Hf-Mo-Nb-W-Zr alloy. As yet another example, the second electrode 440 may include a higher-order alloy containing Ta. In some embodiments, the higher-order alloy may further contain vanadium (V).

[0058] In some embodiments, the second electrode 440 may include multiple alloys. Each of these alloys may be a Ta alloy containing Ta and one or more other metallic elements (e.g., Hf, W, Mo, Nb, Zr, etc.). The Ta alloy may be a binary alloy, ternary alloy, quaternary alloy, pentary alloy, hexa-component alloy, higher-order alloy, etc., and / or may include such alloys. As an example, the second electrode 440 may include two or more of the following: a first alloy containing Ta, a second alloy containing Ta, a third alloy containing Ta, a fourth alloy containing Ta, a fifth alloy containing Ta, and a sixth alloy containing Ta. In some embodiments, the first alloy containing Ta, the second alloy containing Ta, the third alloy containing Ta, the fourth alloy containing Ta, the fifth alloy containing Ta, and the sixth alloy containing Ta may be a binary alloy, a ternary alloy, a quaternary alloy, a pentary alloy, a hexa-component alloy, and a higher-order alloy, respectively.

[0059] In some embodiments, multiple alloys within the second electrode 440 can correspond to the same number of combinations of metallic elements. For example, a first alloy containing Ta and a second alloy containing Ta can each include a first binary alloy containing Ta (e.g., a Ta-W alloy) and a second binary alloy containing Ta (e.g., a Ta-Mo alloy). Another example is that a first alloy containing Ta and a second alloy containing Ta can each include a first ternary alloy containing Ta (e.g., a Ta-Hf-Mo alloy) and a second ternary alloy containing Ta (e.g., a Ta-Hf-Nb alloy). Further examples show that the second electrode 440 can include multiple alloy systems. Each of these alloy systems can contain alloys containing mixtures of specific metallic elements with diverse compositions. For example, a binary system can include one or more binary alloys of two metallic elements (e.g., Ta and Hf) with diverse compositions. Each of these binary alloys can be a combination of two metallic elements with a specific composition. As another example, a ternary system may include one or more ternary alloys of three metallic elements (e.g., Ta, Hf, and W) with diverse compositions. Each of these ternary alloys may be a combination of three metallic elements with a specific composition. In some embodiments, the second electrode 440 may include a Ta alloy system containing one or more alloy systems. In some embodiments, the Ta alloy system may include two or more alloy systems. For example, the Ta alloy system may include a hexa-system containing one or more alloys of Ta, Hf, W, Mo, Nb, and Zr. Furthermore, the Ta alloy system may include one or more binary, ternary, quaternary, and / or penta-systems containing Ta alloys. A binary system may include one or more of the Ta-Hf alloy system, Ta-W alloy system, Ta-Mo alloy system, Ta-Nb alloy system, and / or Ta-Zr alloy system.A ternary system may include one or more of the following: Ta-Hf-Mo alloy system, Ta-Hf-Nb alloy system, Ta-Hf-W alloy system, Ta-Hf-Zr alloy system, Ta-Mo-Nb alloy system, Ta-Mo-W alloy system, Ta-Mo-Zr alloy system, Ta-Nb-W alloy system, Ta-Nb-Zr alloy system, and / or Ta-W-Zr alloy system. A quaternary system may include one or more of the following: Ta-Hf-Mo-Nb alloy system, Ta-Hf-Mo-W alloy system, Ta-Hf-Mo-Zr alloy system, Ta-Hf-Nb-W alloy system, Ta-Hf-Nb-Zr alloy system, Ta-Mo-Nb-W alloy system, Ta-Mo-Nb-Zr alloy system, and Ta-Nb-W-Zr alloy system. The pentagonal system can include one or more of the following: Ta-Hf-Mo-Nb-W alloy system, Ta-Mo-Nb-W-Zr alloy system, Ta-Hf-Nb-W-Zr alloy system, Ta-Hf-Mo-W-Zr alloy system, and / or Ta-Hf-Mo-Nb-Zr alloy system. Each alloy system contained within the second electrode 440 can have unique thermodynamic and kinematic properties and can be considered as a component of the electrode. Thus, the second electrode 440 can include multiple electrode components to provide multiple state variables that can lead to rich dynamics with diverse time constants for computing and learning. For example, each electrode component can have different reactivity to switching oxides or affinity to oxygen. Each electrode element can have different diffusivity (e.g., self-diffusion, interdiffusion, diffusion time constant, etc.). The second electrode 440 with multiple components can provide multiple dynamic motions for IMC applications. Therefore, RRAM devices incorporating a multi-component second electrode can exhibit dynamic memristor behavior in multiple dimensions. Furthermore, the implementation of a multi-component second electrode can also generate electron defects within the switching oxide suitable for RRAM operations requiring high resistance. RRAM devices with electron defects can exhibit specific electron behaviors crucial for IMC applications, such as low current, analog resistance, multi-level resistance, and IV (current-voltage) linearity.

[0060] Figures 4E and 4F illustrate semiconductor devices 400e and 400f that can correspond to the low-resistance and high-resistance states, respectively, of the RRAM device 400d. The incorporation of the discontinuous film 422a can reduce contact between the switching oxide layer 430 and the first electrode 420. As illustrated in Figure 4E, a conductive channel 435a (e.g., a filament) can be formed from the second electrode 440 through the interface layer 422 and the switching oxide layer 430 to the first electrode 420. As illustrated in Figure 4F, a partially interrupted conductive channel 435b can be formed in the switching oxide layer 430 during the reset process. Compared to Figures 3B and 3C, the lateral sizes of the conductive channel 435a and the partially interrupted conductive channel 435b can be smaller than those of 335a and 335b, respectively. Therefore, the lateral size of the filaments formed in an RRAM device with a discontinuous film 422a can be made smaller than that of the filaments formed in an RRAM device without a porous and / or discontinuous film formed between the first electrode and the switching oxide layer. For example, forming an RRAM device with a non-porous or continuous film (e.g., a non-porous or continuous interface layer) fabricated in an unused state may require dielectric breakdown of the non-porous or continuous film to establish a circuit through the RRAM device. Dielectric breakdown of a non-porous or continuous film can be sudden and may result in over-formation or over-growth of conductive filaments in the RRAM device, which may reduce or interfere with the subsequent low-current operation of the RRAM device. Incorporating a discontinuous film 422a into the RRAM device results in a less sudden formation process, which can reduce the formation voltage, reduce the reset current, and reduce the voltage and / or current requirements in the subsequent operation process.

[0061] In some embodiments, the RRAM device may include a plurality of interface layers fabricated between a first electrode and a second electrode. Each of these interface layers may include a discontinuous film as described in relation to Figure 4B. For example, as illustrated in Figure 5A, the semiconductor device 500a can be fabricated by fabricating an interface layer 532 (sometimes referred to as the "second interface layer") on top of the semiconductor structure 400c as described in relation to Figure 4C. In some embodiments, the second interface layer 532 may include a discontinuous film 532a of a second material. The second material may be chemically more stable than at least one transition metal oxide in the transition oxide layer 430. As an example, the second material may include Al2O3, MgO, Y2O3, La2O3, etc. The second material may be the same as or different from the first material.

[0062] The discontinuous membrane 532a may contain one or more pores 534 (sometimes referred to as "one or more second pores"). The pores 534 may have any suitable size and / or dimensions. The sizes and / or dimensions of the multiple pores 534 may be identical or different. In some embodiments, the second interface layer 532 and / or the second discontinuous membrane 532a may contain multiple pores 534 randomly dispersed on the second discontinuous membrane 532a. The discontinuous membrane 532a may contain any suitable number of pores.

[0063] In some embodiments, the thickness of the second interface layer 532 and / or the second discontinuous film (sometimes referred to as the "second thickness") can be between approximately 0.2 nm and approximately 0.5 nm. As another example, the second interface layer 532 may include a discontinuous Al2O3 film having a thickness of 0.5 nm or less. In some embodiments, the second interface layer 532 may include a discontinuous Al2O3 film having a thickness of less than 1 nm. The second thickness of the second interface layer 532 may be the same as or different from the first thickness of the first interface layer 422.

[0064] As illustrated in Figure 5B, the semiconductor device 500b can be fabricated by fabricating a second electrode 540 on the second interface layer 532. Thus, the second interface layer 532 can be positioned between the switching oxide layer 430 and the second electrode 540. The second electrode 540 can function as a defect engineering layer for generating electronic defects within the switching oxide layer 430. The second electrode 540 may be and / or include the second electrode 440 as described in relation to Figures 4D-4F. In some embodiments, one or more portions of the second electrode 540 can be placed on the switching oxide layer 430 through one or more pores 534 while the switching oxide layer 430 is being fabricated. Thus, the second electrode 540 can be in contact with one or more portions of the switching oxide layer 430 through one or more pores 534.

[0065] Figures 5C and 5D illustrate semiconductor devices 500c and 500d that can correspond to the low-resistance and high-resistance states, respectively, of the RRAM device 500b. The incorporation of both the first interface layer 422 and the second interface layer 532 can further reduce the contact area between the switching oxide layer 430 and the first electrode 420, and between the switching oxide layer 430 and the second electrode 540. As illustrated in Figure 5C, a conductive channel 535a (e.g., a filament) can be formed from the first electrode 420 through the interface layer 422, the switching oxide layer 430, and the second discontinuous film 532a to the second electrode 540. As illustrated in Figure 5D, a partially interrupted conductive channel 535b can be formed in the switching oxide layer 430 during the reset process. Compared to Figures 3B and 3C, the lateral sizes of the conductive channel 535a and the partially interrupted conductive channel 535b can be made even smaller than those of 335a and 335b, respectively. Therefore, the lateral size of the filaments formed in the RRAM device with both the interface layer 422 and the second interface layer 532 can be further reduced, resulting in a less abrupt formation process, a lower formation voltage, a lower reset current, and lower voltage and / or current requirements in the subsequent operation process.

[0066] In some embodiments, an interface layer can be fabricated on a transition oxide layer in an RRAM device according to some embodiments of this disclosure. For example, as illustrated in Figure 6A, a transition oxide layer 630 can be fabricated on a semiconductor device 400a as depicted in Figure 4A. The semiconductor device 600a can be fabricated by fabricating an interface layer 632 on the transition oxide layer 630. The transition oxide layer 630 may be the transition oxide layer 430, and / or include it, as described in relation to Figures 4C-4F. In some embodiments, the interface layer 632 may include a discontinuous film of a third material. The third material may be chemically more stable than at least one transition metal oxide in the transition oxide layer 630. As an example, the third material may include Al2O3, MgO, Y2O3, La2O3, etc.

[0067] The discontinuous film 632a may contain one or more pores 634 (sometimes referred to here as "one or more third pores"). The pores 634 may have any suitable size and / or dimensions and may be randomly dispersed on the interface layer 632. In some embodiments, the thickness of the interface layer 632 (sometimes referred to as the "third thickness") may be between approximately 0.2 nm and approximately 0.5 nm. As another example, the interface layer 632 may have a thickness of 0.5 nm or less. As yet another example, the interface layer 632 may have a thickness of less than 1 nm.

[0068] As illustrated in Figure 6B, the semiconductor device 600b can be fabricated by fabricating a second electrode 640 on the interface layer 632. The second electrode 640 can function as a defect engineering layer for generating electronic defects within the switching oxide layer 630. Thus, the interface layer 632 can be positioned between the switching oxide layer 630 and the second electrode 640. The second electrode 640 may be a second electrode 440, and / or include it, as described in relation to Figures 4D-4F. In some embodiments, during the fabrication of the second electrode 640, one or more portions of the second electrode 640 can be placed on the switching oxide layer 630 through one or more pores 634. Thus, the second electrode 640 can be in contact with one or more portions of the switching oxide layer 630.

[0069] Figures 6C and 6D illustrate semiconductor devices 600c and 600d, which can correspond to the low-resistance and high-resistance states, respectively, of the RRAM device 600b. The incorporation of the discontinuous film 632 can reduce the contact area between the switching oxide layer 630 and the second electrode 640. As illustrated in Figure 6C, a conductive channel 635a (e.g., a filament) can be formed from the second electrode 640 through the switching oxide layer 630 and the discontinuous film 632 to the first electrode 420. As illustrated in Figure 6D, a partially interrupted conductive channel 635b can be formed in the switching oxide layer 630 during the reset process. Compared to Figures 3B and 3C, the lateral sizes of the conductive channel 635a and the partially interrupted conductive channel 635b can be smaller than those of 335a and 335b, respectively. Therefore, the lateral size of the filament formed in an RRAM device with the discontinuous film 632 can be smaller than that of the filament formed in an RRAM device without the discontinuous film 632. The incorporation of a discontinuous film 632 into the RRAM device results in a less abrupt formation process, lowering the formation voltage, lowering the reset current, and lowering the voltage and / or current requirements in the subsequent operation process. The incorporation of a discontinuous film 632 into the RRAM device can aid in fault engineering because it increases the resistance of the device and allows control over the number of electronic defects involved in high-resistance operation. More specifically, electronic defects can reduce the resistance of the device on their own or make the device leaky. The incorporation of a porous or discontinuous interface layer can increase the resistance of the device by restricting the electrical path through the switching oxide. Thus, a combination of a porous / discontinuous interface film 422 or 532 and a second electrode 540 can generate and control appropriate electronic defects for applications requiring high-resistance RRAM.

[0070] Figure 7 is a schematic diagram illustrating a cross-sectional view of an example upper electrode 700 according to several embodiments of the present disclosure.

[0071] The upper electrode 700 can function as a defect engineering layer as described herein. As shown in the figure, the upper electrode 700 may include a first layer 710 and a second layer 720. The first layer 710 may include a first metallic material capable of scavenging oxygen from the transition metal oxide in the switching oxide layer. The second layer 720 may include a second metallic material capable of scavenging oxygen from the transition metal oxide in the switching oxide layer. The first metallic material may be oxygen-soluble and capable of reacting with the transition metal oxide in the switching oxide layer to scavenge oxygen from there. The oxide of the first metallic material may have lower chemical stability than the first material of the first discontinuity film and the second material of the second discontinuity film. As a result, the first metallic material cannot chemically reduce the first discontinuity film and the second discontinuity film. As described above, Ellingham diagrams can be used to determine the relative chemical stability of two or more elements.

[0072] The first and second metallic materials may contain different chemical elements that have different oxygen affinities and / or different thermodynamic and kinematic fundamental attributes. The first and second metallic materials may be miscible. In some embodiments, the first metallic material may contain Ti. The second metallic material may contain Ta. In some embodiments, the first layer 710 may be and / or contain a layer of Ti metal (e.g., a Ti film). The second layer 720 may be and / or contain a layer of Ta metal (e.g., a Ta film). As shown in the Ta-Ti binary phase diagram of Figure 9, the Ta and Ti phases are miscible and have minimal mutual solubility at 300K (27°C), which falls around the operating temperature of the RRAM apparatus (e.g., around room temperature, below room temperature, or above room temperature). Therefore, the addition of Ti to the RRAM apparatus may not affect the operating mechanism of the Ta filaments in the switching oxide and the switching mechanism of the RRAM apparatus as described herein. As shown in Figure 7, the RRAM apparatus can therefore be used for IMC applications requiring an RRAM apparatus with outstanding performance in terms of analog motion, linearity, retention force, and reliability. The immiscibility and minimal mutual solubility between the Ta and Ti phases also enable a thermodynamic equilibrium between the second layer 720 and the first layer 710. As a result, the thin Ti film can function as designed without reacting with or being dissolved by the Ta film.

[0073] Furthermore, since Ti has a higher oxygen affinity than Ta, it can easily scavenge oxygen from the switching oxide. Therefore, the incorporation of the first layer 710 into the RRAM apparatus can further improve the performance of the RRAM apparatus by reducing the formation voltage required in the RRAM formation process, and the current and voltage requirements in subsequent operation. For example, the second electrode 440 in Figures 4D-4F, the second electrode 540 in Figures 5B-5D, and / or the second electrode 640 in Figures 6B-6D as described above may be and / or include the second electrode 700. During the formation process, both the first and second metallic materials can generate oxygen vacancies within the switching oxide layers 330, 430, and / or 630. Compared to Figures 3B and 3C, the lateral sizes of the conductive channels and the partially interrupted conductive channels can be smaller than those of 335a and 335b, respectively. Since Ti has a higher oxygen affinity than Ta, the unused resistance of an RRAM device including the upper electrode 700 can be lower than that of an RRAM device without the upper electrode 700, resulting in a lower formation voltage, lower reset voltage, lower reset current, and so on.

[0074] Furthermore, Ti can readily store oxygen during the set process (as oxygen moves from the switching oxide to the second electrode). This allows for oxygen storage by the second electrode during the reset process, thus preventing device failure (which may result from the presence of oxygen molecules between the switching oxide and the second electrode) and / or operational failure (which may result from oxygen moving back to the switching oxide after the set voltage is removed, or from volatile switches). Moreover, the incorporation of a Ti film into an RRAM device can generate electron defects within the switching oxide of that RRAM device. These electron defects can be electrons trapped within the oxygen deficiency. Trapped electrons can hop from one trap site to another under an electric field, or be excited to the conduction band with lower excitation energy, generating electron flow when the RRAM device is in a high-resistance state.

[0075] The first layer 710 can be grown to a suitable thickness such that the first metallic material (e.g., Ti) of the first layer 710 can function as described above without affecting the formation of filaments (e.g., Ta filaments) containing the second metallic material within the switching oxide layer 330. In some embodiments, the thickness of the first layer 710 can be between approximately 0.2 nm and approximately 5 nm. In some embodiments, the thickness of the first layer 710 can be between approximately 0.5 nm and approximately 2 nm. In some embodiments, the thickness of the first layer 710 can be approximately 1 nm. In some embodiments, the thickness of the first layer 710 can be less than 1 nm. The second layer 720 can be thicker than the first layer 710. In some embodiments, the thickness of the second layer 720 can be between 5 nm and 300 nm. For example, the thickness of the second layer 720 can be between approximately 10 nm and approximately 100 nm. In some embodiments, the thickness of the second layer 720 can be between approximately 10 nm and approximately 200 nm. In some embodiments, the thickness of the second layer 720 can be approximately 50 nm. The thickness of the first electrode can be roughly between 5 nm and 100 nm. In some embodiments, the thickness of the first electrode can be approximately 30 nm. In some embodiments, the dimensions (e.g., critical dimensions) of the RRAM devices 400d, 500b, and / or 600b can be between 1 μm and an order of magnitude nanometer. In some embodiments, the critical dimensions of the RRAM devices 400d, 500b, and / or 600b can be approximately 0.28 μm or less, and / or between 1 μm and 1 nanometer. In some embodiments, the critical dimensions of the RRAM devices 400d, 500b, and / or 600b can be between 1 μm and 2 nm. In some embodiments, the critical dimensions of the RRAM devices 400d, 500b, and / or 600b can be between 1 μm and 5 nm. In some embodiments, the critical dimensions of the RRAM devices 400d, 500b, and / or 600b can be set to an order of magnitude nanoscale (for example, between approximately 1 nm and approximately 9 nm).

[0076] In one implementation, the second layer 720 can be fabricated directly on top of the first layer 710. For example, as shown in Figure 7, the surface of the second layer 720 can be in direct contact with one or more portions of the surface of the first layer 710. In another implementation, one or more other layers of suitable material can be deposited between the first layer 710 and the second layer 720.

[0077] The transition metal oxides in the transition oxide layers described herein (e.g., transition oxide layers 430, 530, and / or 630) may have a band gap between their balance band and conduction band when functioning as insulators. Excitation of electrons from the balance band to the conduction band, where electrons can participate in conduction, requires energy higher than that represented by the band gap. It is important to have appropriate electron defects at an appropriate density within the band gap as electron traps, either for trapped electrons to be excited to the conduction band (thermal release) or for hopping from one trap site to another (tunneling). The incorporation of defect engineering layers as described herein (e.g., alloy 440 containing Ta, first layer 710, etc.) can generate appropriate density of electron defects within the transition metal oxides in the transition oxide layers 430, 530, and / or 630. These electron defects are, for example, in the transition metal oxide (e.g., TaO x or HfO x This can include oxygen-deficient defects within the substoichiometric oxides. Electron defects can assist in charge transport through transition metal oxides at room temperature and above. In some embodiments, this charge is carried by an oxygen ion O₂ carrying a -2 charge. -2 , or oxygen-deficient Vo carrying a +2 charge +2 The ionic charge can be such as the following. In some embodiments, the charge is such that the electron e carrying a charge of -1 -1These can be electronic charges such as those mentioned above. In this case, when the RRAM device incorporating the defect engineering device is operating in a non-filamental state, the trapped electrons can be excited to the conduction band under an electric field, or they can hop from one trap site to another, generating an electron flow.

[0078] The incorporation of the first layer 710 within the RRAM device thus reduces the unused resistance of the RRAM device, lowers the formation voltage, and lowers the reset current, resulting in a less abrupt formation process, a filament with lower conductance, lower voltage and lower current in the subsequent operation process, and the generation of appropriate electronic defects within the switching oxide for IMC operation in the high-resistance state.

[0079] Figures 4D-4F, 5B-5D, and 6B-6D show specific components of RRAM devices 400d-f, 500b-d, and 600b-d, but this is merely illustrative. RRAM devices 400d-f, 500b-d, and 600b-d may include one or more other layers of suitable material for implementing IMC applications. For example, one or more interface layers (not shown) can be fabricated between the switching oxide layer and one or more of the second and first electrodes to improve interface stability and device performance.

[0080] Figure 10 is a flowchart illustrating an example method 1000 for fabricating an RRAM device according to some embodiments of the present disclosure.

[0081] In block 1010, a first electrode can be fabricated on the substrate. The fabrication of the first electrode may involve depositing one or more layers of one or more inert metals such as Pt, Pd, Ir using physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, atomic layer deposition (ALD), and / or any other suitable deposition technique. In some embodiments, the fabrication of the first electrode may involve depositing one or more layers of Pt. The first electrode may be and / or include the first electrodes 320, 420 as described above in relation to Figures 3A-6D.

[0082] In block 1020, an interface layer can be fabricated on the first electrode. Fabricating the first interface layer may involve depositing a first material on the first electrode to form a first discontinuous film of the first material. The first discontinuous film may contain one or more first pores. The first material may be chemically more stable than the transition metal oxide in the transition oxide layer, as described below. In some embodiments, the first material may include Al2O3, MgO, Y2O3, La2O3, etc. The first interface layer may be and / or include the first interface layer 422 as described above in relation to Figures 4B-5D in some embodiments. In some embodiments, fabricating the first interface layer may involve depositing a layer of the first material having an appropriate thickness to form a first discontinuous film. For example, fabricating the first interface layer may involve depositing the first material to a thickness between approximately 0.2 nm and approximately 1 nm. The first discontinuous film can be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0083] In block 1030, a transition oxide layer can be fabricated on the interface layer. The transition oxide layer may contain one or more transition metal oxides. For example, the transition metal oxide may be TaO x , HfO x , TiO x NbOx ZrO x This may include, for example, one or more portions of a transition metal oxide on the first electrode through one or more of the first pores while the transition oxide layer is being fabricated. The transition oxide layer can be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique. The transition oxide layer may be and / or include the transition oxide layer 430 as described above in relation to Figures 4C-5D.

[0084] In block 1040, a defect engineering layer can be fabricated on the transition oxide layer to generate electronic defects within the transition oxide layer. The defect engineering layer can function as a second electrode (e.g., an upper electrode) of the RRAM device to be fabricated. The defect engineering layer may contain one or more alloys. Each of the alloys may contain a first metal element and one or more second metal elements. Each of the second metal elements and the first metal element may have different reactivity with respect to the transition metal oxide in the transition oxide layer. In some embodiments, the first metal element may be Ta. The second metal element may be one or more of W, Hf, Mo, Nb, Zr, etc. As shown in Figures 14A-14E, based on the binary phase diagrams relating Ta and a second metallic element W, Hf, Mo, Nb, or Zr, Ta-W (Figure 14B), Ta-Mo (Figure 14C), and Ta-Nb (Figure 14D) form continuous solid solutions, while Ta-Hf (Figure 14A) and Ta-Zr (Figure 14E) are immiscible at the operating temperature of the RRAM device. In all of these binary systems, binary intermetallic compounds cannot be formed. The absence of intermetallic compounds in these binary systems is advantageous for IMC applications requiring alloy electrodes that can be easily fabricated and controlled. For example, the fabrication of a second electrode can involve the fabrication of an alloy by simultaneous sputtering of the first and second metals. As another example, the fabrication of the second electrode may involve sputtering from an alloy target (e.g., Ta-W alloy, Ta-Hf alloy, Ta-Mo alloy, Ta-Nb alloy, Ta-Zr alloy, etc.) for the desired composition between the first metal element (e.g., pure Ta metal) and the second metal element (e.g., pure Hf metal).

[0085] In some embodiments, the fabrication of the defect engineering layer may involve the fabrication of multiple electrode components including Ta, Hf, Nb, Mo, W, and / or Zr. Each of these electrode components may be and / or include a binary alloy, ternary alloy, quaternary alloy, pentary alloy, hexary alloy, and / or higher-order alloy of Ta. For example, the fabrication of the defect engineering layer may involve the fabrication of a second electrode 340 comprising one or more alloys and / or alloy systems, as described in relation to Figure 4D. More specifically, for example, the fabrication of the second electrode may involve the fabrication of two or more of the following alloys containing Ta: a first alloy containing Ta, a second alloy containing Ta, a third alloy containing Ta, a fourth alloy containing Ta, a fifth alloy containing Ta, and a sixth alloy containing Ta. The first alloy containing Ta, the second alloy containing Ta, the third alloy containing Ta, the fourth alloy containing Ta, the fifth alloy containing Ta, and the sixth alloy containing Ta can be a binary alloy, a ternary alloy, a quaternary alloy, a pentary alloy, a hexary alloy, and a higher-order alloy, respectively.

[0086] In some embodiments, the fabrication of the defect engineering layer may involve the fabrication of multiple layers of metallic material, such as layers 710 and 720, as described in relation to Figure 7. In some embodiments, the defect engineering layer may be fabricated by performing one or more operations, as described in relation to Figure 13.

[0087] The defect engineering layer can be fabricated using PVD, CVD, ALD, and / or any other suitable deposition technique. The defect engineering layer may be and / or include the second electrode 440 as described above in relation to Figures 4D-4F.

[0088] Figure 11 is a flowchart illustrating an example method 1100 for fabricating an RRAM device according to some embodiments of the present disclosure.

[0089] In block 1110, a first electrode can be fabricated on the substrate. The first electrode can be fabricated on the substrate by performing one or more operations as described in relation to block 1010 in Figure 10. The first electrode may be the first electrode 320 and / or 420, and / or include them, as described above in relation to Figures 3A-6D.

[0090] In block 1120, a first interface layer can be fabricated on the first electrode. Fabrication of the first interface layer may involve fabricating a first discontinuous film of the first material. The first interface layer can be fabricated on the first electrode by performing one or more operations as described in relation to block 1020 in Figure 10. The first interface layer may be and / or include the first interface layer 422 as described above in relation to Figures 4B-5D.

[0091] In block 1130, a transition oxide layer can be fabricated on the first interface layer. The transition oxide layer can be fabricated on the first interface layer by performing one or more operations as described in relation to block 1030 in Figure 10. The transition oxide layer may be and / or include the transition oxide layer 430 as described above in relation to Figures 4C-5D.

[0092] In block 1140, a second interface layer can be fabricated on the transition oxide layer. Fabrication of the second interface layer may involve fabricating a second discontinuous film of a second material that is chemically more stable than the transition metal oxide of the transition oxide layer. In some embodiments, the second material may include Al2O3, MgO, Y2O3, La2O3, etc. In some embodiments, fabrication of the second interface layer may involve depositing the second material to an appropriate thickness (e.g., a thickness between 0.2 nm and 1 nm) to form a second discontinuous film. This discontinuous film can be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique. The second interface layer may be and / or include the second interface layer 532 as described in relation to Figures 5A-5D.

[0093] In block 1150, a defect engineering layer can be fabricated on the second interface layer to generate electronic defects within the switching oxide layer. The defect engineering layer can function as a second electrode (e.g., an upper electrode) of the RRAM device to be fabricated. The defect engineering layer can be fabricated by performing one or more operations as described in relation to block 1040 in Figure 10. In some embodiments, one or more portions of the defect engineering layer can be deposited on the switching oxide layer through one or more second pores while the defect engineering layer is being fabricated. The defect engineering layer may be and / or include a second electrode 540 as described above in relation to Figures 5B-5D.

[0094] Figure 12 is a flowchart illustrating an example method 1200 for fabricating an RRAM device according to some embodiments of the present disclosure.

[0095] In block 1210, a first electrode can be fabricated on the substrate. The first electrode can be fabricated on the substrate by performing one or more operations as described in relation to block 1010 in Figure 10. The first electrode may be the first electrode 320 as described above in relation to Figures 3A-6D, and / or may include it.

[0096] In block 1220, a transition oxide layer can be fabricated on the first electrode. The transition oxide layer may contain one or more transition metal oxides. For example, the transition metal oxide may be TaO x , HfO x , TiO x NbO x ZrO x This may include the following. The transition oxide layer can be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique. The transition oxide layer may be and / or include the transition oxide layer 630 as described above in relation to Figures 6A-6D.

[0097] In block 1230, an interface layer can be fabricated on the transition oxide layer. The interface layer may include a discontinuous film of a material that is more chemically stable than the transition metal oxide in the transition oxide layer. The interface layer can be fabricated on the transition oxide layer by performing one or more operations as described in relation to block 1140 in Figure 11. The interface layer may be interface layer 632 as described above in relation to Figures 6A-6D, and / or may include it. As shown above, discontinuous or porous interface layers can contribute to the electron defect engineering in the transition oxide by controlling the number of electron defects that may be involved in high-resistance operation.

[0098] In block 1240, a defect engineering layer can be fabricated on the interface layer. The defect engineering layer can function as a second electrode (e.g., upper electrode) of the RRAM device. The defect engineering layer can be fabricated on the interface layer by performing one or more operations as described in relation to block 1040 in Figure 10. The defect engineering layer may be and / or include the second electrode 640 as described above in relation to Figures 6B-6D.

[0099] Figure 13 is a flowchart illustrating an example method 1300 for fabricating a defect engineering layer for an RRAM device according to some embodiments of the present disclosure. The defect engineering layer can function as the upper electrode of the RRAM device.

[0100] In block 1310, a first layer of a first metallic material can be fabricated. The first metallic material may contain first metallic elements such as Ti, Hf, and Zr. The first layer of the first metallic material can be fabricated by depositing the first metal (e.g., Ti metal) using PVD, CVD, sputtering, ALD, and / or any other suitable deposition technique. Fabrication of the defect engineering layer may involve depositing a layer of the first metal having a suitable thickness, such as between approximately 0.2 nm and approximately 5 nm, or between approximately 0.5 nm and approximately 2 nm.

[0101] In block 1320, a second layer containing a second metallic material can be fabricated on a first layer of a first metallic material. The second metallic material can also contribute to the engineering and generation of electronic defects in the switching oxide. The second metallic material may contain a second metallic element different from the first metallic element. For example, the second metallic element may be Ta. In some embodiments, the fabrication of the second layer containing the second metallic material may involve the deposition of the second metal (e.g., Ta metal) using PVD, CVD, sputtering, ALD, and / or any other suitable deposition technique. The fabrication of the second layer of the second metal may involve depositing a layer of the second metal having an appropriate thickness such that the layer of the second metal is thicker than the first layer of the first metal. In some embodiments, a layer of the second metal having a thickness between 10 nm and 100 nm can be deposited. In some embodiments, the second layer of the second metal can be deposited directly on top of the layer of the first metal. In such embodiments, the surface of a first layer of a first metal can be in direct contact with one or more portions of the surface of a second layer of a second metal.

[0102] In some embodiments, the fabrication of a second layer containing a second metallic material may involve the fabrication of a layer containing one or more alloys. As described above, each of the alloys may contain a first metallic element and one or more second metallic elements. Each of the second metallic elements may have a different reactivity with respect to the transition metal oxides in the transition oxide layer than the first metallic element. In some embodiments, the first metallic element may be Ta. The second metallic elements may be one or more of W, Hf, Mo, Nb, Zr, etc. The fabrication of the second layer of Ta alloy may involve the deposition of the Ta alloy using PVD, CVD, sputtering, ALD, and / or any other suitable deposition technique. The fabrication of the second layer of Ta alloy may involve depositing a layer of Ta alloy having an appropriate thickness such that the layer of Ta alloy is thicker than the first layer of the first metal. In some embodiments, one or more layers of Ta alloy having thicknesses between about 5 nm and about 100 nm can be deposited.

[0103] For the sake of simplicity, the methods disclosed herein are illustrated and described as a series of actions. However, the actions according to this disclosure can occur in various orders and / or simultaneously, and together with other actions not presented or described herein. Furthermore, not all illustrated actions may be necessary for implementing the methods according to the gist of the disclosed invention. In addition, as those skilled in the art will understand and recognize, these methods can alternatively be represented as a series of interrelated states via a state diagram or events.

[0104] Figures 15A, 15B, 15C, and 15D illustrate multi-level resistance and linearity data for examples of RRAM devices according to several embodiments of the present disclosure. Figure 15A illustrates the current-voltage characteristics of an RRAM device 1500A in the range of 1kΩ–10kΩ. As shown herein, according to the conductance quantum Go (12.9kΩ), the resistance R of the device never exceeds Go, and the device operates in filament mode (as shown, for example, in Figure 3B). Conduction in an RRAM device can exhibit metallic motion.

[0105] Figure 15B illustrates the current-voltage characteristics of an example RRAM device 1500B with high resistance (e.g., 10kΩ–100kΩ) according to one implementation of the present disclosure. The RRAM device operates in transitions from filament mode (e.g., with a resistance of 10kΩ not exceeding Go) to non-filament mode (e.g., with a resistance of 100kΩ exceeding Go), or from the RRAM device shown in Figure 3B to the RRAM device shown in Figure 3C.

[0106] Figure 15C illustrates the current-voltage characteristics 1500C of an example RRAM device with high resistance (e.g., 100kΩ–1MΩ) according to another implementation of the present disclosure. The RRAM device operates entirely in non-filament mode. Conduction in the RRAM device can exhibit semiconducting motion. However, multi-level high resistance and linearity have been demonstrated through electron defect engineering including a discontinuous interface layer 532, a Ta alloy as the second electrode 540, and / or a two-layer metal as the second electrode 710 / 720.

[0107] Figure 15D illustrates the current-voltage characteristics 1500D of an example RRAM device with very high resistance (e.g., 1 MΩ–10 MΩ) according to one implementation of this disclosure. Implementing this type of high resistance in the non-filament mode high resistance range may require balanced fault engineering for the RRAM device. As shown herein, RRAM devices with engineered faults exhibit excellent linearity and analog behavior in this high resistance range.

[0108] As used herein, the terms “approximately,” “about,” and “substantially” may mean within two standard deviations of the mean, within ±20% of the target dimension in some embodiments, within ±10% of the target dimension in some embodiments, within ±5% of the target dimension in some embodiments, within ±2% of the target dimension in some embodiments, within ±1% of the target dimension in some embodiments, and even within ±0.1% of the target dimension in some embodiments. The terms “approximately” and “about” may include the target dimension. Unless otherwise stated or obvious from the context, all numerical values ​​described herein are modified by the term “about.”

[0109] When used herein, a range includes all values ​​within that range. For example, the range from 1 to 10 may include any number, combination of numbers, or subranges derived from 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10, and their fractions.

[0110] The above description includes several details. However, as will become clear, this disclosure can be implemented without these specific details. In some cases, well-known structures and devices are shown in block diagram form rather than in detail, in order to avoid obscuring the disclosure.

[0111] As used herein, terms such as "1st," "2nd," "3rd," "4th," etc., are labels used to distinguish different elements and do not necessarily have an orderly meaning according to their numerical designation.

[0112] The terms “example” or “exemplary” as used herein mean to provide an example, case, or illustration. No aspect or design described herein as “example” or “exemplary” is necessarily to be interpreted as being preferable or advantageous to any other aspect or design. Rather, the use of the terms “example” or “exemplary” is intended to present a concept in a specific aspect. The term “or” as used in this application is intended to mean an inclusive “or” rather than an exclusive “or.” In other words, unless otherwise specified or evident from the context, “X includes A or B” is intended to mean any natural inclusive reordering. That is, “X includes A or B” is satisfied under any of these cases: X includes A; X includes B; or X includes both A and B. In addition, the use of “a certain” and the absence of a quantity designation in this application and accompanying claims should generally be interpreted as meaning “one or more,” unless otherwise specified or the singular form is clear from the context. Whenever “a certain implementation” or “one implementation” is referred to throughout this specification, it means that the specific features, structures, or characteristics described in relation to that implementation are included in at least one implementation. Therefore, it is not necessary that every instance of the phrase “implementation” or “one implementation” appearing throughout this specification refers to the same implementation.

[0113] When used herein, if an element or layer is referred to as being "on top of" another element or layer, it may also mean that the element or layer is directly on top of the other element or layer, or that there is an intervening element or layer. In contrast, if an element or layer is referred to as being "directly on top of" another element or layer, there is no intervening element or layer.

[0114] After reading the above description, it will be clear that many variations and modifications of this disclosure will be apparent to those skilled in the art; however, it will be understood that no particular embodiment shown or described for illustrative purposes is intended in any way to be considered limiting. Accordingly, references to details of various embodiments are not intended to limit the scope of the claims, and they merely enumerate the features that are considered to be part of the disclosure. [Explanation of symbols]

[0115] 100 Crossbar Circuit 111a-n row wire 111a, 111b, ..., 111i, ..., 111n row wire 113a-m row wire 113a, 113b, ..., 113j, ..., 113m row wire 120a, 120b, ..., 120z Crosspoint device 120ij Crosspoint device 200 Crosspoint device 201 RRAM device 203 Transistors 211 bit lines 213 Selection Line 215 Wordlines 300a RRAM device 300b RRAM device 300c RRAM device 310 circuit board 320 First electrode 330 Switching oxide layer 335a Conductive Channel 335b Interrupted filament 335c oxide gap 340 Second electrode 400a Semiconductor 400c semiconductor structure 400d RRAM device 400e Semiconductor Equipment 410 circuit board 420 First electrode 422 Interface layer, first interface layer 422a Discontinuous membrane 424 pores 430 Switching Oxide Layer 435a Conductive Channel 440 Second electrode 500a Semiconductor 500b Semiconductor devices, RRAM devices 500c Semiconductor Device 532 Interface layer, second interface layer 532a Discontinuous membrane, second discontinuous membrane 534 pores 535a Conductive Channel 540 Second electrode 600a Semiconductor 600b Semiconductor devices, RRAM devices 600c semiconductor device 630 Switching oxide layer 632 Interfacial layer, discontinuous film 632a Discontinuous membrane 634 pores 635a Conductive Channel 640 Second electrode 700 Upper electrode, second electrode 710 First layer 720 Second layer One example method for fabricating a 1000 RRAM device. 1100 An example method for fabricating an RRAM device An example method for fabricating a 1200 RRAM device. 1300 An example method for fabricating a defective engineering layer 1500A Current-Voltage Characteristics 1500B Current-Voltage Characteristics 1500C Current-Voltage Characteristics 1500D Current-Voltage Characteristics

Claims

1. A method for fabricating a resistive random-access memory (RRAM) device, A first interface layer is fabricated on the first electrode of the RRAM device, encompassing a first discontinuous film of the first material. A transition oxide layer containing at least one transition metal oxide is fabricated on the first interface layer, The method involves creating a second interface layer on the aforementioned switching oxide layer, wherein the second interface layer encompasses a second discontinuous film of the second material. A defect engineering layer is fabricated on the second interface layer to generate electronic defects within the switching oxide layer, It includes, The fabrication of the aforementioned defective engineering layer is A first layer of the first metallic material is fabricated on the second interface layer, A second layer of the second metal material is fabricated on the first layer of the first metal material, It includes, At least a portion of the first layer of the first metal material is deposited on the switching oxide layer via the second interface layer. The first layer of the first metal material and the second layer of the second metal material are configured to trap and release oxygen during the operation of the RRAM apparatus, and the operation of the RRAM apparatus includes a non-filament mode. method.

2. The at least one transition metal oxide is HfO ｘ or TaO ｙ The method according to claim 1, wherein at least one of the following is included, and x ≤ 2.0 and y ≤ 2.

5.

3. The first material is Al ２ O ３ , MgO, Y ２ O ３ , or La ２ O ３ The method according to claim 2, comprising at least one of the above.

4. The method according to claim 3, wherein the fabrication of a first interface layer encompassing the first discontinuous film of the first material on the first electrode of the RRAM apparatus includes depositing the first material on the first electrode to form the first discontinuous film.

5. The method according to claim 1, wherein the thickness of the first interface layer is between 0.2 nm and 1 nm.

6. The second material is Al ２ O ３ , MgO, Y ２ O ３ , or La ２ O ３ The method according to claim 1, comprising at least one of them.

7. The process of fabricating the first layer of the first metallic material on the second interface layer is as follows: To create a Ti layer on the second interface layer, It includes, At least a portion of the Ti layer is deposited on the switching oxide layer via the second interface layer, The process of creating a second layer of the second metal material on top of the first layer of the first metal material includes depositing the second metal material on top of the Ti layer. The method according to claim 1.

8. The method according to claim 1, wherein the first metallic material comprises at least one of Ti, Hf, or Zr.

9. The method according to claim 7, wherein the second metal material includes tantalum.

10. The method according to claim 7, wherein the second layer of the second metal material does not come into contact with the switching oxide layer.

11. The method according to claim 7, wherein the second layer of the second metallic material comprises one or more alloys containing tantalum.

12. The method according to claim 1, wherein the defective engineering layer comprises one or more alloys containing tantalum.

13. The method according to claim 12, wherein the one or more alloys containing tantalum further comprises at least one of hafnium, molybdenum, tungsten, niobium, or zirconium.

14. The method according to claim 12, wherein the one or more alloys containing tantalum include at least one of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a pentary alloy containing tantalum, a hexary alloy containing tantalum, or a higher-order alloy containing tantalum.

15. The method according to claim 1, wherein the thickness of the first layer comprising the first metal material is between 0.2 nm and 5 nm.

16. The method according to claim 1, wherein the electronic defects in the switching oxide layer include oxygen-deficient defects within the switching oxide layer.

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