Semiconductor devices and electronic equipment

Abstract

High heat dissipation is achieved with a simple and inexpensive structure in this semiconductor device that is configured to include a semiconductor element provided in a cavity of a cavity substrate mounted on a main substrate.　The semiconductor device comprises: a main substrate; a cavity substrate that has a cavity formed in the back surface being a plate surface on the main substrate side, and that is mounted on the main substrate; and a semiconductor element that is positioned in the cavity, that is mounted on the cavity substrate, and that is metal-joined to the main substrate by causing one surface of the semiconductor element, the one surface being on the main substrate side, to be positioned on the same or substantially the same plane as that of the back surface of the cavity substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an electronic device.

Background Art

[0002] As a configuration of a semiconductor device, there is provided a package structure including a main substrate as a mother board and a cavity substrate having a recess (cavity) formed facing the plate surface on the main substrate side and mounted on the main substrate, and a semiconductor element such as an IC chip is provided in the recess of the cavity substrate. In such a package structure, from the viewpoint of maintaining a good operating state and obtaining desired characteristics, it is important to dissipate heat generated from the semiconductor element serving as a heat generating body.

[0003] Regarding heat dissipation from the semiconductor element, conventionally, a configuration in which heat is dissipated from the semiconductor element through the cavity substrate to the main substrate has been used. In such a configuration, for example, when another electronic component such as an IC chip serving as a heat generating body is mounted on the surface which is the plate surface on the opposite side of the recess of the cavity substrate, it becomes difficult to sufficiently dissipate heat generated from both the semiconductor element in the recess and the electronic component on the surface side.

[0004] Therefore, in order to improve heat dissipation performance, for example, it is possible to form thermal via holes penetrating in the plate thickness direction of the cavity substrate, or change the material of the cavity substrate to a material with good thermal conductivity. However, the formation of thermal via holes in the cavity substrate and the change of the substrate material cause an increase in the substrate size and the manufacturing cost.

[0005] For example, Patent Document 1 discloses a configuration in which an IC chip, provided in a recess of a cavity substrate, is mounted on a printed circuit board, which is the main substrate. With such a configuration, heat generated by the IC chip is directly conducted to the main substrate for heat dissipation. However, in the configuration disclosed in Patent Document 1, wiring connected to the IC chip and wiring connecting the IC chip and the cavity substrate are provided within the main substrate, resulting in longer wiring lengths. Longer wiring lengths can increase inductance and impedance, potentially leading to a deterioration of the electrical characteristics of the device.

[0006] Therefore, as a technique to improve heat dissipation, a technique is known in which a heat dissipation member such as a heat sink is provided to the semiconductor element, as disclosed in Patent Document 2, for example. Patent Document 2 describes a method in which a semiconductor element provided in a recess of a cavity substrate is mounted on the cavity substrate, a metal heat sink is provided connected to the semiconductor element and in a state that it closes the recess, and the heat sink is connected to the main substrate. height A configuration is disclosed. With this configuration, a heat dissipation path is formed from the semiconductor element to the main substrate via a heat sink. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2017-27970 [Patent Document 2] Japanese Patent Publication No. 2003-60523 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] As mentioned above, a configuration in which a heat dissipation member such as a heat sink is provided between the semiconductor element and the main substrate has the problem that the number of parts increases, the number of manufacturing steps increases, and the manufacturing cost rises because a heat dissipation member is required.

[0009] The objective of this technology is to provide semiconductor and electronic devices that can achieve good heat dissipation with a simple and inexpensive configuration, in which semiconductor elements are provided in recesses of cavity substrates mounted on a main substrate. [Means for solving the problem]

[0010] The semiconductor device according to this technology comprises a main substrate, a cavity substrate mounted on the main substrate and having a recess formed facing the back surface which is the board surface of the main substrate, and a semiconductor element located within the recess and mounted on the cavity substrate, with one of its surfaces facing the main substrate positioned on the same or substantially the same plane as the back surface of the cavity substrate, and metal-bonded to the main substrate.

[0011] Another embodiment of the semiconductor device relating to this technology is the semiconductor device in which the cavity substrate has a stepped portion in the recess that contacts the other surface of the semiconductor device which is opposite to the one surface of the semiconductor device, thereby restricting the sinking of the semiconductor device into the recess.

[0012] Another embodiment of the semiconductor device relating to this technology is the semiconductor device in which the recess includes a bottom surface parallel to the back surface of the cavity substrate and a plurality of sides formed around the bottom surface, and the step includes a first surface parallel to the bottom surface and facing or in contact with the other surface of the semiconductor element and a second surface that forms a step between the first surface and the bottom surface.

[0013] Another embodiment of the semiconductor device according to this technology is such that, in the semiconductor device, the recess is formed in a rectangular shape including the bottom surface and the four sides, and the stepped portion is formed along at least two opposing sides of the rectangular shape formed by the recess.

[0014] Another embodiment of the semiconductor device according to this technology is the semiconductor device in which the recess is formed in a rectangular shape including the bottom surface and the four sides, and the stepped portion is formed at two corners located at least diagonally in the rectangular shape formed by the recess.

[0015] Another embodiment of the semiconductor device according to this technology is a semiconductor device in which a heat conduction portion made of a thermally conductive material is provided in the recess so as to fill the gap between the cavity substrate and the semiconductor element.

[0016] Another embodiment of the semiconductor device relating to this technology is a semiconductor device in which the heat conduction portion comprises a first heat conduction portion formed of a first resin material having thermal conductivity and forming the portion of the heat conduction portion on the main substrate side, and a second heat conduction portion formed of a second resin material having lower thermal conductivity than the first resin material and forming the portion of the heat conduction portion opposite to the main substrate side.

[0017] Another embodiment of the semiconductor device relating to this technology is characterized in which a metal film made of a metallic material is formed on one side of the semiconductor element.

[0018] Another embodiment of the semiconductor device relating to this technology is the semiconductor device wherein the semiconductor element has a connection terminal for mounting on the cavity substrate, and the connection terminal includes a metal layer made of copper or a copper-containing alloy and a solder layer made of solder provided on the tip side of the connection terminal relative to the metal layer.

[0019] Another embodiment of the semiconductor device according to this technology is the semiconductor device, which includes an active component mounted on the side of the cavity substrate opposite to the back surface.

[0020] The electronic device according to the present technology has a semiconductor device including a main board, a cavity board mounted on the main board, and a semiconductor element located in a recess formed facing the back surface which is the board surface on the main board side, mounted on the cavity board, and metal-bonded to the main board, with one surface which is the surface on the main board side positioned on the same or substantially the same plane as the back surface of the cavity board.

Brief Description of the Drawings

[0021] [Figure 1] It is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present technology. [Figure 2] It is a bottom view showing the mounting state of the IC chip on the cavity board according to the first embodiment of the present technology. [Figure 3] It is a bottom view showing the configuration of the cavity board according to the first embodiment of the present technology. [Figure 4] It is a cross-sectional view taken along the line B-B in FIG. 3. [Figure 5] It is a cross-sectional view showing the configuration of the IC chip according to the first embodiment of the present technology. [Figure 6] It is an explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Figure 7] It is an explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Figure 8] It is a diagram showing the configuration of Modification 1 of the semiconductor device according to the first embodiment of the present technology. FIG. 8A is a bottom view showing the configuration of the cavity board of Modification 1. FIG. 8B is a cross-sectional view taken along the line C-C in FIG. 8A. [Figure 9] It is a bottom view showing the mounting state of the IC chip on the cavity board according to Modification 1 of the first embodiment of the present technology. [Figure 10] It is a diagram showing the configuration of Modification 2 of the semiconductor device according to the first embodiment of the present technology. FIG. 10A is a bottom view showing the configuration of the cavity board of Modification 2. FIG. 10B is a cross-sectional view taken along the line D-D in FIG. 10A. [Figure 11]This is a bottom view showing the mounting state of an IC chip on a cavity substrate according to a modified example 2 of the first embodiment of this technology. [Figure 12] This figure shows the configuration of Modified Example 3 of the semiconductor device according to the first embodiment of this technology. Figure 12A is a bottom view showing the configuration of the cavity substrate of Modified Example 3. Figure 12B is an EE cross-sectional view in Figure 12A. [Figure 13] This is a bottom view showing the mounting state of an IC chip on a cavity substrate according to Modification 3 of the first embodiment of this technology. [Figure 14] This figure shows the configuration of Modification 4 of the semiconductor device according to the first embodiment of this technology. Figure 14A is a bottom view showing the configuration of the cavity substrate of Modification 4. Figure 14B is a cross-sectional view of the front end in Figure 14A. [Figure 15] This is a bottom view showing the mounting state of an IC chip on a cavity substrate according to Modification 4 of the first embodiment of this technology. [Figure 16] This figure shows the configuration of Modified Example 5 of the semiconductor device according to the first embodiment of this technology. Figure 16A is a bottom view showing the configuration of the cavity substrate of Modified Example 5. Figure 16B is a cross-sectional view of GG in Figure 16A. [Figure 17] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example 5 of the first embodiment of this technology. [Figure 18] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example 6 of the first embodiment of this technology. [Figure 19] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example 7 of the first embodiment of this technology. [Figure 20] This is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of this technology. [Figure 21] This is a bottom view showing the mounting state of the IC chip on the cavity substrate according to the second embodiment of this technology. [Figure 22] This is a cross-sectional view showing the configuration of an IC chip according to a second embodiment of this technology. [Figure 23] This is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment of this technology. [Figure 24]This is an explanatory diagram of a method for manufacturing a semiconductor device according to the third embodiment of this technology. [Figure 25] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example of the third embodiment of this technology. [Figure 26] This is a block diagram showing an example configuration of an electronic device equipped with a semiconductor device according to an embodiment of this technology. [Modes for carrying out the invention]

[0022] This technology aims to achieve good heat dissipation with a simple and inexpensive configuration by devising the mounting method of the semiconductor element on the cavity substrate, in a configuration in which a semiconductor element is provided in a recess of a cavity substrate mounted on a main substrate.

[0023] The embodiments for implementing this technology (hereinafter referred to as "embodiments") will be described below with reference to the drawings. The descriptions of the embodiments will be given in the following order. 1. Example of semiconductor device configuration according to the first embodiment 2. Method for manufacturing a semiconductor device according to the first embodiment 3. Modified examples of the semiconductor device according to the first embodiment 4. Example of a semiconductor device configuration according to the second embodiment 5. Example of semiconductor device configuration according to the third embodiment 6. Method for manufacturing a semiconductor device according to the third embodiment 7. Modified Examples of Semiconductor Devices According to the Third Embodiment 8. Example of Electronic Device Configuration

[0024] <1. Example of semiconductor device configuration according to the first embodiment> An example of the configuration of a semiconductor device according to the first embodiment of this technology will be described with reference to Figures 1 to 5. Figure 1 is a cross-sectional view corresponding to position AA in Figure 2.

[0025] As shown in Figure 1, the semiconductor device 1 comprises a main substrate 2, a cavity substrate 3, and an IC chip 4, which is an example of a semiconductor element, and these components form an integrated package structure. In the semiconductor device 1, the thickness direction of the main substrate 2 (the vertical direction in Figure 1) is defined as the vertical direction.

[0026] The main board 2 is the motherboard of the semiconductor device 1 and is a circuit board having a predetermined circuit. The main board 2 is, for example, an organic substrate made of an organic material such as plastic, or a ceramic substrate formed from a material such as ceramics.

[0027] The main substrate 2 has a rectangular plate shape, with one surface, surface 2a, being the side that receives the mounting of the cavity substrate 3, and the other surface, surface 2b, being the side opposite surface 2a. Both surface 2a and surface 2b are horizontal surfaces.

[0028] The cavity substrate 3 is a ceramic substrate formed from a ceramic material such as alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4). However, the cavity substrate 3 may also be of other types, such as an organic substrate formed from an organic material such as glass epoxy resin, which is a type of fiber-reinforced plastic.

[0029] The cavity substrate 3 has a rectangular plate shape and has a back surface 3b, which is the plate surface facing the main substrate 2, and a front surface 3a, which is the surface opposite to the back surface 3b. Both the back surface 3b and the front surface 3a are horizontal surfaces. The cavity substrate 3 also has vertical side surfaces 3c on all four sides.

[0030] The cavity substrate 3 has a recess 5 formed on the back surface 3b as a cavity. As shown in Figures 3 and 4, the recess 5 is a recessed portion formed to form a rectangular shape along the outer shape of the cavity substrate 3.

[0031] The recess 5 includes a bottom surface 5a parallel to the back surface 3b of the cavity substrate 3, and a plurality of side surfaces 5b formed around the bottom surface 5a. In this embodiment, the recess 5 is formed in a rectangular shape including the bottom surface 5a and the four side surfaces 5b. However, the shape of the recess 5 is not particularly limited, and may be a polygonal shape other than a rectangle, or a shape formed by partially curved or curved surfaces, etc.

[0032] As shown in Figure 1, the cavity substrate 3 is mounted on the main substrate 2. On the back surface 3b of the cavity substrate 3, multiple electrodes (not shown) are formed using an LGA (Land Grid Array) as an external terminal structure, and these electrodes electrically connect the cavity substrate 3 to the main substrate 2.

[0033] The cavity substrate 3 is solder-bonded to the main substrate 2. Therefore, a solder layer 6, formed of solder material, is interposed between the back surface 3b of the cavity substrate 3 and the front surface 2a of the main substrate 2 as a bonding layer. The solder layer 6 is formed in a frame shape along the frame shape of the back surface 3b surrounding the recess 5 on the cavity substrate 3. The solder layer 6 is formed entirely or partially on the back surface 3b of the cavity substrate 3.

[0034] The solder layer 6 has a substantially constant thickness overall. Therefore, a clearance d1 corresponding to the thickness dimension of the solder layer 6 exists between the surface 2a of the main substrate 2 and the back surface 3b of the cavity substrate 3.

[0035] The cavity substrate 3 may be bonded and fixed to the main substrate 2 with an insulating or conductive adhesive. In this case, the bonding layer interposed between the cavity substrate 3 and the main substrate 2 will be a layer formed by an insulating or conductive adhesive. Furthermore, the external terminal structure provided on the back surface 3b of the cavity substrate 3 may be a BGA (Ball Grid Array) in which multiple solder balls are arranged in a grid pattern.

[0036] The IC chip 4 is a rectangular semiconductor chip having a predetermined circuit structure as an integrated circuit. The IC chip 4 has a configuration in which transistors, diodes, resistors, etc. are formed and wired on a semiconductor substrate such as a silicon substrate. The IC chip 4 has one side facing the main substrate 2 as the back surface 4b, and the other side opposite the back surface 4b as the front surface 4a. Both the back surface 4b and the front surface 4a are horizontal surfaces.

[0037] As shown in Figure 5, the IC chip 4 has a rectangular plate-shaped chip body 11 that makes up the majority of the IC chip 4. One of the plate surfaces 11a of the chip body 11 becomes the surface 4a of the IC chip 4. Multiple solder balls 12 made of BGA are formed on the surface 11a of the chip body 11 as connection terminals for external connections.

[0038] Each solder ball 12 is provided on an external connection terminal electrode formed on the surface 11a of the chip body 11. Multiple solder balls 12 are formed in a grid-like arrangement in two dimensions, for example, following the rectangular outer shape of the chip body 11 (see Figure 2). The solder balls 12 serve as terminals for the electrical connection of the IC chip 4 to the cavity substrate 3.

[0039] A metal film made of a metal material is formed on the back surface 4b of the IC chip 4. In the IC chip 4, as shown in Figure 5, a first metal film, a sputtered film 14, and a second metal film, a plating film 15, are formed on the back surface 11b, which is the other plate surface of the chip body 11.

[0040] The sputtered film 14 is formed on the back surface 11b of the chip body 11 by sputtering so as to cover the entire back surface 11b. The sputtered film 14 is formed from a metallic material such as titanium (Ti), tungsten (W), copper (Cu), platinum (Pt), or gold (Au), or from a combination of these metallic materials.

[0041] The plating film 15 is formed on the sputtered film 14 by plating so as to cover the entire surface of the sputtered film 14. The plating film 15 is formed by plating with, for example, nickel (Ni) or gold (Au). The surface 15a of the plating film 15 is the IC chip 4 back face 4 b This is the result. Furthermore, the metal film formed on the back surface 4b of the IC chip 4 may be formed using printing or other film formation methods.

[0042] The IC chip 4 is located within a recess 5 of the cavity substrate 3 and is mounted to the cavity substrate 3 by a plurality of solder balls 12. The IC chip 4 has a planar external shape that is smaller than the dimensions of the rectangular recess 5 when viewed from the back surface 3b of the cavity substrate 3. The IC chip 4 is positioned such that its planar center coincides with the recess 5.

[0043] A gap s1 exists around the entire circumference of the IC chip 4 between the four outer surfaces 4c of the IC chip 4 and the side surfaces 5b of the recesses 5 that face each outer surface 4c. In other words, the IC chip 4 is positioned such that a gap s1 is formed around the entire circumference of the IC chip 4 relative to the recesses 5 (see Figures 1 and 2). The size of the gap s1 between the IC chip 4 and the side surfaces 5b on all four sides may be a common (constant) size, may vary depending on the position, and in some positions, there may be no gap s1 at all.

[0044] The IC chip 4 is reflow mounted to the bottom surface 5a of the recess 5 by multiple solder balls 12. That is, the IC chip 4 is set in a predetermined position within the recess 5 with its surface 4a facing the bottom surface 5a relative to the cavity substrate 3, and is soldered and mounted to the cavity substrate 3 by undergoing a reflow process at a predetermined temperature.

[0045] Terminal electrodes (not shown) for connection are formed on the bottom surface 5a of the cavity substrate 3 to receive electrical connections of the solder balls 12. When the IC chip 4 is mounted on the cavity substrate 3, the solder balls 12 formed on the IC chip 4 are temporarily melted by reflow soldering between the surface 4a of the IC chip 4 and the bottom surface 5a of the recess 5, and then solidify to form a solder connection portion 12X.

[0046] The height of the solder joint 12X relative to the surface 4a of the IC chip 4, that is, the amount of protrusion of the solder joint 12X from the surface 4a, is smaller than the height of the solder ball 12 relative to the surface 4a. The circuit inside the IC chip 4 is electrically connected to the wiring on the main board 2 via the solder joint 12X and the wiring formed in the cavity substrate 3. The height of the solder joint 12X is, for example, about 30 μm.

[0047] The IC chip 4 is mounted on the cavity substrate 3 within the recess 5 and fixed to the main substrate 2 by metal bonding. In this embodiment, the cavity substrate 3 is fixed to the main substrate 2 by solder bonding. Therefore, a solder layer 16 formed of solder material is interposed between the back surface 4b of the IC chip 4 (the surface 15a of the plating film 15) and the surface 2a of the main substrate 2 as a bonding layer. The solder layer 16 is formed to cover the entire back surface 4b of the IC chip 4. However, the solder layer 16 may be formed partially on the back surface 4b of the IC chip 4.

[0048] The solder layer 16 has a substantially constant thickness overall. Therefore, a clearance corresponding to the thickness of the solder layer 16 exists between the surface 2a of the main substrate 2 and the back surface 4b of the IC chip 4. The IC chip 4 may also be bonded and fixed to the main substrate 2 with an insulating or conductive adhesive. In this case, the bonding layer interposed between the IC chip 4 and the main substrate 2 will be a layer formed by an insulating or conductive adhesive.

[0049] The IC chip 4 has its back surface 4b positioned on the same or substantially the same plane as the back surface 3b of the cavity substrate 3. That is, as shown in Figure 1, the back surface 4b of the IC chip 4 and the back surface 3b of the cavity substrate 3 are located on a substantially common horizontal virtual plane O1.

[0050] In other words, the mounting height A1 of the IC chip 4 when mounted in the recess 5 of the cavity substrate 3 is equal to or approximately equal to the depth A2 of the recess 5. That is, the mounting height A1 of the IC chip 4 and the depth A2 of the recess 5 are substantially the same. Here, the mounting height A1 of the IC chip 4 is the vertical dimension from the bottom surface 5a of the recess 5 to the back surface 4b of the IC chip 4 (see Figure 1). The depth A2 of the recess 5 is the vertical dimension from the bottom surface 5a to the back surface 3b of the cavity substrate 3, that is, the vertical dimension of the side surface 5b of the recess 5 (see Figure 4). The mounting height A1 of the IC chip 4 is, for example, a value in the range of 0.1 to 1 mm.

[0051] Such a configuration is achieved by taking into account the difference in height between the solder ball 12 and the solder connection portion 12X, and by adjusting the depth of the recess 5 and the mounting portion of the IC chip 4 so that the mounting height A1 of the IC chip 4 on the cavity substrate 3 matches the depth A2 of the recess 5. Specifically, adjustments to the mounting portion of the IC chip 4 include, for example, adjustments to the size and material of the solder ball 12.

[0052] In this configuration, the clearance between the IC chip 4 and the main substrate 2 is the same as or approximately the same as the clearance d1 between the cavity substrate 3 and the main substrate 2. In a structure in which the IC chip 4 is mounted in the recess 5 of the cavity substrate 3, the back surface 3b of the cavity substrate 3 and the back surface 4b of the IC chip 4, which are located on a common virtual plane O1, become the mounting surfaces for the main substrate 2.

[0053] The cavity substrate 3 has a stepped portion 20 within the recess 5, which is configured to facilitate positioning the back surface 4b of the IC chip 4 on the same or substantially the same plane as the back surface 3b of the cavity substrate 3. The stepped portion 20 is a part that contacts the surface 4a of the IC chip 4, thereby restricting the IC chip 4 from sinking into the recess 5, and is provided in the recess 5 as part of the cavity substrate 3.

[0054] The sinking of the IC chip 4 into the recess 5 is a phenomenon that can occur when the solder balls 12 temporarily melt due to the reflow process during the mounting of the IC chip 4 to the cavity substrate 3. In other words, the sinking of the IC chip 4 occurs when, in the state where the solder balls 12 are melted, the chip body 11 moves closer to the bottom surface 5a due to its own weight, etc., so that the back surface 4b of the IC chip 4 is located on the bottom surface 5a side of the recess 5 than the back surface 3b of the cavity substrate 3, resulting in a decrease in the mounting height of the IC chip 4. Therefore, the stepped portion 20 is provided on the bottom surface 5a side of the recess 5 and contacts the IC chip 4 that is trying to sink into the recess 5, thereby restricting the sinking of the IC chip 4.

[0055] The stepped portion 20 is provided to form a stepped shape relative to the corner formed by the bottom surface 5a and the side surface 5b of the recess 5. The stepped portion 20 has a support surface 21 which is a first surface parallel to the bottom surface 5a of the recess 5, and a side surface 22 which is a second vertical surface that forms a step between the support surface 21 and the bottom surface 5a.

[0056] The stepped portion 20 is provided so as to form a right-angled ridge portion 23 by the support surface 21 and the side surface 22. In the area where the stepped portion 20 is formed, a stepped portion is formed by the bottom surface 5a of the recess 5, the side surface 22 and support surface 21 of the stepped portion 20, the side surface 5b of the recess 5, and the back surface 3b of the cavity substrate 3.

[0057] In the stepped portion 20, the support surface 21 is the surface that faces or contacts the surface 4a of the IC chip 4. That is, if the height difference between the solder ball 12 and the solder connection portion 12X is smaller than the gap between the surface 4a of the IC chip 4 and the support surface 21 of the stepped portion 20 (hereinafter referred to as the "chip-step gap") when the solder ball 12 is in contact with the bottom surface 5a of the recess 5 before melting, the support surface 21 of the stepped portion 20 will have a small gap between it and the surface 4a of the IC chip 4, and will be in a state of facing (or nearly in contact with) the surface 4a.

[0058] On the other hand, if the height difference between the solder ball 12 and the solder connection portion 12X is greater than the gap between the chip and the stepped portion, the support surface 21 of the stepped portion 20 will be in contact with the surface 4a of the IC chip 4. In this state, the height of the stepped portion 20 will be the same as the height of the solder connection portion 12X. Here, the height of the stepped portion 20 is the vertical dimension from the bottom surface 5a of the recess 5 to the support surface 21, that is, the vertical dimension B1 of the side surface 22 of the stepped portion 20 (see Figure 4). Thus, in the semiconductor device 1, the IC chip 4 and the stepped portion 20 may be in contact with each other, or there may be a gap between them.

[0059] As described above, the cavity substrate 3 is designed such that the height B1 of the stepped portion 20 in the recess 5 matches or approximately matches the height of the solder connection portion 12X. In other words, by matching the height B1 of the stepped portion 20 to the height of the solder connection portion 12X, the height of the back surface 4b of the IC chip 4 mounted on the cavity substrate 3 and the height of the back surface 3b of the cavity substrate 3, which is the mounting surface on the main substrate 2, can be matched. Preferably, the height B1 of the stepped portion 20 is within the range of -30 to 0 μm relative to the height of the solder connection portion 12X.

[0060] Here, if the height B1 of the stepped portion 20 is a negative value relative to the height of the solder connection portion 12X, a gap will exist between the surface 4a of the IC chip 4 and the support surface 21 of the stepped portion 20. Also, if the height B1 of the stepped portion 20 and the height of the solder connection portion 12X are the same, that is, if the above value is -0 μm, the surface 4a of the IC chip 4 will be in contact with the support surface 21 of the stepped portion 20 at a position at the height of the solder connection portion 12X from the bottom surface 5a of the recess 5.

[0061] In other words, the above numerical range of -30 to 0 μm corresponds to the chip-to-step gap being less than 30 μm when the IC chip 4 is mounted on the cavity substrate 3. The value of -30 μm that defines the above numerical range is based on the fact that the layer thickness of the solder paste 16X (see Figure 6C) that forms the solder layer 16 for mounting the IC chip 4 to the main substrate 2 is approximately 30 μm. Note that it is undesirable for the height B1 of the step 20 to be greater than the height of the solder connection 12X (i.e., the above value is positive) from the viewpoint of obtaining a good connection state of the solder connection 12X to the bottom surface 5a of the cavity substrate 3.

[0062] In this embodiment, the stepped portion 20 is formed along two opposing sides of the rectangular shape formed by the recess 5. As shown in Figure 3, the cavity substrate 3 has, as the stepped portion 20, a first linear stepped portion 20A formed along one of the four sides 5b of the rectangular recess 5 (the left side in Figure 3) in a view of the back surface 3b of the cavity substrate 3, and a second linear stepped portion 20B formed along the other side 5b2 (the right side in Figure 3) opposite to side 5b1.

[0063] The first linear step portion 20A and the second linear step portion 20B are both formed along the entire length of the side surface 5b of the recess 5 in the extending direction. Therefore, both sides of the support surface 21 and side surface 22 of these step portions 20 are connected to the side surface 5b (5b3) on which the step portion 20 is not formed. The side surfaces 22 of the first linear step portion 20A and the second linear step portion 20B face each other.

[0064] The first linear stepped portion 20A and the second linear stepped portion 20B, with their respective support surfaces 21, have their inner edges in the opposing directions of the two stepped portions 20 (left-right direction in Figure 3) facing or in contact with the edges of the surface 4a of the IC chip 4, which are the areas outside the formation sites of the multiple solder balls 12 on the surface 4a.

[0065] Furthermore, as shown in Figure 1, the semiconductor device 1 includes a thermally conductive resin portion 25 as a heat conduction part within the recess 5. That is, in the semiconductor device 1, a thermally conductive resin portion 25 made of a thermally conductive resin material is provided within the recess 5 to fill the gap between the cavity substrate 3 and the IC chip 4.

[0066] The thermally conductive resin portion 25 is formed by filling the recess 5 with a resin material and curing it while the IC chip 4 is mounted. As the resin material for forming the thermally conductive resin portion 25, for example, thermosetting resins such as epoxy resin and polyimide resin, thermoplastic resins such as polyamide-imide, polypropylene, and liquid crystal polymer, rubber, and other known resin materials with relatively high thermal conductivity can be used alone or in combination of several.

[0067] Furthermore, the thermal conductivity of the material forming the thermal conductive resin part 25 can be increased by incorporating a thermally conductive filler with high thermal conductivity into the resin material forming the thermal conductive resin part 25. As the filler, known materials such as those mainly composed of silicon oxide can be used. The thermal conductive resin part 25 also has insulating properties.

[0068] The thermally conductive resin portion 25 includes an upper forming portion 25a and a lower forming portion 25b. Of the thermally conductive resin portion 25, the upper forming portion 25a is the part above the surface 4a of the IC chip 4, and the side forming portion 25b is the part below the upper forming portion 25a. The upper forming portion 25a and the side forming portion 25b are connected to each other.

[0069] The upper forming portion 25a is a portion that fills gaps between multiple solder connection portions 12X and gaps between the left and right stepped portions 20 and the solder connection portions 12X, between the surface 4a of the IC chip 4 and the bottom surface 5a of the recess 5. The side forming portion 25b is a portion that fills the space between the outer surface 4c of the IC chip 4 and the side surface 5b of the recess 5. The thermal conductive resin portion 25 is formed such that the bottom surface 25c, which is the lower surface of the side forming portion 25b, is positioned above the virtual plane O1 along which the back surface 3b of the cavity substrate 3 is aligned, so that it does not protrude from the recess 5 to the back surface 3b side.

[0070] Furthermore, the semiconductor device 1 includes a solid-state imaging device 30 that employs a WL-CSP (wafer-level chip-size (or scale) package) structure as an active component mounted on the surface 3a of the cavity substrate 3. A WL-CSP is a package structure that is manufactured by first processing the wafer to create the package, and then separating it into individual chip-sized pieces.

[0071] The solid-state imaging device 30 comprises an image sensor 31 which is a solid-state image element, a glass 32 which is a transparent material, and a support portion 33 which supports the glass 32 on the image sensor 31. A void-like cavity 34 is formed between the image sensor 31 and the glass 32.

[0072] The image sensor 31 is a rectangular plate-shaped chip made of a semiconductor such as silicon, and the side facing the glass 32 serves as a light-receiving surface on which multiple light-receiving elements are formed. The image sensor 31 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor or a CCD (Charge Coupled Device) type image sensor.

[0073] The glass 32 is a rectangular plate-shaped member having approximately the same external dimensions as the image sensor 31 in a plan view. The glass 32 transmits light incident from its surface side and directs it onto the light-receiving surface of the image sensor 31 through the cavity 34. The glass 32 may be, for example, a plastic plate or a silicon plate.

[0074] The support portion 33 is formed in a rectangular frame shape along the outer edge of the image sensor 31 and functions as a sealing portion that seals the periphery of the cavity 34. The material of the support portion 33 is, for example, a photosensitive adhesive such as an acrylic resin UV (ultraviolet) curable resin, a thermosetting resin such as an epoxy resin, or a mixture thereof. However, the support portion 33 may also be made of, for example, ceramics such as glass, or inorganic materials such as metal or silicon. Furthermore, the solid-state imaging device 30 may have a cavity-less structure in which a light-transmitting resin is filled between the image sensor 31 and the glass 32.

[0075] Multiple solder connection points 35 are formed on the back side of the image sensor 31 as electrodes for external connection. Each solder connection point 35 is a portion formed by a solder ball and is provided for an external connection terminal electrode formed on the back side of the image sensor 31. The multiple solder connection points 35 are formed in a two-dimensional grid-like arrangement that follows the rectangular outer shape of the image sensor 31. The solder connection points 35 serve as terminals for the electrical connection of the solid-state imaging device 30 to the cavity substrate 3.

[0076] On the other hand, multiple terminal electrodes (not shown) for connecting external devices are formed on the surface 3a side of the cavity substrate 3. Each electrode receives connections from solder balls (solder connection parts 35) of the solid-state imaging device 30 mounted on the cavity substrate 3. This electrically connects the solid-state imaging device 30 to the cavity substrate 3. When the solid-state imaging device 30 operates in the semiconductor device 1, it becomes a heat source with the image sensor 31 as the heat source.

[0077] <2. Method for manufacturing a semiconductor device according to the first embodiment> A method for manufacturing the semiconductor device 1 according to the first embodiment of this technology will be described with reference to Figures 6 and 7.

[0078] In the manufacturing method of the semiconductor device 1, a step of preparing the IC chip 4 is carried out. First, as shown in Figure 6A, a chip body 11 is prepared in which a plurality of solder balls 12 are formed on the surface 11a. A step of forming a sputtered film 14 is carried out on the back surface 11b of this chip body 11. The sputtered film 14 is formed by sputtering using a metallic material such as titanium (Ti), tungsten (W), copper (Cu), platinum (Pt), Au (gold), or a material that is a combination of these metallic materials.

[0079] Next, as shown in Figure 6B, a step is performed to form a plating film 15 on the sputtered film 14. The plating film 15 is formed by plating using a metallic material such as nickel (Ni) or gold (Au).

[0080] Next, as shown in Figure 6C, flux-containing solder paste 16X is applied onto the plating film 15 by a method such as transfer (printing). The solder paste 16X is used to mount the IC chip 4 onto the main substrate 2.

[0081] Furthermore, in the manufacturing method of the semiconductor device 1, a step is performed to prepare a cavity substrate 3 having a recess 5 and a stepped portion 20 formed within the recess 5. For example, if the cavity substrate 3 is a multilayer ceramic substrate formed by laminating sheet-like members made of ceramic material or the like, the following manufacturing method can be used.

[0082] In this method, a cavity substrate 3 having recesses 5 and stepped portions 20 is formed by creating through-holes in each sheet-like member to form recesses 5 or stepped portions 20, and then stacking the sheet-like members. Alternatively, in a stacked state of the sheet-like members, the portions that will become recesses 5 or stepped portions 20 are formed using a processing device such as a drill to obtain a cavity substrate 3 having recesses 5 and stepped portions 20.

[0083] Examples of multilayer ceramic substrates include low-temperature co-fired ceramic substrates known as LTCC (Low Temperature Co-fired Ceramics) substrates. Furthermore, if the cavity substrate 3 is a multilayer resin substrate formed by laminating sheet-like resin members, the same manufacturing method as for the multilayer ceramic substrate can be used to obtain the cavity substrate 3 having the recesses 5 and the stepped portions 20.

[0084] For the cavity substrate 3, flux-containing solder paste 6X is applied to the back surface 3b around the recess 5 by a method such as transfer (printing) (see Figure 6D). The solder paste 6X is used to mount the cavity substrate 3 onto the main substrate 2.

[0085] Next, as shown in Figure 6D, the IC chip 4 is mounted on the cavity substrate 3. Here, with the cavity substrate 3 facing upwards with its back surface 3b (the opening side of the recess 5) facing upwards, the IC chip 4 is set in a predetermined position within the recess 5 by a chip mounter or the like, and reflow soldering is performed at a predetermined temperature. As a result, the solder balls 12 melt and solidify to form solder connections 12X, and the IC chip 4 is electrically connected to and fixed to the cavity substrate 3.

[0086] Next, as shown in Figure 7A, a step is taken to form a thermally conductive resin portion 25 in the recess 5 of the cavity substrate 3 on which the IC chip 4 is mounted. Here, the resin material 25X that will become the thermally conductive resin portion 25 is extruded, for example, from the nozzle of a dispenser and applied and filled from the gap around the IC chip 4 in the recess 5 to fill the gap between the cavity substrate 3 and the IC chip 4 within the recess 5.

[0087] The resin material 25X filled into the recess 5 is cured at a predetermined time to form a thermally conductive resin portion 25. If the resin material 25X is a thermosetting resin, after the step of filling the recess 5 with the resin material 25X, a step of heating the resin material 25X to a predetermined temperature to cure it is performed. As a result, as shown in Figure 7A, a first package structure 41 is obtained in which the IC chip 4 is mounted in the recess 5 of the cavity substrate 3 and the thermally conductive resin portion 25 is formed.

[0088] Next, as shown in Figure 7B, a solid-state imaging device 30, which is an example of an active component, is mounted on the first package structure 41. Here, with the first package structure 41 with the surface 3a of the cavity substrate 3 facing upwards, the solid-state imaging device 30 is set in a predetermined position on the surface 3a by a chip mounter or the like, and reflow is performed at a predetermined temperature.

[0089] During the reflow process, the solder balls formed on the back side of the image sensor 31 melt and solidify to form a solder connection 35, electrically connecting and fixing the solid-state imaging device 30 to the cavity substrate 3. As a result, as shown in Figure 7B, a second package structure 42 is obtained in which the solid-state imaging device 30 is mounted on the first package structure 41.

[0090] The solid-state imaging device 30 can be obtained, for example, by the following manufacturing method. First, a wafer-state CSP is manufactured by attaching a glass plate, which will become the glass 32, to a silicon wafer that has undergone various processes for forming the image sensor 31, via a portion that will become the support part 33. Multiple solid-state imaging devices 30 can be obtained by dicing these wafer-state CSPs into individual pieces.

[0091] Then, as shown in Figure 7C, the second package structure 42 is mounted on the main substrate 2. Here, the second package structure 42 is set in a predetermined position on the surface 2a of the main substrate 2 by a chip mounter or the like, and reflow is performed at a predetermined temperature. As a result, the solder pastes 6X and 16X applied to the cavity substrate 3 and IC chip 4, respectively, melt and solidify to form solder layers 6 and 16, and the cavity substrate 3 and IC chip 4 are fixed to the main substrate 2, respectively. In this way, the semiconductor device 1 is obtained.

[0092] According to the semiconductor device 1 of this embodiment described above, in a configuration in which an IC chip 4 is provided in a recess 5 of a cavity substrate 3 mounted on a main substrate 2, good heat dissipation can be obtained with a simple and inexpensive configuration.

[0093] In other words, in the semiconductor device 1, the back surface 4b of the IC chip 4 mounted on the cavity substrate 3 and the back surface 3b of the cavity substrate 3 are located on substantially the same plane, so the IC chip 4 can be reliably mounted on the main substrate 2 together with the cavity substrate 3. As a result, the heat generated by the IC chip 4 can be conducted to the main substrate 2 without the need for heat dissipation materials such as heat sinks. Therefore, since there is no need to add new heat dissipation materials, the heat generated from the IC chip 4 can be efficiently dissipated with an inexpensive and simple configuration without increasing the number of components or the number of manufacturing processes, which would lead to increased costs.

[0094] Furthermore, if a metal film such as a plating film 15 is formed on the surface 4a of the IC chip 4, it is expected that sufficient adhesion to the main substrate 2 may not be obtained due to the influence of the unevenness of the surface of the metal film that forms the contact surface with the main substrate 2. In this regard, in the semiconductor device 1 of this embodiment, the IC chip 4 is metal-bonded to the main substrate 2 by solder. Therefore, the IC chip 4 can be firmly fixed to the main substrate 2, and the adhesion of the IC chip 4 to the main substrate 2 can be improved, so that good heat dissipation from the IC chip 4 to the main substrate 2 can be obtained. Thus, according to the semiconductor device 1 of this embodiment, a compact, inexpensive, and highly heat-dissipating mounting structure can be obtained as a package structure.

[0095] Furthermore, in the semiconductor device 1, the IC chip 4 is mounted in a state where it is electrically connected to the cavity substrate 3 within the recess 5. With this configuration, it is possible to omit wiring such as the wiring connected to the IC chip 4 and the wiring connecting the IC chip 4 and the cavity substrate 3 within the main substrate 2, thereby shortening the wiring length. This makes it possible to improve the electrical characteristics of the device.

[0096] Furthermore, the semiconductor device 1 is provided with a stepped portion 20 within the recess 5 of the cavity substrate 3, which restricts the sinking of the IC chip 4 into the recess 5. With this configuration, the IC chip 4 can be positioned such that its back surface 4b lies on the same plane as the back surface 3b of the cavity substrate 3 in the depth direction of the recess 5. In other words, the maximum amount of sinking of the IC chip 4 into the recess 5 can be kept constant. As a result, the mounting surfaces of the cavity substrate 3 and the IC chip 4 to the main substrate 2 can be reliably positioned on a common plane, thus providing good mountability to the main substrate 2 and good heat dissipation from the IC chip 4.

[0097] Furthermore, in the semiconductor device 1, the stepped portion 20 has a support surface 21 and a side surface 22. With this configuration, the IC chip 4 can be supported by the stepped portion 20 across its surface. As a result, the IC chip 4 can be firmly supported, ensuring reliable positioning, and improving heat dissipation from the IC chip 4 to the cavity substrate 3.

[0098] Furthermore, the semiconductor device 1 has a first linear stepped portion 20A and a second linear stepped portion 20B formed along two opposing sides of the rectangular recess 5 as stepped portions 20. With this configuration, the IC chip 4 can be supported at both ends, so that tilting of the IC chip 4 can be suppressed, and a good mounting condition can be obtained when mounting the IC chip 4 on the cavity substrate 3.

[0099] Furthermore, in the semiconductor device 1, a thermally conductive resin portion 25 is formed within the recess 5. With this configuration, the thermally conductive resin portion 25 can form a heat dissipation path from the IC chip 4 to the cavity substrate 3, thereby effectively dissipating the heat generated from the IC chip 4 to the main substrate 2. Specifically, the upper forming portion 25a of the thermally conductive resin portion 25 forms a heat dissipation path from the surface 4a side, which is the connection terminal surface of the IC chip 4, to the cavity substrate 3, and the side forming portion 25b forms a heat dissipation path from the outer surface 4c of the IC chip 4 to the cavity substrate 3. As a result, the heat generated from the IC chip 4 can be efficiently transferred to the cavity substrate 3, and the heat from the IC chip 4 can be effectively dissipated to the main substrate 2 via the cavity substrate 3.

[0100] Furthermore, with the configuration that includes the thermally conductive resin part 25, the connection portion of the IC chip 4 to the cavity substrate 3 is covered by the thermally conductive resin part 25, thereby improving the reliability of connections such as solder connections of the IC chip 4.

[0101] Furthermore, in the semiconductor device 1, a sputtered film 14 and a plating film 15 are formed as metal films on the back surface 4b side of the IC chip 4. With this configuration, the sputtered film 14 and the plating film 15 can function as heat dissipation parts in response to the heat generated by the IC chip 4. This improves the thermal conductivity in the layer portion between the chip body 11 and the main substrate 2, thereby improving the heat dissipation of the IC chip 4.

[0102] In other words, in the semiconductor device 1, the cavity substrate 3 is mounted on the main substrate 2, and at the same time, the IC chip 4 is soldered to the main substrate 2. That is, in this embodiment, the plating film 15 of the IC chip 4 is soldered to the main substrate 2 by the solder layer 16 at the same time as the mounting of the cavity substrate 3 on the main substrate 2. As a result, the heat generated by the IC chip 4 can be directly dissipated to the main substrate 2 via the plating film 15, and good heat dissipation can be obtained.

[0103] The metal film formed on the back surface 4b of the IC chip 4 may be either the sputtered film 14 or the plated film 15, and three or more layers of film may be formed. Furthermore, the method of forming the metal film is not limited to plating or sputtering; printing or other film formation methods may be used. In addition, the material is not limited to a metal film; for example, a sheet-like member made of a TIM (Thermal Interface Material) such as elastomer or silicon may be attached to the back surface 4b of the IC chip 4.

[0104] Furthermore, the semiconductor device 1 includes a solid-state imaging device 30 mounted on the surface 3a side of the cavity substrate 3. With this configuration, the heat generated by the solid-state imaging device 30, which generates heat when in operation, can be dissipated to the main substrate 2 via the cavity substrate 3, thereby improving the heat dissipation performance of the semiconductor device 1.

[0105] In other words, if we assume a configuration in the semiconductor device 1 where, for example, the IC chip 4 is not in contact with the main substrate 2, the only heat dissipation path from the IC chip 4 and the solid-state imaging device 30 to the main substrate 2 is the cavity substrate 3. As a result, heat dissipation from the IC chip 4 and the solid-state imaging device 30 is hindered by each other in the cavity substrate 3, and heat tends to accumulate in the cavity substrate 3. When heat accumulates in the cavity substrate 3, it can cause malfunctions or prevent the desired characteristics from being obtained.

[0106] Therefore, according to the semiconductor device 1 of this embodiment, since heat is directly dissipated from the IC chip 4 to the main substrate 2, the heat from the IC chip 4 can be efficiently released to the main substrate 2. As a result, heat dissipation from the solid-state imaging device 30 in the cavity substrate 3 is not hindered by heat dissipation from the IC chip 4, and heat can be efficiently dissipated from both the IC chip 4 and the solid-state imaging device 30 to the main substrate 2.

[0107] <3. Modified Examples of Semiconductor Device According to the First Embodiment> Modifications of the semiconductor device 1 according to this embodiment will now be described. Modifications 1 to 5 described below are modifications of the cavity substrate 3. Modifications 6 and 7 are modifications of the active components mounted on the surface 3a side of the cavity substrate 3.

[0108] (Variation 1) As shown in Figures 8A and 8B, in Modification 1, the cavity substrate 3 has a frame-shaped stepped portion 20C formed along the four sides of the rectangular shape formed by the recess 5, as a stepped portion 20. That is, the frame-shaped stepped portion 20C has four linear stepped portions 20a formed along each of the four sides 5b of the rectangular recess 5 when viewed from the back surface 3b of the cavity substrate 3, and is formed in a frame shape along the shape of the recess 5.

[0109] The support surface 21 of the frame-shaped step portion 20C has a frame shape that is continuous along the rectangular shape of the recess 5. In addition, the side surface 22 of the frame-shaped step portion 20C is perpendicular to the adjacent straight step portions 20a.

[0110] As shown in Figure 9, the frame-shaped stepped portion 20C has the inner edges of each of the four linear stepped portions 20a of the support surface 21 facing or in contact with the edges of the surface 4a that are in the outer region of the multiple solder ball 12 formation areas on the surface 4a of the IC chip 4.

[0111] In the configuration of Modified Example 1, when the IC chip 4 contacts the stepped portion 20, the IC chip 4 is supported by the stepped portion 20 around its entire circumference, thus providing stable support for the IC chip 4. Furthermore, compared to a configuration having stepped portions 20 along two opposing sides of the recess 5, the contact area of ​​the IC chip 4 with the stepped portion 20 is increased, improving heat dissipation from the IC chip 4 to the cavity substrate 3. Note that the stepped portion 20 formed along the rectangular sides of the recess 5 only needs to be formed along at least two opposing sides, and the stepped portion 20 may, for example, be formed along three sides of the rectangular shape formed by the recess 5.

[0112] (Modification 2) As shown in Figures 10A and 10B, in the modified example 2, the cavity substrate 3 has corner steps 20D formed at two diagonally opposite corners in the rectangular shape formed by the recess 5, as steps 20.

[0113] The support surface 21 of the corner step 20D has a rectangular shape. The corner step 20D also has two right-angled side surfaces 22.

[0114] As shown in Figure 11, the two corner steps 20D each face or contact the edge of the surface 4a of the IC chip 4, which is the outer region of the area where the multiple solder balls 12 are formed, with the inner corner of the support surface 21 facing or in contact with it.

[0115] Even with a configuration like that of Modification 2, the IC chip 4 can be supported when it comes into contact with the stepped portion 20, and the IC chip 4 can be positioned in the vertical direction.

[0116] (Variation 3) As shown in Figures 12A and 12B, in Modification 3, the cavity substrate 3 has corner stepped portions 20D formed at the four corners of the rectangular shape formed by the recess 5, as stepped portions 20. In other words, in Modification 3, corner stepped portions 20D are provided at the four corners of the recess 5.

[0117] As shown in Figure 13, each of the four corner steps 20D has its inner corner of the support surface 21 facing or in contact with the edge of the surface 4a of the IC chip 4, which is the area outside the formation site of the multiple solder balls 12 on the surface 4a.

[0118] In the configuration of Modified Example 3, when the IC chip 4 contacts the stepped portion 20, the rectangular IC chip 4 is supported by the stepped portions 20 at its four corners, thus providing stable support for the IC chip 4. Furthermore, compared to a configuration having corner stepped portions 20D at two opposing corners of the recess 5, the contact area of ​​the IC chip 4 with the stepped portion 20 is increased, thereby improving heat dissipation from the IC chip 4 to the cavity substrate 3. Note that the corner stepped portions 20D formed at the rectangular corners of the recess 5 only need to be formed at at least two opposing corners; for example, the corner stepped portions 20D may be formed at three corners of the rectangular shape formed by the recess 5.

[0119] (Modification 4) As shown in Figures 14A and 14B, in the modified example 4, the cavity substrate 3 has a stepped portion 20, which is a linear stepped portion 20E formed in the middle of each side so as to be along two opposing sides in the rectangular shape formed by the recess 5. The linear stepped portion 20E has side end faces 24 at both ends in its longitudinal direction (up and down direction in Figure 14A). The side end faces 24 are the surfaces facing the adjacent side 5b of the side 5b on which the linear stepped portion 20E is formed.

[0120] As shown in Figure 15, the inner edges of the two linear stepped portions 20E each face or come into contact with the edges of the surface 4a of the IC chip 4, which are the outer regions of the areas where multiple solder balls 12 are formed on the surface 4a of the IC chip 4.

[0121] Even with a configuration like that of Modification 4, the IC chip 4 can be supported when it comes into contact with the stepped portion 20, and the IC chip 4 can be positioned in the vertical direction. The linear stepped portion 20E formed along the rectangular sides of the recess 5 only needs to be formed along at least two opposing sides, and the linear stepped portion 20E may be formed, for example, along three or four sides of the rectangular shape formed by the recess 5.

[0122] (Variation 5) As shown in Figures 16A, 16B, and 17, in Modification 5, the stepped portion 20 is not formed in the cavity substrate 3. In other words, the semiconductor device 1A of Modification 5 does not have a stepped portion 20 in the recess 5. In the configuration of Modification 5, the opening shape of the recess 5 matches the shape of the bottom surface 5a, and the entire bottom of the recess 5 becomes the bottom surface 5a. In the semiconductor device 1A, the back surface 4b of the IC chip 4 and the back surface 3b of the cavity substrate 3 are located on a common horizontal virtual plane O1.

[0123] According to the configuration of Modified Example 5, since the stepped portion 20 is absent, the volume of the thermally conductive resin portion 25 increases. This allows the heat dissipation path from the IC chip 4 to the cavity substrate 3 via the thermally conductive resin portion 25 to be expanded, thereby effectively dissipating the heat generated from the IC chip 4 to the main substrate 2 via the cavity substrate 3.

[0124] (Experimental variation 6) As shown in Figure 18, the semiconductor device 1B of the modified example 6 includes an image sensor device 50 as an active component mounted on the surface 3a of the cavity substrate 3. The image sensor device 50 comprises an image sensor 51 which is a solid-state image sensor, a glass 52 which is a transparent material, a substrate 53 such as an organic substrate on which the image sensor 51 is mounted, and a rectangular frame-shaped resin frame 54 which supports the glass 52 on the substrate 53.

[0125] The image sensor device 50 has a package structure in which the image sensor 51 is positioned inside a frame 54 on a substrate 53, a glass 52 is mounted on the substrate 53 via the frame 54, and a cavity 55 is provided between the substrate 53 and the glass 52. The image sensor 51 is die-bonded to the substrate 53 by an adhesive layer 56 formed of a die-bonding material. The image sensor 51 and the substrate 53 are electrically connected to each other by a plurality of bonding wires 57.

[0126] The image sensor device 50 is mounted on the cavity substrate 3 by electrically connecting the substrate 53 to the surface 3a side of the cavity substrate 3. The substrate 53 is joined to the cavity substrate 3 by, for example, soldering. When the image sensor device 50 operates in the semiconductor device 1B, it becomes a heating element with the image sensor 51 as the heat source.

[0127] In the configuration of the modified example 6, heat dissipation from the image sensor device 50 is not hindered by heat dissipation from the IC chip 4, etc., in the cavity substrate 3, and heat can be efficiently dissipated from both the IC chip 4 and the image sensor device 50 to the main substrate 2.

[0128] (Example 7) As shown in Figure 19, the semiconductor device 1C of the modified example 7 includes a VCSEL (Vertical Cavity Surface Emitting Laser) 60 as an active component mounted on the surface 3a of the cavity substrate 3. The VCSEL 60 includes a light source 61 having a laser light-emitting element as a VCSEL.

[0129] The light source 61 has a predetermined emission surface from which laser light is emitted. The light source 61 is mounted on the surface 3a side of the cavity substrate 3 by a bonding layer 62 formed by die bonding or the like. The light source 61 and the cavity substrate 3 are electrically connected to each other by bonding wires 63. When the VCSEL 60 operates in the semiconductor device 1C, it becomes a heat source with the light source 61 as the heat source.

[0130] In the configuration of Modified Example 7, heat dissipation from the VCSEL 60 on the cavity substrate 3 is not hindered by heat dissipation from the IC chip 4, and heat can be efficiently dissipated from both the IC chip 4 and the VCSEL 60 to the main substrate 2.

[0131] <4. Example of semiconductor device configuration according to the second embodiment> An example of the configuration of a semiconductor device according to the second embodiment of this technology will be described with reference to Figures 20 to 22. Figure 20 is a cross-sectional view corresponding to the HH position in Figure 21. The semiconductor device 71 according to this embodiment differs from the first embodiment in the configuration of the connection terminals for external connection that the IC chip 4 has. In the embodiments described below, components common to the first embodiment are denoted by the same reference numerals and their descriptions are omitted as appropriate.

[0132] As shown in Figures 20 to 22, in the semiconductor device 71, the IC chip 4 has pillar bumps 80 as connection terminals for mounting on the cavity substrate 3. The pillar bumps 80 are formed as cylindrical protrusions on the surface 11a of the chip body 11.

[0133] The pillar bump 80 includes a copper layer 81, which is a metal layer made of copper or a copper-containing alloy, and a solder layer 82, which is provided on the tip side of the pillar bump 80 relative to the copper layer 81 and is formed of solder. The solder layer 82 is made of a solder material that mainly consists of tin (Sn) and contains silver (Ag). A barrier metal layer 83, made of a metallic material such as nickel (Ni) or gold (Au), is interposed between the copper layer 81 and the solder layer 82.

[0134] The pillar bumps 80 are provided with their base copper layer portion 81 connected to external connection terminal electrodes formed on the surface 11a of the chip body 11. Multiple pillar bumps 80 are formed, for example, in a two-dimensional grid-like arrangement that follows the rectangular outer shape of the chip body 11 (see Figure 21). The pillar bumps 80 serve as terminals for the electrical connection of the IC chip 4 to the cavity substrate 3.

[0135] The copper layer 81 is formed by plating, sputtering, vapor deposition, etc., of copper (Cu) or a copper alloy. The barrier metal layer 83 is formed on the leading edge surface of the copper layer 81 by plating, sputtering, vapor deposition, etc. Subsequently, the solder layer 82 is formed by applying flux-containing solder paste to the surface of the barrier metal layer 83 by a method such as transfer (printing).

[0136] In the example shown in Figure 22, the copper layer 81 and the solder layer 82 have approximately the same thickness (vertical dimension). However, the relative thicknesses of the layers forming the pillar bump 80 are not particularly limited.

[0137] In the manufacturing method of the semiconductor device 71 of this embodiment, in the step of mounting the IC chip 4 on the cavity substrate 3, with the cavity substrate 3 with its back surface 3b, which is the opening side of the recess 5, facing upwards, the IC chip 4 is set in a predetermined position within the recess 5 by a chip mounter or the like, and reflow is performed at a predetermined temperature. As a result, the solder layer portion 82 of the pillar bump 80 melts and solidifies to form a solder connection portion 82X, and the IC chip 4 is electrically connected to and fixed to the cavity substrate 3.

[0138] The height of the pillar bump 80X relative to the surface 4a of the IC chip 4, with the solder layer 82 becoming the solder connection portion 82X, is smaller than the height of the pillar bump 80 before mounting, which has the solder layer 82. The circuitry within the IC chip 4 is electrically connected to the wiring portion of the main substrate 2 via the pillar bump 80X and the wiring portion formed in the cavity substrate 3. The height of the pillar bump 80X is, for example, about 30 μm.

[0139] As shown in Figure 20, in the semiconductor device 71, the back surface 4b of the IC chip 4 and the back surface 3b of the cavity substrate 3 are located on a common horizontal virtual plane O1. That is, in the semiconductor device 71, the mounting height E1 of the IC chip 4 when mounted in the recess 5 of the cavity substrate 3 is equal to or approximately equal to the depth A2 of the recess 5 (see Figure 4). The mounting height E1 of the IC chip 4 is, for example, a value in the range of 0.1 to 1 mm.

[0140] Such a configuration is achieved by taking into account the difference in height between the pillar bump 80 before mounting and the pillar bump 80X after mounting, and by adjusting the depth of the recess 5 and the mounting portion of the IC chip 4 so that the mounting height E1 of the IC chip 4 on the cavity substrate 3 matches the depth A2 of the recess 5. Specifically, adjustments to the mounting portion of the IC chip 4 include, for example, adjusting the thickness and material of the solder layer 82 on the pillar bump 80.

[0141] Furthermore, if the difference in height between the pillar bump 80 before mounting and the pillar bump 80X after mounting, that is, the difference in thickness between the solder layer 82 and the solder connection 82X, is smaller than the gap between the surface 4a of the IC chip 4 and the support surface 21 of the stepped portion 20 (chip-step gap) when the solder layer 82 before melting is in contact with the bottom surface 5a of the recess 5, then the support surface 21 of the stepped portion 20 will have a small gap between it and the surface 4a of the IC chip 4, and will be in a state of facing (approximately in contact with) the surface 4a.

[0142] On the other hand, if the difference in thickness between the solder layer 82 and the solder connection portion 82X is greater than the gap between the chip and the stepped portion, the support surface 21 of the stepped portion 20 will be in contact with the surface 4a of the IC chip 4. In this state, the height B1 of the stepped portion 20 (see Figure 4) will be the same as the height of the pillar bump 80X after mounting.

[0143] As described above, the cavity substrate 3 is designed such that the height B1 of the stepped portion 20 in the recess 5 matches or approximately matches the height of the pillar bump 80X after mounting. In other words, by matching the height B1 of the stepped portion 20 to the height of the pillar bump 80X after mounting, the height of the back surface 4b of the IC chip 4 mounted on the cavity substrate 3 can be matched with the height of the back surface 3b of the cavity substrate 3, which is the mounting surface on the main substrate 2. Preferably, the height B1 of the stepped portion 20 is in the range of -10 μm to 0 μm relative to the height of the pillar bump 80X after mounting.

[0144] Here, if the height B1 of the stepped portion 20 is a negative value relative to the height of the pillar bump 80X after mounting, a gap exists between the chip and the stepped portion. Also, if the height B1 of the stepped portion 20 and the height of the pillar bump 80X after mounting are the same, that is, if the above value is -0 μm, the surface 4a of the IC chip 4 will be in contact with the support surface 21 of the stepped portion 20 at a position from the bottom surface 5a of the recess 5 to the height of the pillar bump 80X after mounting.

[0145] In other words, the above numerical range of -10 to 0 μm corresponds to the chip-to-step gap being less than 10 μm when the IC chip 4 is mounted on the cavity substrate 3. Note that it is undesirable for the height B1 of the step 20 to be greater than the height of the pillar bump 80X after mounting (i.e., the above value is positive) from the viewpoint of obtaining a good connection between the pillar bump 80X and the bottom surface 5a of the cavity substrate 3. Furthermore, the fact that the above numerical range is narrower than in the case of the first embodiment is based on the fact that the pillar bump 80 includes a copper layer 81 that does not melt when the IC chip 4 is mounted, and the solder layer 82 that melts when the IC chip 4 is mounted is smaller than the solder ball 12.

[0146] According to the semiconductor device 71 of this embodiment, similar to the semiconductor device 1 of the first embodiment, in a configuration in which the IC chip 4 is provided in a recess 5 of the cavity substrate 3 mounted on the main substrate 2, good heat dissipation can be obtained with a simple and inexpensive configuration. Furthermore, in this embodiment, since the IC chip 4 has pillar bumps 80 including a copper layer portion 81 as connection terminals to the cavity substrate 3, the dimensions of the pillar bumps 80X can be easily adjusted after mounting the IC chip 4.

[0147] In other words, because the copper layer 81 reduces the amount of solder that melts during reflow mounting of the IC chip 4 on the pillar bump 80 compared to the solder ball 12, the amount of deformation due to mounting is reduced, and thus the height fluctuation of the pillar bump 80X after mounting can be suppressed. As a result, variations in the mounting height of the IC chip 4 can be suppressed, and a configuration in which the back surface 4b of the IC chip 4 aligns with the virtual plane O1 on which the surface 3a of the cavity substrate 3 is located, in relation to the depth of the recess 5, can be easily realized.

[0148] <5. Example of semiconductor device configuration according to the third embodiment> An example of the configuration of a semiconductor device according to the third embodiment of this technology will be described with reference to Figure 23. In comparison with the first embodiment, the configuration of the thermally conductive resin portion 25 in the recess 5 of the cavity substrate 3 of the semiconductor device 91 according to this embodiment is different.

[0149] As shown in Figure 23, in the semiconductor device 91, the thermally conductive resin portion 25 has a high thermal conductivity resin portion 101 which is a first thermal conductive portion forming the lower part of the thermally conductive resin portion 25, and a low thermal conductivity resin portion 102 which is a second thermal conductive portion forming the upper part of the thermally conductive resin portion 25. That is, the thermally conductive resin portion 25 according to this embodiment has a high thermal conductivity resin portion 101 and a low thermal conductivity resin portion 102 as resin portions formed from two types of resins with different thermal conductivity characteristics in the upper and lower parts.

[0150] The high thermal conductivity resin portion 101 is formed from a first resin material having thermal conductivity and forms the main substrate 2 side (lower side) of the thermal conductivity resin portion 25. The low thermal conductivity resin portion 102 is formed from a second resin material having lower thermal conductivity than the first resin material and forms the opposite side (upper side) of the thermal conductivity resin portion 25 from the main substrate 2 side.

[0151] The high thermal conductivity resin portion 101 is provided as a side forming portion 25b of the thermal conductivity resin portion 25. That is, the high thermal conductivity resin portion 101 is provided as a portion of the thermal conductivity resin portion 25 that fills the space between the outer surface 4c of the IC chip 4 and the side surface 5b of the recess 5. The low thermal conductivity resin portion 102 is provided as an upper forming portion 25a of the thermal conductivity resin portion 25. That is, the low thermal conductivity resin portion 102 is provided as a portion of the thermal conductivity resin portion 25 that fills the gaps between multiple solder connection portions 12X and the gaps between the left and right stepped portions 20 and the solder connection portions 12X between the surface 4a of the IC chip 4 and the bottom surface 5a of the recess 5. The high thermal conductivity resin portion 101 and the low thermal conductivity resin portion 102 may be provided in contact with each other or in a non-contact state.

[0152] As the first resin material for forming the high thermal conductivity resin part 101, for example, a resin material with relatively high thermal conductivity having a thermal conductivity value of 2 W / (m·K) or more is used. As the second resin material for forming the low thermal conductivity resin part 102, for example, a resin material with relatively low thermal conductivity having a thermal conductivity value of less than 1 W / (m·K) is used. However, the thermal conductivity values ​​of the first resin material and the second resin material are not particularly limited. Both the first resin material and the second resin material are insulating.

[0153] The first and second resin materials can be, for example, thermosetting resins such as epoxy resins and polyimide resins, thermoplastic resins such as polyamide-imide, polypropylene, and liquid crystal polymers, rubber, and other known resin materials, either individually or in combination. Regarding the first resin material, its thermal conductivity can be increased relative to the second resin material by including a highly thermally conductive filler, such as one primarily composed of silicon oxide.

[0154] <6. Method for manufacturing a semiconductor device according to the third embodiment> A method for manufacturing the semiconductor device 91 according to the third embodiment of this technology will be described with reference to Figure 24. In the method for manufacturing the semiconductor device 91 according to this embodiment, in the step of forming the thermally conductive resin part 25, the low thermal conductivity resin part 102 is formed first, and then the high thermal conductivity resin part 101 is formed.

[0155] First, as shown in Figure 24A, a step is taken to form a low thermal conductivity resin portion 102 in the recess 5 of the cavity substrate 3 on which the IC chip 4 is mounted. Here, a second resin material 102X, which will become the low thermal conductivity resin portion 102, is extruded, for example, from the nozzle of a dispenser and applied to fill the gap between the bottom surface 5a of the cavity substrate 3 and the surface 4a of the IC chip 4 within the recess 5, from the gap around the IC chip 4 in the recess 5.

[0156] The second resin material 102X filled into the recess 5 is cured at a predetermined time to form a low thermal conductivity resin portion 102. If the second resin material 102X is a thermosetting resin, after the step of filling the recess 5 with the second resin material 102X, a step of heating the second resin material 102X at a predetermined temperature to cure it is performed. As a result, the low thermal conductivity resin portion 102 is formed as shown in Figure 24A.

[0157] Next, as shown in Figure 24B, a step is taken to form a high thermal conductivity resin portion 101 within the recess 5 where the low thermal conductivity resin portion 102 is formed. Here, the first resin material 101X, which will become the high thermal conductivity resin portion 101, is dispensed, for example, from the nozzle of a dispenser and applied to fill the gap around the IC chip 4 within the recess 5.

[0158] The first resin material 101X filled into the recess 5 is cured at a predetermined time to form a high thermal conductivity resin portion 101. If the first resin material 101X is a thermosetting resin, after the step of filling the recess 5 with the first resin material 101X, a step of heating the first resin material 101X at a predetermined temperature to cure it is performed. As a result, as shown in Figure 24B, a high thermal conductivity resin portion 101 is formed, and a first package structure 41 is obtained in which the IC chip 4 is mounted in the recess 5 of the cavity substrate 3 to form a thermal conductivity resin portion 25. Other steps are the same as in the first embodiment.

[0159] According to the semiconductor device 91 of this embodiment, similar to the semiconductor device 1 of the first embodiment, in a configuration in which an IC chip 4 is provided in a recess 5 of a cavity substrate 3 mounted on a main substrate 2, good heat dissipation can be obtained with a simple and inexpensive configuration. Furthermore, in this embodiment, by creating differences in thermal conductivity depending on the part of the resin filling in the recess 5, it is possible to control the heat dissipation path of the heat generated by the IC chip 4, thereby effectively improving heat dissipation.

[0160] For example, in a configuration in which a solid-state imaging device 30, which acts as a heat-generating element, is mounted on the surface 3a side of the cavity substrate 3, as shown in Figure 23 of the semiconductor device 91 according to this embodiment, the following effects can be obtained. With regard to heat conduction from the IC chip 4 to the cavity substrate 3, heat conduction from the outer surface 4c side of the IC chip 4, where the relatively high thermal conductivity resin portion 101 is located, is superior to heat conduction from the surface 4a side of the IC chip 4, where the relatively low thermal conductivity resin portion 102 is located, to the cavity substrate 3. In other words, the main heat dissipation path from the IC chip 4 to the cavity substrate 3 is the path via the high thermal conductivity resin portion 101, compared to the path via the low thermal conductivity resin portion 102 (see Figure 23, dashed arrow F1).

[0161] Furthermore, the heat generated by the IC chip 4 is dissipated to the solder-jointed main substrate 2 via the layer 16 with relatively high conductivity (see Figure 23, dashed arrow F2). Thus, the main heat dissipation paths from the IC chip 4 are the heat dissipation path from the outer surface 4c side via the high thermal conductivity resin part 101 (F1) and the heat dissipation path from the back surface 4b side via the solder layer 16 (F2).

[0162] On the other hand, the heat generated in the solid-state imaging device 30 is dissipated from the cavity substrate 3 to the main substrate 2 via the solder layer 6 (see Figure 23, dashed arrow F3).

[0163] These factors prevent heat from accumulating in the cavity substrate 3 due to interference between heat dissipation from the IC chip 4 and the solid-state image device 30 in the area sandwiched between the IC chip 4 and the solid-state image device 30. This allows heat generated from both the IC chip 4 and the solid-state image device 30 to be efficiently dissipated to the main substrate 2. Specifically, by making the upper portion of the thermally conductive resin portion 25, on the side where the solid-state image device 30 is located relative to the IC chip 4, a low thermal conductivity resin portion 102 can be used, thereby suppressing heat dissipation from the IC chip 4 to the solid-state image device 30. This allows the heat dissipation paths from the IC chip 4 and the solid-state image device 30 to be separated, resulting in more efficient heat dissipation.

[0164] <7. Modified Examples of Semiconductor Devices According to the Third Embodiment> A modified example of the semiconductor device 91 according to this embodiment will now be described. In this modified example, as shown in Figure 25, the low thermal conductivity resin portion 102 is omitted in the thermal conductivity resin portion 25. In other words, in this modified example, only the high thermal conductivity resin portion 101 corresponding to the side forming portion 25b is formed as the thermal conductivity resin portion 25, and a cavity 103 exists between the surface 4a of the IC chip 4 in the recess 5 and the bottom surface 5a of the recess 5.

[0165] This modified configuration can be easily realized, for example, by using a cavity substrate 3 having a frame-shaped stepped portion 20C as shown in Figures 8A and 8B. That is, when mounting the IC chip 4 on the cavity substrate 3 having the frame-shaped stepped portion 20C (see Figure 6D), the surface 4a of the IC chip 4 is brought into close contact with the support surface 21 of the frame-shaped stepped portion 20C around its entire circumference, thereby forming a cavity 103 as a sealed space between the surface 4a and the bottom surface 5a of the recess 5. Subsequently, similar to the process of forming the high thermal conductivity resin portion 101 shown in Figure 24B, a resin material is filled into the recess 5 to fill the gap around the IC chip 4 and then cured, thereby forming a thermal conductivity resin portion 25 between the outer surface 4c of the IC chip 4 and the side surface 5b of the recess 5 without allowing the resin material to penetrate into the cavity 103.

[0166] With this modified configuration, the cavity 103 above the IC chip 4 within the recess 5 can act as a heat insulating section, thereby suppressing heat dissipation from the IC chip 4 to the solid-state imaging device 30. This prevents interference between the heat generated by the IC chip 4 and the solid-state imaging device 30 in the cavity substrate 3, enabling efficient heat dissipation.

[0167] <8. Examples of Electronic Device Configurations> An example of applying the semiconductor device according to the above embodiment to electronic equipment will be explained with reference to Figure 26. Here, the semiconductor device 1,71,91 equipped with a solid-state imaging device 30 as an active component will be referred to as the imaging device 210, and an example of the application of the semiconductor device 1,71,91 will be described.

[0168] The imaging device 210 is applicable to all electronic devices that use an image sensor in the image acquisition unit (photoelectric conversion unit), such as camera devices like digital still cameras and video cameras, portable terminal devices with imaging functions, and photocopiers that use an image sensor in the image reading unit. The image sensor may be formed as a single chip, or it may be in the form of a module with imaging functions in which the imaging unit and the signal processing unit or optical system are packaged together.

[0169] As shown in Figure 26, the camera device 200 as an electronic device comprises an optical unit 202, an imaging device 210, a DSP (Digital Signal Processor) circuit 203 which is a camera signal processing circuit, a frame memory 204, a display unit 205, a recording unit 206, an operation unit 207, and a power supply unit 208. The DSP circuit 203, frame memory 204, display unit 205, recording unit 206, operation unit 207, and power supply unit 208 are appropriately connected via connection lines 209 such as bus lines.

[0170] The optical unit 202 includes multiple lenses and captures incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 210. The imaging device 210 converts the amount of incident light formed on the imaging surface by the optical unit 202 into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal.

[0171] The display unit 205 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro-Luminescence) panel, and displays video or still images captured by the imaging device 210. The recording unit 206 records the video or still images captured by the imaging device 210 onto a recording medium such as a hard disk or semiconductor memory.

[0172] The control unit 207 issues operation commands for various functions of the camera device 200 under the user's control. The power supply unit 208 appropriately supplies various power sources to the DSP circuit 203, frame memory 204, display unit 205, recording unit 206, and control unit 207.

[0173] With the camera device 200 described above, in the imaging device 210, the IC chip 4 is provided in a recess 5 of the cavity substrate 3 mounted on the main substrate 2, and good heat dissipation can be obtained with a simple and inexpensive configuration. As a result, the camera device 200 can maintain a good operating state and obtain the desired characteristics.

[0174] The above-described embodiments are merely examples of the present technology, and the present technology is not limited to the embodiments described above. Therefore, even with embodiments other than those described above, various modifications are possible depending on the design, etc., as long as they do not depart from the technical concept of this disclosure. Furthermore, the effects described in this disclosure are merely examples and not limiting, and other effects may also exist. In addition, the configurations of each of the above-described embodiments and their modified configurations can be combined as appropriate.

[0175] This technology can be widely used as a heat dissipation measure for component mounting module products.

[0176] In the embodiment described above, the connection terminals of the IC chip 4 are solder balls 12 or pillar bumps 80, but are not limited to these, and may be other connection terminals such as gold bumps or plated bumps.

[0177] Furthermore, in the embodiments described above, soldering using solder material is used for the metal bonding of the IC chip 4 to the main substrate 2, but the bonding of the IC chip 4 to the main substrate 2 may also be done using metal bonding with other metal materials.

[0178] Furthermore, in the embodiment described above, the thermally conductive resin portion 25 provided in the recess 5 of the cavity substrate 3 has an upper forming portion 25a and a side forming portion 25b, but the formation area of ​​the thermally conductive resin portion 25 is not particularly limited. The thermally conductive resin portion 25 only needs to be formed so as to contact both the IC chip 4 and the cavity substrate 3 within the recess 5. Therefore, the thermally conductive resin portion 25 does not need to fill the recess 5 completely, and may be partially formed within the recess 5, for example, having only one of the upper forming portion 25a and the side forming portion 25b.

[0179] Furthermore, in the embodiment described above, the stepped portion 20 in the recess 5 is formed as part of the cavity substrate 3, but the stepped portion 20 may also be provided by attaching a separate component to the cavity substrate 3. However, from the viewpoint of ease of manufacturing and reduction of the number of parts, it is preferable that the stepped portion 20 be provided as part of the cavity substrate 3.

[0180] Furthermore, the semiconductor elements included in the semiconductor device relating to this technology are not limited to the IC chip 4 in the above-described embodiment, but may also be other semiconductor chips such as optical elements such as photodetectors. Also, the active components included in the semiconductor device relating to this technology are not limited to the solid-state imaging device 30, image sensor device 50, and VCSEL 60 in the above-described embodiment, but may also be other components or devices that generate heat in the semiconductor device, such as memory or other LSIs (Large Scale Integrations).

[0181] Furthermore, this technology can be configured as follows: (1) Main board and A cavity substrate mounted on the main substrate has a recess formed on the back surface, which is the board surface of the main substrate, A semiconductor element is located within the recess, mounted on the cavity substrate, with one side facing the main substrate positioned on the same or substantially the same plane as the back surface of the cavity substrate, and is metal-bonded to the main substrate. Semiconductor equipment. (2) The cavity substrate has a stepped portion in the recess that contacts the other surface of the semiconductor element, which is the surface opposite to the one surface of the semiconductor element, thereby restricting the semiconductor element from sinking into the recess. The semiconductor device described in (1) above. (3) The recess includes a bottom surface parallel to the back surface of the cavity substrate and a plurality of side surfaces formed around the bottom surface. The stepped portion includes a first surface parallel to the bottom surface and facing or in contact with the other surface of the semiconductor element, and a second surface that forms a step between the first surface and the bottom surface. The semiconductor device described in (2) above. (4) The recess is formed in a rectangular shape, including the bottom surface and the four sides. The stepped portion is formed along at least two opposing sides of the rectangular shape formed by the recess. The semiconductor device described in (3) above. (5) The recess is formed in a rectangular shape, including the bottom surface and the four sides. The stepped portion is formed at at least two diagonally opposite corners in the rectangular shape formed by the recess. The semiconductor device described in (3) above. (6) A heat conduction portion made of a thermally conductive material is provided within the recess to fill the gap between the cavity substrate and the semiconductor element. A semiconductor device as described in any one of (1) to (5) above. (7) The aforementioned heat conduction section is A first heat conduction portion is formed from a first resin material having thermal conductivity and forms the portion of the heat conduction portion on the main substrate side, The present invention has a second heat conduction portion formed of a second resin material having a lower thermal conductivity than the first resin material, and which forms the portion of the heat conduction portion opposite to the main substrate side. The semiconductor device described in (6) above. (8) A metal film made of a metallic material is formed on one side of the semiconductor element. A semiconductor device as described in any one of (1) to (7) above. (9) The semiconductor element has connection terminals for mounting on the cavity substrate, The aforementioned connection terminal includes a metal layer made of copper or a copper-containing alloy, and a solder layer made of solder provided on the tip side of the connection terminal relative to the metal layer. A semiconductor device as described in any one of (1) to (8) above. (10) The cavity substrate comprises active components mounted on the side opposite to the back surface. A semiconductor device as described in any one of (1) to (9) above. (11) Main board and A cavity substrate mounted on the main substrate has a recess formed on the back surface, which is the board surface of the main substrate, A semiconductor element is located within the recess, mounted on the cavity substrate, with one side facing the main substrate positioned on the same or substantially the same plane as the back surface of the cavity substrate, and is metal-bonded to the main substrate. Semiconductor equipment electronic equipment. [Explanation of Symbols]

[0182] 1 Semiconductor device 2 Main board 3 Cavity substrate 3b back side 4 IC chips (semiconductor devices) 4a Surface (the other side) 4b Reverse side (one side) 5 recesses 5a Bottom 5b side 12 solder balls 14. Sputtered film (metal film) 15. Plating film (metal film) 20 steps 20A First linear step 20B 2nd linear step 20C Frame step 20D Corner Step 20E Straight step 21 Support surface (first surface) 22 Side view (second side) 25. Thermally conductive resin part (thermal conductive part) 30. Solid-state imaging device (active component) 50 Image sensor device (active component) 60 VCSEL (Active Components) 80 Pillar bump (connection terminal) 81 Copper layer part (metal layer part) 82 Solder layer 101 High thermal conductivity resin part (first thermal conductive part) 102 Low thermal conductivity resin part (second thermal conductivity part) 200 Camera equipment (electronic devices) 210 Imaging device

Claims

1. Main board and A cavity substrate mounted on the main substrate has a recess formed on the back surface, which is the board surface of the main substrate, The device comprises a semiconductor element located within the recess, mounted on the cavity substrate, with one side facing the main substrate positioned on the same or substantially the same plane as the back surface of the cavity substrate, and metal-bonded to the main substrate, The cavity substrate has a stepped portion in the recess that contacts the other surface of the semiconductor element, which is the surface opposite to the one surface of the semiconductor element, thereby restricting the semiconductor element from sinking into the recess. Semiconductor equipment.

2. The recess includes a bottom surface parallel to the back surface of the cavity substrate and a plurality of side surfaces formed around the bottom surface. The stepped portion includes a first surface that is parallel to the bottom surface and faces or contacts the other surface of the semiconductor element, and a second surface that forms a step between the first surface and the bottom surface. The semiconductor device according to claim 1.

3. The recess is formed in a rectangular shape, including the bottom surface and the four sides. The stepped portion is formed along at least two opposing sides of the rectangular shape formed by the recess. The semiconductor device according to claim 2.

4. The recess is formed in a rectangular shape, including the bottom surface and the four sides. The stepped portion is formed at at least two diagonally opposite corners in the rectangular shape formed by the recess. The semiconductor device according to claim 2.

5. A heat conduction portion made of a thermally conductive material is provided within the recess to fill the gap between the cavity substrate and the semiconductor element. A semiconductor device according to any one of claims 1 to 4.

6. The aforementioned heat conduction section is A first heat conduction portion formed of a first resin material having thermal conductivity and forming the portion of the heat conduction portion on the main substrate side, The material has a second heat conduction portion formed of a second resin material having a lower thermal conductivity than the first resin material, and which forms the portion of the heat conduction portion opposite to the main substrate side. The semiconductor device according to claim 5.

7. A metal film made of a metallic material is formed on one side of the semiconductor element. A semiconductor device according to any one of claims 1 to 6.

8. The semiconductor element has connection terminals for mounting on the cavity substrate, The aforementioned connection terminal includes a metal layer made of copper or a copper-containing alloy, and a solder layer made of solder provided on the tip side of the connection terminal relative to the metal layer. A semiconductor device according to any one of claims 1 to 7.

9. The cavity substrate comprises active components mounted on the side opposite to the back surface. A semiconductor device according to any one of claims 1 to 8.

10. Main board and A cavity substrate mounted on the main substrate has a recess formed on the back surface, which is the board surface of the main substrate, The device comprises a semiconductor element located within the recess, mounted on the cavity substrate, with one side facing the main substrate positioned on the same or substantially the same plane as the back surface of the cavity substrate, and metal-bonded to the main substrate, The cavity substrate has a stepped portion in the recess that contacts the other surface of the semiconductor element, which is the surface opposite to the one surface of the semiconductor element, thereby restricting the semiconductor element from sinking into the recess. Semiconductor equipment electronic equipment.

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