Successive approximation A / D converter

Abstract

A capacitive array D / A converter 110 samples an input voltage IN and outputs a signal corresponding to a threshold voltage VTH based on the input voltage IN and control data ctrl. A comparison circuit 120, responsive to the output of the capacity array D / A converter 110, performs a comparison process in accordance with a comparison clock cmpclk. A clock generation circuit 130 generates a successive-approximation register clock sarclk. A logic circuit 140 supplies the comparison clock cmpclk based on the successive-approximation register clock sarclk to the comparison circuit. The logic circuit 140 makes a determination of normality if the successive-approximation register clock sarclk is detected for a predetermined second number of cycles before an external clock AD16CLK is detected for a predetermined first number of cycles since the start of an A / D conversion operation; if not, the logic circuit 140 makes a determination of abnormality.

Description

Technical Field

[0001] The present disclosure relates to a successive approximation type A / D converter.

Background Art

[0002] As a medium-resolution to high-resolution (for example, 8 bits or more) A / D converter (ADC: Analog Digital Converter), a successive approximation type (SAR: Successive Approximation Register) is used. The SAR ADC samples and holds an input voltage and compares it with a first threshold voltage. Then, according to the comparison result, a second threshold voltage is determined and the comparison is performed again. By repeating this operation, an analog voltage is converted into a digital signal by binary search.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure relates to a SAR ADC, and an exemplary object of one of its aspects is to provide a successive approximation type A / D converter capable of detecting conversion abnormalities.

Means for Solving the Problems

[0005] A part of this disclosure relates to a successive approximation type A / D converter. The successive approximation type A / D converter includes a capacitive array type D / A converter that samples an input voltage, converts control data into a threshold voltage, and outputs a signal corresponding to the input voltage and the threshold voltage; a comparator circuit that receives the output of the capacitive array type D / A converter and performs a comparison process according to a comparison clock; a clock generation circuit that generates a successive comparison clock based on the output of the comparator circuit; and a logic circuit that receives a comparison signal indicating the comparison result of the comparator circuit and the successive comparison clock, updates the control data, and supplies a comparison clock based on the successive comparison clock to the comparator circuit. The logic circuit determines that the operation is normal if it detects the successive comparison clock for a predetermined second number of cycles before detecting an external clock for a predetermined first number of cycles from the start of the A / D conversion operation, and determines that the operation is abnormal if it has not detected the successive comparison clock for a predetermined second number of cycles when it has detected the external clock for a predetermined first number of cycles.

[0006] Furthermore, any combination of the above components, or conversion of the expressions of this disclosure between methods, apparatus, etc., are also valid embodiments of the present invention. [Effects of the Invention]

[0007] According to certain aspects of this disclosure, anomalies can be detected. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing the basic configuration of SARADC according to an embodiment. [Figure 2] Figure 2 illustrates the operation of SARADC under normal conditions. [Figure 3] Figure 3 illustrates the operation of SARADC when an abnormality occurs. [Figure 4] Figure 4 is a circuit diagram showing a specific configuration example of SARADC. [Figure 5] Figure 5 is a circuit diagram showing an example of the configuration of an anomaly detection circuit. [Figure 6]Figure 6 is a circuit diagram showing a specific example of the configuration of an anomaly detection circuit. [Figure 7] Figure 7 is a time chart illustrating the normal operation of SARADC as shown in Figure 4. [Figure 8] Figure 8 is a time chart illustrating the operation of SARADC during an abnormal situation, as shown in Figure 4. [Figure 9] Figure 9 is a circuit diagram of SARADC according to Modification 1. [Modes for carrying out the invention]

[0009] (Summary of the embodiment) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow. It is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify essential elements of all embodiments or to delineate the scope of some or all aspects. For convenience, “one embodiment” may be used to refer to one or more embodiments (examples or variations) disclosed herein.

[0010] A successive approximation A / D converter according to one embodiment includes a capacitive array type D / A converter that samples the input voltage, converts the control data into a threshold voltage, and outputs a signal corresponding to the input voltage and the threshold voltage; a comparator circuit that receives the output of the capacitive array type D / A converter and performs a comparison process according to a comparison clock; a clock generation circuit that generates a successive comparison clock based on the output of the comparator circuit; and a logic circuit that receives a comparison signal indicating the comparison result of the comparator circuit and the successive comparison clock, updates the control data, and supplies a comparison clock based on the successive comparison clock to the comparator circuit. The logic circuit determines that the operation is normal if it detects the successive comparison clock for a predetermined second number of cycles before detecting the external clock for a predetermined first number of cycles from the start of the A / D conversion operation, and determines that it is abnormal if it has not detected the successive comparison clock for a predetermined second number of cycles when it has detected the external clock for a predetermined first number of cycles.

[0011] In this configuration, a sequential comparison clock and a comparison clock are exchanged between the comparator circuit and the logic circuit, generating an asynchronous, self-propelled clock. The sequential comparison process of the successive approximation A / D converter is then performed asynchronously with respect to the external clock, based on this self-propelled clock. The external clock is used to define a time limit for the completion of the A / D conversion process, and if the A / D conversion process is not completed within this time limit, it can be determined to be an abnormality.

[0012] When this A / D converter is viewed externally, it is guaranteed that the output data of the A / D converter is finalized after the first cycle of the external clock has elapsed, regardless of the frequency of the A / D converter's internal clock.

[0013] In one embodiment, the logic circuit includes a first circuit that asserts a first timing signal after an external clock has occurred for a first number of cycles after an assertion of a start signal indicating the start of the conversion operation of the A / D converter, and a second circuit that asserts a second timing signal after a successive comparison clock has occurred for a second number of cycles after the assertion of the start signal, and a determination circuit that generates a fail signal indicating the presence or absence of an abnormality based on the first timing signal and the second timing signal.

[0014] In one embodiment, the first circuit may include a counter synchronized with an external clock, and may be configured to be able to read the count value of the counter when the second timing signal is asserted. This count value can be used for optimization of parameters and debugging at the design stage. Also, during actual operation, the stability of circuit operation and the like can be confirmed by referring to this count value from a microcontroller that controls the A / D converter.

[0015] In one embodiment, the second circuit may include an enable data generation circuit that generates enable data having the same number of bits as the number of bits of the output data of the successive comparison type A / D converter, and in which a bit that is 1 shifts from the most significant bit to the least significant bit for each cycle of the successive comparison clock. The second circuit may assert the second timing signal when the next successive comparison clock occurs in a state where the least significant bit of the enable data is 1. Thereby, the second timing signal indicates the timing at which the processing of all bits ends.

[0016] In one embodiment, the comparison circuit may include a first delay circuit that delays a comparison clock, and a comparator that compares the output of the capacitive array type D / A converter according to the latch clock delayed by the first delay circuit. The first delay circuit can define the frequency of the self-running clock.

[0017] In one embodiment, the first delay circuit may be a variable delay circuit. Thereby, the frequency of the self-running clock can be adjusted.

[0018] In one embodiment, the delay time of the first delay circuit may be settable from the outside.

[0019] In one embodiment, the successive approximation type A / D converter may further include a delay time adjustment circuit that automatically adjusts the delay time of the first delay circuit.

[0020] In one embodiment, the comparator is a differential comparator having two outputs. When the latch clock is at the first level, the two outputs become high. When the latch clock is at the second level, one of the two outputs becomes low according to the comparison result. The clock generation circuit may include a NAND gate that receives the two outputs of the comparator.

[0021] In one embodiment, after the start of the A / D conversion operation, the logic circuit generates a seed pulse synchronized with an external clock, and the seed pulse may be input to the clock generation circuit. Thereby, the timing of the start of A / D conversion can be synchronized with the external clock.

[0022] In one embodiment, the successive approximation type A / D converter may further include a second delay circuit that delays the output of the clock generation circuit and generates a successive approximation clock. Thereby, the operation timing of the logic circuit can be adjusted.

[0023] In one embodiment, the successive approximation type A / D converter may be integrally integrated on one semiconductor substrate. "Integral integration" includes cases where all components of the circuit are formed on the semiconductor substrate and cases where the main components of the circuit are integrally integrated. For adjustment of circuit constants, some resistors, capacitors, etc. may be provided outside the semiconductor substrate. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of circuit elements can be kept uniform.

[0024] (Embodiment)

[0025] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0026] Similarly, "the state in which member C is connected (provided) between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the function or effect produced by their combination.

[0027] Figure 1 is a block diagram showing the basic configuration of a successive approximation type A / D converter (SARADC) 100 according to an embodiment. The SARADC 100 is integrated as a single unit on a semiconductor substrate. The SARADC 100 may be a dedicated chip for the A / D converter, or it may be integrated into an IC (Integrated Circuit) with other functions.

[0028] First, let's explain the inputs and outputs of the SARADC100. The SARADC100 converts an analog input voltage input to the input terminal IN into digital N-bit (N is an integer greater than or equal to 2) output data AD16DAT. In this embodiment, SARADC100 has N=16 bits, and the output data is denoted as AD16DAT[15:0]. The input signal IN may be a single-ended signal or a differential signal.

[0029] The SARADC100 is supplied with at least one reference voltage VREF.

[0030] The SARADC100 is supplied with an external clock (system clock) AD16CLK. The SARADC100 also receives a start signal AD16CNV to instruct the start of A / D conversion. The SARADC100 basically operates in synchronization with the external clock AD16CLK, but the successive comparison process is performed based on a clock generated internally by the SARADC100 (collectively referred to as the internal clock), and is therefore asynchronous with the external clock AD16CLK. After asserting the start signal AD16CNV, the SARADC100 asserts (for example, high) the flag (end signal) AD16FLG, which indicates the confirmation of the output data AD16DAT[15:0].

[0031] As described below, the SARADC100 has an anomaly detection feature. When the SARADC100 detects an anomaly (specifically, an A / D conversion failure), it asserts the fail signal AD16CNVFAIL (for example, high).

[0032] The above describes the inputs and outputs of the SARADC100. Next, we will explain its configuration.

[0033] The SARADC100 includes a capacitive array type D / A converter 110, a comparator circuit 120, a clock generation circuit 130, and a logic circuit 140.

[0034] The capacitive array type D / A converter 110, comparator circuit 120, and clock generation circuit 130 are formed in the analog block 102, and the logic circuit 140 is formed in the digital block 104. If the power supply voltages of the analog block 102 and the digital block 104 are different, a level shifter 106 is provided between the analog block 102 and the digital block 104.

[0035] The capacitive array type D / A converter 110 includes multiple capacitors and multiple switches. The capacitive array type D / A converter 110 can be constructed using known techniques. The capacitive array type D / A converter 110 samples the input voltages INP and INN using a reference voltage VREF, and internally generates a threshold voltage VTH corresponding to the control data ctrl.

[0036] The capacitive array D / A converter 110 receives a timing signal vins generated by the logic circuit 140. The timing signal vins is a signal that instructs the sampling of the input voltage IN. The capacitive array D / A converter 110 uses the input voltage IN to charge its internal capacitor and samples the input voltage IN during the period when the timing signal vins is asserted (e.g., high).

[0037] The capacitive array D / A converter 110 receives control data ctrlk from the logic circuit 140 during the k (k=1,2,…) cycle of the successive conversion. The capacitive array D / A converter 110 converts the control data ctrlk into a threshold voltage VTHk. The capacitive array D / A converter 110 then outputs a signal corresponding to the input voltage IN and the threshold voltage VTHk.

[0038] The comparison circuit 120 receives the output of the capacitive array type D / A converter 110 and performs comparison processing according to the comparison clock cmpclk. The comparison clock cmpclk is supplied from the logic circuit 140.

[0039] The comparison circuit 120 outputs a comparison signal comp that indicates the comparison result. For example, the comparison signal comp is H (high) when the input signal IN is greater than the threshold voltage VTHk, and L (low) when it is less than the threshold voltage VTHk.

[0040] The clock generation circuit 130 generates a successive approximation clock sarclk based on the output comp of the comparison circuit 120. The successive approximation clock sarclk, along with the comparison signal comp, is supplied to the logic circuit 140.

[0041] The logic circuit 140 receives the comparison signal comp, which indicates the comparison result from the comparison circuit 120, and the successive comparison clock sarclk, and updates the control data ctrl, which defines the threshold voltage VTH in the next successive comparison cycle. This process is similar to that of a typical SARADC.

[0042] Furthermore, logic circuit 140 generates a comparison clock cmpclk based on the successive comparison clock sarclk and supplies it to comparison circuit 120. In Figure 1, the comparison clock cmpclk and the successive comparison clock sarclk are shown as simply flowing on signal line 142, but in reality, the comparison clock cmpclk is delayed relative to the successive comparison clock sarclk.

[0043] The signal line 142, the comparator circuit 120, and the clock generation circuit 130 form a delay loop 144. During one cycle of propagation within this delay loop 144, the clock signal is logically inverted an odd number of times. In other words, this delay loop 144 can be understood as a ring oscillator. The oscillation frequency of the ring oscillator (delay loop) 144 depends on its delay time, and the comparator clock cmpclk and the successive comparator clock sarclk become self-propelled clocks asynchronous with the external clock AD16CLK.

[0044] The logic circuit 140 includes an anomaly detection circuit 200. The anomaly detection circuit 200 counts the number of cycles of the external clock AD16CLK and the successive conversion clock sarclk from the start of the A / D conversion operation, in other words, from the assertion of the start signal AD16CNV. The anomaly detection circuit 200 determines that the operation is normal and negates the fail signal AD16CNVFAIL if it detects the successive comparison clock sarclk for a predetermined second number of cycles (CYC2) before detecting the external clock AD16CLK for a predetermined first number of cycles (CYC1).

[0045] Conversely, the abnormality detection circuit 200 determines that an abnormality exists if it fails to detect the external clock AD16CLK for the first cycle (CYC1) or the successive comparison clock sarclk for the second cycle (CYC2) before detecting it from the start of the A / D conversion operation, and asserts the fail signal AD16CNVFAIL.

[0046] The time Tend from the start of A / D conversion until the first cycle (CYC1) of the external clock AD16CLK occurs is: Tend = CYC1 × 1 / fext This is represented as follows: fext is the frequency of the external clock AD16CLK, and 1 / fext represents the period of the external clock AD16CLK. This time Tend is the time limit for when the SARADC100 is functioning correctly and the A / D conversion should be completed.

[0047] If the sequential conversion clock sarclk is detected at its second cycle (CYC2) before the external clock AD16CLK is detected at its first cycle (CYC1), it means that the conversion process for all 16 bits is completed before the time limit, and the output data AD16DAT[15:0] is finalized. In other words, it means that the A / D conversion process has completed successfully.

[0048] Conversely, if the external clock AD16CLK is detected at the first cycle (CYC1), but the sequential conversion clock sarclk is not detected at the second cycle (CYC2), it means that the conversion of all 16 bits has not been completed before the time limit. In other words, the A / D conversion process has failed.

[0049] The second cycle number, CYC2, can be defined according to the number of bits N of the SARADC100 (16 in this example). In a 16-bit SARADC, 16 successive comparison operations are required to determine the output AD16DAT[15:0] of all 16 bits, and therefore, the A / D conversion is completed in 16 cycles of the successive comparison clock sarclk. The second cycle number, CYC2, should be set to be equal to or longer than the number of bits N of the SARADC100. CYC2≧N

[0050] The A / D conversion is considered complete when the successive comparison clock sarclk reaches its second cycle (CYC2) and is detected.

[0051] During the design phase of the SARADC100, the frequency of the successive conversion clock sarclk, which is known from the circuit design values, can be determined from the design values. Therefore, the conversion time Tsarfin required for the A / D conversion process of the SARADC100 is: Tsarfin = CYC2 × (1 / fint) It can be estimated as follows: 1 / fint is the period of the self-propelled clock.

[0052] The first cycle number CYC1 can be determined based on the conversion time Tsarfin and the frequency fext of the external clock AD16CLK. For example, CYC1 = Tsarfin × fext + CYCmergin The first cycle number, CYC1, may be defined as shown above. CYCmargin is the cycle number margin, but it may be set to 0.

[0053] The above describes the configuration of the SARADC100. Next, we will explain its operation.

[0054] Figure 2 illustrates the operation of the SARADC100 under normal conditions.

[0055] Here, we assume that CYC1 = 19 and CYC2 = 16.

[0056] When the start signal AD16CNV is asserted, the logic circuit 140 injects a seed pulse SP into the delay loop 144, which is a ring oscillator. Here, a seed pulse SP with a length of 4 cycles of the external clock AD16CLK is injected. Using this seed pulse SP as a seed, the delay loop 144 oscillates, and the successive approximation clock sarclk is generated.

[0057] The logic circuit 140 counts the external clock AD16CLK after the start signal AD16CNV is asserted. The time limit Tend occurs after CYC1 = 19 cycles have elapsed.

[0058] For each pulse of the successive comparison clock sarclk, successive comparison is performed, and the output data AD16DAT[15:0] is determined in order from the most significant bit (MSB) to the least significant bit. Then, when the successive comparison clock sarclk is detected for 16 cycles (=CYC2) before the time limit Tend, the abnormality detection circuit 200 determines that it is normal.

[0059] After the elapse of the first cycle count CYC1, for example, at the 20th cycle, which is one cycle after the first cycle count CYC1, the logic circuit 140 asserts the end signal AD16FLG.

[0060] Since SARADC100 is normal, the fail signal AD16CNVFAIL is negated (L).

[0061] Figure 3 is a diagram for explaining the operation of SARADC100 when it is abnormal.

[0062] After the start signal AD16CNV is asserted, the logic circuit 140 counts the external clock AD16CLK. The time limit Tend is reached after the elapse of CYC1 = 19 cycles.

[0063] For each pulse of the successive comparison clock sarclk, successive comparison is performed, and the output data AD16DAT[15:0] is determined in order from the most significant bit (MSB) to the least significant bit.

[0064] When the time limit Tend has elapsed, the successive comparison clock sarclk has only been detected for 14 cycles (<CYC2). Therefore, the abnormality detection circuit 200 determines that it is abnormal.

[0065] After the elapse of the first cycle count CYC1, for example, at the 20th cycle, which is one cycle after the first cycle count CYC1, the logic circuit 140 asserts the end signal AD16FLG.

[0066] Since SARADC100 is abnormal, the fail signal AD16CNVFAIL is asserted (H).

[0067] The above describes the operation of SARADC100. With SARADC100, the successive comparison clock sarclk and the comparison clock cmpclk are exchanged between the comparison circuit 120 and the logic circuit 140, generating self-propelled clocks sarclk and cmpclk that are asynchronous with the external clock AD16CLK. The successive comparison process of SARADC100 is performed asynchronously with the external clock AD16CLK, based on these self-propelled clocks.

[0068] In this method, the setting of the threshold voltage VTH to the comparator circuit 120 and the comparator operation in the comparator circuit 120 are in accordance with the comparator clock cmpclk, which is a delayed signal of the successive comparator clock sarclk from one cycle prior. Therefore, it is guaranteed that the data required by the comparator circuit 120 (control signal ctrlk) is determined when the comparator circuit 120 is operating.

[0069] Similarly, the digital signal processing in logic circuit 140 is in response to the successive approximation clock sarclk, which is a delayed version of the comparison clock cmpclk of the same cycle. Therefore, it is guaranteed that the signal necessary for signal processing (comparison signal comp) is determined at the time of signal processing in logic circuit 140.

[0070] If the comparator circuit 120 and the logic circuit 140 are operated in synchronization with the external clock AD16CLK, a timing violation will occur and the successive comparison operation will fail if the frequency of the external clock AD16CLK deviates from the normal range. In contrast, in this embodiment, since a self-propelled clock is used, there is an advantage that timing violations are less likely to occur even if the frequency of the external clock AD16CLK fluctuates.

[0071] When SARADC100 is viewed externally, it is guaranteed that the output data AD16DAT[15:0] of SARADC100 is finalized after the first cycle (CYC1) of the external clock AD16CLK has elapsed, regardless of the frequency of SARADC100's internal clocks sarclk and cmpclk.

[0072] Furthermore, by detecting the successive comparison clock sarclk at the second cycle number CYC2, it is possible to detect when the successive comparison processing of all bits has been completed. Then, using the external clock AD16CLK, a time limit is set for when the A / D conversion process should be completed, and if the A / D conversion process is not completed within this time limit, it can be determined to be an abnormality.

[0073] This disclosure extends to various devices and methods as understood in the block diagram and circuit diagram of Figure 1, or derived from the above description, and is not limited to any particular configuration. More specific configuration examples and embodiments are described below, not to narrow the scope of this disclosure, but to aid in understanding and clarifying the essence and operation of this disclosure and the present invention.

[0074] Figure 4 is a circuit diagram showing a specific configuration example (100A) of the SARADC100. The SARADC100A receives differential inputs INP and INN and generates 16-bit digital data AD16DAT[15:0]. First, the configuration of the analog block 102 will be explained.

[0075] The capacitive array D / A converter 110 receives differential inputs INP and INN. The capacitive array D / A converter 110 also receives reference voltages VREF50 (e.g., 5V), VREF0 (e.g., 0V), and VCM (e.g., a midpoint voltage of 2.5V). The capacitive array D / A converter 110 samples the input voltages INP and INN according to the timing signal vins.

[0076] Furthermore, in the k-th cycle, the capacitive array type D / A converter 110 uses the reference voltages VREF50 and VREF0 to generate differential threshold voltages VTHPk and VTHNk corresponding to the control signal ctrlk.

[0077] The capacitive array type D / A converter 110 outputs signals daoutp and daoutn corresponding to the differential inputs INP and INN and the differential threshold voltages VTHP and VTHN. For example, the following relationship holds: daoutp = A × (INP - VTHPk) daoutn = A × (INN - VTHNk) A is the gain.

[0078] The comparison circuit 120 receives the outputs daoutp and daoutn from the capacitive array type D / A converter 110 and performs comparison processing according to the comparison clock cmpclk. The comparison clock cmpclk is supplied from the logic circuit 140.

[0079] The comparison signal comp, which is the output of the comparison circuit 120, is daoutp<daoutnのときH(ハイ)、daoutp> When daoutn, it becomes L (low). In other words, the comparison signal comp shows the result of comparing the signal components of the differential input (INP-INN) with the signal components of the reference voltage (VTHP-VTHN).

[0080] The comparison circuit 120 includes a comparator 122 and a first delay circuit 124. The first delay circuit 124 delays the comparison clock cmpclk and generates a latch clock latchclk.

[0081] Comparator 122 compares the outputs daoutp and daoutn of comparator circuit 120 in accordance with the latch clock latchclk.

[0082] In this embodiment, the comparator 122 has differential outputs compop and compon. The comparison signal comp is one of the differential outputs compop. For example, when the latch clock latchclk is at the first level (e.g., H), both differential outputs compop and compon of the comparator 122 become H. Also, when the latch clock latchclk is at the second level (e.g., L), one of the differential outputs compop and compon becomes H and the other becomes L, depending on the relative magnitudes of daoutp and daoutn.

[0083] The clock generation circuit 130 receives the outputs compop and compon from the comparator circuit 120 and generates a successive approximation clock sarclk. The clock generation circuit 130 includes a logic gate 132 and a second delay circuit 134. The logic gate 132 is a NAND gate that receives the two outputs compop and compon from the comparator 122. The logic gate 132 outputs one pulse each time the comparator circuit 120 operates. The second delay circuit 134 delays the output of the logic gate 132 and outputs it to the logic circuit 140 as a successive approximation clock sarclk.

[0084] By providing the second delay circuit 134, the operating timing of the logic circuit 140 can be adjusted. Specifically, for example, a setup margin for comparison data can be secured.

[0085] The NAND gate, which is logic gate 132, has an inverting input. The timing signal vins generated by logic circuit 140 is input to this inverting input as a seed pulse SP. The ring oscillator starts operating when the timing signal vins is injected into the delay loop 144 as a seed pulse SP.

[0086] Next, I will explain the configuration of the digital block 104.

[0087] The logic circuit 140 includes a SAR processing unit 160, a clock processing unit 162, a timing processing unit 164, and an anomaly detection circuit 200.

[0088] The processing related to the clock signal in the logic circuit 140 is consolidated in the clock processing unit 162. The clock processing unit 162 receives the external clock AD16CLK as input. The clock processing unit 162 buffers the external clock AD16CLK and supplies it to the timing processing unit 164 as the timing clock TIMCLK. The timing processing unit 164 operates in synchronization with the timing clock TIMCLK. The successive approximation clock sarclk from the analog block 102 is output to the analog block 102 as the comparison clock cmpclk via the clock processing unit 162. The successive approximation clock sarclk is also input to the SAR processing unit 160 as the successive approximation clock SARCLK.

[0089] The SAR processing unit 160 operates in synchronization with the successive approximation clock SARCLK. The SAR processing unit 160 determines the current bit value SAR_Data in response to the comparison signal comp from the approximation circuit 120 in the k-th cycle, determines the threshold voltage VTH(k+1) for the next cycle k+1 by binary search, and outputs the control signal ctrl.

[0090] The timing processing unit 164 controls the timing of the logic circuit 140 and the analog block 102. Specifically, the timing processing unit 164 outputs the signals AD16DAT[15:0], AD16FLG, and AD16CNVFAIL generated by the analog block 102 and the digital block 104 in synchronization with the external clock AD16CLK. It also receives the start signal AD16CNV input from an external source in synchronization with the external clock AD16CLK. The timing processing unit 164 generates various timing signals (such as vins) in synchronization with the external clock AD16CLK.

[0091] The timing processing unit 164 receives the sample period cycle setting signal AD16VINSL[4:0]. The length of the timing signal vins (number of cycles of the external clock AD16CLK) is set according to this setting signal AD16VINSL[4:0].

[0092] As described above, the anomaly detection circuit 200 performs time-related processing, such as counting the number of cycles of the external clock AD16CLK. Therefore, the anomaly detection circuit 200 can be implemented as part of the timing processing unit 164, or it can be implemented by sharing some hardware with the timing processing unit 164.

[0093] The timing processing unit 164 receives the sample period cycle setting signal AD16VINSL[4:0] as well as the successive comparison period cycle setting signal AD16SARL[4:0]. These setting signals AD16SARL[4:0] and AD16VINSL[4:0] define the first cycle number CYC1, which defines the time limit.

[0094] Figure 5 is a circuit diagram showing an example configuration of the anomaly detection circuit 200. The anomaly detection circuit 200 includes a first circuit 210, a second circuit 220, and a determination circuit 230. The first circuit 210 asserts the start signal AD16CNV, which indicates the start of the conversion operation of SARADC100A, and then asserts the first timing signal r_flgen after the external clock AD16CLK has been generated for the first cycle number CYC1. The first timing signal r_flgen indicates a time limit.

[0095] The second circuit 220 asserts the start signal AD16CNV, and after the successive comparison clock sarclk has been generated for 2 cycles (CYC2), it asserts the second timing signal r_sarfin.

[0096] The determination circuit 230 generates a fail signal AD16CNVFAIL, which indicates the presence or absence of an abnormality, based on the first timing signal r_flgen and the second timing signal r_sarfin. Specifically, if the assertion of the second timing signal r_sarfin is earlier than the assertion of the first timing signal r_flgen, it is determined to be normal, and the fail signal AD16CNVFAIL is negated. Conversely, if the assertion of the first timing signal r_flgen is earlier than the assertion of the second timing signal r_sarfin, the fail signal AD16CNVFAIL is asserted.

[0097] For example, the first circuit 210 and the determination circuit 230 can be configured as part of the timing processing unit 164. The second circuit 220 can also be configured as part of the SAR processing unit 160.

[0098] Figure 6 is a circuit diagram showing a specific configuration example of the anomaly detection circuit 200. The first circuit 210 includes a counter 212. The counter 212 performs counting operations synchronized with the external clock AD16CLK. When the external clock AD16CLK reaches the first cycle number CYC1, the counter 212 asserts the first timing signal r_flgen.

[0099] The operation of counter 212 is set by the successive approximation period cycle setting signal AD16SARL[4:0] and the sample period cycle setting signal AD16VINSL[4:0]. The sum of the successive approximation period cycle setting signal AD16SARL[4:0] and the sample period cycle setting signal AD16VINSL[4:0] gives the initial value of counter 212, for example, "14h". Counter 212 is a down counter and counts down with each cycle of the external clock AD16CLK, and when the value of the count value r_cnvcnt[5:0] reaches a predetermined value (for example, "03h"), it asserts the first timing signal r_flgen.

[0100] The first circuit 210 includes a memory (register) 214 that holds the count value of the counter 212 when the second timing signal r_sarfin is asserted. This memory 214 may be readable from a tester during testing of the SARADC100A. It may also be readable from an external microcontroller of the SARADC100A when the SARADC100A is mounted on an electronic device.

[0101] This count value can be used for parameter optimization and debugging during the design phase. Furthermore, during actual operation, the microcontroller controlling the A / D converter can refer to this count value to verify the stability of the circuit operation.

[0102] The second circuit 220 includes an enable data generation circuit 222, a selector 224, and a flip-flop 226. The enable data generation circuit 222 generates enable data w_daten[15:0]. The enable data w_daten[15:0] has the same number of bits as the SARADC100A and indicates the position of the bit currently being processed. That is, the enable data w_daten[15:0] initially has the most significant bit as 1 and the rest as 0, and as the sequential comparison progresses, the position of the bit with a value of 1 moves towards the least significant bit. Finally, when all bits become 0, the processing ends. In other words, the value of the enable data w_daten[15:0] expressed in hexadecimal is initially "8000h", then changes to "4000h", "2000h", and finally becomes "0001h" and "0000h".

[0103] Selector 224 receives the value "1" and the output of flip-flop 226. The initial value of flip-flop 226 is 0. Selector 224 selects the output of flip-flop 226 when the value of enable data w_daten[15:0] is not "0001h", and selects the value "1" when the value of enable data w_daten[15:0] is "0001h".

[0104] When the value of the enable data w_daten[15:0] is "0001h", the value of flip-flop 226 changes from 0 to 1 when the next successive approximation clock sarclk is input, and the second timing signal r_sarfin is asserted. This indicates that all bits have been processed.

[0105] The determination circuit 230 includes flip-flops 232 and 234, a selector 236, and a flip-flop 238. The determination circuit 230 receives the first timing signal r_flgen generated by the first circuit 210 and the second timing signal r_sarfin generated by the second circuit 220 as inputs.

[0106] The second timing signal r_sarfin is asynchronous with the external clock AD16CLK. The two-stage flip-flops 232 and 234 synchronize the second timing signal r_sarfin with the external clock AD16CLK. The output r_sarfin2 of flip-flop 234 is input to selector 236.

[0107] Selector 236 receives the inverted output of flip-flop 234 and the output of flip-flop 238. The initial value of flip-flop 238 is 0. Selector 236 selects the output of flip-flop 238 while the first timing signal r_flgen is negated (0). When the first timing signal r_flgen is asserted (1), selector 236 selects the inverted signal / r_sarfin2 of the output of flip-flop 234.

[0108] When the first timing signal r_flgen is asserted, if the second timing signal r_sarfin is asserted, the fail signal AD16CNVFAIL, which is the output of flip-flop 238, remains low (negated). When the first timing signal r_flgen is asserted, if the second timing signal r_sarfin is negated, the fail signal AD16CNVFAIL, which is the output of flip-flop 238, is asserted (high).

[0109] The above is the configuration of the SAR ADC 100A and the abnormality detection circuit 200.

[0110] FIG. 7 is a time chart for explaining the normal operation of the SAR ADC 100A in FIG. 4. r_vinscnt[4:0] is the count value of a counter that defines the sampling period of the input signal (the pulse width of the timing signal vins). While this counter counts down, the timing signal vins becomes high. This timing signal vins becomes the seed pulse, the delay loop 144 starts oscillating, and the successive comparison clock sarclk and the comparison clock cmpclk become active.

[0111] The value (hexadecimal value) of the enable data w_daten[15:0] decreases according to the successive comparison clock sarclk, and when it becomes "0000h" at time t0, the second timing signal r_sarfin is asserted. The timing signal r_sarfin2 after synchronization by the external clock AD16CLK is asserted at time t1. Also, after the start signal AD16CNV is asserted, at time t2 in the 19th cycle, the first timing signal r_flgen is asserted.

[0112] Since t1 < t2, the fail signal AD16CNVFAIL is negative. After the start signal AD16CNV is asserted, at time t3 in the 20th cycle, the end signal AD16FLG is asserted. Triggered by the end signal AD16FLG, the value of the output data AD16DAT[15:0] is determined.

[0113] Figure 8 is a time chart illustrating the operation of the SARADC100A in abnormal conditions as shown in Figure 4. When the value (hexadecimal value) of the enable data w_daten[15:0] becomes "0000h" at time t0, the second timing signal r_sarfin is asserted. The timing signal r_sarfin2, synchronized by the external clock AD16CLK, is asserted at time t1. This time t1 is later than time t2, the 19th cycle when the first timing signal r_flgen is asserted. As a result, the fail signal AD16CNVFAIL is asserted.

[0114] The above describes the operation of the SARADC100A and the anomaly detection circuit 200. The anomaly detection circuit 200 can detect anomalies in the SARADC100A.

[0115] The embodiments described above are illustrative, and it will be understood by those skilled in the art that various modifications are possible in combinations of their components and processing steps. Such modifications will be described below.

[0116] (Variation 1) Figure 9 is a circuit diagram of SARADC100B according to Modification 1. In SARADC100B, the first delay circuit 124 is composed of a variable delay circuit. The delay amount of the first delay circuit 124 can be set according to the delay time setting signal clkdly[2:0] from the logic circuit 140. The delay time of the first delay circuit 124 can be adjusted to control the round trip time of the delay loop 144, i.e., the frequencies of the self-propelled clocks cmpclk and sarclk.

[0117] In this modified example, logic circuit 140B includes a delay time adjustment circuit 170 in addition to the logic circuit 140 in Figure 4. The delay time adjustment circuit 170 is active in calibration mode. The delay time adjustment circuit 170 automatically adjusts the delay time of the first delay circuit 124 using the delay setting signal clkdly[2:0] so that the fail signal AD16CNVFAIL is not asserted.

[0118] For example, in calibration mode, the delay time adjustment circuit 170 sweeps the delay setting signal clkdly[2:0] and monitors the fail signal AD16CNVFAIL for each value. It may then select a value for the delay setting signal clkdly[2:0] such that the fail signal AD16CNVFAIL is not asserted.

[0119] Alternatively, the delay time adjustment circuit 170 may determine the value of the delay setting signal clkdly[2:0] based on the count value stored in the memory 214 in Figure 6.

[0120] (Modification 2) The delay time setting signal clkdly[2:0] may be set externally from the SARADC100B using a register or similar method.

[0121] Those skilled in the art will understand that the embodiments are illustrative, and that various modifications exist for each component and combination of processing steps, and that such modifications are also included within the scope of this disclosure or the present invention. [Industrial applicability]

[0122] This disclosure relates to a successive approximation type A / D converter. [Explanation of Symbols]

[0123] 100 SARADC 102 Analog Blocks 104 Digital Blocks 106 Level Shifter 110 Capacitive Array Type D / A Converter 120 Comparison circuit 122 Comparator 124 First Delay Circuit 130 Clock generation circuit 132 Logic Gates 134 Second Delay Circuit 140 Logic Circuits 142 signal line 144 Delay Loop 160 SAR Processing Unit 162 Clock Processing Unit 164 Timing Processing Unit 170 Delay Time Adjustment Circuit 200 Anomaly detection circuit 210 1st circuit 212 counters 214 memory 220 2nd circuit 222 Enable Data Generation Circuit 224 Selector 226 Flip-Flops 230 Judgment circuit 232,234 flip-flops 236 Selector 238 Flip-flops comp comparison signal cmpclk comparison clock sarclk Sequential approximation clock AD16CLK External Clock AD16CNV Start Signal AD16FLG Termination signal AD16CNVFAIL Fail signal AD16DATA Output Data VREF50 Reference Voltage VCM Common Voltage VREF00 Reference Voltage INP, INN Input Signals

Claims

1. A successive approximation A / D converter, A capacitive array type D / A converter that samples the input voltage, converts the control data into a threshold voltage, and outputs a signal corresponding to the input voltage and the threshold voltage, A comparison circuit that receives the output of the aforementioned capacitive array type D / A converter and performs comparison processing according to the comparison clock, A clock generation circuit that generates a successive comparison clock based on the output of the comparison circuit, A logic circuit that receives a comparison signal indicating the comparison result of the comparison circuit and the successive comparison clock, updates the control data, and supplies the comparison clock based on the successive comparison clock to the comparison circuit, Equipped with, The logic circuit determines that the operation is normal if the successive approximation clock is detected for a predetermined second number of cycles before the external clock is detected for a predetermined first number of cycles from the start of the A / D conversion operation, and determines that the operation is abnormal if the successive approximation clock is not detected for the second number of cycles at the time the external clock is detected for the first number of cycles.

2. The aforementioned logic circuit is A first circuit asserts a first timing signal after the start signal indicating the start of the A / D converter's conversion operation has been asserted, and after the external clock has generated the first number of cycles. A second circuit asserts a second timing signal after the start signal has been asserted and the successive comparison clock has occurred for the second number of cycles. A determination circuit that generates a fail signal indicating the presence or absence of the abnormality based on the first timing signal and the second timing signal, A successive approximation A / D converter according to claim 1, comprising:

3. The successive approximation A / D converter according to claim 2, wherein the first circuit includes a counter synchronized with the external clock and is configured to read the count value of the counter when the second timing signal is asserted.

4. The second circuit is, Enable data having the same number of bits as the output data of the successive approximation A / D converter, and including an enable data generation circuit that generates the enable data in which the bits that are 1 shift from the most significant bit to the least significant bit with each cycle of the successive approximation clock, The successive approximation A / D converter according to claim 2 or 3, wherein the second timing signal is asserted when the next successive approximation clock occurs while the least significant bit of the enable data is 1.

5. The aforementioned comparison circuit is A first delay circuit that delays the comparison clock, A comparator that compares the output of the capacitive array type D / A converter in accordance with the latch clock delayed by the first delay circuit, A successive approximation A / D converter according to any one of claims 1 to 3, including the following:

6. The successive approximation A / D converter according to claim 5, wherein the first delay circuit is a variable delay circuit.

7. The successive approximation A / D converter according to claim 6, wherein the delay time of the first delay circuit is set externally.

8. The successive approximation A / D converter according to claim 6, further comprising a delay time adjustment circuit for automatically adjusting the delay time of the first delay circuit.

9. The comparator is a differential comparator having two outputs, where the two outputs are high when the latch clock is at a first level, and one of the two outputs is low depending on the comparison result when the latch clock is at a second level. The successive approximation A / D converter according to claim 5, wherein the clock generation circuit includes a NAND gate that receives the two outputs of the comparator.

10. The logic circuit generates a seed pulse synchronized with the external clock after the A / D conversion operation has started. The successive approximation A / D converter according to any one of claims 1 to 3, wherein the seed pulse is input to the clock generation circuit.

11. The successive approximation A / D converter according to any one of claims 1 to 3, further comprising a second delay circuit that delays the output of the clock generation circuit and generates the successive approximation clock.

12. A successive approximation type A / D converter according to any one of claims 1 to 3, which is integrated as a single semiconductor substrate.

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