Memory and method for manufacturing the same

Abstract

The memory of this solution can reduce the difficulty of the process technology while improving the storage density.SOLUTION: The present invention relates to the field of semiconductor technology, and in particular to a memory and a manufacturing method thereof, wherein the memory comprises a substrate and at least one storage layer, the storage layer is formed on the substrate, and the storage layer comprises a storage unit; The storage unit cell comprises a first gate, a first semiconductor layer at least horizontally surrounding a peripheral side of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer, the first gate comprises a gate bottom wall and a gate sidewall, the gate sidewall is disposed horizontally surrounding the gate bottom wall and extends in a direction away from the substrate, and the gate sidewall and the gate bottom wall form a surrounding gate groove; The write transistor includes a second gate, a second semiconductor layer surrounding an outer peripheral side of the second gate at least in a horizontal direction, and a second gate insulating layer formed between the second gate and the second semiconductor layer, and a part of the second semiconductor layer is fitted into the gate groove and is in contact with at least a part of the gate groove.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a memory and a manufacturing method thereof.

Background Art

[0002] With the miniaturization of technology nodes, the storage cells of DRAM (Dynamic Random Access Memory) have gradually changed from a 1T1C structure (a combination of one transistor and one capacitor) to a planar 2T0C structure (that is, two transistors are arranged horizontally and there is no capacitor). However, with such a design, the storage density of DRAM is still low and the manufacturing process is complicated.

Summary of the Invention

[0003] The present invention provides a memory and a manufacturing method thereof that can reduce the difficulty of process technology while improving the storage density.

[0004] A first aspect of the present disclosure provides a memory including a substrate and at least one storage layer, the storage layer being formed on the substrate, the storage layer including storage cells, the storage cells including a read transistor and a write transistor, the read transistor including a first gate, a first semiconductor layer at least horizontally surrounding an outer peripheral side of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer, the first gate including a gate bottom wall and a gate side wall, the gate side wall being installed horizontally surrounding the gate bottom wall, extending in a direction away from the substrate, and the gate side wall and the gate bottom wall forming a surrounding gate trench, The writing transistor comprises a second gate, a second semiconductor layer that surrounds the outer periphery of the second gate at least horizontally, and a second gate insulating layer formed between the second gate and the second semiconductor layer, wherein a portion of the second semiconductor layer is fitted into the gate groove and is in contact with at least a portion of the gate groove.

[0005] In some exemplary embodiments of the present disclosure, the second semiconductor layer, the second gate, and the second gate insulating layer each have a fitted portion that is fitted into the gate groove and an extension portion located on one side of the fitted portion away from the substrate, wherein the extension portion is positioned to protrude away from the substrate relative to the read transistor.

[0006] In some exemplary embodiments of the present disclosure, the storage cell further comprises an insulating medium sidewall which is fitted into the gate groove and horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer. The outer circumferential surface of the fitting portion of the second semiconductor layer is installed insulated from the gate sidewall by the insulating medium sidewall, and the bottom surface of the fitting portion of the second semiconductor layer is in contact with the gate bottom wall.

[0007] In some exemplary embodiments of the present disclosure, the insulating medium sidewall comprises a low dielectric material portion, the low dielectric material portion horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer, and / or The insulating medium sidewall comprises a silicon dioxide material layer, and the silicon dioxide material layer horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer.

[0008] In some exemplary embodiments of the present disclosure, the second semiconductor layer settling portion comprises a second semiconductor sidewall and a second semiconductor bottom wall, wherein the second semiconductor sidewall is positioned horizontally surrounding the second semiconductor bottom wall and extends away from the substrate, the second semiconductor sidewall and the second semiconductor bottom wall form a second semiconductor groove, and the second gate settling portion and the second gate insulating layer settling portion are located within the second semiconductor groove. The bottom surface of the second semiconductor bottom wall and the bottom surface of the second semiconductor side wall are both in contact with the bottom surface of the gate groove.

[0009] In some exemplary embodiments of the present disclosure, the storage layer further comprises a first signal line and a second signal line, The first signal line is formed on the substrate, and the first signal line extends in a first horizontal direction and contacts the bottom region of the bottom surface and / or the outer peripheral surface of the first semiconductor layer. The second signal line is formed on one side of the first signal line away from the substrate, a first interlayer insulating layer is formed between the layer on which the second signal line is located and the layer on which the first signal line is located, the second signal line extends in a second horizontal direction intersecting the first horizontal direction, the second signal line and the first interlayer insulating layer horizontally surround the outer periphery of the first semiconductor layer, the second signal line contacts the upper region of the outer periphery of the first semiconductor layer, one of the first signal line and the second signal line is a read bit line and the other is a read word line.

[0010] In some exemplary embodiments of the present disclosure, the first semiconductor layer is formed on one side of the first signal line away from the substrate, the first semiconductor layer comprises a first semiconductor sidewall and a first semiconductor bottom wall, the first semiconductor sidewall is positioned horizontally surrounding the first semiconductor bottom wall and extends away from the substrate, and the first semiconductor sidewall and the first semiconductor bottom wall form surrounding a first semiconductor groove. The first gate insulating layer comprises a first gate insulating side wall and a first gate insulating bottom wall, wherein the first gate insulating bottom wall is located within the first semiconductor groove and contacts the upper surface of the first semiconductor bottom wall, the first gate insulating side wall is located at least within the first semiconductor groove and is installed horizontally surrounding the first gate insulating bottom wall, the first gate insulating side wall extends in a direction away from the substrate and is formed surrounding the first gate insulating bottom wall and the first gate insulating groove, and the outer peripheral surface of the first gate insulating side wall contacts the inner peripheral surface of the first semiconductor side wall. The gate bottom wall is located within the first gate insulation groove and is in contact with the upper surface of the first gate insulation bottom wall, and the gate side wall is located within the first gate insulation groove, and the outer peripheral surface of the gate side wall is in contact with the inner peripheral surface of the first gate insulation side wall.

[0011] In some exemplary embodiments of the present disclosure, the upper surface of the first semiconductor sidewall, the upper surface of the first gate insulating sidewall, and the upper surface of the gate sidewall are flush with the upper surface of the second signal line, or The upper part of the first semiconductor sidewall has a first semiconductor wrap portion extending horizontally outward, and the first semiconductor wrap portion is formed on the upper surface of the second signal line. The upper part of the first gate insulating sidewall has a first gate insulating wrap portion extending horizontally outward, and the first gate insulating wrap portion is formed on the upper surface of the first semiconductor wrap portion. The upper part of the gate sidewall has a gate wrap portion extending horizontally outward, and the gate wrap portion is formed on the upper surface of the first gate insulating wrap portion.

[0012] In some exemplary embodiments of the present disclosure, the storage layer further comprises write bit lines and write word lines, The write bit line is formed on one side of the second signal line away from the substrate, a second interlayer insulating layer is formed between the layer where the write bit line is located and the layer where the second signal line is located, the write bit line and the second interlayer insulating layer horizontally surround the outer periphery of the extension of the second semiconductor layer, and the write bit line is in contact with the outer periphery of the first semiconductor layer. The write word line is formed on one side of the write bit line and the extension of the second gate, away from the substrate, a third interlayer insulating layer is formed between the layer where the write word line is located and the layer where the write bit line is located, and the write word line is connected to the upper surface of the extension of the second gate. One of the write bit line and the write word line extends in a first horizontal direction, and the other extends in a second horizontal direction.

[0013] In some exemplary embodiments of the present disclosure, the write bit line extends in a first horizontal direction, the write word line extends in a second horizontal direction, and / or The upper part of the extension of the second semiconductor layer has a second semiconductor wrap portion extending horizontally outward, the second semiconductor wrap portion is formed on the upper surface of the write bit line, the upper part of the extension of the second gate insulating layer has a second gate insulating wrap portion extending horizontally outward, the second gate insulating wrap portion is formed on the upper surface of the second semiconductor wrap portion, the upper surface of the extension of the second gate is flush with the upper surface of the second gate insulating wrap portion, the storage layer further comprises a conductive contact pad, the bottom surface of the conductive contact pad is in contact with the upper surface of the second gate insulating wrap portion and the upper surface of the extension of the second gate, and the top surface of the conductive contact pad is in contact with the bottom surface of the write word line.

[0014] In some exemplary embodiments of the present disclosure, the number of storage layers is multiple, and the multiple storage layers are stacked perpendicular to the substrate, and of two adjacent storage layers, the storage layer closer to the substrate is defined as the bottom storage layer, and the storage layer further away from the substrate is defined as the top storage layer. In at least two adjacent storage layers, a fourth interlayer insulating layer is formed between the layer where the first signal line of the top storage layer is located and the layer where the write word line of the bottom storage layer is located, and / or In at least two adjacent storage layers, the write word line of the bottom storage layer is shared as the first signal line of the top storage layer.

[0015] A second aspect of this disclosure provides a method for manufacturing a memory, the manufacturing method being: The steps include providing a substrate and The step of forming at least one storage layer on the substrate is included. The step of forming the aforementioned preservation layer is, A step of forming a readout transistor on the substrate, wherein the readout transistor comprises a first gate, a first semiconductor layer that surrounds the outer periphery of the first gate at least horizontally, and a first gate insulating layer formed between the first gate and the first semiconductor layer, the first gate comprises a gate bottom wall and a gate side wall, the gate side wall is installed horizontally surrounding the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall are formed surrounding a gate groove, A step of forming a storage cell by forming a writing transistor in the gate groove, wherein the writing transistor comprises a second gate, a second semiconductor layer that surrounds the outer periphery of the second gate at least horizontally, and a second gate insulating layer formed between the second gate and the second semiconductor layer, and a part of the second semiconductor layer is fitted into the gate groove and in contact with at least a part of the gate groove.

[0016] The technical solutions provided by embodiments of this disclosure have at least the following advantages:

[0017] This invention, by vertically fitting a portion of the CAA-type write transistors within the storage cell into the CAA-type read transistors, can reduce the horizontal area occupied by the storage cell while maintaining storage density, and also reduce the vertical height of the storage cell, compared to a planar 2T0C-type storage cell. In other words, the overall volume of the storage cell can be reduced, meaning the space occupied by the storage cell is reduced, allowing more storage cells to be placed within a given volume of memory, thereby improving the memory's storage density.

[0018] In addition, by disposing the semiconductor layer of the write transistor in the gate groove of the gate of the read transistor to make direct contact with the gate of the read transistor, the connection between the write transistor and the read transistor is realized. Compared with the planar 2T0C type storage cell, since there is no need to design an additional connection pattern for connecting the write transistor and the read transistor together, the requirements for the photolithography process in the manufacturing process can be reduced, the product yield can be improved, and the manufacturing cost can be reduced.

Brief Description of the Drawings

[0019] The accompanying drawings here are incorporated into this specification, form a part of this specification, and show embodiments consistent with the present disclosure, and are helpful for interpreting the principles of the present disclosure together with the specification. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative work. [Figure 1] It is a schematic diagram showing the structure of a memory according to different embodiments of the present disclosure. [Figure 2] It is a schematic diagram showing the structure of a memory according to different embodiments of the present disclosure. [Figure 3] It is a schematic diagram showing the structure of a memory according to different embodiments of the present disclosure. [Figure 4] It is a schematic diagram showing the structure of a memory according to different embodiments of the present disclosure. [Figure 5] It is a schematic diagram showing the structure of a memory according to different embodiments of the present disclosure. [Figure 6] It is a schematic diagram showing the structure of a memory according to different embodiments of the present disclosure. [Figure 7] They are respectively schematic diagrams showing the structure in the manufacturing method of the memory of the present disclosure after different steps are executed. [Figure 8] They are respectively schematic diagrams showing the structure in the manufacturing method of the memory of the present disclosure after different steps are executed. [Figure 9]These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 10] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 11] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 12] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 13] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 14] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 15] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 16] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 17] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 18] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 19] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 20] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 21] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 22]These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 23] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Figure 24] These are schematic diagrams showing the structure of the memory manufacturing method of the present disclosure after different steps have been performed. [Modes for carrying out the invention]

[0020] The following describes the exemplary embodiments in more detail with reference to the attached drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as being limited to the examples described herein. Rather, by providing these embodiments, the present application becomes more comprehensive and complete, and the ideas of the exemplary embodiments can be comprehensively conveyed to those skilled in the art.

[0021] Furthermore, the described features, structures, or properties can be combined in any preferred manner in one or more embodiments. Many specific details are provided in the following description to provide a complete understanding of the embodiments of the present application. However, those skilled in the art will understand that it is possible to implement the technical embodiments of the present application without one or more specific details, or to employ other methods, components, apparatus, steps, etc. In other cases, well-known methods, apparatus, implementations, or operations are not shown or described in detail so as not to obscure the embodiments of the present application.

[0022] This application is described in further detail below in reference to the accompanying drawings and specific embodiments. It should be noted that the technical features relating to the various embodiments of the application described below can be combined with each other, insofar as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are illustrative and are intended for use in interpreting the application, and should not be understood as limiting the application.

[0023] Embodiments of this disclosure provide a memory which may include a substrate and at least one storage layer.

[0024] The memory according to the embodiment of this disclosure will be described in detail below with reference to the attached drawings.

[0025] Referring to Figure 1, the substrate 1 may have a multilayer structure. For example, the substrate 1 may include a semiconductor base layer 10 and an insulating base layer 11 formed on the semiconductor base layer 10. The semiconductor base layer 10 may include a semiconductor material such as single-crystal silicon, but is not limited to this, and may also include a semiconductor material such as germanium (Ge). The insulating base layer 11 may include an insulating material such as silicon dioxide, but is not limited to this, and depending on the actual situation, the insulating base layer 11 may be made of other insulating materials.

[0026] It should be noted that the substrate 1 in this embodiment is not limited to the laminated structure shown in Figure 1, but may also be a single-layer structure. For example, depending on the specific circumstances, the substrate 1 may be a single-layer structure made of a semiconductor material, or a single-layer structure made of an insulating material, etc.

[0027] As shown in Figure 1, a storage layer 2 can be formed on the substrate 1. For example, if the substrate 1 is a laminated structure including a semiconductor base layer 10 and an insulating base layer 11, the storage layer 2 may be formed on the upper surface of the insulating base layer 11, away from the semiconductor base layer 10.

[0028] Continuing to refer to the figure, the storage layer 2 may include a storage cell. The storage cell may include, for example, two transistors, a read transistor 201 and a write transistor 202, and both the read transistor 201 and the write transistor 202 may be of CAA (Channel-All-Around, vertical annular channel structure) type. Specifically, the read transistor 201 may comprise a first gate 2011, a first semiconductor layer 2012 that surrounds the outer periphery of the first gate 2011 at least horizontally, and a first gate insulating layer 2013 formed between the first gate 2011 and the first semiconductor layer 2012. The write transistor 202 may comprise a second gate 2021, a second semiconductor layer 2022 that surrounds the outer periphery of the second gate 2021 at least horizontally, and a second gate insulating layer 2023 formed between the second gate 2021 and the second semiconductor layer 2022.

[0029] For example, the materials of the first semiconductor layer 2012 and the second semiconductor layer 2022 may be the same. For instance, both the first and second semiconductor layers 2012 and 2022 may be made of IGZO (indium gallium zinc oxide). By manufacturing the semiconductor layers using IGZO, it becomes unnecessary to dope the first and second semiconductor layers 2012 and 2022 to form source and drain regions, resulting in reduced leakage current, longer storage time, and improved storage performance. However, this is not limited to this, and the first and second semiconductor layers 2012 and 2022 can be formed from other semiconductor materials such as IAZO (indium aluminum zinc oxide), as long as the storage time and storage performance of the transistor can be guaranteed. Furthermore, the materials of the first and second semiconductor layers 2012 and 2022 may differ depending on the specific circumstances.

[0030] For example, the materials of the first gate 2011 and the second gate 2021 may be the same. For instance, both the first gate 2011 and the second gate 2021 may be manufactured from a conductive material such as metallic tungsten, but are not limited to this. Other materials with good conductivity may be used depending on the specific needs. Furthermore, the materials of the first gate 2011 and the second gate 2021 may also be different depending on the specific circumstances.

[0031] For example, the materials of the first gate insulating layer 2013 and the second gate insulating layer 2023 may be the same. For instance, both the first gate insulating layer 2013 and the second gate insulating layer 2023 may be composed of an insulating material such as silicon dioxide, but are not limited to this, and may be composed of other insulating materials. Furthermore, the materials of the first gate insulating layer 2013 and the second gate insulating layer 2023 may be different depending on the specific circumstances.

[0032] In this embodiment, the first gate 2011 of the read transistor 201 can be designed in a groove shape, specifically, in the read transistor 201, the first gate 2011 may include a gate sidewall 2011a and a gate bottom wall 2011b, the gate sidewall 2011a is arranged horizontally surrounding the gate bottom wall 2011b and extends away from the substrate 1, and the gate sidewall 2011a and the gate bottom wall 2011b form a gate groove, and a part of the write transistor 202 may be fitted vertically into the read transistor 201, specifically, a part of the second semiconductor layer 2022 in the write transistor 202 may be fitted into the gate groove of the first gate 2011 and in contact with at least a part of the gate groove of the first gate 2011, that is, in contact with at least one of the gate sidewall 2011a and the gate bottom wall 2011b.

[0033] This invention, by vertically embedding a portion of the CAA-type write transistor 202 of the storage cell into the CAA-type read transistor 201, can reduce the horizontal area occupied by the storage cell while ensuring storage density, compared to a planar 2T0C-type storage cell. It can also reduce the vertical height of the storage cell, thus reducing the overall volume of the storage cell. This reduces the space occupied by the storage cell, allowing more storage cells to be placed within a given volume of memory, thereby improving the memory's storage density.

[0034] Furthermore, the present invention achieves connection between the write transistor 202 and the read transistor 201 by placing the semiconductor layer of the write transistor 202 in the gate groove of the gate of the read transistor 201, thereby directly contacting the gate of the read transistor 201. Compared to planar 2T0C type storage cells, there is no need to design an additional connection pattern to connect the write transistor 202 and the read transistor 201 together, thus reducing the requirements of the photolithography process in the manufacturing process, improving product yield, and lowering manufacturing costs.

[0035] The position where the gate groove of the first gate 2011 contacts the second semiconductor layer 2022 may be understood as a storage node of the storage cell. For example, in Figure 1, the position where the gate bottom wall 2011b contacts the second semiconductor layer 2022 may be understood as a storage node.

[0036] In some embodiments, referring to Figure 1, in the write transistor 202, the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 may have a fitting portion and an extension portion, the fitting portion may be a part of the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 fitted into the gate groove. The fitting portion of the second semiconductor layer 2022 is in contact with at least a part of the gate groove to realize a connection between the write transistor 202 and the read transistor 201, and the extension portion is a part of the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 located on the side of the fitting portion away from the substrate 1, and it should be understood that this extension portion is positioned to protrude away from the substrate 1 relative to the read transistor 201.

[0037] In this embodiment, by fitting the bottoms of the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 of the writing transistor 202 into the gate groove of the first gate 2011, the vertical height of the storage cell can be further reduced while ensuring storage density.

[0038] As an example, referring to Figure 1, the fitting portion of the second semiconductor layer 2022 may include a second semiconductor sidewall 2022a and a second semiconductor bottom wall 2022b, the second semiconductor sidewall 2022a is arranged horizontally surrounding the second semiconductor bottom wall 2022b and extends away from the substrate 1, the second semiconductor sidewall 2022a and the second semiconductor bottom wall 2022b form a surrounding second semiconductor groove, and the fitting portion of the second gate 2021 and the fitting portion of the second gate insulating layer 2023 are arranged within the second semiconductor groove.

[0039] Referring to Figure 1, both the bottom surface of the second semiconductor bottom wall 2022b and the bottom surface of the second semiconductor side wall 2022a are in contact with the gate bottom wall 2011b. This design ensures a sufficient contact area between the second semiconductor layer 2022 and the first gate 2011, and also reduces the difficulty of the manufacturing process.

[0040] In some embodiments, referring to Figure 1, the storage cell includes an insulating medium sidewall 203a that is fitted into the gate groove and horizontally surrounds the outer periphery of the fitted portion of the second semiconductor layer 2022, the outer periphery of the fitted portion of the second semiconductor layer 2022 being insulated from the gate sidewall 2011a by the insulating medium sidewall 203a, and the bottom surface of the fitted portion of the second semiconductor layer 2022 being in contact with the gate bottom wall 2011b. Such a design allows the fitted portion of the second semiconductor layer 2022 to be part of the channel of the write transistor 202 while enabling connection between the write transistor 202 and the read transistor 201, thereby reducing the height of the second semiconductor layer 2022 protruding from the read transistor 201, that is, reducing the height of the extension of the second semiconductor layer 2022, and thereby further reducing the vertical height of the storage cell.

[0041] In some embodiments, the insulating medium sidewall 203a may include a low-dielectric material portion made from a material with a dielectric constant of less than 3.0, which horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer 2022, thereby reducing parasitic capacitance between the second semiconductor layer 2022 and the first gate 2011.

[0042] In other embodiments, the insulating medium sidewall 203a also includes a silicon dioxide material layer that horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer 2022, thereby reducing material costs while achieving insulation between the fitting portion of the second semiconductor layer 2022 and the gate sidewall 2011a of the first gate 2011.

[0043] In other embodiments, the insulating medium sidewall 203a includes a laminated structure in which a low dielectric material portion and a silicon dioxide material layer are fitted together, thereby reducing parasitic capacitance while reducing material costs.

[0044] In some embodiments of the present disclosure, referring to Figure 1, the storage layer 2 may include a first signal line 204 and a second signal line 205 in addition to the storage cell. As shown in relation to Figures 1 to 3, the first signal line 204 is formed on the substrate 1, and the first signal line 204 extends in a first horizontal direction X and contacts the bottom surface and / or bottom region of the outer surface of the first semiconductor layer 2012. The second signal line 205 is formed on one side of the first signal line 204 away from the substrate 1, and a first interlayer insulating layer 206 is formed between the layer where the second signal line 205 is located and the layer where the first signal line 204 is located. The second signal line 205 extends in a second horizontal direction Y that intersects the first horizontal direction X. The second signal line 205 and the first interlayer insulating layer 206 horizontally surround the outer periphery of the first semiconductor layer 2012, and the second signal line 205 contacts the upper region of the outer periphery surface of the first semiconductor layer 2012. One of the first signal line 204 and the second signal line 205 is a read bit line, and the other is a read word line.

[0045] For example, the first signal line 204 and the second signal line 205 may be made of the same material, or both may be made of a conductive material such as metallic tungsten, but are not limited to this, and may be made of other conductive materials. Also, the first signal line 204 and the second signal line 205 may be signal lines formed from a single material, but are not limited to this, and may be composite signal lines formed by laminating multiple materials depending on the specific situation. The first interlayer insulating layer 206 may be made of a material such as silicon dioxide, but are not limited to this, and may be made of other insulating materials depending on the specific situation.

[0046] Referring to Figure 1, the first semiconductor layer 2012 of the readout transistor 201 is formed on one side of the first signal line 204 away from the substrate 1, and both the first semiconductor layer 2012 and the first gate insulating layer 2013 of the readout transistor 201 can be designed in a groove shape. In this embodiment, the first gate insulating layer 2013 and the first gate 2011 are designed according to the shape of the first semiconductor layer 2012 and work together to simplify process steps and reduce process costs while ensuring the channel length of the readout transistor 201.

[0047] Referring in detail to Figure 1, the first semiconductor layer 2012 includes a first semiconductor sidewall 2012a and a first semiconductor bottom wall 2012b, the first semiconductor sidewall 2012a is arranged horizontally surrounding the first semiconductor bottom wall 2012b and extends away from the substrate 1, the first semiconductor sidewall 2012a and the first semiconductor bottom wall 2012b form a surrounding first semiconductor groove, and the bottom surfaces of both the first semiconductor sidewall 2012a and the first semiconductor bottom wall 2012b are in contact with the first signal line 204.

[0048] Referring to Figure 1, the first gate insulating layer 2013 includes a first gate insulating sidewall 2013a and a first gate insulating bottom wall 2013b, the first gate insulating bottom wall 2013b is located within the first semiconductor groove and in contact with the upper surface of the first semiconductor bottom wall 2012b, the first gate insulating sidewall 2013a is located at least within the first semiconductor groove and horizontally surrounds the first gate insulating bottom wall 2013b, and the first gate insulating sidewall 2013a extends away from the substrate 1. Furthermore, the first gate insulating bottom wall 2013b and the first gate insulating groove are formed surrounding each other, the outer circumferential surface of the first gate insulating side wall 2013a is in contact with the inner circumferential surface of the first semiconductor side wall 2012a, the gate bottom wall 2011b is located within the first gate insulating groove and is in contact with the upper surface of the first gate insulating bottom wall 2013b, the gate side wall 2011a is located at least within the first gate insulating groove and the outer circumferential surface of the gate side wall 2011a is in contact with the inner circumferential surface of the first gate insulating side wall 2013a.

[0049] In some embodiments, referring to Figure 1, the upper surface of the first semiconductor sidewall 2012a, the upper surface of the first gate insulating sidewall 2013a, and the upper surface of the gate sidewall 2011a may be flush with the upper surface of the second signal line 205. However, the embodiments are not limited to this, and in other embodiments, referring to Figure 4, a first semiconductor wrap portion 2012c extending horizontally outward is provided on the upper part of the first semiconductor sidewall 2012a, and the first semiconductor wrap portion 2012c is formed on the upper surface of the second signal line 205; a first gate insulating wrap portion 2013c extending horizontally outward is provided on the upper part of the first gate insulating sidewall 2013a, and the first gate insulating wrap portion 2013c is formed on the upper surface of the first semiconductor wrap portion 2012c; and a gate wrap portion 2011c extending horizontally outward is provided on the upper part of the gate sidewall 2011a, and the gate wrap portion 2011c is formed on the upper surface of the first gate insulating wrap portion 2013c.

[0050] In some embodiments of the present disclosure, referring to Figure 1, the storage layer 2 may include a write bit line 207 and a write word line 208 in addition to the storage cell, the first signal line 204 and the second signal line 205. The write bit line 207 is formed on one side of the second signal line 205 away from the substrate 1, and a second interlayer insulating layer 209 is formed between the layer in which the write bit line 207 is located and the layer in which the second signal line 205 is located, and the write bit line 207 and the second interlayer insulating layer 209 horizontally surround the outer periphery of the extension of the second semiconductor layer 2022, and the write bit line 207 is in contact with the outer periphery of the first semiconductor layer 2012. The write word line 208 is formed on one side of the extension of the write bit line 207 and the second gate 2021, away from the substrate 1. A third interlayer insulating layer 210 is formed between the layer where the write word line 208 is located and the layer where the write bit line 207 is located, and the write word line 208 is connected to the upper surface of the extension of the second gate 2021.

[0051] As shown in Figures 2 and 3, the write bit line 207 extends in the first horizontal direction X, and the write word line 208 extends in the second horizontal direction Y. This reduces the overlapping area between the write bit line 207 and the second signal line 205, thereby reducing the occurrence of parasitic capacitance between them. However, this is not the only option, and depending on the specific situation, the write bit line 207 may also extend in the second horizontal direction Y, and the write word line 208 may also extend in the first horizontal direction X.

[0052] For example, the writing word line 208 and the writing bit line 207 may be made of the same material, and for example, both may be made of a conductive material such as metallic tungsten, but are not limited to this, and may be made of other conductive materials. Also, the writing word line 208 and the writing bit line 207 may be signal lines formed from a single material, but are not limited to this, and may be composite signal lines formed by laminating multiple materials depending on the specific situation. The second interlayer insulating layer 209 and the third interlayer insulating layer 210 may be made of a material such as silicon dioxide, but are not limited to this, and may be made of other insulating materials depending on the specific situation.

[0053] In some embodiments, referring to Figures 1 and 4, a second semiconductor wrap portion 2022c is provided on the upper part of the extension of the second semiconductor layer 2022, extending horizontally outward, and the second semiconductor wrap portion 2022c is formed on the upper surface of the write word line 208. A second gate insulating wrap portion 2023c is provided on the upper part of the extension of the second gate insulating layer 2023, extending horizontally outward, and the second gate insulating wrap portion 2023c is formed on the upper surface of the second semiconductor wrap portion 2022c. The upper surface is flush with the upper surface of the second gate insulating wrap portion 2023c, and a conductive contact pad 2024 is provided in the storage layer 2023. The bottom surface of the conductive contact pad 2024 is in contact with the upper surface of the second gate insulating wrap portion 2023c and the upper surface of the extension of the second gate 2021, and the upper surface of the conductive contact pad 2024 is in contact with the bottom surface of the write word line 208. This design increases the contact area between the write transistor 202 and the write word line 208, thereby ensuring connection stability.

[0054] For example, the conductive contact pad 2024 of this embodiment may be manufactured integrally with the second gate 2021 to reduce process costs, but is not limited thereto, and may be manufactured separately depending on the specific circumstances.

[0055] In embodiments of the present disclosure, as shown in combination in Figures 2 and 3, the storage layer 2 may include a plurality of storage cells, which are arranged in an array in a first horizontal direction X and a second horizontal direction Y. The number of first signal lines 204 is equal to the number of rows in the storage cell array structure, and the number of second signal lines 205 is equal to the number of rows in the storage cell array structure. The first signal lines 204 are spaced apart in the second horizontal direction Y, and each first signal line 204 is connected to the first semiconductor layer 2012 of the read transistor 201 in all storage cells in the corresponding row. The second signal lines 205 are spaced apart in the first horizontal direction X, and each second signal line 205 is connected to the first semiconductor layer 2012 of the read transistor 201 in all storage cells in the corresponding column.

[0056] Referring to Figures 2 and 3, if the write bit lines 207 extend in a first horizontal direction X and the write word lines 208 extend in a second horizontal direction Y, then the number of write bit lines 207 is equal to the number of rows in the storage cell array structure, and the number of write word lines 208 is equal to the number of rows in the storage cell array structure. The write bit lines 207 are spaced apart in the second horizontal direction Y, and each write bit line 207 is connected to the second semiconductor layer 2022 of the write transistor 202 in all storage cells in the corresponding row, and the write word lines 208 are spaced apart in the first horizontal direction X, and each write word line 208 is connected to the second gate 2021 of the write transistor 202 in all storage cells in the corresponding column.

[0057] If the write bit lines 207 extend in a second horizontal direction Y and the write word lines 208 extend in a first horizontal direction X, then the number of write bit lines 207 is equal to the number of columns in the storage cell array structure, and the number of write word lines 208 is equal to the number of rows in the storage cell array structure. The write bit lines 207 are spaced apart in the first horizontal direction X, and each write bit line 207 is connected to the second semiconductor layer 2022 of the write transistor 202 in all storage cells in the corresponding column, and the write word lines 208 are spaced apart in the second horizontal direction Y, and each write word line 208 is connected to the second gate 2021 of the write transistor 202 in all storage cells in the corresponding row.

[0058] In this embodiment, by using vertically fitted storage cells, the horizontal area occupied by the storage cells is reduced, and the space occupied by the storage cells is reduced, so that more storage cells can be placed in each storage layer 2, and the storage density of the storage layer 2 is improved.

[0059] In embodiments of this disclosure, referring to Figures 5 and 6, the number of storage layers 2 may be multiple layers, and multiple storage layers 2 may be stacked in a direction perpendicular to the substrate 1. In this embodiment, by employing vertically fitted storage cells, the vertical height of the storage layers 2 is reduced, thereby allowing more storage layers 2 to be placed when the memory height is constant, and improving the memory storage density.

[0060] In some embodiments, of two adjacent storage layers 2, the storage layer 2 closer to the substrate 1 is defined as the bottom storage layer, and the storage layer 2 further away from the substrate 1 is defined as the top storage layer. Referring to Figure 5, in at least two adjacent storage layers 2, a fourth interlayer insulating layer 211 is formed between the layer where the first signal line 204 of the top storage layer is located and the layer where the write word line 208 of the bottom storage layer is located. This design allows for more flexible control of each storage layer 2.

[0061] In another embodiment, referring to Figure 6, at least two adjacent storage layers 2 can share the write word line 208 of the bottom storage layer as the first signal line 204 of the top storage layer. This design allows more storage layers 2 to be placed at a given height, thereby improving the storage density of the memory.

[0062] The disclosed embodiments further provide a method for manufacturing the memory used to produce the memory described in any of the embodiments described above. Below, the structure of the memory will not be described repeatedly, and the method for manufacturing the memory will be described in detail.

[0063] In one embodiment of the present disclosure, the method for manufacturing the memory may include steps S100 and S102.

[0064] Step S100: Provide the substrate 1. For example, as shown in Figure 7, the substrate 1 may be formed by forming an insulating base layer 11 on a semiconductor base layer 10.

[0065] Step S102: Form at least one storage layer 2 on the substrate 1. The step of forming the storage layer 2 may include at least the following:

[0066] In step S1021, a readout transistor 201 is formed on the substrate 1, and the readout transistor 201 in this embodiment has a gate groove.

[0067] In step S1022, a write transistor 202 is formed in the gate groove of the read transistor 201 to form a storage cell.

[0068] The manufacturing method for forming a storage layer on the substrate 1 of this disclosure will be described in detail below with reference to Figures 1 to 24.

[0069] In some embodiments of this disclosure, the step of forming the storage layer 2 prior to step S1021 may further include steps S10200, S10201, S10202, and S10203.

[0070] Step S10200: A first signal line 204 is formed on the substrate 1, and the first signal line 204 extends in the first horizontal direction X as shown in Figure 8. For example, as shown in Figure 9, a first metal film covering the entire surface can be deposited on the insulating base layer 11 of the substrate 1, and then the first metal film can be patterned to form a plurality of first signal lines 204 spaced apart in the second horizontal direction Y.

[0071] As shown in Figure 9, a first insulating isolation column 212 is formed between adjacent first signal lines 204 to achieve mutual insulation between adjacent first signal lines 204, and the upper surface of the first insulating isolation column 212 may be flush with the upper surface of the first signal line. The first insulating isolation column 212 may be formed on the substrate 1 before the first signal line 204, or the first signal line 204 may be formed on the substrate 1 before the first insulating isolation column 212.

[0072] Step S10201: A first interlayer insulating layer 206 is formed on the upper surface of the first signal line 204. For example, after forming a plurality of first signal lines 204 spaced apart in a second horizontal direction Y, a first interlayer insulating layer 206 covering the entire surface may be deposited, and the first interlayer insulating layer 206 may cover not only the upper surface of the first signal line 204 but also the upper surface of the first insulating isolation column 212, and thereafter, the upper surface of the first interlayer insulating layer 206 may be polished to a flat surface using a chemical mechanical polishing process.

[0073] Furthermore, when the first insulating isolation column 212 is formed after the first signal line 204, the first interlayer insulating layer 206 may be formed integrally with the first insulating isolation column 212, but is not limited to this, and may be formed separately. That is, the first insulating isolation column 212 is formed first, and then the first interlayer insulating layer 206 is formed.

[0074] In step S10202, a second signal line 205 is formed on the upper surface of the first interlayer insulating layer 206. The second signal line 205 extends in a second horizontal direction Y, and the orthographic projection of the second signal line 205 onto the substrate 1 and the orthographic projection of the first signal line 204 onto the substrate 1 have a first overlapping region.

[0075] For example, step S10202 may include steps S102021 and S102022. Here, in step S102021, first, as shown in Figure 10, a second metal film 205a is deposited to cover the entire upper surface of the first interlayer insulating layer 206. In step S102022, the second metal film 205a is patterned to form a plurality of second signal lines 205 arranged at intervals in the first horizontal direction X.

[0076] In step S10203: The first housing hole 213 is formed, and the orthographic projection of the first housing hole 213 onto the substrate 1 is located within the first overlapping region, the first housing hole 213 penetrates the second signal line 205 and the first interlayer insulating layer 206, and exposes the first signal line 204.

[0077] Referring to Figure 11, step S10203 can be performed after step S102021 and before step S102022. In this case, the passage of the first housing hole 213 through the second signal line 205, as mentioned in step S10203, can be understood as the passage of the first housing hole 213 through a portion of the second metal film 205a used to form the second signal line 205, and it should be understood that, depending on the specific situation, step S10203 can also be performed after step S102022.

[0078] For example, referring to Figure 11, the first housing hole 213 extends into the interior of the first signal line 204, thereby ensuring the contact area between the subsequently formed readout transistor 201 and the first signal line 204, but is not limited to this. Depending on the specific circumstances, the first housing hole 213 may extend just to the top surface of the first signal line 204, or it may penetrate the first signal line 204. Furthermore, the first housing holes 213 in this embodiment may be provided in multiples and arranged in an array in the first horizontal direction X and the second horizontal direction Y, as shown in Figure 12.

[0079] In some embodiments of the present disclosure, the step of forming the readout transistor 201 may include the step of forming a first semiconductor layer 2012, a first gate insulating layer 2013, and a first gate 2011 within a first accommodating hole 213. The first semiconductor layer 2012 surrounds the outer periphery of the first gate 2011 at least horizontally, and the first gate insulating layer 2013 is formed between the first gate 2011 and the first semiconductor layer 2012. The first gate 2011 includes a gate bottom wall 2011b and a gate side wall 2011a, the gate side wall 2011a surrounding the gate bottom wall 2011b horizontally and extending away from the substrate 1, and the gate side wall 2011a and the gate bottom wall 2011b form surrounding the gate groove, where the first signal line 204 can contact the bottom region of the bottom surface and / or the outer periphery surface of the first semiconductor layer 2012, and the second signal line 205 surrounds the outer periphery of the first semiconductor layer 2012 and contacts the upper region of the outer periphery surface of the first semiconductor layer 2012.

[0080] Step S102022 can be performed after forming the readout transistor 201, but is not limited to this; it can also be performed before forming the readout transistor 201, depending on the specific circumstances.

[0081] More specifically, the step of forming the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011 includes steps S10210, S10211, S10212, S10213, and S10214.

[0082] In step S10210: A first semiconductor film 214 is formed on the substrate 1, and as shown in Figure 13, the first semiconductor film 214 completely covers the upper surface of the second signal line 205, the hole wall surface of the first accommodating hole 213, and the exposed surface of the first signal line 204 exposed by the first accommodating hole 213. For example, the first semiconductor film 214 may be deposited by atomic layer deposition, and the first semiconductor film 214 may be formed according to the shape of the underlying structural layer. It should be understood that the portion of the first semiconductor film 214 located within the first accommodating hole 213 belongs to the first semiconductor layer 2012 described above.

[0083] Furthermore, if step S102022 is performed after forming the readout transistor 201, the first semiconductor film 214 can completely cover the upper surface of the second signal line 205 in step S10210. This can be understood as the first semiconductor film 214 covering the second metal film 205a, as shown in Figure 13.

[0084] In step S10211: A first gate insulating film 215 is formed on the first semiconductor film 214 so that the first gate insulating film 215 completely covers the first semiconductor film 214, as shown in Figure 13. For example, the first gate insulating film 215 may be deposited by atomic layer deposition, and the first gate insulating film 215 may be formed according to the shape of the underlying structural layer. It should be understood that the portion of the first gate insulating film 215 located within the first accommodating hole 213 belongs to the first gate insulating layer 2013 described above.

[0085] In step S10212: A first conductive film 216 is formed on the first gate insulating film 215, so that the first conductive film 216 completely covers the first gate insulating film 215, as shown in Figure 13. For example, the first conductive film 216 may be deposited by atomic layer deposition, and the first conductive film 216 may be formed according to the shape of the underlying structural layer. It should be understood that the portion of the first conductive film 216 located within the first accommodating hole 213 belongs to the first gate 2011.

[0086] In step S10213, a filling layer 217 is formed on the first conductive film 216, and the filling layer 217 completely covers the first conductive film 216 and fills the first accommodating hole 213. The filling layer 217 may include an insulating medium film 217a and a sacrificial material film 217b formed on the insulating medium film 217a, and the insulating medium film 217a completely covers the first conductive film 216.

[0087] The portion of the insulating medium film 217a located in the gate groove belongs to the insulating medium portion 203. The insulating medium portion 203 may include an insulating medium side wall 203a and an insulating medium bottom wall 203b. The insulating medium side wall 203a is arranged horizontally surrounding the insulating medium bottom wall 203b and extends away from the substrate 1. The insulating medium side wall 203a and the insulating medium bottom wall 203b form a surrounding insulating medium groove. The sacrificial material film 217b completely covers the insulating medium film 217a and fills the first housing hole 213.

[0088] For example, after depositing the sacrificial material film 217b to completely cover the insulating medium film 217a and filling the first housing hole 213, the sacrificial material film 217b can be polished using a chemical mechanical polishing process to make the upper surface of the sacrificial material film 217b a flat surface, which is useful for the accuracy of subsequent processes.

[0089] In some embodiments, the material of the insulating medium film 217a may be a low dielectric material, and the material of the sacrificial material film 217b may be a polysilicon material or a silicon dioxide material. It can also be understood that the insulating medium portion 203 may include a low dielectric material portion, and the sacrificial material portion may include a polysilicon material layer or a silicon dioxide material layer.

[0090] In step S10214: The portions of the filling film layer 217, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that are outside the target range of the first accommodating hole 213 are completely removed, exposing the second signal line 205, and simultaneously forming the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011.

[0091] Furthermore, if step S102022 is performed after the formation of the readout transistor 201, the exposure of the second signal line 205 mentioned in step S10214 can be understood as at least a portion of the second metal film 205a used to form the second signal line 205 being exposed.

[0092] In some embodiments, the step of completely removing portions of the packing film layer 217, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that are outside the target range of the first accommodating hole 213 may include steps S102140, S102141, S102142, S102143, S102144, and S102145.

[0093] In step S102140, as shown in Figure 14, the portion of the filling film layer 217 that is higher than the upper surface of the first conductive film 216 is removed, and the upper surface of the first conductive film 216 is exposed.

[0094] In step S102141: The portion of the packing film layer 217 that is higher than the upper surface of the second signal line 205 is continued to be etched away so that the upper surface of the retained packing portion of the packing film layer 217 becomes flush with the upper surface of the second signal line 205, as shown in Figure 15.

[0095] Furthermore, if step S102022 is performed after the formation of the readout transistor 201, the fact that the upper surface of the retained portion of the packing film layer 217 mentioned in step S10214 becomes flush with the upper surface of the second signal line 205 can be understood as the upper surface of the retained portion of the packing film layer 217 becoming flush with the upper surface of the second metal film 205a.

[0096] As shown in Figure 15, the filling and holding portion may include an insulating medium portion 203 and a sacrificial material portion 218. The insulating medium portion 203 is located in the gate groove of the first gate 2011, and the sacrificial material portion 218 may be filled into the insulating medium groove of the insulating medium portion 203.

[0097] For example, if the insulating medium film 217a of the packing film layer 217 is made of a low dielectric material and the sacrificial material film 217b is made of a polysilicon material, then in steps S102140 and S102141, Cl2 (chlorine) and CHF3 (trifluoromethane) can be used to etch the packing film layer 217, and it should be understood that during etching, attention must be paid to the flatness of the packing and holding portion of the packing film layer 217 that is held.

[0098] In step S102142, as shown in Figure 16, a protective film layer 219 is formed on the upper surface of the first conductive film 216 and the upper surface of the filling and holding portion. Here, the protective film layer 219 is used to protect the filling and holding portion in the subsequent etching process. The upper surface of the formed protective film layer 219 can be understood as a horizontal plane, and this horizontal plane can be a plane parallel or nearly parallel to the substrate 1.

[0099] Here, under the same etching conditions, the etching rate of the protective film layer 219 is lower than that of the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214. For example, the protective film layer 219 in this embodiment may be a carbon coating (Spin-On-Carbon, abbreviated as SOC), but is not limited thereto; it is sufficient that the etching rate of the protective film layer 219 is guaranteed to be lower than that of the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214.

[0100] In step S102143: Using the first etching agent, the portion of the protective film layer 219 that is higher than the upper surface of the first conductive film 216 is etched away so that the remaining protective portion 2190 of the protective film layer 219 held in the filling and holding portion becomes flush with the upper surface of the first conductive film 216, as shown in Figure 17. In embodiments of this disclosure, the first etching agent may be an etching gas, for example, if the protective film layer 219 is a carbon coating, the first etching agent may contain a mixed gas of CF4 (carbon tetrafluoride) and O2 (oxygen).

[0101] In step S102144: The portion of the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that is higher than the upper surface of the second signal line 205 is completely removed using the second etching agent to form the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011. At the same time, a portion of the height of the remaining protective portion 2190 is etched away by the second etching agent, so that a portion of the remaining protective portion 2190 remains covering the filled retaining portion, as shown in Figure 18.

[0102] In embodiments of this disclosure, the second etching agent may be an etching gas, for example, the second etching agent may contain a mixed gas containing fluorine, chlorine, and oxygen, or for example, a mixed gas containing CF4, Cl2 (chlorine), and O2, which has relatively low etching selectivity for the first conductive film material, the first gate insulating film material, and the first semiconductor film material, can improve etching uniformity, and ensures that the upper surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011 are flush.

[0103] In step S102145: Using a third etching agent, the remaining portion of the protective part 2190 remaining in the filling and holding area is completely removed. Referring to Figure 19, the upper surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013, the first gate 2011, and the filling and holding area are flush with the upper surface of the second signal line 205, and the portion outside the target area is located outside the first housing hole 213.

[0104] Furthermore, if step S102022 is performed after the formation of the readout transistor 201, the upper surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013, the first gate 2011, and the fill-hold portion mentioned in step S10215 become flush with the upper surface of the second signal line 205, which means that the upper surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013, the first gate 2011, and the fill-hold portion become flush with the upper surface of the second metal film 205a.

[0105] In embodiments of this disclosure, an ashing method or a wet cleaning method can be used to completely remove the remaining protective portion 2190 remaining on the packing film layer 217. When using the ashing method, the third etching agent may be an asher gas, for example, the asher gas may contain oxygen.

[0106] Furthermore, if the material of the insulating medium portion 203 is a low dielectric material, care should be taken in step S102145 to select an asher gas ratio that reduces oxidation of the low dielectric material, thereby reducing the formation of defects in the insulating medium portion 203.

[0107] In other embodiments, the step of completely removing portions of the packing film layer 217, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that are outside the target range of the first accommodating hole 213 may include steps S102146 and S102147.

[0108] In step S102146: As shown in Figure 20, the portion of the sacrificial material film 217b that is higher than the upper surface of the insulating medium film 217a is removed, exposing the upper surface of the insulating medium film 217a. The portion of the sacrificial material film 217b held within the insulating medium groove becomes the sacrificial material portion 218, and the upper surface of the sacrificial material portion 218 becomes flush with the upper surface of the insulating medium film 217a.

[0109] In step S102147: The portions of the insulating medium film 217a, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that are outside the target range of the first housing hole 213 are etched away, and as shown in Figure 21, the insulating medium portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011 are formed. Here, the region outside the target range is the region where the distance from the hole boundary of the first housing hole 213 exceeds the target value and the target value is greater than 0. Therefore, a first semiconductor wrap portion 2012c extending horizontally outward is formed on the upper part of the first semiconductor layer 2012, and the first semiconductor wrap portion 2012c is formed on the upper surface of the second signal line 205. A first gate insulating wrap portion 2013c extending horizontally outward is formed on the upper part of the first gate insulating layer 2013, and the first gate The insulating wrap portion 2013c is formed on the upper surface of the first semiconductor wrap portion 2012c, and a gate wrap portion 2011c extending horizontally outward is formed on the upper part of the gate sidewall 2011a, and the gate wrap portion 2011c is formed on the upper surface of the first gate insulating wrap portion 2013c, and an insulating medium wrap portion 203c extending horizontally outward is located on the upper part of the insulating medium sidewall 203a, and the insulating medium wrap portion 203c is formed on the upper surface of the gate wrap portion 2011c.

[0110] Furthermore, if step S102022 is performed after forming the read transistor 201, the formation of the first semiconductor wrap portion 2012c mentioned in step S10214 on the upper surface of the second signal line 205 can be understood as the formation of the first semiconductor wrap portion 2012c on the upper surface of the second metal film 205a.

[0111] For example, in step S102147: the insulating medium film 217a, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 located outside the target range of the first accommodating hole 213 can be etched off by a photolithography process to form the insulating medium portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011. Specifically, after step S102146, a BARC material layer and a photoresist layer covering the entire surface are formed in sequence, and then the BARC material layer The BARC material layer and the photoresist layer are patterned using a mask to form a mask structure having a target pattern. Subsequently, an etching process is performed using this mask structure to etch away portions of the insulating medium film 217a, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that are outside the target range of the first accommodating hole 213, thereby forming the insulating medium portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011.

[0112] Here, the BARC (Bottom Anti-Reflection Coating) material layer is primarily used to reduce the amount of light reflected by the photoresist layer during the exposure process, thereby reducing standing wave effects and improving the accuracy of the photolithography process. The BARC material layer is formed by spin coating, and its main components include a crosslinkable resin, a thermal acid generator, a surfactant, and a solvent, which reduce light interference.

[0113] It should be understood that after forming the insulating medium portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011, the mask structure formed by the BARC material layer and the photoresist layer may be removed.

[0114] For example, step S102022 in this embodiment may be performed after step S102147.

[0115] In some embodiments of the present disclosure, the step of forming the write transistor 202 may include steps S10220, S10221, S10222, and S10223.

[0116] In step S10220, a second interlayer insulating layer 209 is formed on the upper surfaces of the readout transistor 201, the insulating medium portion 203, and the sacrificial material portion 218. The second interlayer insulating layer 209 may completely cover the underlying structural layer, and the upper surface of the second interlayer insulating layer 209 may be a plane parallel or substantially parallel to the substrate 1 in order to ensure the flatness of subsequent film layer formation.

[0117] In step S10221: A write bit line 207 is formed on one side of the second interlayer insulating layer 209, away from the substrate 1, and as shown in Figure 22, the orthographic projection of the write bit line 207 onto the substrate 1 completely covers the orthographic projection of the sacrificial material portion 218 onto the substrate 1. For example, a third metal film can be deposited on the upper surface of the second interlayer insulating layer 209 to cover the entire surface, and then the third metal film can be patterned to form a plurality of write bit lines 207 spaced apart in the second horizontal direction Y (or the first horizontal direction X). A second insulating isolation column can be placed between adjacent write bit lines 207, and the upper surface of the second insulating isolation column will be flush with the upper surface of the write bit line 207, ensuring the flatness of subsequent film layer formation.

[0118] In this embodiment, depending on the specific circumstances, the second insulating isolation column may be formed before the write bit line 207, or the write bit line 207 may be formed before the second insulating isolation column.

[0119] In step S10222: The sacrificial material portion 218 and the insulating medium bottom wall 203b of the insulating medium portion 203 are completely etched, and the second interlayer insulating layer 209 and the portion of the write bit line 207 located on the sacrificial material portion 218 are completely etched to form a second accommodating hole 220 that exposes a portion of the gate bottom wall 2011b. The insulating medium side wall 203a of the insulating medium portion 203 is retained. For example, the second accommodating hole 220 may extend into the interior of the gate bottom wall 2011b, thereby securing storage capacity by securing the area for forming subsequent storage nodes, but is not limited to this. Referring to Figure 23, the second accommodating hole 220 may extend just to the top surface of the gate bottom wall 2011b, or it may penetrate the gate bottom wall 2011b, depending on the specific circumstances. It should be understood that in this embodiment, there may be multiple second accommodation holes 220, and they may be arranged in an array in the first horizontal direction X and the second horizontal direction Y.

[0120] In step S10223, as shown in Figure 24, a second semiconductor layer 2022, a second gate insulating layer 2023, and a second gate 2021 are formed in the second housing hole 220. For example, the second semiconductor layer 2022, the second gate insulating layer 2023, and the second gate 2021 may correspond to the manufacturing methods of the first semiconductor layer 2012, the second gate insulating layer 2023, and the second gate 2021, which will not be described in detail here.

[0121] Furthermore, the step of forming the storage layer 2 after forming the writing transistor 202 may further include the step of sequentially forming the third interlayer insulating layer 210 and the writing word line 208, as shown in Figure 3, but this will not be described in detail here.

[0122] Here, as shown in Figure 5, if the first signal line 204 of the top storage layer is not shared with the write word line 208 of the bottom storage layer in two adjacent storage layers 2, the fourth interlayer insulating layer 211 shown in Figure 5 may be formed before the first signal line 204 of the top storage layer is formed, but this will not be explained in detail here. As shown in Figure 6, if the first signal line 204 of the top storage layer is shared with the write word line 208 of the bottom storage layer in two adjacent storage layers 2, the manufacturing of one insulating layer and signal line can be omitted, that is, the manufacturing steps of the fourth interlayer insulating layer 211 and the first signal line 204 of the top storage layer can be omitted, thereby reducing manufacturing costs and improving storage density.

[0123] Furthermore, in this disclosure, terms such as “first,” “second,” “third,” and “fourth” are used for descriptive purposes only and should not be understood as indicating or implying relative importance, or implicitly indicating the number of designated technical features. Therefore, the “first,” “second,” “third,” and “fourth” features may explicitly or implicitly include one or more features. In this description, “multiple” means two or more unless otherwise specified.

[0124] In this specification, any description referring to the terms "several examples," "exemplary," etc., means that the specific features, structures, materials, or properties described in such examples or exemplary are included in at least one example of this application. In this specification, exemplary expressions for the above terms do not necessarily refer to the same example or example. Furthermore, the specific features, structures, materials, or properties described may be combined in an appropriate manner in any one or more examples or examples. Also, a person skilled in the art may combine and combine different examples or examples and features of different examples or examples described herein, as long as they do not conflict with each other.

[0125] Although embodiments of the present application have been described above, these embodiments are illustrative and should not be understood as limitations on the present application. A person skilled in the art may make changes, modifications, substitutions, and alterations to the above embodiments within the scope of the present application, but any changes or modifications made in the claims and specification of the present application shall all fall within the scope of the claims of the present application. [Explanation of Symbols]

[0126] 1. Substrate; 10. Semiconductor base layer; 11. Insulating base layer; 2. Storage layer; 20. Storage cell.

[0127] 201, readout transistor; 2011, first gate; 2011a, gate sidewall; 2011b, gate bottom wall; 2011c, gate wrap portion; 2012, first semiconductor layer; 2012a, first semiconductor sidewall; 2012b, first semiconductor bottom wall; 2012c, first semiconductor wrap portion; 2013, first gate insulating layer; 2013a, first gate insulating sidewall; 2013b, first gate insulating bottom wall; 2013c, first gate insulating wrap portion; 202, writing transistor; 2021, second gate; 2022, second semiconductor layer; 2022a, second semiconductor sidewall; 2022b, second semiconductor bottom wall; 2022c, second semiconductor wrap portion; 2023, second gate insulating layer; 2023c, second gate insulating wrap portion; 2024, conductive contact pad; 203a, Insulating medium sidewall 204, First signal line 205, Second signal line 206, First interlayer insulating layer 207, write bit line 208, Writing Word Lines 209. Second interlayer insulating layer; 210, Third interlayer insulating layer 211. The fourth interlayer insulating layer; X, first horizontal direction; Y, second horizontal direction.

Claims

1. A memory comprising a substrate and at least one storage layer, wherein the storage layer is formed on the substrate and the storage layer comprises storage cells. The storage cell comprises a read transistor and a write transistor, The readout transistor comprises a first gate, a first semiconductor layer that surrounds the outer periphery of the first gate at least horizontally, and a first gate insulating layer formed between the first gate and the first semiconductor layer, wherein the first gate comprises a gate bottom wall and a gate side wall, the gate side wall is installed horizontally surrounding the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall are formed surrounding a gate groove. The writing transistor comprises a second gate, a second semiconductor layer that surrounds the outer periphery of the second gate at least horizontally, and a second gate insulating layer formed between the second gate and the second semiconductor layer, wherein a portion of the second semiconductor layer is fitted into the gate groove and contacts at least a portion of the gate groove. A memory characterized by the following features.

2. The second semiconductor layer, the second gate, and the second gate insulating layer all have a fitting portion that is fitted into the gate groove and an extension portion located on one side of the fitting portion away from the substrate, the extension portion being positioned to protrude away from the substrate relative to the read transistor. The memory according to feature 1.

3. The storage cell further comprises an insulating medium side wall, the insulating medium side wall is fitted into the gate groove, and horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer. The outer circumferential surface of the fitting portion of the second semiconductor layer is installed insulated from the gate sidewall by the insulating medium sidewall, and the bottom surface of the fitting portion of the second semiconductor layer is in contact with the gate bottom wall. The memory according to feature 2.

4. The insulating medium sidewall comprises a low dielectric material portion, the low dielectric material portion horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer, and / or The insulating medium sidewall comprises a silicon dioxide material layer, and the silicon dioxide material layer horizontally surrounds the outer periphery of the fitting portion of the second semiconductor layer. The memory according to feature 3.

5. The fitting portion of the second semiconductor layer comprises a second semiconductor side wall and a second semiconductor bottom wall, the second semiconductor side wall is installed horizontally surrounding the second semiconductor bottom wall and extends in a direction away from the substrate, the second semiconductor side wall and the second semiconductor bottom wall form surrounding the second semiconductor groove, and the fitting portion of the second gate and the fitting portion of the second gate insulating layer are located within the second semiconductor groove. The bottom surface of the second semiconductor bottom wall and the bottom surface of the second semiconductor side wall are all in contact with the bottom surface of the gate groove. The memory according to feature 3.

6. The storage layer further comprises a first signal line and a second signal line. The first signal line is formed on the substrate, and the first signal line extends in a first horizontal direction and contacts the bottom region of the bottom surface and / or the outer peripheral surface of the first semiconductor layer. The second signal line is formed on one side of the first signal line away from the substrate, a first interlayer insulating layer is formed between the layer where the second signal line is located and the layer where the first signal line is located, the second signal line extends in a second horizontal direction intersecting the first horizontal direction, the second signal line and the first interlayer insulating layer horizontally surround the outer periphery of the first semiconductor layer, and the second signal line contacts the upper region of the outer periphery surface of the first semiconductor layer. One of the first signal line and the second signal line is a read bit line, and the other is a read word line. The memory according to feature 1.

7. The first semiconductor layer is formed on one side of the first signal line away from the substrate, and the first semiconductor layer comprises a first semiconductor sidewall and a first semiconductor bottom wall, the first semiconductor sidewall is installed horizontally surrounding the first semiconductor bottom wall and extends in a direction away from the substrate, and the first semiconductor sidewall and the first semiconductor bottom wall are formed surrounding a first semiconductor groove. The first gate insulating layer comprises a first gate insulating side wall and a first gate insulating bottom wall, wherein the first gate insulating bottom wall is located within the first semiconductor groove and contacts the upper surface of the first semiconductor bottom wall, the first gate insulating side wall is located at least within the first semiconductor groove and is installed horizontally surrounding the first gate insulating bottom wall, the first gate insulating side wall extends in a direction away from the substrate and is formed surrounding the first gate insulating bottom wall and the first gate insulating groove, and the outer peripheral surface of the first gate insulating side wall contacts the inner peripheral surface of the first semiconductor side wall. The gate bottom wall is located within the first gate insulating groove and in contact with the upper surface of the first gate insulating bottom wall, and the gate side wall is located within the first gate insulating groove, and the outer peripheral surface of the gate side wall is in contact with the inner peripheral surface of the first gate insulating side wall. The memory according to feature 6.

8. The upper surface of the first semiconductor sidewall, the upper surface of the first gate insulating sidewall, and the upper surface of the gate sidewall are flush with the upper surface of the second signal line, or The upper part of the first semiconductor sidewall has a first semiconductor wrap portion extending horizontally outward, and the first semiconductor wrap portion is formed on the upper surface of the second signal line; the upper part of the first gate insulating sidewall has a first gate insulating wrap portion extending horizontally outward, and the first gate insulating wrap portion is formed on the upper surface of the first semiconductor wrap portion; the upper part of the gate sidewall has a gate wrap portion extending horizontally outward, and the gate wrap portion is formed on the upper surface of the first gate insulating wrap portion. The memory according to feature 7.

9. The storage layer further comprises write bit lines and write word lines, The write bit line is formed on one side of the second signal line away from the substrate, a second interlayer insulating layer is formed between the layer where the write bit line is located and the layer where the second signal line is located, the write bit line and the second interlayer insulating layer horizontally surround the outer periphery of the extension of the second semiconductor layer, and the write bit line is in contact with the outer periphery of the second semiconductor layer. The write word line is formed on one side of the write bit line and the extension of the second gate, away from the substrate, a third interlayer insulating layer is formed between the layer where the write word line is located and the layer where the write bit line is located, and the write word line is connected to the upper surface of the extension of the second gate. One of the write bit line and the write word line extends in the first horizontal direction, and the other extends in the second horizontal direction. The memory according to feature 6.

10. The write bit line extends in the first horizontal direction, the write word line extends in the second horizontal direction, and / or The upper part of the extension of the second semiconductor layer has a second semiconductor wrap portion extending horizontally outward, the second semiconductor wrap portion is formed on the upper surface of the write bit line, the upper part of the extension of the second gate insulating layer has a second gate insulating wrap portion extending horizontally outward, the second gate insulating wrap portion is formed on the upper surface of the second semiconductor wrap portion, the upper surface of the extension of the second gate is flush with the upper surface of the second gate insulating wrap portion, the storage layer further comprises a conductive contact pad, the bottom surface of the conductive contact pad is in contact with the upper surface of the second gate insulating wrap portion and the upper surface of the extension of the second gate, and the top surface of the conductive contact pad is in contact with the bottom surface of the write word line. The memory according to feature 9.

11. The number of storage layers is multiple, and the multiple storage layers are stacked in a direction perpendicular to the substrate, and of two adjacent storage layers, the storage layer closer to the substrate is defined as the bottom storage layer, and the storage layer further away from the substrate is defined as the top storage layer. In at least two adjacent storage layers, a fourth interlayer insulating layer is formed between the layer where the first signal line of the top storage layer is located and the layer where the write word line of the bottom storage layer is located, and / or In at least two adjacent storage layers, the write word line of the bottom storage layer is shared as the first signal line of the top storage layer. The memory according to feature 9.

12. A method for manufacturing memory, The steps include providing a substrate and The step of forming at least one storage layer on the substrate is included. The step of forming the aforementioned preservation layer is, A step of forming a readout transistor on the substrate, wherein the readout transistor comprises a first gate, a first semiconductor layer that surrounds the outer periphery of the first gate at least horizontally, and a first gate insulating layer formed between the first gate and the first semiconductor layer, the first gate comprises a gate bottom wall and a gate side wall, the gate side wall is installed horizontally surrounding the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall are formed surrounding a gate groove, A step of forming a storage cell by forming a write transistor in the gate groove, wherein the write transistor comprises a second gate, a second semiconductor layer that surrounds the outer periphery of the second gate at least horizontally, and a second gate insulating layer formed between the second gate and the second semiconductor layer, and a part of the second semiconductor layer is fitted into the gate groove and in contact with at least a part of the gate groove. A method for manufacturing memory characterized by the following:

13. Before the step of forming the readout transistor, the step of forming the storage layer is performed. A first signal line is formed on the substrate, and the first signal line extends in a first horizontal direction. The steps include forming a first interlayer insulating layer on the upper surface of the first signal line, A second signal line is formed on the upper surface of the first interlayer insulating layer, the second signal line extends in a second horizontal direction, and the orthographic projection of the second signal line onto the substrate and the orthographic projection of the first signal line onto the substrate have a first overlapping region. The steps include forming a first housing hole, the orthographic projection of the first housing hole onto the substrate being located within the first overlapping region, the first housing hole penetrating the second signal line and the first interlayer insulating layer, and exposing the first signal line, and further comprising The manufacturing method according to claim 12, characterized in that it is a feature of the present invention.

14. The step of forming the readout transistor is: The step of forming a first semiconductor layer, a first gate insulating layer, and a first gate within the first housing hole, wherein the first semiconductor layer horizontally surrounds at least the outer periphery of the first gate, the first gate insulating layer is formed between the first gate and the first semiconductor layer, the first gate includes a gate bottom wall and a gate side wall, the gate side wall is installed horizontally surrounding the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall are formed surrounding a gate groove, The first signal line contacts the bottom region of the bottom surface and / or the outer surface of the first semiconductor layer, and the second signal line surrounds the outer surface of the first semiconductor layer and contacts the upper region of the outer surface of the first semiconductor layer. The manufacturing method according to claim 13, characterized in that it

15. The steps of forming the first semiconductor layer, the first gate insulating layer, and the first gate are as follows: The first semiconductor film is formed on the substrate, the first semiconductor film completely covers the upper surface of the second signal line, the hole wall surface of the first housing hole, and the exposed surface of the first signal line exposed by the first housing hole, and the portion of the first semiconductor film located within the first housing hole belongs to the first semiconductor layer, The first gate insulating film is formed on the first semiconductor film, the first gate insulating film completely covers the first semiconductor film, and the portion of the first gate insulating film located within the first housing hole belongs to the first gate insulating layer, A first conductive film is formed on the first gate insulating film, the first conductive film completely covers the first gate insulating film, and the portion of the first conductive film located within the first housing hole belongs to the first gate. The steps include forming a filling film layer on the first conductive film, the filling film layer completely covering the first conductive film, and filling the first accommodating holes, The process includes the steps of completely removing the portions of the filling film layer, the first conductive film, the first gate insulating film, and the first semiconductor film that are outside the target range of the first accommodating hole to expose the second signal line, and simultaneously forming the first semiconductor layer, the first gate insulating layer, and the first gate. The manufacturing method according to claim 14, characterized by the above.

16. The step of completely removing the portion of the filling film layer, the first conductive film, the first gate insulating film, and the first semiconductor film that is outside the target range of the first accommodating hole is: The steps include removing the portion of the filling film layer that is higher than the upper surface of the first conductive film, thereby exposing the upper surface of the first conductive film, The steps include etching away the portion of the filling film layer that is higher than the upper surface of the second signal line, so that the upper surface of the filling holding portion held in the filling film layer becomes flush with the upper surface of the second signal line, A protective film layer is formed on the upper surface of the first conductive film and the upper surface of the filling and holding portion, the upper surface of the protective film layer is a horizontal plane, and under the same etching conditions, the etching rate of the protective film layer is lower than the etching rates of the first conductive film, the first gate insulating film, and the first semiconductor film. The steps include using a first etching agent to etch away the portion of the protective film layer that is higher than the upper surface of the first conductive film, so that the remaining protective portion of the protective film layer held in the filling and holding portion becomes flush with the upper surface of the first conductive film, The steps include using a second etching agent to completely remove the portions of the first conductive film, the first gate insulating film, and the first semiconductor film that are higher than the upper surface of the second signal line, thereby forming the first semiconductor layer, the first gate insulating layer, and the first gate, and simultaneously, due to the action of the second etching agent, a portion of the height of the remaining protective portion is etched away, so that the remaining portion of the remaining protective portion covers the filled and holding portion, The process includes the step of completely removing the remaining protective portion remaining in the filling and holding portion using a third etching agent, The upper surfaces of the first semiconductor layer, the first gate insulating layer, the first gate, and the filling and holding portion are flush with the upper surface of the second signal line, and the area outside the target range is located outside the first housing hole. The manufacturing method according to claim 15, characterized in that it

17. The filling and holding portion comprises an insulating medium portion and a sacrificial material portion. The insulating medium portion is located in the gate groove of the first gate, and the insulating medium portion comprises an insulating medium bottom wall and an insulating medium side wall, the insulating medium side wall is installed horizontally surrounding the insulating medium bottom wall and extends in a direction away from the substrate, and the insulating medium side wall and the insulating medium bottom wall are formed surrounding the insulating medium groove. The sacrificial material portion is filled into the insulating medium groove. The manufacturing method according to claim 16.

18. The filling film layer comprises an insulating medium film and a sacrificial material film formed on the insulating medium film, wherein the insulating medium film completely covers the first conductive film, the portion of the insulating medium film located in the gate groove belongs to the insulating medium portion, the insulating medium portion comprises an insulating medium bottom wall and an insulating medium side wall, the insulating medium side wall is installed horizontally surrounding the insulating medium bottom wall and extends away from the substrate, the insulating medium side wall and the insulating medium bottom wall form surrounding the insulating medium groove, the sacrificial material film completely covers the insulating medium film and fills the first housing hole. The step of completely removing the portion of the filling film layer, the first conductive film, the first gate insulating film, and the first semiconductor film that is outside the target range of the first accommodating hole is: The steps include etching away the portion of the sacrificial material film that is higher than the upper surface of the insulating medium film, exposing the upper surface of the insulating medium film, the portion of the sacrificial material film held within the insulating medium groove being the sacrificial material portion, and the upper surface of the sacrificial material portion being flush with the upper surface of the insulating medium film, The process includes the step of etching away portions of the insulating medium film, the first conductive film, the first gate insulating film, and the first semiconductor film that are outside the target range of the first housing hole, thereby forming the insulating medium portion, the first semiconductor layer, the first gate insulating layer, and the first gate. The area outside the target range is a region where the distance from the hole boundary of the first housing hole exceeds the target value and the target value is greater than 0, a first semiconductor wrap portion extending horizontally outward is formed on the upper part of the first semiconductor layer, the first semiconductor wrap portion is formed on the upper surface of the second signal line, the first gate insulating layer has a first gate insulating wrap portion extending horizontally outward, the first gate insulating wrap portion is formed on the upper surface of the first semiconductor wrap portion, the upper part of the gate side wall has a gate wrap portion extending horizontally outward, the gate wrap portion is formed on the upper surface of the first gate insulating wrap portion, and the upper part of the insulating medium side wall has an insulating medium wrap portion extending horizontally outward, the insulating medium wrap portion is formed on the upper surface of the gate wrap portion The manufacturing method according to claim 15, characterized in that it

19. The insulating medium sidewall comprises a low dielectric material portion, and the sacrificial material portion includes a polysilicon material layer or a silicon dioxide material layer. The manufacturing method according to claim 17 or 18, characterized by the above.

20. The step of forming the writing transistor is: The steps include forming a second interlayer insulating layer on the upper surfaces of the readout transistor, the insulating medium portion, and the sacrificial material portion, The steps include forming a write bit line on one side of the second interlayer insulating layer away from the substrate, such that the orthographic projection of the write bit line onto the substrate completely covers the orthographic projection of the sacrificial material portion onto the substrate, The steps include: completely etching the sacrificial material portion and the bottom wall of the insulating medium, completely etching the second interlayer insulating layer and the portion of the writing bit line located on the sacrificial material portion to form a second housing hole, and exposing the portion of the gate bottom wall in the second housing hole; The process includes the steps of forming the second semiconductor layer, the second gate insulating layer, and the second gate within the second housing hole. The manufacturing method according to claim 17 or 18, characterized by the above.

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