Memory system

Abstract

To provide a memory system that can reduce deterioration in I / O performance.SOLUTION: A controller of a memory system executes a command for reading first data from a non-volatile memory in response to reception of a first read command requesting reading of first data and specifying a first virtual address from a host. The controller executes address conversion processing for converting the first virtual address to a first physical address for accessing a memory of the host. The controller transmits an address conversion request for acquiring first address conversion information to the host. The controller interrupts command processing until the first address conversion information is acquired in response to reception of a response indicative of a failed acquisition of the first address conversion information from the host, and resumes command processing after acquiring the first address conversion information.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] Embodiments of the present invention relate to a technique for controlling a non-volatile memory.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memories have become widely popular. As one such memory system, a solid state drive (SSD) equipped with a NAND type flash memory is known.

[0003] The controller of a memory system processes input / output (I / O) commands received from a host. Then, the controller transmits various information such as data, responses, and interrupts to the host.

[0004] If the transmission of information from the controller to the host is delayed, the information to be transmitted to the host may accumulate in the controller. Such accumulation of information can be a factor in reducing the I / O performance of the memory system.

[0005] Therefore, in a memory system, there is a need for a technique that can reduce the degradation of I / O performance caused by the accumulation of information to be transmitted to the host in the controller.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] One embodiment of the present invention aims to solve the problem of providing a memory system that can mitigate the degradation of I / O performance. [Means for solving the problem]

[0008] According to one embodiment, the memory system is connectable to a host. The memory system comprises a non-volatile memory and a controller electrically connected to the non-volatile memory and configured to control the non-volatile memory. In response to receiving a first read command from the host requesting the reading of first data and specifying a first virtual address in the host's virtual address space, the controller executes command processing to read the first data from the non-volatile memory. The controller executes address translation processing to translate the first virtual address to a first physical address for accessing the host's memory. In the address translation processing, the controller sends an address translation request to the host to obtain first address translation information for translating the first virtual address to the first physical address. In response to receiving a response from the host indicating that obtaining the first address translation information failed, the controller suspends the command processing until it obtains the first address translation information, and then resumes the command processing after obtaining the first address translation information. [Brief explanation of the drawing]

[0009] [Figure 1] A block diagram showing an example configuration of an information processing system including a memory system according to the embodiment. [Figure 2] A diagram illustrating a series of processing steps for handling I / O commands, as executed in a memory system according to this embodiment. [Figure 3] A diagram illustrating the operation of a memory system according to an embodiment accessing host memory and the operation of a virtual machine on the host accessing host memory. [Figure 4]A diagram illustrating the relationship between the guest physical address space and the host physical address space used by the host. [Figure 5] A diagram showing a physical region page (PRP) entry and a physical region page list (PRP list) specified in a read command issued to the memory system according to the embodiment. [Figure 6] A diagram showing the address translation process performed in the memory system according to the embodiment. [Figure 7] A flowchart illustrating the procedure for address translation processing performed in the memory system according to the embodiment. [Figure 8] A sequence diagram showing a first example of the procedure for processing a read command in a memory system according to an embodiment. [Figure 9] A sequence diagram showing a second example of the command processing procedure for a read command, which is performed in the memory system according to the embodiment. [Figure 10] A sequence diagram showing a third example of the command processing procedure for a read command, which is performed in the memory system according to the embodiment. [Figure 11] A sequence diagram showing the procedure for address translation processing performed in the memory system according to the embodiment. [Figure 12] A sequence diagram showing an example of a procedure for interrupting a command process that reads data from non-volatile memory, which is performed in a memory system according to the embodiment. [Figure 13] A sequence diagram showing a first example of a procedure for controlling a command fetch operation, which is performed in a memory system according to an embodiment. [Figure 14] A sequence diagram showing a second example of a procedure for controlling a command fetch operation, which is performed in a memory system according to the embodiment. [Figure 15] A sequence diagram showing the procedure for invalidation processing performed in the memory system according to the embodiment. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, it is assumed that the memory system according to the embodiment is realized as an SSD. FIG. 1 is a block diagram showing a configuration example of an information processing system 1 including the memory system according to the embodiment. The information processing system 1 includes a host (host device) 2 and a solid state drive (SSD) 3. The host 2 and the SSD 3 can be connected via a bus 7.

[0011] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile terminal. The host 2 accesses the SSD 3. Specifically, the host 2 transmits a write command, which is a command for writing data, to the SSD 3. Also, the host 2 transmits a read command, which is a command for reading data, to the SSD 3.

[0012] The host 2 includes a processor 21, a memory 22, a root complex (RC) 23, and an input / output memory management unit (IOMMU) 213. The processor 21, the memory 22, the root complex 23, and the IOMMU 213 are interconnected via an internal bus 20.

[0013] The SSD 3 is a storage device connectable to the host 2. The SSD 3 includes a non-volatile memory. The SSD 3 writes data to the non-volatile memory. Then, the SSD 3 reads data from the non-volatile memory.

[0014] Communication between the SSD 3 and the host 2 is executed via the bus 7. The bus 7 is a transmission path connecting the host 2 and the SSD 3. The bus 7 is, for example, PCI express TM (PCIe TMThe PCIe bus is a full-duplex transmission path. A full-duplex transmission path includes both a transmission path that sends data and input / output (I / O) commands from host 2 to SSD 3, and a transmission path that sends data and responses from SSD 3 to host 2. I / O commands are commands for writing data to or reading data from non-volatile memory. Examples of I / O commands include write commands and read commands.

[0015] For example, NVM Express is a standard for the logical interface used to connect Host 2 and SSD 3. TM (NVMe TM The NVMe standard may be used. In the NVMe standard interface, communication between host 2 and SSD3 takes place using a pair of queues, which includes at least one submission queue (SQ) and a completion queue (CQ) associated with this at least one submission queue (SQ). This pair of queues is called a submission queue / completion queue pair (SQ / CQ pair).

[0016] A submission queue (SQ) is a queue used to issue commands to SSD3. Each submission queue (SQ) contains multiple slots, each capable of storing a command. Host 2 creates the submission queue (SQ) in its memory 22. Host 2 also issues a submission queue (SQ) create command to SSD3. The submission queue (SQ) create command notifies SSD3 of the address of the memory location in memory 22 where the submission queue (SQ) was created, the size of this submission queue (SQ), the identifier of the completion queue (CQ) associated with this submission queue (SQ), etc.

[0017] A completion queue (CQ) is a queue used to receive completion responses from SSD3 indicating the completion of a command. A completion response contains information indicating the status of the completed command. A completion response is also called a command completion or command completion notification. A completion queue (CQ) contains multiple slots, each capable of storing a completion response. Host 2 creates a completion queue (CQ) in its memory 22. Host 2 also issues a completion queue (CQ) create command to SSD3. The address indicating the storage location in memory 22 where the completion queue (CQ) was created, the size of this completion queue (CQ), etc., are notified to SSD3 by the completion queue (CQ) create command.

[0018] Next, we will describe the configuration of Host 2.

[0019] The processor 21 is, for example, a central processing unit (CPU). The processor 21 executes software (host software) loaded into memory 22 from SSD 3 or other storage devices connected to host 2. The host software includes, for example, a virtual machine monitor, a guest operating system (guest OS) which is an operating system that runs on the virtual machine monitor, application programs, etc.

[0020] Memory 22 is, for example, volatile memory. Memory 22 is also called main memory, system memory, or host memory. Memory 22 is, for example, dynamic random access memory (DRAM). A portion of the storage area of ​​memory 22 is used to store SQ / CQ pairs.

[0021] In communication between host 2 and SSD3, SQ / CQ pairs are used to issue commands from host 2 to SSD3 and to send completion replies from SSD3 to host 2. The transfer of commands, data, and completion replies between host 2 and SSD3 is performed via bus 7.

[0022] The root complex 23 is a circuit that connects an I / O device (SSD3 in this case) connected to the PCIe bus to the processor 21 and memory 22, respectively. The root complex 23 is connected to the processor 21 and memory 22, respectively. The root complex 23 may also be connected to the processor 21 and memory 22, for example, via the internal bus 20. The root complex 23 also communicates with SSD3 via bus 7.

[0023] The IOMMU213 is a circuit that translates addresses included in various requests received from the SSD3. The IOMMU213 translates the addresses used by the SSD3 to addresses used internally by the host 2.

[0024] Next, the internal configuration of SSD3 will be described. SSD3 includes a controller 4 and non-volatile memory 5. An example of non-volatile memory 5 is, for example, NAND flash memory. Hereafter, non-volatile memory 5 will be referred to as NAND memory 5. SSD3 may also further include random access memory, for example, dynamic random access memory (DRAM) 6.

[0025] Controller 4 is a memory controller. Controller 4 is a control circuit, such as a system-on-a-chip (SoC). Controller 4 is electrically connected to the NAND memory 5. Controller 4 performs data write operations to write data to the NAND memory 5 and data read operations to read data from the NAND memory 5. Controller 4 also communicates with the host 2 via bus 7. A Toggle NAND Flash Interface or an Open NAND Flash Interface (ONFI) can be used as the physical interface connecting Controller 4 and the NAND memory 5. The functions of each part of Controller 4 can be realized by dedicated hardware, a processor that runs programs, or a combination of these.

[0026] The NAND memory 5 is a non-volatile memory. The NAND memory 5 includes a memory cell array 51 and a page buffer 52. The memory cell array 51 includes a plurality of memory cells arranged in a matrix. The NAND memory 5 may be a two-dimensional flash memory or a three-dimensional flash memory.

[0027] The memory cell array 51 of the NAND memory 5 includes multiple blocks BLK0 to BLKx-1. Each of blocks BLK0 to BLKx-1 includes multiple pages (here, pages P0 to Py-1). Each page includes, for example, multiple memory cells connected to the same word line. Each of blocks BLK0 to BLKx-1 is a unit of data erasure operation that erases data. Each of pages P0 to Py-1 is a unit of program operation and sense operation, which will be described later.

[0028] The page buffer 52 is composed of, for example, static RAM (SRAM). The page buffer 52 temporarily stores data being transferred between the controller 4 and the NAND memory 5.

[0029] During a data write operation, data received from the controller 4 is temporarily stored in the page buffer 52 and then programmed into the memory cell array 51. The operation of temporarily storing data received from the controller 4 in the page buffer 52 is called the data-in operation. The operation of programming the data temporarily stored in the page buffer 52 into the memory cell array 51 is called the program operation.

[0030] During a data read operation, the data read from the memory cell array 51 is temporarily stored in the page buffer 52 and then output to the controller 4. The operation of temporarily storing the data read from the memory cell array 51 in the page buffer 52 is called a sense operation. The operation of outputting the data temporarily stored in the page buffer 52 to the controller 4 is called a data out operation.

[0031] Each of the data-in and data-out operations is an operation that transfers data between the controller 4 and the NAND memory 5. Each of the program and sense operations is an operation that involves data transfer within the NAND memory 5 but without data transfer between the controller 4 and the NAND memory 5. Therefore, each I / O operation performed on the NAND memory 5 (data write operation, data read operation) includes at least an operation that transfers data between the controller 4 and the NAND memory 5, and an operation that involves data transfer within the NAND memory 5 but without data transfer between the controller 4 and the NAND memory 5.

[0032] DRAM6 is volatile memory. Part of the memory area of ​​DRAM6 is used to store, for example, a logical-to-physical translation table (L2P table) 61. The L2P table 61 stores mapping information that shows the mapping between each logical address and each physical address in the NAND memory 5. In addition, part of the memory area of ​​DRAM6 is also used as an internal buffer 62. The internal buffer 62 temporarily holds, for example, write data received from host 2 or read data read from NAND memory 5.

[0033] Next, the internal configuration of controller 4 will be described. Controller 4 includes a host interface (host I / F) 41, a CPU 42, a direct memory access controller (DMAC) 43, static RAM (SRAM) 44, a NAND interface (NAND I / F) 45, an ECC encode / decode unit 46, and a DRAM interface (DRAM I / F) 47. These host interface 41, CPU 42, DMAC 43, SRAM 44, NAND interface 45, ECC encode / decode unit 46, and DRAM interface 47 are interconnected via a bus 40.

[0034] Among the components of the controller 4, the component that controls communication with the host 2 is called the front end (FE). The front end (FE) includes the host interface 41.

[0035] Furthermore, among the components of the controller 4, the component that controls communication with the NAND memory 5 is called the backend (BE). The backend (BE) includes the NAND interface 45 and the ECC encode / decode unit 46.

[0036] The host interface 41 is a communication interface circuit. The host interface 41 performs communication with host 2. The host interface 41 is, for example, a PCIe controller.

[0037] The host interface 41 includes an arbitration mechanism. This arbitration mechanism selects a submission queue from among multiple submission queues on host 2 to which a command should be fetched. The arbitration mechanism is, for example, a round-robin arbitration mechanism or a weighted round-robin arbitration mechanism.

[0038] The host interface 41 manages the submission queue tail pointer (SQTP) and the submission queue head pointer (SQHP) for each submission queue (SQ). Furthermore, the host interface 41 manages the completion queue tail pointer (CQTP) and the completion queue head pointer (CQHP) for each completion queue (CQ).

[0039] The CPU 42 is a processor. The CPU 42 controls the host interface 41, DMAC 43, SRAM 44, NAND interface 45, ECC encode / decode unit 46, and DRAM interface 47. The CPU 42 loads a control program (firmware) stored in the NAND memory 5 or a ROM (not shown) into the SRAM 44 and performs various processes by executing this firmware. The firmware may also be loaded into the DRAM 6.

[0040] The CPU 42, for example, as the Flash Translation Layer (FTL), manages the data stored in the NAND memory 5 and the blocks contained within the NAND memory 5. Managing the data stored in the NAND memory 5 includes, for example, managing mapping information, which is information indicating the correspondence between each logical address and each physical address in the NAND memory 5. A logical address is an address used by the host 2 to access the NAND memory 5. A logical address is, for example, an LBA (logical block address). The physical address of the NAND memory 5 is an address indicating the physical storage location contained within the NAND memory 5. The CPU 42 uses an L2P table 61 to manage the mapping between each logical address and each physical address. Furthermore, managing the blocks contained within the NAND memory 5 includes managing bad blocks, wear leveling, and garbage collection.

[0041] The DMAC43 is a circuit that performs direct memory access (DMA). The DMAC43 performs data transfer between the host 2's memory 22 and the SRAM 44 or DRAM 6. When transferring data from the controller 4 to the host 2's memory 22, the DMAC43 sends a memory write request to the host 2's root complex 23 to write the data to memory 22. The memory write request includes specifying the address that indicates the storage location in memory 22 to which this data should be transferred. When transferring data from the host 2's memory 22 to the controller 4, the DMAC43 sends a memory read request to the root complex 23 to retrieve the data from memory 22. The memory read request includes specifying the memory address that indicates the storage location in memory 22 where this data is stored.

[0042] SRAM44 is volatile memory. A portion of the SRAM44's memory area is used by the CPU42 as an Address Translation Cache (ATC)441. The ATC441 is a cache that stores address translation information. Address translation information is information used to translate virtual addresses in the host 2's virtual address space to physical addresses for accessing the host 2's memory 22. The host 2's virtual address space is the address space allocated to virtual machines running on host 2. As a virtual address within the virtual address space, for example, the guest physical address (GPA), which is the address used by the guest OS to access memory 22, is used.

[0043] The NAND interface 45 is a circuit that controls the NAND memory 5. If the NAND memory 5 is composed of multiple NAND flash memory dies, the NAND interface 45 may be connected to each of these multiple NAND flash memory dies via multiple channels.

[0044] The ECC encoding / decoding unit 46 is a circuit that performs data encoding and data decoding. The ECC encoding / decoding unit 46 performs encoding when writing data to the NAND memory 5. During encoding, the ECC encoding / decoding unit 46 adds error correction codes (ECC) as redundant codes to the data to be written. The ECC encoding / decoding unit 46 performs decoding when data is read from the NAND memory 5. During decoding, the ECC encoding / decoding unit 46 uses the ECC added to the data read from the NAND memory 5 to perform error correction on the data.

[0045] The DRAM interface 47 is a circuit that controls the DRAM 6. The DRAM interface 47 stores data in the DRAM 6 and reads data stored in the DRAM 6.

[0046] Next, the functional configuration of the CPU 42 will be described. The CPU 42 includes a command fetch unit 421, a command processing unit 422, and a virtual address translation control unit 423. Parts or all of each of the command fetch unit 421, the command processing unit 422, and the virtual address translation control unit 423 may be implemented by dedicated hardware of the controller 4. For example, the command fetch unit 421 may be implemented by the host interface 41.

[0047] The command fetch unit 421 fetches each I / O command from the submission queue (SQ) of host 2 via the host interface 41. This allows the controller 4 to receive multiple I / O commands from host 2.

[0048] The command processing unit 422 interprets the fetched I / O commands and executes command processing corresponding to the I / O commands. Command processing corresponding to I / O commands is, for example, processing to write data to or read data from the NAND memory 5. Specifically, the command processing unit 422 instructs the NAND memory 5 to execute a data write operation or a data read operation corresponding to the I / O command. The instruction for a data write operation or a data read operation to the NAND memory 5 is sent to the NAND memory 5 via the NAND interface 45.

[0049] For example, if the I / O command received (fetched) from host 2 is a read command, the command processing unit 422 executes a command to read the data to be read specified by the I / O command from NAND memory 5. The data to be read read from NAND memory 5 is temporarily stored in internal buffer 62. Then, the command processing unit 422 transfers the data to be read from internal buffer 62 to memory 22 of host 2.

[0050] Furthermore, the command processing unit 422 sends a completion response indicating the completion of the I / O command to the host 2 via the host interface 41. In this case, the command processing unit 422 stores the completion response in the completion queue (CQ) associated with the submission queue (SQ) from which the I / O command was fetched.

[0051] Furthermore, the command processing unit 422 sends an interrupt message to host 2 to notify host 2 that a new completion response has been stored in the completion queue (CQ).

[0052] The virtual address translation control unit 423 performs the address translation process necessary to access the memory 22 of host 2. The address translation process is the process of translating a virtual address notified to the controller 4 by a command from host 2 into a physical address for accessing the memory 22 of host 2. The virtual addresses notified to the controller 4 by a command from host 2 are, for example, (1) a virtual address corresponding to a storage location in memory 22 where write data to be written to NAND memory 5 is stored, (2) a virtual address corresponding to a storage location where a list containing multiple virtual addresses corresponding to multiple storage locations in memory 22 where write data is stored is stored, (3) a virtual address corresponding to a storage location in memory 22 to which read data read from NAND memory 5 should be transferred, (4) a virtual address corresponding to a storage location where a list containing multiple virtual addresses corresponding to multiple storage locations in memory 22 to which read data should be transferred is stored, (5) a virtual address corresponding to a storage location in memory 22 where a submission queue (SQ) exists, (6) a virtual address corresponding to a storage location in memory 22 where a completion queue (CQ) exists, or (7) a virtual address corresponding to a storage location in memory 22 to which an interrupt message should be transferred. The virtual address translation control unit 423 performs, for example, ATC search processing, address translation request issuance processing, or page request issuance processing.

[0053] In the ATC search process, the virtual address translation control unit 423 determines whether address translation information corresponding to the target virtual address is stored in the ATC 441. If address translation information is stored in the ATC 441, the virtual address translation control unit 423 uses the address translation information stored in the ATC 441 to translate the virtual address to the physical address in memory 22. If address translation information is not stored in the ATC 441, the address translation process using the ATC 441 fails. In this case, the virtual address translation control unit 423 executes an address translation request issuance process.

[0054] In the address translation request issuance process, the virtual address translation control unit 423 sends an address translation request to the host 2 to translate the target virtual address to the physical address of memory 22. Upon receiving the address translation request, the host 2 executes a process to obtain address translation information corresponding to the virtual address specified in the address translation request. If the address translation information can be obtained, the host 2 sends the address translation information to the virtual address translation control unit 423 of SSD3. The virtual address translation control unit 423 uses the received address translation information to translate the virtual address to the physical address of memory 22. If the address translation information cannot be obtained, the host 2 sends a response to the virtual address translation control unit 423 of SSD3 indicating that the acquisition of address translation information failed. Upon receiving a response from the host 2 indicating that the acquisition of address translation information failed, the virtual address translation control unit 423 executes a page request issuance process.

[0055] In the page request issuance process, the virtual address translation control unit 423 sends a page request to host 2. The page request is a message requesting that the host 2 prepare the address translation information necessary for address translation processing. Upon receiving the page request, host 2 executes the process of preparing the address translation information necessary to translate virtual addresses to physical memory addresses. Once the preparation of the address translation information is complete, host 2 sends a response to the SSD3's virtual address translation control unit 423 indicating that the preparation of the address translation information is complete. Upon receiving the response indicating that the preparation of the address translation information is complete, the virtual address translation control unit 423 sends an address translation request to host 2 again. Upon receiving the address translation request, host 2 sends a response to the address translation request, including the prepared address translation information, to the SSD3's virtual address translation control unit 423. The virtual address translation control unit 423 uses the address translation information included in the received response to translate the virtual addresses to the physical addresses of memory 22.

[0056] Furthermore, the virtual address translation control unit 423 notifies the command processing unit 422 or the command fetch unit 421 of information regarding the status of the address translation process, for example, (1) information indicating the success (cache hit) or failure (cache miss) of the ATC search process, (2) information indicating the success or failure of obtaining address translation information executed on host 2 in response to an address translation request, or (3) information indicating the completion of the process of preparing address translation information executed on host 2 in response to a page request.

[0057] The time required to obtain the physical address of memory 22 varies depending on the status of the address translation process. For example, if a cache miss occurs in ATC441, the time required to obtain the physical address of memory 22 will be longer than if a cache hit occurs in ATC441. Furthermore, if a response indicating that the acquisition of address translation information failed is received from host 2, the time required to obtain the physical address of memory 22 will be even longer. Until the physical address of memory 22 is acquired, controller 4 cannot send information such as read data, completion responses, and interrupt messages to host 2. Therefore, if command processing corresponding to an I / O command is executed without considering the status of the address translation process, information that cannot be sent to host 2 may accumulate in, for example, the controller 4's internal buffer 62, and the internal buffer 62 may be occupied by information that cannot be sent to host 2. In this case, not only will the processing of this I / O command be delayed, but it will also become impossible to fetch other I / O commands, which can lead to a decrease in the performance of SSD3's I / O processing.

[0058] Therefore, the controller 4 adaptively controls the processing of I / O commands based on the status of the address translation process.

[0059] For example, if the controller 4 receives a read command from host 2 that specifies a virtual address in host 2's virtual address space, the controller 4 starts command processing to read the data to be read specified by the read command from the NAND memory 5.

[0060] Furthermore, the controller 4 performs address translation processing to convert the virtual address specified by the read command into a physical address for accessing the memory 22 of the host 2.

[0061] If the address translation process is successful, the controller 4 identifies the storage location in memory 22 to which the data should be transferred based on the physical address obtained during the address translation process. If the virtual address specified by the command from host 2 is a virtual address corresponding to the storage location in memory 22 to which the data should be transferred, the controller 4 identifies the storage location indicated by the obtained physical address as the storage location in memory 22 to which the data should be transferred. If the size of the data specified by the read command is relatively large, the specified virtual address may be a virtual address corresponding to a storage location in memory 22 where a list containing multiple virtual addresses is stored. In this case, the controller 4 performs a first address translation process and a second address translation process to identify the storage location in memory 22 to which the data should be transferred. The first address translation process is the process of translating the specified virtual address to a first physical address indicating a storage location where a list containing multiple virtual addresses is stored. The second address translation process is the process of translating the multiple virtual addresses included in the list to multiple second physical addresses in memory 22. The controller 4 identifies each of the multiple storage locations in memory 22, indicated by the second physical address, as a storage location in memory 22 to which the data should be transferred.

[0062] The controller 4 then transfers the data read from the NAND memory 5 to one or more specified storage locations in the memory 22.

[0063] On the other hand, if the address translation process fails, the controller 4 suspends the command processing for reading the target data from the NAND memory 5 until the address translation information necessary for the address translation process becomes available. Once the address translation information becomes available, the controller 4 resumes the command processing.

[0064] For example, when a cache miss occurs, controller 4 may interrupt command processing. Alternatively, controller 4 may interrupt command processing not when a cache miss occurs, but when it receives a response from host 2 indicating that the acquisition of address translation information failed.

[0065] To interrupt command processing, controller 4 may stop sending each of the instructions required to read the data specified by the read command that have not yet been sent to NAND memory 5. For example, consider a case where reading the data specified by a single read command requires sending 10 sense instructions to NAND memory 5 to perform 10 sense operations. For example, if 4 sense instructions have already been sent to NAND memory 5 and the remaining 6 sense instructions have not yet been sent, controller 4 will not send the remaining 6 sense instructions to NAND memory 5. The data based on the 4 sense instructions already sent to NAND memory 5 is transferred from NAND memory 5 to controller 4. Controller 4 maintains this data in its internal buffer 62 and does not send it to host 2. When command processing resumes, controller 4 sends the remaining 6 sense instructions to NAND memory 5 and reads the remaining data of the data to be read from NAND memory 5. The controller 4 then sends the data maintained in the internal buffer 62 and the remaining data read from the NAND memory 5 to the host 2.

[0066] In this way, interrupting command processing prevents the internal buffer 62 from being occupied for a long period of time by read data that cannot be sent to host 2. Also, interrupting command processing prevents read data that cannot be sent to host 2 from being transferred from NAND memory 5 to controller 4. This reduces the peak value of data transfer volume between NAND memory 5 and controller 4, and therefore also reduces the peak power consumption of both NAND memory 5 and controller 4.

[0067] Furthermore, when the controller 4 sends first information (a completion response or interrupt message) to the host 2 to notify the host 2 of the completion of an I / O command, it also performs address translation processing. In this address translation processing, a process is performed to translate the virtual address corresponding to the storage location in the host 2's memory 22 to which the first information (a completion response or interrupt message) should be transferred, into a physical address for accessing memory 22.

[0068] If this address translation process is successful, the controller 4 uses the physical address obtained during the address translation process to transfer the first piece of information (completion response or interrupt message) to the memory 22.

[0069] On the other hand, if the address translation process fails, the controller 4 suspends the first process of fetching the I / O command from each submission queue associated with the completion queue where the completion response for this I / O command should be stored, until the address translation information necessary for the address translation process becomes available, and then resumes the first process after the address translation information becomes available. As a result, it is possible to prevent resources within the controller 4 (e.g., SRAM 44) from being occupied by completion responses or interrupt messages that cannot be sent to the host 2.

[0070] Next, a series of processing steps for handling I / O commands will be described. Figure 2 is a diagram showing a series of processing steps for handling I / O commands executed in the memory system according to the embodiment. Figure 2 shows the steps from when an I / O command is issued by host 2 until a completion response corresponding to this I / O command is processed by host 2.

[0071] Step 1: Host 2 stores one or more new I / O commands to send to SSD3 in one or more free SQ slots of the submission queue (SQ). These one or more new I / O commands are stored in one or more free SQ slots starting from the slot indicated by the current value of the submission queue tail pointer (SQTP). The new I / O commands stored in the submission queue (SQ) may be write commands, read commands, or other I / O commands. In Figure 2, each I / O command stored in the submission queue (SQ) is denoted as "CMD".

[0072] Step 2: To notify the SSD3 controller 4 that one or more new I / O commands have been stored in the submission queue (SQ), host 2 writes to the submission queue tail doorbell register in SSD3 corresponding to this submission queue (SQ) and updates the value of the submission queue tail pointer (SQTP) corresponding to this submission queue (SQ). The value of the submission queue tail pointer (SQTP) is incremented by the number of new I / O commands stored in the submission queue (SQ). Such an update of the submission queue tail pointer (SQTP) triggers controller 4 to start processing each of the I / O commands stored in the submission queue (SQ).

[0073] Step 3: The controller 4 can determine the number of new I / O commands stored in the submission queue (SQ) from the difference between the new value of the submission queue tail pointer (SQTP) and the value of the submission queue head pointer (SQHP). The controller 4 fetches one or any number of I / O commands from the submission queue (SQ). Each fetched I / O command is temporarily stored in the controller 4's SRAM 44.

[0074] Step 4: Controller 4 updates the value of the submission queue head pointer (SQHP) corresponding to this submission queue (SQ) so that the value of the SQHP increases by the number of I / O commands fetched in Step 3.

[0075] Step 5: The controller 4 executes each of the fetched I / O commands. That is, the controller 4 executes the command processing corresponding to each of the fetched I / O commands. The order in which these command processing operations corresponding to each I / O command are executed is not restricted, and these I / O commands may be processed in an order different from the order in which they were fetched. In the command processing corresponding to each I / O command, the controller 4 transfers data from memory 22 to the internal buffer 62, or from the internal buffer 62 to memory 22, as necessary.

[0076] Step 6: Once command processing corresponding to an I / O command is complete, controller 4 first updates the completion queue tail pointer (CQTP) corresponding to the completion queue (CQ) associated with the submission queue (SQ) from which the completed I / O command was fetched, by incrementing the value of this completion queue tail pointer (CQTP) by 1.

[0077] Step 7: Controller 4 stores a new completion response indicating the status of this completed I / O command in the next free CQ slot of this completion queue (CQ). In Figure 2, each completion response stored in the completion queue (CQ) is denoted as "CPL".

[0078] Step 8: The controller 4 sends an interrupt message to the host 2 associated with the completion queue (CQ) in which the completion response was stored in Step 7, notifying the host 2 that a new completion response has been stored in the completion queue (CQ). In this case, the controller 4 transfers the interrupt message to memory 22 by sending a memory write request to the host 2 specifying a predetermined memory address. The storage location in memory 22 to which the interrupt message should be transferred may be predetermined by the host 2 for each completion queue (CQ), for example.

[0079] Step 9: Host 2 retrieves completion responses from the CQ slots indicated by the current value of the Completion Queue Head Pointer (CQHP) and processes the retrieved completion responses.

[0080] Step 10: Host 2 writes to the Completion Queue Head Doorbell Register in SSD3 corresponding to this Completion Queue (CQ) to update the value of the Completion Queue Head Pointer (CQHP). The value of the Completion Queue Head Pointer (CQHP) is incremented by the number of completion responses processed in Step 9.

[0081] Next, we will describe the operation of accessing the memory 22 of host 2. Figure 3 is a diagram showing the operation of the memory system according to the embodiment accessing the host's memory and the operation of the virtual machine on the host accessing the host's memory.

[0082] On host 2, the Virtual Machine Monitor (VMM) 211 is run. VMM211 is software that creates one or more virtual machines on the computer acting as host 2. VMM211 operates each of the virtual machines it creates. In Figure 3, VMM211 creates virtual machine VM0 and virtual machine VM1, and virtual machine VM0 and virtual machine VM1 run on VMM211. The operation of virtual machine VM0 is controlled by guest OS#0, which is an operating system running on VMM211. The operation of virtual machine VM1 is controlled by guest OS#1, which is another operating system running on VMM211.

[0083] The guest OS#0 of virtual machine VM0 accesses memory 22 using the guest physical address (GPA) in the guest physical address space (GPA space) allocated to virtual machine VM0 by VMM211. The GPA space allocated to virtual machine VM0 is the virtual address space used by guest OS#0 to access memory 22.

[0084] The guest OS#1 of virtual machine VM1 accesses memory 22 using the guest physical address (GPA) in the guest physical address space (GPA space) allocated to virtual machine VM1 by VMM211. The GPA space allocated to virtual machine VM1 is the virtual address space used by guest OS#1 to access memory 22.

[0085] Host 2 includes a Memory Management Unit (MMU) 212 in addition to the IOMMU 213.

[0086] The MMU212 translates the GPA included in the memory access requests issued by each of the processors 21 (guest OS#0 and guest OS#1 in Figure 3) into a host physical address (HPA). The HPA is the physical address for accessing memory 22. The MMU212 uses the HPA to access memory 22.

[0087] The IOMMU213 translates the memory address included in the memory access request issued by SSD3 into an HPA. In other words, the address that SSD3 issues to access memory 22 is the GPA in the GPA space used by the guest OS. Therefore, the IOMMU213 translates the GPA included in the memory access request issued by SSD3 into an HPA. For example, if SSD3 is mapped to virtual machine VM0 as an I / O device for virtual machine VM0, the IOMMU213 translates the GPA included in the memory access request issued by SSD3 into an HPA based on the correspondence between the GPA space of guest OS#0 and the HPA space of memory 22.

[0088] Here, we will explain the case where a read command is issued to SSD3 from guest OS#0. The read command specifies the starting logical block address corresponding to the data to be read, the length of the data to be read (number of logical block addresses), and a data pointer. The data pointer is information about the storage location in memory 22 to which the data to be read should be transferred.

[0089] Memory 22 is logically divided into multiple storage locations called memory pages. The size of the memory pages is set by host 2. The minimum configurable memory page size is, for example, 4 KiB.

[0090] A read command can specify one or more memory locations (memory pages) in memory 22 to which the data to be read should be transferred, using a physical region page (PRP) entry, a PRP list, or a scatter-gather list (SGL). Here, we assume that the read command uses a PRP entry. The read command includes a first PRP entry field (PRP1) and a second PRP entry field (PRP2). Each of PRP1 and PRP2 uses a PRP entry to specify a memory page. A PRP entry is a pointer to a memory page. A PRP entry includes the page base address of the memory page and the offset within that memory page. The page base address is the address that identifies a single memory page.

[0091] Since guest OS#0 is only aware of its own GPA space, PRP1 and PRP2, each included in the read command issued by guest OS#0, use GPA to specify the page base address of the memory page.

[0092] Upon receiving a read command, SSD3 executes the command processing corresponding to the received read command. Based on the received read command, SSD3 starts command processing to read the data to be read from NAND memory 5. Then, SSD3 refers to PRP1 and PRP2 included in the read command and obtains the GPA corresponding to one or two memory pages to which the data to be read should be transferred. Note that if the size of the data to be read is small, the read command may use only PRP1 to specify only the GPA corresponding to one memory page.

[0093] SSD3 sends a memory write request to host 2 specifying the acquired GPA in order to transfer the data to be read from NAND memory 5 to memory 22. This memory write request is received by IOMMU213. If SSD3 is an I / O device associated with virtual machine VM0, IOMMU213 converts the GPA included in the memory write request to HPA based on the correspondence between the HPA space and the GPA space of virtual machine VM0. Then, IOMMU213 writes the data to be read to memory 22 using HPA. As a result, the data to be read is stored in the memory location (memory page) in memory 22 indicated by the HPA.

[0094] Next, we will explain the relationship between the GPA space and the HPA space. Figure 4 shows the relationship between the GPA space and the HPA space used by the host. Here, as with Figure 3, it is assumed that two virtual machines (virtual machines VM0 and VM1) are running on host 2.

[0095] Virtual machine VM0 is allocated GP space #0, which ranges from 0x000000 to 0x0FFFFF. Similarly, virtual machine VM1 is allocated GP space #1, which ranges from 0x000000 to 0x0FFFFF. Here, 0x represents the hexadecimal representation.

[0096] Each of these GP spaces is a subset of the HPA space and is mapped to a specific range within the HPA space. In the example in Figure 4, GPA space #0 is mapped, for example, to the range 0x200000 to 0x2FFFFF in the HPA space. In this case, for example, 0x050000 in GPA space #0 is converted to 0x250000 in the HPA space by the MMU212 or IOMMU213. GPA space #1 is mapped, for example, to the range 0x100000 to 0x1FFFFF in the HPA space. In this case, for example, 0x050000 in GPA space #1 is converted to 0x150000 in the HPA space by the MMU212 or IOMMU213.

[0097] Next, we will describe the PRP list specified in the read command. Figure 5 shows the PRP entry and PRP list specified in the read command issued to the memory system according to this embodiment.

[0098] If the size of the data to be read is greater than the total size that can be described by the two PRP entry fields (PRP1, PRP2) of the read command, i.e., greater than the size corresponding to two memory pages, then at least one of the two PRP entry fields of the read command is used to specify a PRP list. A PRP list is a collection of multiple PRP entries. A PRP list containing multiple PRP entries is stored in a single memory page. The PRP entry field that specifies a PRP list indicates the page base address of the memory page in which the PRP list is stored.

[0099] Figure 5 illustrates a case where a read command uses PRP1 and PRP2 to specify four memory pages in memory 22 to which the data to be read should be transferred. In Figure 5, PRP1 included in the read command specifies one memory page using a PRP entry. PRP2 included in the read command specifies three memory pages using a PRP list.

[0100] PRP1 indicates the page base address of a single memory page. In this case, PRP1 indicates, for example, the page base address of memory page #0.

[0101] PRP2 indicates the page base address of another memory page that stores the PRP list. The memory page indicated by PRP2 contains multiple PRP entries. In this case, the memory page indicated by PRP2 contains, for example, three PRP entries, namely PRP entries #0 to #2. PRP entries #0 to #2 each indicate the page base addresses of three memory pages, for example, pages #1 to #3.

[0102] Consider the case where the read command specifies start LBA=LBA#0 and data length=4LBA. If the data size corresponding to 1LBA is 4KiB and the size of the memory page is 4KiB, then the four data corresponding to LBA#0 to #3, each with a size of 4KiB, will be transferred to the four memory pages corresponding to pages #0 to #3, respectively.

[0103] In cases where this read command is issued to SSD3 by guest OS#0 or guest OS#1, PRP1 and PRP2 each specify a memory page using the GPA. That is, the address stored in PRP1 of the read command indicates the GPA corresponding to the memory page #0. The address stored in PRP2 of the read command indicates the GPA corresponding to the memory page storing the PRP list.

[0104] Each of the multiple PRP entries in the PRP list also uses GPA to specify a memory page. For example, the address stored in PRP entry #0 in the PRP list indicates the GPA corresponding to the memory page #1. The address stored in PRP entry #1 in the PRP list indicates the GPA corresponding to the memory page #2. The address stored in PRP entry #2 in the PRP list indicates the GPA corresponding to the memory page #3.

[0105] Therefore, in order to access the three memory pages (pages #1 to #3), it is necessary to perform the following steps: (1) convert the GPA indicated by PRP2 to the HPA in memory 22 and obtain the PRP list from memory 22; (2) convert the GPA indicated by PRP entry #0 included in the obtained PRP list to the HPA in memory 22; (3) convert the GPA indicated by PRP entry #1 included in the obtained PRP list to the HPA in memory 22; and (4) convert the GPA indicated by PRP entry #2 included in the obtained PRP list to the HPA in memory 22.

[0106] Similar to the PRP entry fields (PRP1, PRP2) included in the read command, the PRP entry fields (PRP1, PRP2) included in the write command can also specify the memory page where the PRP list is stored.

[0107] Furthermore, SGL can be used instead of PRP lists for both read and write commands. SGL, like PRP lists, is used to utilize more memory pages for data transfer than the number of memory pages that can be written to the command itself.

[0108] Next, the address translation process will be described. Figure 6 shows the address translation process performed in the memory system according to the embodiment. The IOMMU213 includes a translation agent (TA)214 and an address translation protection table (ATPT)215. The functions of each part of the IOMMU213 can be realized by dedicated hardware, a processor that executes a program, or a combination thereof.

[0109] In the PCIe standard, the functions related to IOMMU213 are defined as address translation services (ATS). ATS is a protocol for address translation communication between host 2 and SSD3. In the following, the address translation request described with reference to Figure 1 will be referred to as an ATS translation request. An ATS translation request is an address translation request that translates a virtual address to a physical address for accessing memory 22.

[0110] The translation agent 214 receives an ATS translation request from SSD3 via RC23 and executes the ATS translation process. The ATS translation process is the process of obtaining address translation information corresponding to the virtual address specified by the received ATS translation request from the address translation protection table 215. In ATS, the virtual address is defined as an Untranslated Address, and the physical address of memory 22 is defined as a Translated Address. The virtual address is, for example, GPA. The physical address is, for example, HPA. The translation agent 214 then sends an ATS completion response containing the address translation information obtained from the address translation protection table 215 to SSD3 via RC23.

[0111] The address translation protection table 215 is a table that stores address translation information.

[0112] When translating a virtual address specified by host 2 (e.g., guest OS) to a physical address in memory 22, the virtual address translation control unit 423 first searches the ATC 441 to determine whether address translation information corresponding to that virtual address is stored in the ATC 441. If address translation information is not stored in the ATC 441, the virtual address translation control unit 423 sends an ATS translation request specifying that virtual address to the RC 23 of host 2. When the RC 23 receives an ATS translation request from SSD 3, it sends the received ATS translation request to the translation agent 214.

[0113] Upon receiving an ATS translation request, the translation agent 214 searches the address translation protection table 215 to determine whether address translation information corresponding to the virtual address specified in the ATS translation request is stored in the address translation protection table 215. If address translation information is stored in the address translation protection table 215, the translation agent 214 retrieves the retrieved address translation information from the address translation protection table 215. The address translation information retrieved from the address translation protection table 215 includes the physical address corresponding to the virtual address specified in the ATS translation request, or both this physical address and the virtual address specified in the ATS translation request. The translation agent 214 sends an ATS completion response containing the retrieved address translation information to the virtual address translation control unit 423 via the RC23. If address translation information is not stored in the address translation protection table 215, or if other errors occur, the translation agent 214 sends an ATS completion response via the RC23 to the virtual address translation control unit 423 indicating that the ATS translation process failed, that is, that the retrieval of address translation information failed.

[0114] When an ATS completion response containing address translation information is received, the virtual address translation control unit 423 stores in the ATC 441 the physical address included in the address translation information of the received ATS completion response, or both the virtual address and the physical address included in the address translation information of the received ATS completion response.

[0115] If the ATS completion response indicating that the acquisition of address translation information failed is received from the translation agent 214, the virtual address translation control unit 423 sends a page request message to the RC23 of host 2, which is a message requesting that the address translation information be prepared. Upon receiving the page request, the RC23 notifies, for example, the processor 21 or VMM211 of the received page request. This causes host 2 (processor 21 or VMM211) to begin the process of preparing the address translation information in the address translation protection table 215. Once the address translation information is prepared, host 2 sends a response to the page request via the RC23 to the virtual address translation control unit 423, indicating that the preparation of the address translation information is complete. The response to the page request is a response indicating that the preparation of the address translation information is complete. Upon receiving the response to the page request, the virtual address translation control unit 423 sends the ATS translation request again to the translation agent 214.

[0116] Furthermore, if the address translation information in the address translation protection table 215 is changed, for example, by updating the correspondence between the GPA space and the HPA space, the translation agent 214 sends a deactivation request to the virtual address translation control unit 423 via RC23 to invalidate the old address translation information stored in the ATC441. The deactivation request is a request that specifies a range of specific virtual addresses. Upon receiving the deactivation request, the virtual address translation control unit 423 invalidates each of the entries in the ATC441 that store the address translation information corresponding to the specified range of virtual addresses.

[0117] Next, the procedure for address translation processing will be described. Figure 7 is a flowchart showing the procedure for address translation processing performed in the memory system according to the embodiment. When a memory read request or memory write request is sent to the host 2, the virtual address translation control unit 423 of the controller 4 starts the address translation processing.

[0118] The virtual address translation control unit 423 searches the ATC 441 for address translation information necessary to translate the target GPA to the physical address of memory 22, and determines whether or not address translation information corresponding to the target GPA exists in the ATC 441 (step S101).

[0119] If address translation information corresponding to the target GPA exists in ATC441, that is, if a cache hit occurs in ATC441 (Yes in step S101), the virtual address translation control unit 423 obtains the address translation information from ATC441. The virtual address translation control unit 423 uses the address translation information obtained from ATC441 to translate the target GPA to the physical address (HPA) of memory 22 (step S102).

[0120] If address translation information corresponding to the target GPA does not exist in ATC441, that is, if a cache miss occurs in ATC441 (No in step S101), the virtual address translation control unit 423 sends an ATS translation request specifying the target GPA to host 2 (step S103). Upon receiving the ATS translation request, host 2 executes an ATS translation process to obtain address translation information corresponding to the specified GPA from the address translation protection table 215. Once the ATS translation process is complete, host 2 sends an ATS completion response to the virtual address translation control unit 423. If the acquisition of address translation information is successful, host 2 sends an ATS completion response to the virtual address translation control unit 423 that includes the address translation information and a status indicating that the acquisition of address translation information was successful, i.e., that the ATS translation process was successful. If the acquisition of address translation information fails, host 2 sends an ATS completion response to the virtual address translation control unit 423 that includes a status indicating that the acquisition of address translation information failed, i.e., that the ATS translation process failed.

[0121] The virtual address translation control unit 423 receives an ATS completion response from host 2 (step S104).

[0122] The virtual address translation control unit 423 determines whether the received ATS completion response includes a status indicating success (step S105).

[0123] If the received ATS completion response includes a status indicating success (Yes in step S105), the virtual address translation control unit 423 stores the address translation information included in the received ATS completion response in the ATC 441 (step S106).

[0124] The virtual address translation control unit 423 uses the address translation information received in step S104 to convert the target GPA to HPA (step S102).

[0125] Furthermore, if the received ATS completion response includes a status indicating failure (No in step S105), the virtual address translation control unit 423 sends a page request to host 2 (step S107). Upon receiving the page request, host 2 begins the process of preparing address translation information corresponding to the GPA specified by the page request. In the process of preparing the address translation information, host 2 prepares the address translation information corresponding to the GPA specified by the page request in the address translation protection table 215. Once the process of preparing the address translation information is complete, host 2 sends a response to the page request to the virtual address translation control unit 423.

[0126] The virtual address translation control unit 423 receives a response to the page request from host 2 (step S108).

[0127] The virtual address translation control unit 423 sends an ATS translation request to host 2 again, specifying the target GPA (step S109). Upon receiving the ATS translation request, host 2 executes an ATS translation process to obtain address translation information corresponding to the specified GPA from the address translation protection table 215. The address translation information corresponding to the specified GPA is already prepared in the address translation protection table 215. Therefore, the ATS translation process is expected to succeed. Once the ATS translation process is complete, host 2 sends an ATS completion response to the virtual address translation control unit 423, which includes a status indicating success and the address translation information.

[0128] The virtual address translation control unit 423 receives an ATS completion response from host 2 (step S110).

[0129] The virtual address translation control unit 423 determines whether the received ATS completion response includes a status indicating success (step S111).

[0130] If the received ATS completion response includes a status indicating success (Yes in step S111), the virtual address translation control unit 423 stores the address translation information contained in the received ATS completion response in the ATC 441 (step S112).

[0131] The virtual address translation control unit 423 uses the address translation information contained in the received ATS completion response to convert the target GPA to HPA (step S102).

[0132] If the received ATS completion response contains a status indicating failure (No in step S111), the virtual address translation control unit 423 resends the page request to host 2 (step S107).

[0133] Thus, when performing address translation processing, the time required for address translation processing differs depending on whether address translation information can be obtained from ATC441, whether address translation information can be obtained by sending an ATS translation request, or whether address translation information can be obtained by sending a page request and then sending an ATS translation request again. Therefore, in the SSD3 according to this embodiment, command processing is controlled according to the status of the address translation processing.

[0134] First, the control of processing for read commands will be explained. Figure 8 is a sequence diagram showing a first example of the procedure for processing read commands executed in the memory system according to the embodiment. In Figure 8, it is assumed that the PRP list is specified by the PRP entry field included in the read command, that is, that the PRP entry field indicates the GPA corresponding to the storage location (memory page) where the PRP list is stored. Also, in Figure 8, it is assumed that a cache hit occurs in all address translation operations.

[0135] In the command fetch process, the front end (FE) of controller 4 issues a fetch request for an I / O command using the GPA (step S201). This GPA is a virtual address corresponding to the SQ slot of the submission queue (SQ) to which the I / O command should be fetched. The FE of controller 4 passes the issued fetch request to the virtual address translation control unit 423.

[0136] The virtual address translation control unit 423 searches the ATC441 for address translation information corresponding to the GPA included in the fetch request received from the FE (step S202). If the address translation information corresponding to this GPA is stored in the ATC441 (cache hit), the virtual address translation control unit 423 retrieves the address translation information from the ATC441 and uses the retrieved address translation information to convert the GPA to HPA (step S203).

[0137] The command fetch unit 421 issues a memory read request to fetch an I / O command from memory 22 using the HPA translated by the virtual address translation control unit 423 (step S204). Hereinafter, the memory read request will be referred to as a DMA read request. In step S204, the command fetch unit 421 sends the DMA read request, including the translated HPA, to the RC23 of host 2. Based on the HPA included in the DMA read request received from controller 4, RC23 reads an I / O command (in this case, a read command) from the SQ slot of memory 22 and sends the read command to controller 4 as a response corresponding to the DMA read request. As a result, FE receives the read command from host 2 (step S205). The received read command is passed from FE to BE. BE starts command processing to read the data to be read specified by the read command from NAND memory 5. Then, FE proceeds to data transfer processing.

[0138] In the data transfer process, the FE issues a fetch request for the PRP list using the GPA contained in the PRP entry field of the received read command (step S206). The FE passes the issued fetch request to the virtual address translation control unit 423.

[0139] The virtual address translation control unit 423 searches the ATC441 for address translation information corresponding to the GPA included in the fetch request received from the FE (step S207). If the address translation information corresponding to this GPA is stored in the ATC441 (cache hit), the virtual address translation control unit 423 retrieves the address translation information from the ATC441 and uses the retrieved address translation information to convert the GPA to HPA (step S208).

[0140] The command fetch unit 421 issues a DMA read request to fetch the PRP list from memory 22 using the HPA translated by the virtual address translation control unit 423 (step S209). In step S209, the command fetch unit 421 sends the DMA read request, including the translated HPA, to the RC23 of host 2. Based on the HPA included in the DMA read request received from controller 4, RC23 reads the PRP list from memory 22 and sends the read PRP list to controller 4 as a response corresponding to the DMA read request. As a result, the FE of controller 4 receives the PRP list from host 2 (step S210).

[0141] The PRP list contains multiple GPAs, each corresponding to a different storage location in memory 22 to which the read data should be transferred. For each GPA included in the PRP list, the FE performs the following processing:

[0142] The FE selects one GPA from the PRP list and issues a request to transfer read data to memory 22 using the selected GPA (step S211). The FE passes the issued transfer request to the virtual address translation control unit 423.

[0143] The virtual address translation control unit 423 searches the ATC441 for address translation information corresponding to the GPA included in the forwarding request received from the FE (step S212). If a cache hit occurs, the virtual address translation control unit 423 uses the address translation information from the ATC441 to translate the GPA to the HPA (step S213).

[0144] The DMAC43 issues a memory write request to transfer the read data to memory 22 using the HPA translated by the virtual address translation control unit 423 (step S214). Hereinafter, the memory write request will be referred to as a DMA write request. In step S214, the DMAC43 sends a DMA write request containing the translated HPA and the read data to the RC23 of host 2. The RC23 stores the read data included in the received DMA write request in the storage location in memory 22 indicated by the HPA included in the DMA write request received from the controller 4. To perform the transfer process for all the read data, the controller 4 performs the processes in steps S211 to S214 a number of times equal to the number of GPAs included in the PRP list. Once the transfer process for all the read data is complete, the FE moves on to the completion response transfer process.

[0145] In the completion response transfer process, the FE issues a transfer request for the completion response to memory 22 using the GPA (step S215). This GPA is the GPA corresponding to the storage location in memory 22 to which this completion response should be transferred, that is, the GPA corresponding to the next free CQ slot in the completion queue (CQ) associated with the SQ from which the completed read command was fetched. The FE passes the issued transfer request to the virtual address translation control unit 423.

[0146] The virtual address translation control unit 423 searches the ATC441 for address translation information corresponding to the GPA included in the forwarding request received from the FE (step S216). If a cache hit occurs, the virtual address translation control unit 423 uses the address translation information from the ATC441 to translate the GPA into HPA (step S217).

[0147] The DMAC43 issues a DMA write request to transfer a completion response to memory 22 using the HPA translated by the virtual address translation control unit 423 (step S218). In step S218, the DMAC43 sends the DMA write request, which includes the translated HPA and the completion response, to the RC23 of host 2. The RC23 stores the completion response included in the received DMA write request in the storage location in memory 22 indicated by the HPA included in the DMA write request received from controller 4. Then, the FE proceeds to interrupt transmission processing.

[0148] In interrupt transmission processing, the FE issues a request to send an interrupt message to memory 22 using the GPA (step S219). This GPA is the GPA corresponding to the storage location in memory 22 to which the interrupt message should be sent. The interrupt message includes an interrupt vector associated with the completion queue (CQ) in which the completion response was stored in step S218. The FE passes the issued transmission request to the virtual address translation control unit 423.

[0149] The virtual address translation control unit 423 searches the ATC441 for address translation information corresponding to the GPA included in the transmission request received from the FE (step S220). If a cache hit occurs, the virtual address translation control unit 423 uses the address translation information from the ATC441 to convert the GPA to HPA (step S221).

[0150] The DMAC43 issues a DMA write request to send an interrupt message to memory 22 using the HPA translated by the virtual address translation control unit 423 (step S222). In step S222, the DMAC43 sends the DMA write request, which includes the translated HPA and the interrupt message, to the RC23 of host 2. The RC23 stores the received interrupt message in the memory location in memory 22 indicated by the HPA included in the DMA write request received from controller 4. Then, the series of processes for the read command is completed.

[0151] Next, we will explain the case where a cache miss occurs in ATC441. Figure 9 is a sequence diagram showing a second example of the procedure for processing a read command executed in the memory system according to the embodiment.

[0152] In the command fetch process, the controller 4 executes the processes in steps S301 to S302. The processes in steps S301 to S302 are the same as the processes in steps S201 to S202 described in Figure 8. If a cache miss occurs in ATC441 in step S302, the virtual address translation control unit 423 sends an ATS translation request to the host 2 specifying the GPA included in the fetch request received from the FE (step S303). The host 2 searches the address translation protection table 215 for address translation information corresponding to the GPA, which is the Untranslated Address specified by the ATS translation request received from the controller 4. If the address translation information can be obtained from the address translation protection table 215, the host 2 sends an ATS completion response to the controller 4, which includes the obtained address translation information and a status indicating the success of the ATS translation process.

[0153] The virtual address translation control unit 423 receives an ATS completion response from host 2 (step S304).

[0154] Since the ATS translation process was successful, the virtual address translation control unit 423 stores the address translation information included in the received ATS completion response in the ATC 441 (step S305).

[0155] The virtual address translation control unit 423 uses this address translation information to convert GPA to HPA (step S306). The processing from steps S302 to S306 is called ATS processing.

[0156] The virtual address translation control unit 423 executes the processes in steps S307 to S308. The processes in steps S307 to S308 are the same as the processes in steps S204 to S205 described in Figure 8. Then, the FE proceeds to the data transfer process.

[0157] In the data transfer process, the FE issues a fetch request for the PRP list using the GPA contained in the PRP entry field of the acquired read command (step S309). The FE passes the issued fetch request to the virtual address translation control unit 423.

[0158] Then, if a cache miss occurs in ATC441, the virtual address translation control unit 423 executes ATS processing (or ATS+Page Request Interface (PRI) processing, described later) (step S310). The ATS processing executed in step S310 is the same as the ATS processing described in steps S302 to S306. The ATS+PRI processing executed in step S310 is the processing that is executed when the ATS translation processing fails in the ATS processing.

[0159] When the HPA corresponding to the storage location where the PRP list is stored is obtained by ATS processing (or ATS+PRI processing), the controller 4 executes the processes in steps S311 to S313. The processes in steps S311 to S313 are the same as the processes in steps S209 to S211 described in Figure 8.

[0160] If a cache miss occurs in ATC441 during the ATC search process, which searches for address translation information corresponding to the GPA selected from the PRP list, the virtual address translation control unit 423 executes ATS processing (or ATS+PRI processing) (step S314).

[0161] DMAC43 uses the HPA obtained in the ATS processing (or ATS+PRI processing) of step S314 to execute the processing in step S315. The processing in step S315 is the same as the processing in step S214 described in Figure 8. Once the transfer of all read data is complete, the FE moves on to the completion response transfer processing.

[0162] In the completion response transfer process, the FE issues a request to transfer the completion response to memory 22 using the GPA corresponding to the next free CQ slot in the completion queue (CQ) (step S316).

[0163] If a cache miss occurs in ATC441 during the ATC lookup process, which searches for address translation information corresponding to the GPA included in this transfer request, the virtual address translation control unit 423 executes ATS processing (or ATS+PRI processing) (step S317).

[0164] DMAC43 uses the HPA obtained in the ATS processing (or ATS+PRI processing) of step S317 to execute the processing in step S318. The processing in step S318 is the same as the processing in step S218 described in Figure 8. Then, FE proceeds to the interrupt transmission processing.

[0165] In the interrupt transmission process, the FE issues a request to send an interrupt message to memory 22 using the GPA corresponding to the memory location to which the interrupt message should be sent (step S319).

[0166] If a cache miss occurs in ATC441 during the ATC lookup process, which searches for address translation information corresponding to the GPA included in this transmission request, the virtual address translation control unit 423 executes ATS processing (or ATS+PRI processing) (step S320).

[0167] DMAC43 uses the HPA obtained in the ATS processing (or ATS+PRI processing) of step S320 to execute the processing in step S321. The processing in step S321 is the same as the processing in step S222 described in Figure 8.

[0168] Next, we will explain how to process a read command when the ATS conversion process fails. Figure 10 is a sequence diagram showing a third example of the procedure for processing a read command executed in the memory system according to the embodiment.

[0169] In the command fetch process, the controller 4 executes steps S401 to S402. Steps S401 to S402 are the same as steps S201 to S202 described in Figure 8. If a cache miss occurs in ATC441 in step S402, the virtual address translation control unit 423 executes step S403. Step S403 is the same as step S303 described in Figure 9.

[0170] When host 2 receives an ATS translation request from controller 4, it searches the address translation protection table 215 to obtain address translation information corresponding to the GPA specified by the ATS translation request. Now, let's assume that host 2 is unable to obtain address translation information corresponding to the specified GPA. In this case, host 2 sends an ATS completion response to controller 4 that includes a status indicating the failure of the ATS translation process. Therefore, the virtual address translation control unit 423 receives an ATS completion response from host 2 that includes a status indicating the failure of the ATS translation process (step S404).

[0171] The virtual address translation control unit 423 sends a page request to host 2 requesting that address translation information be prepared (step S405). Upon receiving the page request, host 2 begins the process of preparing the address translation information corresponding to the GPA specified in the page request in the address translation protection table 215. Once the process of preparing the address translation information in the address translation protection table 215 is complete, host 2 sends a page request group response to the virtual address translation control unit 423, which is a response indicating that the preparation of the address translation information is complete.

[0172] The virtual address translation control unit 423 receives the page request group response (step S406).

[0173] Upon receiving a page request group response, the virtual address translation control unit 423 sends another ATS translation request to host 2 specifying the same GPA as the ATS translation request sent in step S403 (step S407). Upon receiving the ATS translation request, host 2 searches the address translation protection table 215 and obtains address translation information corresponding to the specified GPA. Host 2 sends an ATS completion response to the virtual address translation control unit 423 of controller 4, which includes the obtained address translation information and a status indicating the success of the ATS translation process.

[0174] The virtual address translation control unit 423 receives an ATS completion response from host 2 (step S408).

[0175] Since the ATS translation process was successful, the virtual address translation control unit 423 stores the address translation information included in the received ATS completion response in the ATC 441 (step S409).

[0176] The virtual address translation control unit 423 uses this address translation information to convert GPA to HPA (step S410). The processing from steps S402 to S410 is called ATS+PRI processing.

[0177] Thus, in ATS+PRI processing, in addition to ATS processing, the process of sending a page request to host 2 and the process of sending an ATS translation request back to host 2 after the page request group response is received from host 2 are executed.

[0178] After the ATS+PRI process is completed, the controller 4 executes steps S411 to S412. Steps S411 to S412 are the same as steps S307 to S308 described in Figure 9.

[0179] The subsequent steps S413 through S425 are the same as the steps S309 through S321 described in Figure 9. In each of steps S414, S418, S421, and S424, if the ATS conversion process fails, the ATS+PRI process is executed.

[0180] Next, we will explain the process by which the virtual address translation control unit 423 notifies the FE and BE of the status of the address translation process. Figure 11 is a sequence diagram showing the procedure of the address translation process executed in the memory system according to the embodiment. In Figure 11, it is assumed that the ATS+PRI process is executed in the address translation process.

[0181] In any of the command fetching process, data transfer process, completion response transfer process, and interrupt transmission process, the controller 4 performs the following processes:

[0182] The FE of controller 4 issues various requests (command fetch request, PRP list fetch request, data transfer request, completion response transfer request, interrupt message transmission request) using the GPA (step S501).

[0183] The virtual address translation control unit 423 searches the ATC 441 for address translation information corresponding to the GPA included in the various requests received from the FE (step S502). If a cache miss occurs in the ATC 441, the virtual address translation control unit 423 sends an ATS translation request specifying the GPA to the host 2 (step S503).

[0184] After sending the ATS translation request, the virtual address translation control unit 423 notifies at least one of the FE or BE of the controller 4 that a cache miss has occurred in the ATC 441 as a result of the ATC lookup (step S504).

[0185] Then, upon receiving an ATS completion response from host 2 that includes a status indicating failure (step S505), the virtual address translation control unit 423 notifies at least one of FE or BE that the ATS translation process has failed as a result of the ATS translation request (step S506).

[0186] After receiving an ATS completion response from host 2 that includes a status indicating failure, the virtual address translation control unit 423 sends a page request to host 2 (step S507).

[0187] Upon receiving a page request group response from host 2 (step S508), the virtual address translation control unit 423 notifies at least one of the FE or BE of controller 4 that the preparation of address translation information is complete as a result of the page request (step S509).

[0188] Then, the virtual address translation control unit 423 sends the ATS translation request to host 2 again (step S510). Upon receiving the ATS translation request, host 2 obtains the address translation information corresponding to the specified GPA from the address translation protection table 215. Host 2 sends an ATS completion response to the virtual address translation control unit 423, which includes the obtained address translation information and a status indicating success.

[0189] Upon receiving an ATS completion response from host 2 (step S511), the virtual address translation control unit 423 notifies at least one of the FE or BE of controller 4 that the ATS translation process was successful as a result of the ATS translation request (step S512).

[0190] The virtual address translation control unit 423 stores the address translation information contained in the received ATS completion response in the ATC 441 (step S513), and uses this address translation information to convert GPA to HPA (step S514).

[0191] Then, the command fetch unit 421 or DMAC 43 uses the HPA translated by the virtual address translation control unit 423 to send a memory access request (DMA read / write request) to the host 2 (step S515).

[0192] In this way, by using a mechanism that notifies at least one of the FE or BE of the status of the address translation process from the virtual address translation control unit 423, the controller 4 can grasp the status of the address translation process.

[0193] In Figure 11, steps S503 and S504 illustrate the case where the virtual address translation control unit 423 notifies the ATC lookup result after issuing an ATS translation request. However, the virtual address translation control unit 423 may notify the ATC lookup result when issuing or before issuing the ATS translation request. Also, steps S506 and S507 illustrate the case where a page request is sent after notifying the result of the ATS translation request. However, the virtual address translation control unit 423 may issue a page request when notifying or before notifying the result of the ATS translation request. Furthermore, steps S509 and S510 illustrate the case where the virtual address translation control unit 423 sends an ATS translation request again after notifying the result of the page request. However, the virtual address translation control unit 423 may notify the result of the page request when sending or after sending the ATS translation request again.

[0194] Next, we will describe the operation of interrupting command processing corresponding to a read command based on the status of address translation processing in data transfer processing. Figure 12 is a sequence diagram showing an example of the procedure for interrupting command processing to read data from non-volatile memory, which is performed in the memory system according to the embodiment. Figure 12 shows an example where a failure of ATS translation processing in data transfer processing is used as a trigger to interrupt command processing.

[0195] The FE performs the command fetch process described in Figure 8, Figure 9, or Figure 10 to obtain a read command from host 2 (step S601).

[0196] FE requests BE to perform a data read operation to read the data to be read specified by the read command from the NAND memory 5 (step S602).

[0197] The BE initiates a data read operation and executes command processing corresponding to the read command (step S603). In the data read operation, the BE first sends a sense instruction to the NAND memory 5 to perform a sense operation to transfer some of the data to be read from the memory cell array 51 to the page buffer 52. The BE waits until the sense operation in the NAND memory 5 is complete. Once the sense operation in the NAND memory 5 is complete, the BE sends several data out instructions to the NAND memory 5 to perform a data out operation. After all the data stored in the page buffer 52 has been transferred to the controller 4 through several data out operations, the BE sends a sense instruction to the NAND memory 5 to perform a sense operation to transfer some of the subsequent data to be read from the memory cell array 51 to the page buffer 52. In this way, in the data read operation, the BE sends multiple instructions (multiple sense instructions, multiple data out instructions) necessary for reading the data to be read to the NAND memory 5.

[0198] After requesting the BE to perform the data read operation, the FE issues a fetch request for the PRP list using the GPA contained in the PRP entry field of the acquired read command (step S604). The FE passes the issued fetch request to the virtual address translation control unit 423.

[0199] The virtual address translation control unit 423 searches the ATC441 for address translation information corresponding to the GPA included in the fetch request received from the FE (step S605).

[0200] If a cache miss occurs in ATC441, the virtual address translation control unit 423 sends an ATS translation request to host 2 specifying the GPA included in the fetch request (step S606).

[0201] If the virtual address translation control unit 423 receives an ATS completion response from host 2 that includes a status indicating failure (step S607), it notifies the BE that the ATS translation process has failed as a result of the ATS translation request (step S608).

[0202] If the BE is notified that the ATS conversion process has failed, it interrupts the command processing corresponding to the read command by temporarily suspending the ongoing data reading operation (step S609). In step S609, for example, the BE temporarily suspends the process of sending each of the instructions that have not yet been sent to the NAND memory 5 out of the multiple instructions required to read the data to be read specified by the read command.

[0203] At this time, if there are other read commands received from host 2, BE may switch the data reading operation to be executed to the data reading operation corresponding to the other read command (step S610) and execute the data reading operation corresponding to the other read command (step S611). This allows BE to execute the data reading operation corresponding to the other read command with priority over the read command for which the ATS conversion process failed.

[0204] Then, after notifying BE of the result of the ATS translation request in step S608, the virtual address translation control unit 423 sends a page request to host 2 to request that address translation information be prepared (step S612). Upon receiving the page request, host 2 begins the process of preparing the address translation information. Once the process of preparing the address translation information is complete, host 2 sends a page request group response to the virtual address translation control unit 423, which is a response indicating that the preparation of the address translation information is complete.

[0205] Upon receiving a page request group response from host 2 (step S613), the virtual address translation control unit 423 sends another ATS translation request to host 2 specifying the same GPA as the ATS translation request sent in step S606 (step S614). Upon receiving the ATS translation request, host 2 searches the address translation protection table 215 and obtains address translation information corresponding to the specified GPA. Host 2 sends an ATS completion response containing the obtained address translation information and a status indicating success to the virtual address translation control unit 423 of controller 4.

[0206] Upon receiving an ATS completion response from host 2, which includes address translation information and a status indicating success (step S615), the virtual address translation control unit 423 notifies BE that the ATS translation process was successful as a result of the ATS translation request (step S616).

[0207] Upon receiving the notification, the BE resumes command processing by restarting the data reading operation that was paused in step S609 (step S617). In step S617, the BE starts sending to the NAND memory 5 any instructions that have not yet been sent to the NAND memory 5, which are among the multiple instructions necessary to read the data to be read corresponding to the interrupted read command from the NAND memory 5.

[0208] The virtual address translation control unit 423 stores the address translation information included in the ATS completion response received in step S615 in the ATC 441 (step S618).

[0209] The virtual address translation control unit 423 uses this address translation information to convert GPA to HPA (step S619).

[0210] The command fetch unit 421 fetches the PRP list from memory 22 using the HPA translated by the virtual address translation control unit 423 (step S620). In step S620, the command fetch unit 421 sends a DMA read request containing the HPA translated by the virtual address translation control unit 423 to the RC23 of host 2. Based on the HPA included in the DMA read request received from controller 4, RC23 reads the PRP list from memory 22 and sends the read PRP list to controller 4. As a result, FE receives the PRP list from host 2 (step S621).

[0211] In data transfer processing, if the ATS translation process fails, it takes longer to obtain address translation information compared to when the ATS translation process is successful. Therefore, by interrupting command processing in response to the failure of the ATS translation process, the storage area of ​​the internal buffer 62 occupied by read data that cannot be sent to host 2 can be minimized. As a result, the degradation of the I / O processing performance of SSD3 can be mitigated. In addition, by interrupting command processing, the peak value of the data transfer amount between controller 4 and NAND memory 5 can be reduced, so the peak values ​​of power consumption of both NAND memory 5 and controller 4 can also be reduced.

[0212] This section describes the case where BE pauses command processing depending on the result indicated by the ATS completion response received in step S607. However, instead of step S607, a cache miss when searching for ATC441 in step S605 may also be used as a trigger to pause command processing.

[0213] In data transfer processing, if an ATC441 cache miss occurs, it takes longer to obtain address translation information compared to when an ATC441 cache hit occurs. Therefore, by interrupting command processing in response to a cache miss, the storage area of ​​the internal buffer 62 that is occupied by read data that cannot be sent to host 2 can be minimized.

[0214] Furthermore, this section describes the case where BE resumes command processing in response to receiving an ATS completion response in step S615. However, instead of step S615, receiving a page request group response in step S613 may be used as a trigger to resume command processing.

[0215] Furthermore, this section describes a case where the failure of the ATS translation process, which converts the GPA corresponding to the storage location where the PRP list is stored to an HPA, is used as a trigger to interrupt command processing. However, even after the PRP list is obtained, an address translation process is performed to convert each GPA included in the PRP list to an HPA. Command processing may also be interrupted if the ATS translation process fails during this address translation process.

[0216] Thus, command processing may be interrupted if the acquisition of address translation information fails in either the ATS translation process that converts the GPA corresponding to the storage location where the PRP list is stored to an HPA, or the ATS translation process that converts each GPA included in the PRP list to an HPA.

[0217] Furthermore, the PRP entry field included in the read command may not be a PRP list, but rather indicate a GPA corresponding to the storage location to which the read data should be transferred. In this case, controller 4 may perform an address translation process to convert the GPA corresponding to the storage location to which the read data should be transferred to an HPA in parallel with the command processing corresponding to the read command. In this case, if the ATS translation process fails in this address translation process, controller 4 will suspend the command processing. Then, in response to receiving a page request group response from host 2, or in response to receiving an ATS completion response indicating success from host 2, controller 4 will resume the command processing.

[0218] Next, we will describe the operation of controlling the command fetch operation based on the status of the address translation process in the completion response transfer process. Figure 13 is a sequence diagram showing a first example of the procedure for controlling the command fetch operation performed in the memory system according to the embodiment. In Figure 13, it is assumed that the command fetch operation is interrupted in response to a failure in the ATS translation process in the completion response transfer process. This completion response transfer process may be a process that sends a completion response for a completed read command, or a process that sends a completion response for a completed write command.

[0219] First, the FE issues a transfer request for the completion response to the completed I / O command using the GPA corresponding to the next free CQ slot in the completion queue (CQ) where the completion response for the completed I / O command should be stored (step S701). The FE then passes the issued transfer request to the virtual address translation control unit 423.

[0220] The virtual address translation control unit 423 searches the ATC 441 for address translation information corresponding to the GPA included in the forwarding request (step S702).

[0221] If a cache miss occurs in ATC441, the virtual address translation control unit 423 sends an ATS translation request specifying the GPA to host 2 (step S703).

[0222] If the virtual address translation control unit 423 receives an ATS completion response from host 2 that includes a status indicating failure (step S704), it notifies the FE that the ATS translation process has failed as a result of the ATS translation request (step S705).

[0223] When notified that the ATS translation process has failed, the FE suspends fetching I / O commands from all submission queues (SQ) associated with the completion queue (CQ) to which completion responses for completed I / O commands should be stored (step S706). This is because the completion queue (CQ) to which completion responses for I / O commands stored in these submission queues (SQ) should be transferred is the same completion queue (CQ) to which completion responses included in the transfer request issued in step S701 should be transferred. Therefore, the HPA for any slot in this completion queue (CQ) cannot be obtained until the address translation information for the memory page where this completion queue (CQ) resides is prepared in the address translation protection table 215. Consequently, if I / O commands were fetched from each of these submission queues (SQ), resources in the controller 4 could be occupied by a large number of completion responses that cannot be sent to host 2. By implementing the control shown in Figure 13, the resources within the controller 4 that would otherwise be occupied by completion responses that cannot be sent to host 2 can be minimized.

[0224] Furthermore, the FE may continue to fetch I / O commands from submission queues (SQ) associated with completion queues (CQ) other than the completion queue (CQ) to which the completion response for completed I / O commands should be forwarded.

[0225] After notifying BE of the result of the ATS translation request in step S705, the virtual address translation control unit 423 sends a page request to host 2 requesting that address translation information be prepared (step S707). Upon receiving the page request, host 2 begins the process of preparing the address translation information. Once the process of preparing the address translation information is complete, host 2 sends a page request group response to the virtual address translation control unit 423, which is a response indicating that the preparation of the address translation information is complete.

[0226] Upon receiving a page request group response from host 2 (step S708), the virtual address translation control unit 423 sends another ATS translation request to host 2 specifying the same GPA as the ATS translation request sent in step S703 (step S709). Upon receiving the ATS translation request, host 2 searches the address translation protection table 215 and obtains address translation information corresponding to the specified GPA. Host 2 sends an ATS completion response containing the obtained address translation information and a status indicating success to the virtual address translation control unit 423 of controller 4.

[0227] Upon receiving an ATS completion response from host 2, which includes address translation information and a status indicating success (step S710), the virtual address translation control unit 423 notifies FE that the ATS translation process was successful as a result of the ATS translation request (step S711).

[0228] Upon receiving the notification, the FE resumes fetching I / O commands from all submission queues (SQs) associated with the CQ where completion responses for completed I / O commands should be stored (step S712).

[0229] The virtual address translation control unit 423 stores the address translation information included in the ATS completion response received in step S710 in the ATC 441 (step S713).

[0230] The virtual address translation control unit 423 uses this address translation information to convert GPA to HPA (step S714).

[0231] The DMAC43 uses the HPA translated by the virtual address translation control unit 423 to forward the completion response to the completion queue (CQ) in memory 22 (step S715).

[0232] This section describes the case where the FE interrupts the command fetch operation depending on the result indicated by the ATS completion response received in step S704. However, instead of step S704, a cache miss when searching for ATC441 in step S702 may be used as a trigger to interrupt the command fetch operation.

[0233] Furthermore, this section describes the case where the FE resumes command fetching operations in response to receiving an ATS completion response in step S710. However, instead of step S710, receiving a page request group response in step S708 may be used as a trigger to resume command fetching operations.

[0234] Next, a procedure for controlling the command fetch operation based on the status of the address translation process in the interrupt transmission process will be described. Figure 14 is a sequence diagram showing a second example of a procedure for controlling the command fetch operation executed in the memory system according to the embodiment. In Figure 14, it is assumed that the command fetch operation is interrupted in response to a failure in the ATS translation process in the interrupt transmission process. This interrupt transmission process may be a process that sends either an interrupt message to notify host 2 that a completion response for a read command has been stored in the completion queue (CQ), or an interrupt message to notify host 2 that a completion response for a write command has been stored in the completion queue (CQ).

[0235] First, the FE issues a transmission request for the interrupt message using the GPA corresponding to the storage location in memory 22 where the interrupt message corresponding to the completion queue (CQ) in which the completion response to the I / O command is stored should be sent (step S801). The FE passes the issued transmission request to the virtual address translation control unit 423.

[0236] The virtual address translation control unit 423 searches the ATC 441 for address translation information corresponding to the GPA included in the transmission request (step S802).

[0237] If a cache miss occurs in ATC441, the virtual address translation control unit 423 sends an ATS translation request specifying the GPA to host 2 (step S803).

[0238] If the virtual address translation control unit 423 receives an ATS completion response from host 2 that includes a status indicating failure (step S804), it notifies the FE that the ATS translation process has failed as a result of the ATS translation request (step S805).

[0239] When notified that the ATS conversion process has failed, the FE suspends fetching I / O commands from all submission queues (SQ) associated with all completion queues (CQ) corresponding to this interrupt message (step S806). This is because the memory locations in memory 22 to which the interrupt messages for the I / O commands stored in these submission queues (SQ) should be sent are the same as the memory locations in memory 22 to which the interrupt messages included in the transmission request issued in step S801 should be sent. Therefore, if I / O commands were fetched from each of these submission queues (SQ), the resources in the controller 4 could be occupied by a large number of interrupt messages that cannot be sent to the host 2. By executing the control shown in Figure 14, the resources in the controller 4 occupied by interrupt messages that cannot be sent to the host 2 can be minimized.

[0240] Furthermore, the FE may continue to fetch I / O commands from submission queues (SQ) associated with completion queues (CQ) other than the completion queue (CQ) corresponding to the interrupt message to be sent.

[0241] After notifying the FE of the result of the ATS translation request in step S805, the virtual address translation control unit 423 sends a page request to host 2 to request that address translation information be prepared (step S807). Upon receiving the page request, host 2 begins the process of preparing the address translation information. Once the process of preparing the address translation information is complete, host 2 sends a page request group response to the virtual address translation control unit 423, which is a response indicating that the preparation of the address translation information is complete.

[0242] Upon receiving a page request group response from host 2 (step S808), the virtual address translation control unit 423 sends another ATS translation request to host 2 specifying the same GPA as the ATS translation request sent in step S803 (step S809). Upon receiving the ATS translation request, host 2 searches the address translation protection table 215 and obtains address translation information corresponding to the specified GPA. Host 2 sends an ATS completion response containing the obtained address translation information and a status indicating success to the virtual address translation control unit 423 of the controller 4.

[0243] Upon receiving an ATS completion response from host 2, which includes address translation information and a status indicating success (step S810), the virtual address translation control unit 423 notifies FE that the ATS translation process was successful as a result of the ATS translation request (step S811).

[0244] Upon receiving the notification, the FE resumes fetching I / O commands from all submission queues (SQ) associated with all completion queues (CQ) corresponding to this interrupt message (step S812).

[0245] The virtual address translation control unit 423 stores the address translation information included in the ATS completion response received in step S810 into the ATC 441 (step S813).

[0246] The virtual address translation control unit 423 uses this address translation information to convert GPA to HPA (step S814).

[0247] The DMAC43 uses the HPA translated by the virtual address translation control unit 423 to transfer the interrupt message to the memory 22 (step S815).

[0248] This section describes the case where the FE interrupts the command fetch operation depending on the result indicated by the ATS completion response received in step S804. However, instead of step S804, a cache miss that occurred when searching for ATC441 in step S802 may be used as a trigger to interrupt the command fetch operation.

[0249] Furthermore, this section describes the case where the FE resumes command fetching operations in response to receiving an ATS completion response in step S810. However, instead of step S810, receiving a page request group response in step S808 may be used as a trigger to resume command fetching operations.

[0250] Next, we will describe the procedure for controlling the command fetch operation in response to the receipt of an invalidation command. Figure 15 is a sequence diagram showing the procedure for the invalidation process performed in the memory system according to the embodiment.

[0251] First, if the address translation information in the address translation protection table 215 is changed, host 2 sends an ATS deactivation request to controller 4 to invalidate the old address translation information in ATC441. This ATS deactivation request specifies the GPA corresponding to the address translation information to be invalidated.

[0252] When the virtual address translation control unit 423 receives an ATS deactivation request from host 2 (step S901), it identifies the entry in ATC441 corresponding to the GPA specified by the received deactivation request and deactivates the address translation information stored in this entry (step S902).

[0253] The virtual address translation control unit 423 sends a completion response to the received ATS deactivation request to host 2 (step S903).

[0254] The virtual address translation control unit 423 notifies the FE of the GPA corresponding to the address translation information that was invalidated in step S902 (step S1204).

[0255] The FE determines whether the notified GPA is a GPA corresponding to a completion queue (CQ). If the notified GPA is a GPA corresponding to any completion queue (CQ), the FE suspends fetching I / O commands from all submission queues (SQ) associated with this completion queue (CQ) until new address translation information for converting the GPA corresponding to the completion queue (CQ) to an HPA is obtained from host 2 (step S905).

[0256] In this case as well, it is possible to prevent the resources within the controller 4 from being occupied by a large number of completion responses that cannot be sent to host 2.

[0257] As described above, according to this embodiment, when the controller 4 receives a read command from host 2 that specifies a virtual address in the virtual address space of host 2, it starts command processing to read the data to be read specified by the read command from the NAND memory 5. The controller 4 also performs address translation processing to convert the virtual address GPA specified by the read command to HPA, which is the physical address for accessing the memory 22 of host 2. If the address translation processing fails, the controller 4 suspends the command processing to read the data to be read from the NAND memory 5 until the address translation information necessary for the address translation processing becomes available. Once the address translation information becomes available, the controller 4 resumes command processing. By suspending command processing in this way, it is possible to prevent the internal buffer 62 from being occupied for a long period of time by read data that cannot be sent to host 2. Furthermore, by suspending command processing, it is possible to prevent read data that cannot be sent to host 2 from being transferred from the NAND memory 5 to the controller 4. As a result, the peak value of the amount of data transferred between the NAND memory 5 and the controller 4 can be reduced, and therefore the peak values ​​of the power consumption of both the NAND memory 5 and the controller 4 can also be reduced.

[0258] Furthermore, when the controller 4 sends information (completion response or interrupt message) to the host 2 to notify the host 2 of the completion of an I / O command, it also performs address translation. In this address translation process, the controller 4 performs a process to translate the GPA, which is a virtual address corresponding to the storage location in the host 2's memory 22 to which the completion response or interrupt message should be forwarded, into the HPA, which is a physical address for accessing the memory 22.

[0259] If this address translation process fails, controller 4 suspends the process of fetching I / O commands from each submission queue associated with the completion queue where the completion response for this I / O command should be stored, until the address translation information necessary for the address translation process becomes available. After the address translation information becomes available, controller 4 resumes the process of fetching I / O commands from each submission queue associated with this completion queue. As a result, it is possible to prevent resources within controller 4 from being occupied by completion responses or interrupt messages that cannot be sent to host 2.

[0260] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0261] 1... Information processing system, 2... Host, 3... SSD, 4... Controller, 5... NAND flash memory, 6... DRAM, 7... Bus, 20... Internal bus, 21... Processor, 22... Memory, 23... Root complex, 40... Bus, 41... Host interface, 42... CPU, 43... DMAC, 44... SRAM, 45... NAND interface, 46... ECC encode / decode unit, 47... DRAM interface, 51... Memory cell array, 52... Page buffer, 61... L2P table, 62... Internal buffer, 211... VMM, 212... MMU, 213... IOMMU, 214... Translation agent, 215... Address translation protection table, 421... Command fetch unit, 422... Command processing unit, 423... Virtual address translation control unit, 441... ATC.

Claims

1. A memory system that can be connected to a host, Non-volatile memory and The system comprises a controller electrically connected to the non-volatile memory and configured to control the non-volatile memory, The aforementioned controller, In response to receiving a first read command from the host requesting the reading of first data and specifying a first virtual address in the host's virtual address space, A command process is executed to read the first data from the non-volatile memory. An address translation process is performed to translate the first virtual address into a first physical address for accessing the host's memory. In the address translation process, an address translation request is sent to the host to obtain first address translation information for translating the first virtual address to the first physical address. In response to receiving a response from the host indicating that the acquisition of the first address translation information failed, the command processing is suspended until the first address translation information is acquired, and then the command processing is resumed after the first address translation information has been acquired. Memory system.

2. The aforementioned controller, If the first virtual address corresponds to a virtual address in the memory to which the first data should be transferred, The storage location indicated by the first physical address is configured to be identified as the storage location in the memory to which the first data is to be transferred. The memory system according to claim 1.

3. The aforementioned controller, If the first virtual address is a virtual address corresponding to a storage location in the memory where a first list containing multiple virtual addresses is stored, In the address translation process, a first address translation process is performed to translate the first virtual address into a first physical address indicating the storage location in the memory where the first list is stored, and a second address translation process is performed to translate each of the multiple virtual addresses included in the first list into a multiple second physical addresses in the memory. Each of the plurality of storage locations in the memory indicated by the plurality of second physical addresses is configured to be identified as the storage location in the memory to which the first data is to be transferred. The memory system according to claim 1.

4. The aforementioned controller, Upon receiving a response from the host indicating that the acquisition of the first address translation information failed, Interrupt the aforementioned command processing, A message requesting the preparation of the first address translation information is sent to the host. Upon receiving a response from the host indicating the completion of the preparation of the first address translation information, the address translation request is sent back to the host. The system is configured to resume command processing upon receiving a response from the host indicating the completion of preparation of the first address translation information, or a response to the retransmitted address translation request that includes the first address translation information. The memory system according to claim 1.

5. The aforementioned controller, If the address translation process is successful, the storage location in the memory to which the first data should be transferred is identified based on the first physical address, and the first data read from the non-volatile memory is transferred to the identified storage location in the memory. If the address translation process fails, the command processing is interrupted until the first address translation information is obtained, and then the command processing is resumed after the first address translation information is obtained. The memory system according to claim 1.

6. It is further equipped with cache memory, The aforementioned controller, In the address translation process, if the first address translation information does not exist in the cache memory, Interrupt the aforementioned command processing, The address translation request is sent to the host, The system is configured to resume command processing upon receiving a response from the host to the address translation request, which includes the first address translation information. The memory system according to claim 1.

7. The aforementioned controller, The command processing is interrupted by stopping the process of sending each of the instructions that have not yet been sent to the non-volatile memory, out of a plurality of instructions that are necessary to be sent to the non-volatile memory in order to read the first data, to the non-volatile memory. The memory system according to claim 1.

8. A memory system that can be connected to a host, Non-volatile memory and The system comprises a controller electrically connected to the non-volatile memory and configured to control the non-volatile memory, The aforementioned controller, I / O commands are fetched from each of the multiple submission queues stored in the host's memory. In response to obtaining the first I / O command, Execute a command process to write data to the non-volatile memory or to read data from the non-volatile memory. An address translation process is performed to translate a first virtual address in the host's virtual address space, which corresponds to the storage location in the host's memory to which the first information for notifying the host of the completion of the first I / O command should be transferred, into a first physical address for accessing the memory. In the address translation process, an address translation request is sent to the host to obtain first address translation information for translating the first virtual address to the first physical address. In response to receiving a response from the host indicating that the acquisition of the first address translation information failed, the system is configured to suspend the first process of fetching an I / O command from each of the one or more first submission queues associated with the first completion queue in the memory where the completion response of the first I / O command should be stored, until the first address translation information is acquired, and then resume the first process after the first address translation information has been acquired. Memory system.

9. The aforementioned controller, Upon receiving a response from the host indicating that the acquisition of the first address translation information failed, Interrupt the first process described above, A message requesting the preparation of the first address translation information is sent to the host. Upon receiving a response from the host indicating the completion of the preparation of the first address translation information, the address translation request is sent back to the host. The system is configured to resume the first processing upon receiving from the host a response indicating the completion of the preparation of the first address translation information, or a response to the retransmitted address translation request that includes the first address translation information. The memory system according to claim 8.

10. The aforementioned controller, If the address translation process is successful, the first information is transferred to the memory using the first physical address. The system is configured to interrupt the first process if the address translation process fails, and to resume the first process after the address translation process is successful. The memory system according to claim 8.

11. It is further equipped with cache memory, The aforementioned controller, In the address translation process, if the first address translation information does not exist in the cache memory, Interrupt the first process described above, The address translation request is sent to the host, The system is configured to resume the first processing upon receiving a response from the host to the address translation request, which includes the first address translation information. The memory system according to claim 8.

12. The aforementioned controller, In response to receiving an invalidation request from the host specifying the first address translation information stored in the cache memory, The first address translation information of the cache memory is invalidated, The first process is configured to be suspended until new address translation information corresponding to the first virtual address is obtained from the host. The memory system according to claim 11.

13. The first piece of information is the completion response of the first I / O command, The first virtual address is a virtual address corresponding to a storage location in the memory where the first completion queue resides. The memory system according to claim 8.

14. The first piece of information is an interrupt message to notify the host that a completion response has been stored in the first completion queue. The first virtual address is a virtual address corresponding to the storage location in the memory to which the interrupt message should be transferred. The memory system according to claim 8.

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