Gate drive circuit

Abstract

A gate drive circuit (10X) is configured to be able to drive a transistor to be driven (QH) having a gate and a first end. The gate drive circuit (10X) comprises: a driving transistor (MOS1) having an application end to which a negative voltage (VEE1) is applied, and a control end for receiving a control signal (MC1), the driving transistor (MOS1) being connected between the gate of the transistor to be driven and the application end; and a bias switching unit (101B) for outputting, at a time delayed from when the logic level of the control signal is switched, a ground potential (GND1) or the negative voltage selectively depending on the logic level of the control signal, to the first end of the transistor to be driven.

Description

Technical Field

[0006] , , , ,

[0001] The present disclosure relates to a gate drive circuit.

Background Art

[0002] Conventionally, in a gate drive circuit that drives the gate of a transistor to be driven, there is known one having a mirror clamp function (for example, Patent Document 1). In the mirror clamp function, a mirror clamp transistor connected to the gate of the transistor to be driven is provided. When the transistor to be driven is in the off state, by turning on the mirror clamp transistor, it becomes possible to extract charge from the gate of the transistor to be driven through the mirror clamp transistor. Thereby, it is possible to suppress the occurrence of a phenomenon (false turn-on) in which the gate voltage of the transistor to be driven rises and the transistor to be driven is accidentally turned on.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in a gate drive circuit, it is desired to suppress the loss when the transistor to be driven is turned off.

[0005] An object of the present disclosure is to provide a gate drive circuit that can suppress false turn-on of a transistor to be driven and suppress the loss when the transistor to be driven is turned off.

Means for Solving the Problems

[0006] For example, the gate drive circuit according to the present disclosure is a gate drive circuit configured to drive a drive target transistor having a gate and a first terminal, and includes a drive transistor having an application terminal to which a negative voltage is applied and a control terminal to which a control signal is received, and connected between the gate and the application terminal of the drive target transistor, and a bias switching unit that selectively outputs ground potential and the negative voltage to the first terminal of the drive target transistor at a timing delayed from the timing at which the logic level of the control signal switches, according to the logic level of the control signal. [Effects of the Invention]

[0007] According to this disclosure, it is possible to suppress false on-on of the driven transistor while reducing losses during the turn-off of the driven transistor. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of a gate drive circuit. [Figure 2] Figure 2 is a timing chart showing an example of the gate-source voltage waveform produced by the gate drive circuit shown in Figure 1. [Figure 3] Figure 3 shows another example of a gate drive circuit. [Figure 4] Figure 4 is a timing chart showing an example of the gate-source voltage waveform produced by the gate drive circuit shown in Figure 3. [Figure 5] Figure 5 shows the configuration of a gate drive circuit according to a comparative example. [Figure 6] Figure 6 shows a part of the internal configuration of a high-side gate driver. [Figure 7] Figure 7 shows the configuration of a gate drive circuit according to the first embodiment of the present invention. [Figure 8] Figure 8 is a timing chart showing an example of the operation of a gate drive circuit according to the first embodiment of the present invention. [Figure 9] Figure 9 shows the configuration of the bias switching unit according to the first modified example. [Figure 10] Figure 10 shows the configuration of the bias switching unit according to the second modified example. [Figure 11] Figure 11 shows the configuration of a gate drive circuit according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0009] Exemplary embodiments of the present invention will be described below with reference to the drawings.

[0010] <1. Regarding the challenges> Figure 1 shows an example of a gate drive circuit. The gate drive circuit GD1 shown in Figure 1 drives the gates of the high-side transistor QH and the low-side transistor QL, which are the transistors to be driven.

[0011] The high-side transistor QH and the low-side transistor QL are composed of NMOS transistors. The drain of the high-side transistor QH is connected to the terminal to which the power supply voltage Vin is applied. The source of the high-side transistor QH is connected to the drain of the low-side transistor QL at node Nsw. The source of the low-side transistor QL is connected to ground. The high-side transistor QH and the low-side transistor QL are composed of MOSFETs (metal-oxide-semiconductor field-effect transistors) using SiC, GaN, or Si as semiconductor materials, for example. Alternatively, the high-side transistor QH and the low-side transistor QL may be composed of IGBTs (Insulated Gate Bipolar Transistors). If the high-side transistor QH and the low-side transistor QL are IGBTs, the collector of the high-side transistor QL is connected to the terminal to which the power supply voltage Vin is applied, and the emitter of the low-side transistor QL is connected to ground.

[0012] The gate drive circuit GD1 includes a high-side driver DrH and a low-side driver DrL.

[0013] The high-side driver DrH drives the gate of the high-side transistor QH. The high-side driver DrH includes a high-side PMOS transistor PM and a low-side NMOS transistor NM. A node Ng where the drain of the PMOS transistor PM and the drain of the NMOS transistor NM are connected is connected to the gate of the high-side transistor QH. The source of the PMOS transistor PM is connected to the power supply voltage application terminal. The source of the NMOS transistor NM is connected to the source of the high-side transistor QH.

[0014] The low-side driver DrL drives the gate of the low-side transistor QL. Since the internal configuration of the low-side driver DrL is the same as that of the above-described high-side driver DrH, illustration in FIG. 1 is omitted.

[0015] By complementarily switching the high-side transistor QH and the low-side transistor QL by the high-side driver DrH and the low-side driver DrL, a switching voltage Vsw is generated at the node Nsw. Note that the term "complementary" includes a case where a dead time during which both the high-side transistor QH and the low-side transistor QL are in an off state is provided.

[0016] FIG. 2 is a timing chart showing waveform examples of the gate-source voltage Vgsh of the high-side transistor QH and the gate-source voltage Vgsl of the low-side transistor QL in FIG. 1. When the PMOS transistor PM in the high-side driver DrH is in an on state and the NMOS transistor NM is in an off state, Vgsh is at a high level. As shown in FIG. 2, the period during which Vgsh is at a high level is the on period Ton during which the high-side transistor QH is in an on state. During the on period Ton, Vgsl of the low-side transistor QL is 0 V, and the low-side transistor QL is in an off state.

[0017] Thereafter, when the PMOS transistor PM is switched to the off state and the NMOS transistor NM is switched to the on state, the turn-off period toff shown in FIG. 2 starts, Vgsh starts to fall toward 0V, and the high-side transistor QH becomes the off state. Then, the dead time Td during which both the high-side transistor QH and the low-side transistor QL are in the off state starts.

[0018] When the dead time Td ends, Vgsl rises from 0V by the low-side driver DrL, and the low-side transistor QL is turned on. At this time, as shown in FIG. 1, a current i flows through the parasitic capacitance Cgd between the gate and drain of the high-side transistor QH and the parasitic inductance Lpar of the line connecting the source of the NMOS transistor NM and the source of the high-side transistor QH. As a result, Vgsh is lifted to the positive side. When Vgsh is lifted and exceeds the threshold voltage Vth, an accidental turn-on occurs in which the high-side transistor QH is accidentally turned on. At this time, as shown in FIG. 1, a through current I flows through the high-side transistor QH and the low-side transistor QL.

[0019] Note that even when the high-side transistor QH is turned on after the dead time, there is a possibility that the Vgsl of the low-side transistor QL will rise and an accidental turn-on of the low-side transistor QL will occur. That is, when one of the drive target transistors is turned on, there is a possibility that the Vgs of the other drive target transistor will rise and an accidental turn-on will occur.

[0020] Figure 3 shows another example of a gate drive circuit. The gate drive circuit GD2 shown in Figure 3 differs from the gate drive circuit GD1 described above in that a negative voltage Vn1 is applied to the source of the NMOS transistor NM in the high-side driver DrH, with the source of the high-side transistor QH as the reference. Also, a negative voltage Vn2 is applied to the source of the NMOS transistor in the low-side driver DrL, with the source of the low-side transistor QL (GND) as the reference. In other words, a negative bias is applied to each driver in the gate drive circuit GD2.

[0021] Figure 4 is a timing chart showing example waveforms of the gate-source voltages Vgsh and Vgsl of the high-side transistor QH and low-side transistor QL, driven by such a gate drive circuit GD2. In Figure 4, the dashed lines show the waveforms in a configuration without negative bias.

[0022] As shown in Figure 4, when the high-side transistor QH is in the off state, Vgsh becomes a negative voltage Vn1. Therefore, even if Vgsh rises when the low-side transistor QL is turned on, it is possible to suppress Vgsh from exceeding the threshold voltage Vth. Thus, the occurrence of false on-states of the high-side transistor QH can be suppressed. Similarly, when the low-side transistor QL is in the off state, Vgsl becomes a negative voltage Vn2. Therefore, even if Vgsl rises when the high-side transistor QH is turned on, it is possible to suppress Vgsl from exceeding the threshold voltage Vth. Thus, the occurrence of false on-states of the low-side transistor QL can be suppressed.

[0023] However, as shown in Figure 4, for example, when the low-side transistor QL is turned off, Vgsl falls to a negative voltage Vn2. Therefore, the fall time Tf2 is longer than the fall time Tf1 when Vgsl falls to 0V, as shown by the dashed line. This presents the problem of increased losses during turn-off. The same applies to the turn-off of the high-side transistor QH.

[0024] Furthermore, as shown in Figure 4, for example, when the low-side transistor QL is turned off while the high-side transistor QH is off, there is a risk that Vgsh may be pulled down to the negative side due to the action of the parasitic inductance Lpar (same as in Figure 1). In this case, the pull-down occurs from the negative bias Vn1, and there is a risk that Vgsh will fall below the Vgs rating Vgst. Similarly, there is also a risk that Vgsl may be pulled down when the high-side transistor QH is turned off.

[0025] <2. Comparative Examples> Here, we will describe comparative examples for comparison with embodiments of the present invention. Figure 5 is a diagram showing the configuration of the gate drive circuit 10 according to the comparative example. The gate drive circuit 10 drives the gates of the high-side transistor QH and the low-side transistor QL, which are the transistors to be driven.

[0026] The high-side transistor QH and the low-side transistor QL are both composed of NMOS transistors. The drain of the high-side transistor QH is connected to the positive terminal of battery E. The source of the high-side transistor QH is connected to the drain of the low-side transistor QL at node Nsw. The source of the low-side transistor QL is connected to the negative terminal of the battery. Battery E is, for example, a lithium battery.

[0027] The source of the high-side transistor QH is connected to the applied terminal of the first ground GND1. The source of the low-side transistor QL is connected to the applied terminal of the second ground GND2.

[0028] The gate drive circuit 10 includes a high-side drive unit 101 and a low-side drive unit 102. The high-side drive unit 101 drives the gate of the high-side transistor QH. The low-side drive unit 102 drives the gate of the low-side transistor QL.

[0029] The high-side drive unit 101 includes a high-side gate driver 1, an ON diode Don 1, an ON resistor Ron 1, an OFF diode Doff 1, an OFF resistor Roff 1, a Miller clamp MOS transistor MOS 1, and a gate protection circuit 101A.

[0030] The high-side gate driver 1 is a semiconductor device (IC package) that packages an IC with its internal components integrated onto, for example, a single chip. The high-side gate driver 1 has terminals T11 to T18 as external terminals for establishing an electrical connection with the outside. As shown in Figure 5, the high-side gate driver 1 is insulated between the primary and secondary sides, with terminals T17 and T18 on the primary side and terminals T11 to T16 on the secondary side.

[0031] The terminal to which the power supply voltage VDD is applied is connected to terminal T17. The terminal to which the ground GND is applied is connected to terminal T18. The terminal to which the power supply voltage VCC1, referenced to the first ground GND1, is applied is connected to terminal T11. The terminal to which the first ground GND1 is applied is connected to terminal T15. The terminal to which the negative voltage VEE1, referenced to the first ground GND1, is applied is connected to terminal T16.

[0032] Terminal T12 is connected to the anode of the ON diode Don1. The cathode of the ON diode Don1 is connected to one end of the ON resistor Ron1. The other end of the ON resistor Ron1 is connected to the gate of the high-side transistor QH.

[0033] Terminal T12 is connected to the cathode of the off diode Doff1. The anode of the off diode Doff1 is connected to one end of the off resistor Roff1. The other end of the off resistor Roff1 is connected to the gate of the high-side transistor QH.

[0034] The Miller clamp MOS transistor MOS1 is composed of NMOS transistors. The drain of the Miller clamp MOS transistor MOS1 is connected to the gate of the high-side transistor QH. The source of the Miller clamp MOS transistor MOS1 is connected to the terminal to which the negative voltage VEE1 is applied. The Miller clamp control signal MC1, output from terminal T14, is applied to the gate of the Miller clamp MOS transistor MOS1.

[0035] Additionally, terminal T13 is connected to the gate of the high-side transistor QH and is a terminal for monitoring the gate potential GT1 of the high-side transistor QH.

[0036] Here, Figure 6 shows a part of the internal configuration of the high-side gate driver 1. The internal configuration shown in Figure 6 is the secondary side configuration. As shown in Figure 6, the high-side gate driver 1 has a logic unit 1A, a PMOS transistor PM1, and an NMOS transistor NM1. The source of the PMOS transistor PM1 is connected to the application terminal of the power supply voltage VCC1. The drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM1 at node N1. The source of the NMOS transistor NM1 is connected to the application terminal of the negative voltage VEE1. Node N1 is connected to terminal T12.

[0037] The high-side gate driver 1 receives a control input signal (not shown) from an external source on the primary side. This control input signal is transmitted to the secondary side while being isolated within the high-side gate driver 1. The logic unit 1A drives the gates of the PMOS transistor PM1 and the NMOS transistor NM1 in accordance with the transmitted control input signal.

[0038] For example, when a control input signal indicating "on" is input, the logic unit 1A turns on the PMOS transistor PM1 and off the NMOS transistor NM1, and outputs a high-level gate output signal OUT1 from terminal T12. In this case, charge is supplied to the gate of the high-side transistor QH via the ON diode Don1 and the ON resistor Ron1. As a result, the gate-source voltage Vgsh of the high-side transistor QH rises, and the high-side transistor QH is turned on.

[0039] On the other hand, if a control input signal indicating "off" is input, the logic unit 1A turns off the PMOS transistor PM1 and turns on the NMOS transistor NM1, and outputs a low-level gate output signal OUT1 from terminal T12. In this case, charge is drawn from the gate of the high-side transistor QH via the off resistor Roff1 and the off diode Doff1. As a result, the gate-source voltage Vgsh of the high-side transistor QH falls, and the high-side transistor QH is turned off.

[0040] As described above, when the high-side transistor QH is turned off, and it is detected that Vgsh has fallen to a predetermined voltage based on the gate potential GT1 applied to terminal T13, the logic unit 1A switches the Miller clamp control signal MC1 output from terminal T14 from a low level to a high level. As a result, the Miller clamp MOS transistor NM1 is turned on, and a negative voltage VEE1 is applied to the gate of the high-side transistor QH. Therefore, even if Vgsh rises when the high-side transistor QH is in the off state, it is suppressed that Vgsh exceeds the threshold voltage Vth. This suppresses the occurrence of false on-states of the high-side transistor QH.

[0041] Furthermore, when the above-mentioned control input signal indicating "on" is input to the high-side gate driver 1, the logic unit 1A switches the Miller clamp control signal MC1 from a high level to a low level. As a result, the Miller clamp MOS transistor NM1 is turned off.

[0042] Furthermore, the gate protection circuit 101A includes a high-side diode DH1 and a low-side diode DL1. The cathode of the high-side diode DH1 is connected to the terminal to which the power supply voltage VCC1 is applied. The anode of the high-side diode DH1 is connected to the gate of the high-side transistor QH. The anode of the low-side diode DL1 is connected to the terminal to which the negative voltage VEE1 is applied. The cathode of the low-side diode DL1 is connected to the gate of the high-side transistor QH.

[0043] This gate protection circuit 101A clamps the Vgsh of the high-side transistor QH to VCC1 even if it attempts to exceed the power supply voltage VCC1. Similarly, it clamps Vgsh to VEE1 even if it attempts to fall below the negative voltage VEE1. Therefore, it prevents Vgsh from dropping below its rated value. However, since the phenomenon of Vgsh falling below the rated value is momentary and has little impact on the high-side transistor QH, the function of clamping Vgsh to VEE1 is not essential.

[0044] On the other hand, the low-side drive unit 102 includes a low-side gate driver 2, an ON diode Don 2, an ON resistor Ron 2, an OFF diode Doff 2, an OFF resistor Roff 2, a Miller clamp MOS transistor MOS 2, and a gate protection circuit 102A.

[0045] The configuration of the low-side drive unit 102 is the same as that of the high-side drive unit 101 described above, so it will be explained in a simplified manner here.

[0046] Specifically, the low-side gate driver 2 has the same configuration as the high-side gate driver 1 and has terminals T21 to T28 corresponding to terminals T11 to T18. In addition, the power supply voltage VDD, ground GND, power supply voltage VCC2, gate output signal OUT2, mirror clamp control signal MC2, second ground GND2, and negative voltage VEE2 are applied to each external terminal of the low-side gate driver 2, corresponding to the power supply voltage VDD, ground GND, power supply voltage VCC1, gate output signal OUT1, Miller clamp control signal MC2, first ground GND1, and negative voltage VEE1. Note that the power supply voltage VCC2 and negative voltage VEE2 are voltages referenced to the second ground GND2.

[0047] The connection configuration of the ON diode Don2, ON resistor Ron2, OFF diode Doff2, OFF resistor Roff2, and terminals T22 and T24 of the Miller clamp MOS transistor MOS2, the gate of the low-side transistor QL, and the terminal to which the negative voltage VEE2 is applied is the same as the connection configuration of the ON diode Don1, ON resistor Ron1, OFF diode Doff1, OFF resistor Roff1, and terminals T12 and T14 of the Miller clamp MOS transistor MOS1, the gate of the high-side transistor QH, and the terminal to which the negative voltage VEE1 is applied in the high-side drive unit 101. In addition, the gate of the low-side transistor QL is connected to terminal T23. Terminal T23 is a terminal for monitoring the gate potential GT2 of the low-side transistor QL and corresponds to terminal T13.

[0048] Furthermore, the gate protection circuit 102A is configured by replacing the high-side diode DH1, low-side diode DL1, power supply voltage VCC1, and negative voltage VEE1 of the gate protection circuit 101A with the high-side diode DH2, low-side diode DL2, power supply voltage VCC2, and negative voltage VEE2, respectively. The anode of the high-side diode DH2 and the cathode of the low-side diode DL2 are commonly connected to the gate of the low-side transistor QL.

[0049] The on / off driving of the low-side transistor QL by the low-side gate driver 2 and the on / off control of the Miller clamp MOS transistor MOS2 are the same as the on / off driving of the high-side transistor QH by the high-side gate driver 1 and the on / off control of the Miller clamp MOS transistor MOS1, so a detailed explanation is omitted here. By applying the negative voltage VEE2 from the Miller clamp MOS transistor MOS2 to the gate of the low-side transistor QL, the occurrence of false on-by of the low-side transistor QL due to a rise in the gate-source voltage Vgsl of the low-side transistor QL can be suppressed.

[0050] Furthermore, the gate protection circuit 102A can clamp Vgsl to VCC2 or VEE2. However, as with the gate protection circuit 101A mentioned earlier, the configuration to clamp to VEE2 is not mandatory.

[0051] However, in such a gate drive circuit 10, when the high-side transistor QH is turned off, the Miller clamp MOS transistor MOS1 is turned on, causing Vgsh to fall to a negative voltage VEE1. As a result, as mentioned earlier, the fall time Tf of Vgsh becomes longer, and the loss during turn-off increases. The same applies to the loss during turn-off of the low-side transistor QL.

[0052] <3. First Embodiment> Figure 7 shows the configuration of the gate drive circuit 10X according to the first embodiment of the present invention. The difference between the gate drive circuit 10X shown in Figure 7 and the comparative example (Figure 5) described above is that it has a bias switching section 101B in the high-side drive section 101 and a bias switching section 102B in the low-side drive section 102.

[0053] The bias switching unit 101B includes an NMOS transistor NM11, an NMOS transistor NM12, resistors R11 and R12, and an inverter IV12. One end of resistor R11 is connected to terminal T14. The other end of resistor R11 is connected to the gate of NMOS transistor NM11. The drain of NMOS transistor NM11 is connected to the application terminal of the first ground GND1. The input terminal of inverter IV12 is connected to terminal T14. The output terminal of inverter IV12 is connected to one end of resistor R12. The other end of resistor R12 is connected to the gate of NMOS transistor NM12. The source of NMOS transistor NM12 is connected to the application terminal of negative voltage VEE1. The node to which the source of NMOS transistor NM11 and the drain of NMOS transistor NM12 are connected is connected to the source of high-side transistor QH.

[0054] The bias switching unit 102B includes an NMOS transistor NM21, an NMOS transistor NM22, resistors R21 and R22, and an inverter IV22. One end of resistor R21 is connected to terminal T24. The other end of resistor R21 is connected to the gate of NMOS transistor NM21. The drain of NMOS transistor NM21 is connected to the application terminal of the second ground GND2. The input terminal of inverter IV22 is connected to terminal T24. The output terminal of inverter IV22 is connected to one end of resistor R22. The other end of resistor R22 is connected to the gate of NMOS transistor NM22. The source of NMOS transistor NM22 is connected to the application terminal of negative voltage VEE2. The node to which the source of NMOS transistor NM21 and the drain of NMOS transistor NM22 are connected is connected to the source of low-side transistor QL.

[0055] Figure 8 is a timing chart relating to the gate driving operation of the transistor to be driven by the gate driving circuit 10X shown in Figure 7. In Figure 8, from top to bottom, examples of waveforms are shown for the gate potential GT1 of the high-side transistor QH, the Miller clamp control signal MC1, the source potential SS1 of the high-side transistor QH, the gate-source voltage Vgsh of the high-side transistor QH, the gate potential GT2 of the low-side transistor QL, the Miller clamp control signal MC2, the source potential SS2 of the low-side transistor QL, and the gate-source voltage Vgsl of the low-side transistor QL.

[0056] At timing t1 shown in Figure 8, when an ON control input signal is input to the high-side gate driver 1, the Miller clamp control signal MC1 is switched to a low level, and the Miller clamp MOS transistor MOS1 is turned OFF. At this time, the gate output signal OUT1 is set to a high level, and both the gate potential GT1 and the gate-source voltage Vgsh begin to rise from a negative voltage VEE1. Therefore, the turn-on of the high-side transistor QH begins. In the bias switching section 101B, the ON state of the NMOS transistor NM11 and the OFF state of the NMOS transistor NM12 are maintained due to the delay caused by resistors R11 and R12. Therefore, the source potential SS1 is maintained at the first ground GND1.

[0057] Subsequently, at timing t3, with a delay of dly1 from timing t1, NMOS transistor NM11 is switched to the off state and NMOS transistor NM12 is switched to the on state, and the source potential SS1 is switched to a negative voltage VEE1. As a result, the gate-source voltage Vgsh rises sharply.

[0058] Subsequently, at timing t4, when an off control input signal is input to the high-side gate driver 1, the gate output signal OUT1 is set to a low level, and both the gate potential GT1 and the gate-source voltage Vgsh begin to fall.

[0059] Subsequently, when it is detected via terminal T13 that the gate potential GT1 has reached a predetermined voltage at timing t5, the high-side gate driver 1 switches the Miller clamp control signal MC1 to a high level. As a result, the Miller clamp MOS transistor MOS1 is turned ON, and the gate potential GT1 falls to a negative voltage VEE1. At this time, the delay caused by resistors R11 and R12 causes the NMOS transistor NM11 to remain OFF and the NMOS transistor NM12 to remain ON. Therefore, the source potential SS1 is maintained at a negative voltage VEE1. Consequently, the gate-source voltage Vgsh falls to 0V (GND1).

[0060] At timing t7, delayed by dly2 from timing t5, NMOS transistor NM11 is switched to the ON state and NMOS transistor NM12 is switched to the OFF state, and the source potential SS1 is switched to the first ground GND1. After timing t5, at timing t6 the gate-source voltage Vgsh reaches 0V and then maintains the first ground GND1 until timing t7. Then, at timing t7 the gate-source voltage Vgsh falls to a negative voltage VEE1.

[0061] Thus, in this embodiment, when the high-side transistor QH is turned off, the gate-source voltage Vgsh falls to the first ground GND1 and then the first ground GND1 is maintained, thus suppressing losses.

[0062] Furthermore, a dead time begins at timing t7 when both the high-side transistor QH and the low-side transistor QL are in the off state, and the dead time ends at timing t8 when both the gate potential GT2 and the gate-source voltage Vgsl of the low-side transistor QL begin to rise. The rising gate-source voltage Vgsl turns on the low-side transistor QL, but at this time, a rise 81 may occur in the gate-source voltage Vgsh of the high-side transistor QH, which is in the off state. However, since the gate-source voltage Vgsh is a negative voltage VEE1, even if a rise 81 occurs, the gate-source voltage Vgsh is prevented from reaching the threshold voltage of the high-side transistor QH. Therefore, false turning on of the high-side transistor QH can be suppressed.

[0063] Furthermore, similar to the high-side transistor QH, when the low-side transistor QL is turned off, as shown in Figure 8, the bias switching unit 102B operates so that the Miller clamp control signal MC2 switches to a high level, and at timing t11, which is delayed by a delay time of dly3 from timing t9, the source potential SS2 is switched from a negative voltage VEE2 to the second ground GND2. As a result, the gate-source voltage Vgsl of the low-side transistor QL falls and reaches the second ground GND2 at timing t10, and is maintained at the second ground GND2 until timing t11. This suppresses losses when the low-side transistor QL is turned off.

[0064] Furthermore, as shown in Figure 8, even if a rise 82 occurs in the gate-source voltage Vgsl when the high-side transistor QH turns on while the low-side transistor QL is off, the gate-source voltage Vgsl is a negative voltage VEE2, thus preventing the gate-source voltage Vgsl from reaching the threshold voltage of the low-side transistor QL. Therefore, false on-by-on of the low-side transistor QL can be suppressed.

[0065] <4. First variation> Figure 9 shows a first modified example of the bias switching unit 101B. A similar modified example can also be applied to the bias switching unit 102B.

[0066] In the configuration shown in Figure 9, a PMOS transistor PM11 is used instead of the NMOS transistor NM11 (Figure 7). More specifically, the source of the PMOS transistor PM11 is connected to the application terminal of the first ground GND1. The drain of the PMOS transistor PM11 is connected to the drain of the NMOS transistor NM12. In addition, an inverter IV11 is inserted between the application terminal of the Miller clamp control signal MC1 (i.e., terminal T14 (Figure 7)) and one end of resistor R11.

[0067] Even with this modified configuration, the source potential SS1 can be switched between the first ground GND1 and the negative voltage VEE1 depending on the logic level of the Miller clamp control signal MC1, similar to the previous embodiment (Figure 7). Specifically, when the Miller clamp control signal MC1 is at a high level, the PMOS transistor PM11 is in the ON state and the NMOS transistor NM12 is in the OFF state, so the source potential SS1 is set to the first ground GND1. On the other hand, when the Miller clamp control signal MC1 is at a low level, the PMOS transistor PM11 is in the OFF state and the NMOS transistor NM12 is in the ON state, so the source potential SS1 is set to the negative voltage VEE1.

[0068] <5. Second variation> Figure 10 shows a second modified example of the bias switching unit 101B. A similar modified example can also be applied to the bias switching unit 102B.

[0069] The modified bias switching unit 101B shown in Figure 10 includes an inverter IV13, a delay circuit 1011, and an NMOS transistor NM13. The application terminal (i.e., terminal T14 (Figure 7)) of the Miller clamp control signal MC1 is connected to the input terminal of the inverter IV13. The output terminal of the inverter IV13 is connected to the input terminal of the delay circuit 1011.

[0070] The delay circuit 1011 is composed of an RC circuit consisting of a resistor R13 and a capacitor C13. One end of resistor R13 is connected to the output terminal of inverter IV13. The other end of resistor R13 is connected to one end of capacitor C13. The other end of capacitor C13 is connected to the application terminal of negative voltage VEE1. The node where the other end of resistor R13 and one end of capacitor C13 are connected (i.e., the output terminal of delay circuit 1011) is connected to the gate of NMOS transistor NM13. The source of NMOS transistor NM13 is connected to the application terminal of negative voltage VEE1. The drain of NMOS transistor NM13 is connected to the source of high-side transistor QH. The source of high-side transistor QH is connected to the application terminal of the first ground GND1.

[0071] Even with this modified configuration, the source potential SS1 can be switched between the first ground GND1 and the negative voltage VEE1 depending on the logic level of the Miller clamp control signal MC1, similar to the previous embodiment (Figure 7). Specifically, when the Miller clamp control signal MC1 is at a high level, the NMOS transistor NM13 is in the off state, so the source potential SS1 is set to the first ground GND1. On the other hand, when the Miller clamp control signal MC1 is at a low level, the NMOS transistor NM13 is in the on state, so the source potential SS1 is set to the negative voltage VEE1.

[0072] Furthermore, the delay circuit 1011 allows the source potential SS1 to be switched at a delayed timing after the logic level of the Miller clamp control signal MC1 has been switched.

[0073] <6. Second Embodiment> Figure 11 shows the configuration of the gate drive circuit 10Y according to the second embodiment of the present invention. In the gate drive circuit 10X (Figure 7) according to the first embodiment described above, a negative voltage VEE1 can be generated inside the high-side gate driver 1 and has a terminal T16. In contrast, the gate drive circuit 10Y according to the second embodiment makes it possible to use a high-side gate driver 1 that does not have a terminal T16.

[0074] The gate drive circuit 10Y has a power supply circuit 1010 located outside the high-side gate driver 1. The power supply circuit 1010 includes a transformer Tr1, an external power supply IC 1010A, and output capacitors Cout1 and Cout2. The transformer Tr1 has a primary winding w1 and secondary windings w21 and w22, and is provided to insulate the primary and secondary sides.

[0075] A DC voltage (not shown) is applied to one end of the primary winding w1. A switching element (not shown) is connected to the other end of the primary winding w1.

[0076] The input terminal of the external power supply IC1010A is connected to one end of the secondary winding w21. The output terminal of the external power supply IC1010A is connected to one end of the output capacitor Cout1. The other end of the output capacitor Cout1 is connected to the ground terminal of the external power supply IC1010A. The other end of the output capacitor Cout1 and the other end of the secondary winding w21 are connected to the application terminal of the first ground GND1.

[0077] The external power supply IC1010A generates a power supply voltage VCC1 at one end of the output capacitor Cout1 based on the voltage generated in the secondary winding w21 by the switching of the primary side switching element.

[0078] One end of the secondary winding w22 is connected to one end of the output capacitor Cout2. The other end of the secondary winding w22 is connected to the other end of the output capacitor Cout2 and the applied terminal of the first ground GND1. Based on the voltage generated in the secondary winding w22 by the switching of the primary-side switching element, a negative voltage VEE1 is generated at one end of the output capacitor Cout2.

[0079] According to this second embodiment, it becomes possible to generate a negative voltage VEE1 outside the high-side gate driver 1, eliminating the need to generate the negative voltage VEE1 inside the high-side gate driver 1.

[0080] Similarly, a power supply circuit that generates a negative voltage VEE2 for the low-side gate driver 2 can be provided outside the low-side gate driver 2. Furthermore, the first and second modifications described above may be applied to the second embodiment.

[0081] <7. Addendum> The gate drive circuit (10X) according to this disclosure is a gate drive circuit configured to drive a drive target transistor (QH) having a gate and a first terminal (source), The application terminal to which a negative voltage (VEE1) is applied, A driving transistor (MOS1) having a control terminal (gate) that receives a control signal (MC1), and connected between the gate and the application terminal of the transistor to be driven, A bias switching unit (101B) that, at a timing delayed from the timing when the logic level of the control signal switches, selectively outputs the ground potential (GND1) and the negative voltage to the first terminal of the driven transistor according to the logic level of the control signal, The configuration includes the following (first configuration, Figure 7).

[0082] Furthermore, in the first configuration described above, the driving transistor may be an NMOS transistor (MOS1) (second configuration, Figure 7).

[0083] Furthermore, in the first or second configuration described above, the bias switching unit (101B) is, A first resistor (R11) having a first end that receives the aforementioned control signal and a second end, A first NMOS transistor (NM11) having a gate connected to the second terminal of the first resistor, a drain receiving the ground potential, and a source, An inverter (IV12) having an input terminal that receives the aforementioned control signal and an output terminal, A second resistor (R12) having a first end and a second end connected to the output terminal of the inverter, A second NMOS transistor (NM12) having a gate connected to the second terminal of the second resistor, a drain connected to the source of the first NMOS transistor, and a source that receives the negative voltage, A configuration having the above is also possible (third configuration, Figure 7).

[0084] Furthermore, in the first or second configuration described above, the bias switching unit (101B) is, A first inverter (IV11) having an input terminal for receiving the aforementioned control signal and an output terminal, A first resistor (R11) having a first end and a second end connected to the output terminal of the first inverter, A PMOS transistor (PM11) having a gate connected to the second terminal of the first resistor, a source that receives the ground potential, and a drain, A second inverter (IV12) having an input terminal that receives the aforementioned control signal and a second terminal, A second resistor (R12) having a first end and a second end connected to the output terminal of the second inverter, An NMOS transistor (NM12) having a gate connected to the second terminal of the second resistor, a drain connected to the drain of the PMOS transistor, and a source that receives the negative voltage, A configuration having the following is also possible (fourth configuration, Figure 9).

[0085] Furthermore, in the first or second configuration described above, the first terminal of the driven transistor receives the ground potential, and the bias switching unit (101B) is An inverter (IV13) having an input terminal that receives the aforementioned control signal and an output terminal, A delay circuit (1011) that delays the output from the inverter, An NMOS transistor (NM13) having a gate that receives the output from the delay circuit, a drain connected to the first end of the driven transistor, and a source that receives the negative voltage, A configuration having the following is also possible (fifth configuration, Figure 10).

[0086] Furthermore, in the fifth configuration described above, the delay circuit (1011) may include an RC circuit having a resistor (R13) and a capacitor (C13) (sixth configuration, Figure 10).

[0087] Furthermore, in any of the above configurations 1 to 6, the driven transistor may be an NMOS transistor (QH, QL) (configuration 7, Figure 7).

[0088] Furthermore, in any of the above configurations 1 to 7, the IC package (1) includes a first external terminal (T12), a second external terminal (T13), and a third external terminal (T14). The IC package may be configured to output a gate output signal (OUT1) to the gate of the driven transistor via the first external terminal, to monitor the gate potential (GT1) of the driven transistor via the second external terminal, and to output a control signal (MC1) to the control terminal of the driving transistor via the third external terminal (eighth configuration, Figure 7).

[0089] Furthermore, in the eighth configuration described above, the IC package (1) has a power supply circuit (1010) located outside it. The aforementioned power supply circuit is A transformer (Tr1) having a primary winding (w1) and a secondary winding (w22), The output capacitor (Cout2) has a first end connected to the first end of the secondary winding, and a second end connectable to the second end of the secondary winding and the ground potential (GND1) application terminal. The output capacitor may be configured to generate the negative voltage (VEE1) at its first terminal (9th configuration, Figure 11).

[0090] Furthermore, in any of the first to ninth configurations described above, a diode (DL1) may be provided that includes a cathode connected to the gate of the transistor to be driven and an anode that receives the negative voltage (Tenth configuration, Figure 7).

[0091] Furthermore, in any of the first to tenth configurations described above, the driven transistor may be one of a high-side transistor (QH) and a low-side transistor (QL) connected in series between the power supply voltage and the reference potential (eleventh configuration, Figure 7).

[0092] <8. Others> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above. [Industrial applicability]

[0093] This disclosure can be used, for example, to drive the gate of a MOS transistor. [Explanation of symbols]

[0094] 1 High-side gate driver 1A Logic section 2 Low-side gate drivers 10 Gate drive circuit 10X, 10Y gate drive circuit 101 High-side drive unit 101A Gate Protection Circuit 101B Bias switching section 102 Low-side drive unit 102A Gate Protection Circuit 102B Bias switching section 1010 Power supply circuit 1010A external power IC 1011 Delay Circuit C13 Capacitor Cgd gate-drain interparasitic capacity Cout1, Cout2 Output Capacitors DH1 High-side diode DH2 High-Side Diode DL1 Low-side diode DL2 Low-Side Diode Doff1 diode for turning off Doff2 diode for turning off Don1 ON diode Don2 ON diode DrH High-Side Driver DRL Lowside Driver E Battery GD1 Gate Drive Circuit GD2 Gate Drive Circuit IV11 Inverter IV12 Inverter IV13 Inverter IV22 Inverter Lpar Parasitic Inductance MOS1 Miller clamp MOS transistor MOS2 Miller clamp MOS transistor NM, NM1 NMOS transistors NM11, NM12, NM13 NMOS transistors NM21, NM22 NMOS transistors PM, PM1, PM11 PMOS transistors QH High-Side Transistor QL Low-Side Transistor R11~R13 Resistors R21,R22 resistance Roff1 is a resistor for turning off the device. Roff2 resistor for turning off R1 is a resistor for turning on. RRON2 ON resistor T11~T18 terminals T21~T28 terminals Tr1 Transformer w1 Primary winding w21, w22 Secondary winding

Claims

1. A gate drive circuit configured to drive a transistor having a gate and a first terminal, The application terminal to which a negative voltage is applied, A driving transistor having a control terminal that receives a control signal, and connected between the gate and the input terminal of the driven transistor, A bias switching unit that, at a second timing delayed from the first timing in which the logic level of the control signal switches, selectively outputs the ground potential and the negative voltage to the first terminal of the driven transistor according to the logic level of the control signal, It has, When the driven transistor is turned off, the logic level of the control signal is switched at the first timing to turn on the driving transistor, and from the first timing to the third timing the gate potential of the driven transistor falls to the negative voltage, and at this time the output of the bias switching unit is maintained at the negative voltage. The output of the bias switching unit is switched from the negative voltage to the ground potential at the second timing, which is delayed by a predetermined delay time from the first timing and is later than the third timing, and the output of the bias switching unit is maintained at the negative voltage between the first timing and the second timing. Gate drive circuit.

2. The gate drive circuit according to claim 1, wherein the drive transistor is an NMOS transistor.

3. The bias switching unit is, A first resistor having a first end that receives the control signal and a second end, A first NMOS transistor having a gate connected to the second end of the first resistor, a drain receiving the ground potential, and a source, An inverter having an input terminal that receives the aforementioned control signal and an output terminal, A second resistor having a first end and a second end connected to the output terminal of the inverter, A second NMOS transistor having a gate connected to the second terminal of the second resistor, a drain connected to the source of the first NMOS transistor, and a source that receives the negative voltage, A gate drive circuit according to claim 1 or claim 2, having the following features.

4. The bias switching unit is, A first inverter having an input terminal for receiving the aforementioned control signal and an output terminal, A first resistor having a first end and a second end connected to the output terminal of the first inverter, A PMOS transistor having a gate connected to the second end of the first resistor, a source that receives the ground potential, and a drain, A second inverter having an input terminal for receiving the aforementioned control signal and an output terminal, A second resistor having a first end and a second end connected to the output terminal of the second inverter, An NMOS transistor having a gate connected to the second end of the second resistor, a drain connected to the drain of the PMOS transistor, and a source that receives the negative voltage, A gate drive circuit according to claim 1 or claim 2, having the following features.

5. The first terminal of the transistor to be driven receives the ground potential, The bias switching unit is, An inverter having an input terminal that receives the aforementioned control signal and an output terminal, A delay circuit that delays the output from the inverter, An NMOS transistor having a gate that receives the output from the delay circuit, a drain connected to the first end of the driven transistor, and a source that receives the negative voltage, A gate drive circuit according to claim 1 or claim 2, having the following features.

6. The gate drive circuit according to claim 5, wherein the delay circuit includes an RC circuit having a resistor and a capacitor.

7. The gate drive circuit according to claim 1, wherein the transistor to be driven is an NMOS transistor.

8. The IC package includes a first external terminal, a second external terminal, and a third external terminal. The gate drive circuit according to claim 1, wherein the IC package is configured to output a gate output signal to the gate of the driven transistor via the first external terminal, to monitor the gate potential of the driven transistor via the second external terminal, and to output the control signal to the control terminal of the drive transistor via the third external terminal.

9. The IC package has a power supply circuit located outside of it. The aforementioned power supply circuit is A transformer having a primary winding and a secondary winding, An output capacitor having a first end connected to the first end of the secondary winding, and a second end connectable to the second end of the secondary winding and the ground potential application terminal, It has, The gate drive circuit according to claim 8, which is capable of generating the negative voltage at the first terminal of the output capacitor.

10. The gate drive circuit according to claim 1, comprising a diode including a cathode connected to the gate of the transistor to be driven and an anode that receives the negative voltage.

11. The gate drive circuit according to claim 1, wherein the transistor to be driven is one of a high-side transistor and a low-side transistor connected in series between the power supply voltage and a reference potential.

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