Output circuit

Abstract

To detect the peak voltage of an output signal over a wide band.SOLUTION: An output circuit 1 includes inductors 3a and 3b, an amplifier circuit 2 that outputs an output signal Vout via the inductors 3a and 3b, output terminals Tout1 and Tout2 for outputting the output signal Vout to the outside, a voltage dividing circuit 4 that includes a capacitor 41 and a capacitor 42 connected in series with each other and that divides the output signal Vout to generate a divided voltage signal Vdiv1, band adjustment elements 5a and 5b that adjust the frequency characteristics of the divided voltage signal Vdiv1 to generate the detection signal Vm1, and a peak detection circuit 6 that detects the peak voltage of the detection signal Vm1 and outputs the peak voltage Vpeak1 according to the detection result.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to an output circuit.

Background Art

[0002] A peak detection circuit for detecting the peak voltage of an output signal is known. For example, Patent Document 1 discloses a configuration in which an output signal is divided by capacitors connected in series, and the peak voltage of the divided signal is detected.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a drive circuit of an optical modulator, high-frequency peaking for amplifying high-frequency components may be performed to compensate for the high-frequency loss of the optical modulator. When high-frequency components are amplified by high-frequency peaking, there is a possibility that the peak voltage composed of signal components in a wide band from low frequency to high frequency cannot be detected.

[0005] In this disclosure, an output circuit capable of detecting the peak voltage of an output signal in a wide band is described.

Means for Solving the Problems

[0006] An output circuit relating to one aspect of this disclosure includes an inductor, an amplification circuit that outputs an output signal via the inductor, an output terminal for outputting the output signal to the outside, a voltage divider circuit that includes a first capacitive element and a second capacitive element connected in series with each other and divides the output signal using the first capacitive element and the second capacitive element to generate a first voltage divider signal, a first band adjustment element having a resistive component and adjusting the frequency characteristics of the first voltage divider signal to generate a first detection signal, and a first peak detection circuit that detects the peak voltage of the first detection signal and outputs a first peak voltage according to the detection result. [Effects of the Invention]

[0007] According to this disclosure, the peak voltage of the output signal can be detected over a wide bandwidth. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows the circuit configuration of an output circuit according to one embodiment. [Figure 2] Figure 2 shows the circuit configuration of an output circuit according to another embodiment. [Figure 3] Figure 3 shows the circuit configuration of an output circuit according to yet another embodiment. [Figure 4] Figure 4 shows the circuit configuration of an output circuit according to yet another embodiment. [Figure 5] Figure 5 shows the circuit configuration of an output circuit according to yet another embodiment. [Figure 6] Figure 6 shows the circuit configuration of an output circuit according to yet another embodiment. [Figure 7] Figure 7 shows the circuit configuration of an output circuit according to yet another embodiment. [Figure 8] Figure 8 shows an example of a voltage divider circuit configuration. [Figure 9] Figure 9 shows the frequency characteristics of each part of the output circuit shown in Figure 4. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the contents of the embodiments of this disclosure will be listed and explained.

[0010] An output circuit relating to one aspect of this disclosure includes an inductor, an amplification circuit that outputs an output signal via the inductor, an output terminal for outputting the output signal to the outside, a voltage divider circuit that includes a first capacitive element and a second capacitive element connected in series with each other and divides the output signal using the first capacitive element and the second capacitive element to generate a first voltage divider signal, a first band adjustment element having a resistive component and adjusting the frequency characteristics of the first voltage divider signal to generate a first detection signal, and a first peak detection circuit that detects the peak voltage of the first detection signal and outputs a first peak voltage according to the detection result.

[0011] In this output circuit, the high-frequency components of the output signal are amplified by the inductor, the first capacitive element, and the second capacitive element. Therefore, the high-frequency components of the first voltage-divided signal obtained by voltage-dividing the output signal are also amplified. A low-pass filter is formed by the first bandwidth adjustment element and the input capacitance of the first peak detection circuit, so the high-frequency components of the first voltage-divided signal are reduced and the first detection signal is generated. Therefore, since the high-frequency components are suppressed in the first detection signal, the first detection signal can be flattened over a wide bandwidth from low to high frequencies. As a result, it becomes possible to detect the first peak voltage over a wide bandwidth.

[0012] In some embodiments, the output circuit may further include a second peak detection circuit that outputs a second peak voltage in response to a first voltage divider signal. In this case, the second peak voltage can be output in addition to the first peak voltage. Therefore, in the external circuit, either the first peak voltage or the second peak voltage can be selected and used.

[0013] In some embodiments, the second peak detection circuit may detect the peak voltage of the first voltage divider signal and output a second peak voltage according to the detection result. Since the first voltage divider signal is a signal obtained by dividing the output signal, the signal strength of the high-frequency component of the first voltage divider signal is greater than the signal strength of the low-frequency component of the first voltage divider signal. Therefore, the second peak voltage can be generated by detecting the peak voltage of the high-frequency component of the first voltage divider signal. On the other hand, the first peak voltage can be generated by detecting the peak voltage consisting of signal components from a wide frequency range, from low to high, of the first detection signal. For this reason, for example, by comparing the first peak voltage and the second peak voltage, it becomes possible to estimate the amount of high-frequency peaking of the output signal.

[0014] In some embodiments, the output circuit may further include a second band-adjusting element having a resistive component that adjusts the frequency characteristics of the first voltage divider signal to generate a second detection signal. The second peak detection circuit may detect the peak voltage of the second detection signal and output a second peak voltage according to the detection result. In this case, a low-pass filter is formed by the second band-adjusting element and the input capacitance of the second peak detection circuit, so that the high-frequency components of the first voltage divider signal are reduced and the second detection signal is generated. For example, by making the resistive components of the first band-adjusting element and the second band-adjusting element different, the amount of reduction of the high-frequency components of the first voltage divider signal can be changed. This makes it possible to estimate how much the high-frequency components contribute to the peak voltage by comparing the first peak voltage and the second peak voltage.

[0015] In some embodiments, the output circuit may further include a second peak detection circuit that outputs a second peak voltage. The second capacitive element may include a third capacitive element and a fourth capacitive element connected in series. The voltage dividing circuit may divide the output signal by the first capacitive element, the third capacitive element, and the fourth capacitive element to generate a second divided voltage signal. The second peak detection circuit may output a second peak voltage according to the second divided voltage signal. In this case, in addition to the first peak voltage, the second peak voltage can be output. The second peak voltage is a peak voltage corresponding to the second divided voltage signal, and the voltage division ratio of the second divided voltage signal with respect to the output voltage is smaller than the voltage division ratio of the first divided voltage signal with respect to the output voltage. For example, in an external circuit, either one of the first peak voltage and the second peak voltage can be selected and used.

[0016] In some embodiments, the second peak detection circuit may detect the peak voltage of the second divided voltage signal and output a second peak voltage according to the detection result. Since the second divided voltage signal is a signal obtained by dividing the output signal, the signal intensity of the high-frequency component of the second divided voltage signal is greater than the signal intensity of the low-frequency component of the second divided voltage signal. Therefore, the second peak voltage can be generated by detecting the peak voltage of the high-frequency component of the second divided voltage signal. On the other hand, the first peak voltage can be generated by detecting a peak voltage composed of signal components in a wide frequency range from low frequency to high frequency of the first detection signal. Thus, for example, by comparing the first peak voltage and the second peak voltage, it becomes possible to estimate the degree to which the low-frequency component of the first detection signal contributes to the peak voltage.

[0017] In some embodiments, the output circuit may further include a second band adjustment element having a resistance component and configured to adjust the frequency characteristics of the second divided voltage signal to generate a second detection signal. The second peak detection circuit may detect the peak voltage of the second detection signal and output a second peak voltage according to the detection result. In this case, since a low-pass filter is formed by the second band adjustment element and the input capacitance of the second peak detection circuit, high-frequency components of the second divided voltage signal are reduced to generate the second detection signal. For example, by making the resistance component of the first band adjustment element different from the resistance component of the second band adjustment element, the spectrum of the second detection signal can be adjusted to a spectrum different from the spectrum of the first detection signal. For example, the spectrum of the first detection signal can be made a wide and flat spectrum from low frequency to high frequency, and the spectrum of the second detection signal can be made a spectrum in which high-frequency components are larger than low-frequency components. In this case, by comparing the first peak voltage and the second peak voltage, it becomes possible to estimate the degree to which the low-frequency components of the first detection signal contribute to the peak voltage.

[0018] In some embodiments, the output circuit may further include a ground wiring for supplying a ground potential. The first capacitive element and the second capacitive element may be connected in series with each other between the output terminal and the ground wiring. In this case, the first capacitive element and the second capacitive element are used for high-frequency peaking. That is, a voltage dividing circuit is configured using the first capacitive element and the second capacitive element used for high-frequency peaking. Therefore, since there is no need to provide dedicated electronic components for the voltage dividing circuit, it is possible to reduce the circuit scale of the output circuit.

[0019] In some embodiments, each of the first capacitive element and the second capacitive element may be constituted by an ESD protection diode. In this case, the output signal can be divided using the diode used for ESD protection. Therefore, since there is no need to provide dedicated circuit elements for the voltage dividing circuit, it is possible to reduce the circuit scale of the output circuit. <00000?9> In some embodiments, the output circuit may further include a semiconductor substrate and a flat first metal member provided on the semiconductor substrate. The output terminal may be an electrode pad provided on the semiconductor substrate. The grounding wiring may include a flat second metal member. The first metal member may be arranged facing the electrode pad. The first capacitive element may be composed of the electrode pad and the first metal member. In this case, the first capacitive element is composed of a metal pad provided on the semiconductor substrate and the first metal member. Therefore, since it is not necessary to configure the first capacitive element as a dedicated electronic component, it is possible to reduce the circuit size of the output circuit.

[0021] In some embodiments, the second metal member may be positioned opposite the first metal member. The second capacitive element may be composed of the first metal member and the second metal member. In this case, the second capacitive element is composed of the first metal member and the second metal member provided on a semiconductor substrate. Therefore, since it is not necessary to configure the second capacitive element as a dedicated electronic component, it is possible to reduce the circuit size of the output circuit.

[0022] [Details of the embodiments of this disclosure] Specific examples of output circuits according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples, and all modifications within the meaning and scope of the claims are intended to be included.

[0023] Figure 1 is a diagram showing the circuit configuration of an output circuit according to one embodiment. The output circuit 1 shown in Figure 1 is a circuit that outputs an output signal Vout to the outside. The output circuit 1 is, for example, a drive circuit that drives an optical modulator. The output circuit 1 is configured as, for example, an IC (Integrated Circuit). In this embodiment, the output signal Vout is a differential signal and includes a positive-sequence component Voutp and a negative-sequence component Voutn. Generally, the positive-sequence and negative-sequence components of a differential signal are complementary signals with a phase difference of 180° from each other. For example, when the positive-sequence component increases, the negative-sequence component decreases, and when the positive-sequence component decreases, the negative-sequence component increases. When the positive-sequence component reaches its peak value (maximum value), the negative-sequence component reaches its bottom value (minimum value), and when the positive-sequence component reaches its bottom value, the negative-sequence component reaches its peak value. The positive-sequence and negative-sequence components may have the same amplitude and the same center value (average value).

[0024] Output circuit 1 has output terminals Tout1 and Tout2 for outputting the output signal Vout to the outside of output circuit 1. Output terminal Tout1 outputs the positive-sequence component Voutp to the outside of output circuit 1. Output terminal Tout2 outputs the negative-sequence component Voutn to the outside of output circuit 1. Output circuit 1 includes a grounding wire GL. The grounding wire GL is a wire for supplying the ground potential.

[0025] The output circuit 1 includes an amplification circuit 2, inductors 3a and 3b, a voltage divider circuit 4, bandwidth adjustment elements 5a and 5b (first bandwidth adjustment elements), and a peak detection circuit 6 (first peak detection circuit).

[0026] Amplifier circuit 2 is a circuit that amplifies a differential input signal to generate a differential current signal (differential output signal). The differential input signal includes a positive-sequence component Vinp and an inverse-sequence component Vinn. Amplifier circuit 2 includes transistors 21, 22, 23, and 24, and a current source 25. Transistors 21, 22, 23, and 24 are, for example, NPN bipolar transistors. Amplifier circuit 2 constitutes, for example, an open-collector type amplifier circuit.

[0027] The positive-sequence component Vinp is input to the base of transistor 21. The negative-sequence component Vinn is input to the base of transistor 22. The emitters of transistor 21 and transistor 22 are electrically connected to each other and further to the current source 25. The collector of transistor 21 is electrically connected to the emitter of transistor 23. The collector of transistor 22 is electrically connected to the emitter of transistor 24. Transistor 21 modulates its collector current with the positive-sequence component Vinp. Transistor 22 modulates its collector current with the negative-sequence component Vinn. The electrical characteristics of transistor 21 may be substantially the same as those of transistor 22.

[0028] Transistors 23 and 24 are cascode transistors. The bases of transistor 23 and transistor 24 are electrically connected to each other and also to the bias supply terminal Tb. That is, a bias voltage is applied to the bases of transistors 23 and 24. The collector of transistor 23 is electrically connected to the output terminal Tout2 via inductor 3b. The collector of transistor 24 is electrically connected to the output terminal Tout1 via inductor 3a. Transistor 23 suppresses voltage fluctuations at the collector of transistor 21, thereby reducing the Miller capacitance of transistor 21. Similarly, transistor 24 suppresses voltage fluctuations at the collector of transistor 22, thereby reducing the Miller capacitance of transistor 22. The electrical characteristics of transistor 23 may be substantially the same as those of transistor 24. The collector currents of transistor 24 and transistor 23 constitute a differential output signal. For example, the collector current of transistor 24 becomes the positive-sequence component of the differential output signal, and the collector current of transistor 23 becomes the negative-sequence component of the differential output signal. Here, the positive-sequence and negative-sequence components are a pair of complementary signals and are relative to each other. The positive-sequence component has a phase 180° different from that of the negative-sequence component. That is, as described above, the positive-sequence and negative-sequence components are related such that when the positive-sequence component increases, the negative-sequence component decreases, and when the positive-sequence component decreases, the negative-sequence component increases. For example, the positive-sequence and negative-sequence components can be swapped and treated as a differential output signal.

[0029] The current source 25 supplies the emitter current of transistor 21 and the emitter current of transistor 22. One end of the current source 25 is electrically connected to the emitters of transistor 21 and transistor 22. The other end of the current source 25 is electrically connected to the ground wire GL. The current source 25 supplies a constant current. Therefore, when the emitter current of transistor 21 increases, the emitter current of transistor 22 decreases, and when the emitter current of transistor 21 decreases, the emitter current of transistor 22 increases. The sum of the emitter currents of transistor 21 and transistor 22 is equal to the constant current supplied by the current source 25.

[0030] Inductors 3a and 3b are circuit elements for generating the output signal Vout in response to the differential output signal output from the amplifier circuit 2. Specifically, inductor 3a is used to generate the positive-sequence component Voutp in response to the positive-sequence component of the differential output signal, and inductor 3b is used to generate the negative-sequence component Voutn in response to the negative-sequence component of the differential output signal.

[0031] Inductor 3a is electrically connected between the collector of transistor 24 and the output terminal Tout1. Specifically, one end of inductor 3a is electrically connected to the collector of transistor 24, and the other end of inductor 3a is electrically connected to the output terminal Tout1. Inductor 3b is electrically connected between the collector of transistor 23 and the output terminal Tout2. Specifically, one end of inductor 3b is electrically connected to the collector of transistor 23, and the other end of inductor 3b is electrically connected to the output terminal Tout2. The amplifier circuit 2 outputs a positive-sequence component Voutp via inductor 3a and a negative-sequence component Voutn via inductor 3b.

[0032] When amplifier circuit 2 is configured as an open-collector type amplifier circuit, the output signal Vout is generated by connecting termination circuits (not shown) to output terminals Tout1 and Tout2, respectively. More specifically, for example, an optical modulator is equipped with a termination resistor connected to the power supply wiring as a termination circuit, and the output signal Vout is generated when current flows through the termination resistor in accordance with the differential output signal. When amplifier circuit 2 is configured as an open-collector type amplifier circuit, the output signal Vout is undefined when output terminals Tout1 and Tout2 are open (not connected).

[0033] The voltage divider circuit 4 is a circuit that divides the output signal Vout to generate a divided voltage signal Vdiv1 (first divided voltage signal). The divided voltage signal Vdiv1 includes a positive-sequence component Vdiv1p and a negative-sequence component Vdiv1n. Specifically, the voltage divider circuit 4 divides the positive-sequence component Voutp and the negative-sequence component Voutn, respectively. The voltage divider circuit 4 includes capacitors 41, 42, 43, and 44.

[0034] Capacitor 41 (first capacitive element) and capacitor 42 (second capacitive element) are connected in series between the output terminal Tout1 and the grounding wire GL. Specifically, one end of capacitor 41 is electrically connected to the output terminal Tout1. The other end of capacitor 41 is electrically connected to one end of capacitor 42. The connection point CP1 between the other end of capacitor 41 and the one end of capacitor 42 is electrically connected to the peak detection circuit 6, which will be described later, via the bandwidth adjustment element 5a. The other end of capacitor 42 is electrically connected to the grounding wire GL.

[0035] The high-frequency component of the positive-sequence component of the differential output signal output from the amplifier circuit 2 is amplified by inductor 3a and capacitors 41 and 42, thereby generating the positive-sequence component Voutp. The inductance of inductor 3a, the capacitance C1 of capacitor 41, and the capacitance C2 of capacitor 42 are determined according to the amount of amplification of the high-frequency component of the positive-sequence component Voutp. Here, the high-frequency component refers to the signal component included in a specific frequency range with relatively high frequencies in the frequency characteristics of the positive-sequence component of the differential output signal. For example, the specific frequency range includes frequencies in which the signal intensity begins to decrease with increasing frequency. The inductance of inductor 3a is, for example, 50pF to 500pF. The capacitance C1 is, for example, 10fF to 100fF. The capacitance C2 is, for example, 10fF to 100fF.

[0036] The voltage divider circuit 4 divides the positive-sequence component Voutp using capacitors 41 and 42 to generate the positive-sequence component Vdiv1p. The voltage divider circuit 4 outputs the positive-sequence component Vdiv1p from the connection point CP1. The voltage value of the positive-sequence component Vdiv1p is expressed by equation (1) using capacitances C1 and C2. For convenience of explanation, in the formula, the voltage value of the positive-sequence component Vdiv1p is sometimes represented as "Vdiv1p" and the voltage value of the positive-sequence component Voutp is sometimes represented as "Voutp". In practice, capacitances C1 and C2 are adjusted so that the desired voltage division ratio is obtained, including the input capacitance of the peak detection circuit 6 and the parasitic capacitance of the bandwidth adjustment element 5a.

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[0037] From equation (1), the voltage division ratio of the voltage divider circuit 4 (the ratio of the positive-sequence component Vdiv1p, which is the output voltage of the voltage divider circuit, to the positive-sequence component Voutp, which is the input voltage of the voltage divider circuit) can be determined by the capacitances C1 and C2. For example, if the value of capacitance C1 is equal to the value of capacitance C2, the voltage division ratio becomes 1 / 2. If the value of capacitance C1 is greater than the value of capacitance C2, the voltage division ratio becomes greater than 1 / 2. If the value of capacitance C1 is less than the value of capacitance C2, the voltage division ratio becomes less than 1 / 2. However, in the frequency range lower than the cutoff frequency determined by capacitances C1 and C2 and the impedance to ground at connection point CP1, the voltage division ratio no longer follows equation (1). Capacitors C1 and C2 and the impedance to ground at connection point CP1 may be appropriately set so that the frequency range required for peak detection is higher than the cutoff frequency.

[0038] Capacitor 43 (first capacitive element) and capacitor 44 (second capacitive element) are connected in series between the output terminal Tout2 and the grounding wire GL. Specifically, one end of capacitor 43 is electrically connected to the output terminal Tout2. The other end of capacitor 43 is electrically connected to one end of capacitor 44. The connection point CP2 between the other end of capacitor 43 and the one end of capacitor 44 is electrically connected to the peak detection circuit 6, which will be described later, via the bandwidth adjustment element 5b. The other end of capacitor 44 is electrically connected to the grounding wire GL.

[0039] The inductor 3b and capacitors 43 and 44 amplify the high-frequency component of the inverse-phase component of the differential output signal output from the amplifier circuit 2, thereby generating the inverse-phase component Voutn. The inductance of inductor 3b, the capacitance C3 of capacitor 43, and the capacitance C4 of capacitor 44 are determined according to the amount of amplification of the high-frequency component of the inverse-phase component Voutn. Here, the high-frequency component refers to the signal component included in a specific frequency range with relatively high frequencies in the frequency characteristics of the inverse-phase component of the differential output signal. For example, the specific frequency range includes frequencies in which the signal intensity begins to decrease with increasing frequency. The inductance of inductor 3b is, for example, 50pF to 500pF. The capacitance C3 is, for example, 10fF to 100fF. The capacitance C4 is, for example, 10fF to 100fF.

[0040] The voltage divider circuit 4 divides the inverse-phase component Voutn using capacitors 43 and 44 to generate the inverse-phase component Vdiv1n. The voltage divider circuit 4 outputs the inverse-phase component Vdiv1n from the connection point CP2. The voltage value of the inverse-phase component Vdiv1n is expressed by equation (2) using capacitances C3 and C4. For the sake of explanation, in the formula, the voltage value of the inverse-phase component Vdiv1n is sometimes represented as "Vdiv1n" and the voltage value of the inverse-phase component Voutn is sometimes represented as "Voutn". In practice, capacitances C3 and C4 are adjusted so that the desired voltage division ratio is obtained, including the input capacitance of the peak detection circuit 6 and the parasitic capacitance of the bandwidth adjustment element 5b.

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[0041] From equation (2), the voltage division ratio of the voltage divider circuit 4 (the ratio of the output voltage of the voltage divider circuit, the inverse-phase component Vdiv1n, to the input voltage of the voltage divider circuit, the inverse-phase component Voutn) can be determined by the capacitances C3 and C4. For example, if the value of capacitance C3 is equal to the value of capacitance C4, the voltage division ratio becomes 1 / 2. If the value of capacitance C3 is greater than the value of capacitance C4, the voltage division ratio becomes greater than 1 / 2. If the value of capacitance C3 is less than the value of capacitance C4, the voltage division ratio becomes less than 1 / 2. However, in the frequency range lower than the cutoff frequency determined by capacitances C3, C4 and the impedance to ground at connection point CP2, the voltage division ratio no longer follows equation (2). Capacitors C3, C4 and the impedance to ground at connection point CP2 may be appropriately set so that the frequency range required for peak detection is higher than the cutoff frequency.

[0042] The bandwidth adjustment elements 5a and 5b are circuit elements that have a resistive component and adjust the bandwidth of the voltage divider signal Vdiv1 to generate a detection signal Vm1 (first detection signal). The detection signal Vm1 includes a positive-sequence component Vm1p and an inverse-sequence component Vm1n. Specifically, bandwidth adjustment element 5a is used to adjust the bandwidth of the positive-sequence component Vdiv1p to generate the positive-sequence component Vm1p, and bandwidth adjustment element 5b is used to adjust the bandwidth of the inverse-sequence component Vdiv1n to generate the inverse-sequence component Vm1n. The bandwidth adjustment elements 5a and 5b are, for example, resistive elements. Note that the bandwidth is an example of the frequency characteristics in this disclosure.

[0043] The bandwidth adjustment element 5a is electrically connected between connection point CP1 and peak detection circuit 6. Specifically, one end of the bandwidth adjustment element 5a is electrically connected to connection point CP1, and the other end of the bandwidth adjustment element 5a is electrically connected to the base of transistor 61. The bandwidth adjustment element 5b is electrically connected between connection point CP2 and peak detection circuit 6. Specifically, one end of the bandwidth adjustment element 5b is electrically connected to connection point CP2, and the other end of the bandwidth adjustment element 5b is electrically connected to the base of transistor 62. The resistance values ​​of the bandwidth adjustment elements 5a and 5b are, for example, 1kΩ to 10kΩ.

[0044] A low-pass filter is formed by the bandwidth adjustment element 5a and the input capacitance of the peak detection circuit 6, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the positive-sequence component Vdiv1p are reduced, and the positive-sequence component Vm1p is generated. Similarly, a low-pass filter is formed by the bandwidth adjustment element 5b and the input capacitance of the peak detection circuit 6, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the negative-sequence component Vdiv1n are reduced, and the negative-sequence component Vm1n is generated.

[0045] The cutoff frequency of the low-pass filter can be increased or decreased by adjusting the resistance values ​​of the bandwidth adjustment elements 5a and 5b. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b lowers the cutoff frequency, and decreasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b raises the cutoff frequency. Therefore, adjusting the resistance values ​​of the bandwidth adjustment elements 5a and 5b increases or decreases the bandwidth of the detection signal Vm1. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b narrows the bandwidth, suppressing the high-frequency components due to high-frequency peaking of the voltage divider signal Vdiv1, and flattening the spectrum of the detection signal Vm1. Decreasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b widens the bandwidth, resulting in a spectrum of the detection signal Vm1 that is similar to the spectrum of the voltage divider signal Vdiv1, where high-frequency components are amplified by high-frequency peaking.

[0046] The peak detection circuit 6 is a circuit that detects the peak voltage of the detection signal Vm1 and outputs a peak voltage Vpeak1 (first peak voltage) according to the detection result. The peak voltage Vpeak1 is a voltage generated according to the peak voltage of the detection signal Vm1. For example, the peak voltage Vpeak1 is smaller than the peak voltage of the detection signal Vm1 due to the base-emitter voltage of transistors 61 and 62, which will be described later. The peak detection circuit 6 outputs the peak voltage Vpeak1 to the outside of the output circuit 1 from the output terminal Tp1. The peak voltage Vpeak1 makes it possible to estimate the magnitude of the peak voltage of the input signal (output signal Vout) of the peak detection circuit 6. This makes it possible to automatically control the voltage gain of the output circuit 1 using, for example, an external control circuit. The output terminal Tp1 is a terminal that outputs the peak voltage Vpeak1 to the outside of the output circuit 1. The peak detection circuit 6 includes transistors 61 and 62, a current source 63, and a capacitor 64.

[0047] Transistors 61 and 62 are, for example, NPN bipolar transistors. The base of transistor 61 is electrically connected to the other end of the band adjustment element 5a. The positive-sequence component Vm1p is input to the base of transistor 61. The base of transistor 62 is electrically connected to the other end of the band adjustment element 5b. The negative-sequence component Vm1n is input to the base of transistor 62. The collectors of transistor 61 and transistor 62 are electrically connected to each other and are further electrically connected to the power supply wiring PL that supplies the power supply voltage. The emitters of transistor 61 and transistor 62 are electrically connected to each other and are further electrically connected to the output terminal Tp1.

[0048] The current source 63 biases transistors 61 and 62. In other words, the current source 63 sets the operating reference potential for transistors 61 and 62. One end of the current source 63 is electrically connected to the output terminal Tp1, and the other end of the current source 63 is electrically connected to the ground wire GL. The capacitor 64 is connected in parallel with the current source 63. In other words, one end of the capacitor 64 is electrically connected to the output terminal Tp1, and the other end of the capacitor 64 is electrically connected to the ground wire GL.

[0049] In the peak detection circuit 6, the capacitor 64 is charged according to the positive-sequence component Vm1p and negative-sequence component Vm1n input to the bases of transistors 61 and 62, respectively. When either transistor 61 or 62 is ON, a charging current flows to the capacitor 64, and charge is stored in the capacitor 64. For example, when the voltage value of the positive-sequence component Vm1p (or negative-sequence component Vm1n) becomes greater than the base-emitter voltage of transistor 61 (transistor 62) relative to the peak voltage Vpeak1, transistor 61 (transistor 62) turns ON. On the other hand, when transistors 61 and 62 are OFF, the charge stored in the capacitor 64 is released (discharged) by the current source 63. As a result of these charging and discharging, a peak voltage Vpeak1 is generated across the capacitor 64.

[0050] In the output circuit 1 described above, the high-frequency components of the positive-sequence component Voutp are amplified by the inductor 3a and capacitors 41 and 42. For example, such amplification increases the intensity of the high-frequency components more than the intensity of the low-frequency components. Here, the low-frequency components refer to signal components contained in a predetermined frequency range with frequencies lower than the predetermined frequency range containing the high-frequency components. Increasing the intensity of the high-frequency components more than the intensity of the low-frequency components is also called high-frequency peaking. In the following explanation, the high-frequency components refer to signal components in the frequency range where the signal intensity is amplified by high-frequency peaking, and the low-frequency components refer to signal components in a frequency range with frequencies lower than the frequency range of high-frequency peaking.

[0051] Since the high-frequency components of the positive-sequence component Voutp are amplified, the high-frequency components of the positive-sequence component Vdiv1p obtained by voltage division of the positive-sequence component Voutp are also amplified. A low-pass filter is formed by the bandwidth adjustment element 5a and the input capacitance of the peak detection circuit 6, so the high-frequency components of the positive-sequence component Vdiv1p with frequencies higher than the cutoff frequency of the low-pass filter are reduced, and the positive-sequence component Vm1p is generated. For example, by setting the cutoff frequency of the low-pass filter lower than a predetermined frequency range containing high-frequency components, the intensity of the high-frequency components can be attenuated.

[0052] Similarly, the high-frequency components of the inverse-phase component Voutn are amplified (high-frequency peaking) by inductor 3b and capacitors 43 and 44. Therefore, the high-frequency components of the inverse-phase component Vdiv1n, obtained by voltage division of the inverse-phase component Voutn, are also amplified. A low-pass filter is formed by the bandwidth adjustment element 5b and the input capacitance of the peak detection circuit 6, so the high-frequency components of the inverse-phase component Vdiv1n with frequencies higher than the cutoff frequency of the low-pass filter are reduced, and the inverse-phase component Vm1n is generated. For example, by setting the cutoff frequency of the low-pass filter lower than a predetermined frequency range containing high-frequency components, the intensity of the high-frequency components can be attenuated.

[0053] As a result, for example, the signal intensity (amplitude) of the high-frequency components of the output signal Vout and the voltage divider signal Vdiv1 is larger than that of the low-frequency components, but the amplitude of the high-frequency components of the detection signal Vm1 can be made substantially equal to the amplitude of the low-frequency components. This process of uniformizing the signal intensity across a wide bandwidth from low to high frequencies is also called flattening. Signal intensity represents the magnitude of the signal components in the spectrum. Amplitude is an example of signal intensity. Therefore, it becomes possible to detect the peak voltage of the detection signal Vm1, which has been flattened across a wide bandwidth from low to high frequencies, and output the peak voltage Vpeak1 according to the detection result.

[0054] In output circuit 1, capacitors 41 and 42 are connected in series between output terminal Tout1 and ground wire GL, and capacitors 43 and 44 are connected in series between output terminal Tout2 and ground wire GL. Capacitors 41, 42, 43, and 44 are used for high-frequency peaking. In other words, the voltage divider circuit 4 is constructed using capacitors 41, 42, 43, and 44, which are used for high-frequency peaking. Therefore, there is no need to provide dedicated electronic components for the voltage divider circuit 4, making it possible to reduce the circuit size of output circuit 1.

[0055] Next, with reference to Figure 2, an output circuit according to another embodiment will be described. Figure 2 is a diagram showing the circuit configuration of an output circuit according to another embodiment. The output circuit 1A shown in Figure 2 differs from output circuit 1 in that it further includes a peak detection circuit 7 (second peak detection circuit).

[0056] The peak detection circuit 7 is a circuit that detects the peak voltage of the voltage divider signal Vdiv1 and outputs a peak voltage Vpeak2 (second peak voltage) according to the detection result. In this embodiment, the peak voltage Vpeak2 is a voltage generated according to the peak voltage of the voltage divider signal Vdiv1. For example, the peak voltage Vpeak2 is smaller than the peak voltage of the voltage divider signal Vdiv1 due to the base-emitter voltage of transistors 71 and 72, which will be described later. The peak detection circuit 7 outputs the peak voltage Vpeak2 to the outside of the output circuit 1A from the output terminal Tp2. The peak voltage Vpeak2 makes it possible to estimate the magnitude of the peak voltage of the input signal (output signal Vout) of the peak detection circuit 7. This makes it possible to automatically control the voltage gain of the output circuit 1A using, for example, an external control circuit. The output terminal Tp2 is a terminal that outputs the peak voltage Vpeak2 to the outside of the output circuit 1A. The peak detection circuit 7 includes transistors 71 and 72, a current source 73, and a capacitor 74.

[0057] Transistors 71 and 72 are, for example, NPN bipolar transistors. The base of transistor 71 is electrically connected to junction CP1. The positive-sequence component Vdiv1p is input to the base of transistor 71. The base of transistor 72 is electrically connected to junction CP2. The negative-sequence component Vdiv1n is input to the base of transistor 72. The collectors of transistor 71 and transistor 72 are electrically connected to each other and further to the power supply wiring PL. The emitters of transistor 71 and transistor 72 are electrically connected to each other and further to the output terminal Tp2.

[0058] The current source 73 biases transistors 71 and 72. In other words, the current source 73 sets the operating reference potential for transistors 71 and 72. One end of the current source 73 is electrically connected to the output terminal Tp2, and the other end of the current source 73 is electrically connected to the ground wire GL. Capacitor 74 is connected in parallel with the current source 73. In other words, one end of capacitor 74 is electrically connected to the output terminal Tp2, and the other end of capacitor 74 is electrically connected to the ground wire GL.

[0059] In the peak detection circuit 7, the capacitor 74 is charged according to the positive-sequence component Vdiv1p and negative-sequence component Vdiv1n input to the bases of transistors 71 and 72, respectively. When either transistor 71 or 72 is ON, a charging current flows to the capacitor 74, and charge is stored in the capacitor 74. For example, when the voltage value of the positive-sequence component Vdiv1p (or negative-sequence component Vdiv1n) becomes greater than the base-emitter voltage of transistor 71 (transistor 72) relative to the peak voltage Vpeak2, transistor 71 (transistor 72) turns ON. On the other hand, when transistors 71 and 72 are OFF, the charge stored in the capacitor 74 is released (discharged) by the current source 73. As a result of these charging and discharging, a peak voltage Vpeak2 is generated across the capacitor 74.

[0060] In output circuit 1A, the same effects as output circuit 1 are achieved with the same configuration as output circuit 1. Furthermore, in output circuit 1A, the peak detection circuit 7 detects the peak voltage of the voltage divider signal Vdiv1 and outputs the peak voltage Vpeak2 according to the detection result. The signal strength (amplitude) of the high-frequency component of the voltage divider signal Vdiv1 is larger than the signal strength (amplitude) of the low-frequency component of the voltage divider signal Vdiv1, for example, due to high-frequency peaking. Therefore, it is possible to detect the peak voltage of the high-frequency component of the voltage divider signal Vdiv1 and output the peak voltage Vpeak2 according to the detection result.

[0061] On the other hand, the peak voltage Vpeak1 is a voltage generated by detecting the peak voltage consisting of signal components from a wide frequency range, from low to high, of the detection signal Vm1, from which the high-frequency components of the divided signal Vdiv1 have been reduced by the low-pass filter described above. As a result, by comparing the peak voltage Vpeak1 and the peak voltage Vpeak2, it is possible to estimate the magnitude of the high-frequency peaking of the divided signal Vdiv1, i.e., the output signal Vout. Alternatively, for example, depending on the spectrum (distribution of signal components in the frequency range) of the output signal Vout, either the peak voltage Vpeak1 or the peak voltage Vpeak2 can be selected and used. For example, when an optical modulator is driven by the output signal Vout, the peak voltage may be selected considering the response characteristics (frequency characteristics) of the optical signal to the drive signal of the optical modulator.

[0062] Output circuit 1A can output peak voltage Vpeak2 in addition to peak voltage Vpeak1. By comparing the results of these different peak voltages with the results of comparing the frequency characteristics of the input signals of peak detection circuit 6 and peak detection circuit 7, it becomes possible to estimate the contribution of signal components in a specific frequency range to the peak voltage, as described above. The specific frequency range is, for example, the frequency range of high-frequency peaking. Alternatively, for example, with respect to the signal intensity (amplitude) spectrum of the output signal Vout, either peak voltage Vpeak2 estimated by a detection signal (voltage divider signal Vdiv1) having the same spectrum as the high-frequency peaked output signal Vout, or peak voltage Vpeak1 estimated by a detection signal Vm1 having a spectrum flattened from low to high frequencies with the effect of high-frequency peaking suppressed, can be selected and used. For example, when an optical modulator is driven by the output signal Vout, the peak voltage may be selected considering the response characteristics (frequency characteristics) of the optical signal to the drive signal of the optical modulator.

[0063] Next, with reference to Figure 3, an output circuit according to yet another embodiment will be described. Figure 3 is a diagram showing the circuit configuration of an output circuit according to yet another embodiment. The output circuit 1B shown in Figure 3 mainly differs from the output circuit 1A in that it further includes bandwidth adjustment elements 5c, 5d (second bandwidth adjustment elements) and the signal detected by the peak detection circuit 7.

[0064] The bandwidth adjustment elements 5c and 5d are circuit elements that have a resistive component and adjust the bandwidth of the voltage divider signal Vdiv1 to generate the detection signal Vm2 (second detection signal). Specifically, the bandwidth adjustment element 5c is used to adjust the bandwidth of the positive-sequence component Vdiv1p to generate the positive-sequence component Vm2p, and the bandwidth adjustment element 5d is used to adjust the bandwidth of the negative-sequence component Vdiv1n to generate the negative-sequence component Vm2n. The bandwidth adjustment elements 5c and 5d are, for example, resistive elements.

[0065] The bandwidth adjustment element 5c is electrically connected between connection point CP1 and peak detection circuit 7. Specifically, one end of the bandwidth adjustment element 5c is electrically connected to connection point CP1, and the other end of the bandwidth adjustment element 5c is electrically connected to the base of transistor 71. The bandwidth adjustment element 5d is electrically connected between connection point CP2 and peak detection circuit 7. Specifically, one end of the bandwidth adjustment element 5d is electrically connected to connection point CP2, and the other end of the bandwidth adjustment element 5d is electrically connected to the base of transistor 72. The resistance values ​​of the bandwidth adjustment elements 5c and 5d are different from the resistance values ​​of the bandwidth adjustment elements 5a and 5b. The resistance values ​​of the bandwidth adjustment elements 5c and 5d are, for example, between 5kΩ and 50kΩ.

[0066] A low-pass filter is formed by the bandwidth adjustment element 5c and the input capacitance of the peak detection circuit 7, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the positive-sequence component Vdiv1p are reduced, and the positive-sequence component Vm2p is generated. Similarly, a low-pass filter is formed by the bandwidth adjustment element 5d and the input capacitance of the peak detection circuit 7, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the negative-sequence component Vdiv1n are reduced, and the negative-sequence component Vm2n is generated.

[0067] The cutoff frequency of the low-pass filter can be increased or decreased by adjusting the resistance values ​​of the bandwidth adjustment elements 5c and 5d. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5c and 5d lowers the cutoff frequency, and decreasing the resistance values ​​of the bandwidth adjustment elements 5c and 5d raises the cutoff frequency. Therefore, adjusting the resistance values ​​of the bandwidth adjustment elements 5c and 5d increases or decreases the bandwidth of the detection signal Vm2. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5c and 5d narrows the bandwidth, suppressing the high-frequency components due to high-frequency peaking of the voltage divider signal Vdiv1, and flattening the spectrum of the detection signal Vm2. Decreasing the resistance values ​​of the bandwidth adjustment elements 5c and 5d widens the bandwidth, resulting in a spectrum of the detection signal Vm2 that is similar to the spectrum of the voltage divider signal Vdiv1, where high-frequency components are amplified by high-frequency peaking.

[0068] In this embodiment, the peak detection circuit 7 is a circuit that detects the peak voltage of the detection signal Vm2 and outputs a peak voltage Vpeak2 according to the detection result. The peak voltage Vpeak2 is a voltage generated according to the peak voltage of the detection signal Vm2. For example, the peak voltage Vpeak2 is smaller than the peak voltage of the detection signal Vm2 due to the base-emitter voltage of transistors 71 and 72.

[0069] In output circuit 1B, the same effects as output circuit 1A are achieved with the same configuration as output circuit 1A. Furthermore, in output circuit 1B, the peak detection circuit 7 detects the peak voltage of the detection signal Vm2 and outputs a peak voltage Vpeak2 according to the detection result. A low-pass filter is formed by the bandwidth adjustment element 5c and the input capacitance of the peak detection circuit 7, so high-frequency components of the positive-sequence component Vdiv1p that are higher than the cutoff frequency of the low-pass filter are reduced, and the positive-sequence component Vm2p is generated. Therefore, for example, by making the resistance values ​​of bandwidth adjustment element 5a and bandwidth adjustment element 5c different, the cutoff frequency of the low-pass filter can be adjusted, and the amount of reduction of high-frequency components of the positive-sequence component Vdiv1p can be changed.

[0070] Similarly, a low-pass filter is formed by the bandwidth adjustment element 5d and the input capacitance of the peak detection circuit 7. As a result, high-frequency components of the inverse-phase component Vdiv1n that are higher than the cutoff frequency of the low-pass filter are reduced, generating the inverse-phase component Vm2n. Therefore, by making the resistance values ​​of the bandwidth adjustment element 5b and the bandwidth adjustment element 5d different, the cutoff frequency of the low-pass filter can be adjusted, thereby changing the amount of reduction of the high-frequency components of the inverse-phase component Vdiv1n. This makes it possible, for example, to make the signal intensity (amplitude) of the high-frequency component of the detection signal Vm2 approximately the same as the signal intensity (amplitude) of the low-frequency component for a high-frequency peaked output signal Vout. As a result, it becomes possible to detect the peak voltage of the detection signal Vm2, which has a spectrum flattened over a wide bandwidth from low to high frequencies, and output the peak voltage Vpeak2 according to the detection result.

[0071] On the other hand, for example, the cutoff frequency of the low-pass filter formed by the bandwidth adjustment element 5a and the input capacitance of the peak detection circuit 6 can be set higher than the cutoff frequency of the low-pass filter formed by the bandwidth adjustment element 5c and the input capacitance of the peak detection circuit 7, and the cutoff frequency of the low-pass filter formed by the bandwidth adjustment element 5b and the input capacitance of the peak detection circuit 6 can be set higher than the cutoff frequency of the low-pass filter formed by the bandwidth adjustment element 5d and the input capacitance of the peak detection circuit 7. In this case, the spectrum of the detection signal Vm1 will be an intermediate spectrum between the spectrum of the high-frequency peaked output signal Vout and the spectrum of the detection signal Vm2 flattened over a wide bandwidth from low to high frequencies. The peak voltage Vpeak1 will be a voltage generated in accordance with the peak voltage of the detection signal Vm1 having such an intermediate spectrum. As a result, by comparing the peak voltage Vpeak1 and the peak voltage Vpeak2, it is possible to estimate how much the high-frequency component of the detection signal Vm1 contributes to the peak voltage.

[0072] Alternatively, for example, one of the following peak voltages can be selected and used: Vpeak2, which is estimated by a detection signal Vm2 having a spectrum flattened from low to high frequencies with suppressed high-frequency peaking effects compared to the signal intensity (amplitude) spectrum of the output signal Vout; and Vpeak1, which is estimated by a detection signal (voltage divider signal Vdiv1) having a spectrum with moderately suppressed high-frequency peaking effects compared to the detection signal Vm2.

[0073] In output circuit 1B, bandwidth adjustment elements 5c and 5d are provided between the voltage divider circuit 4 and the peak detection circuit 7. This configuration reduces the influence of the input capacitance of the peak detection circuit 7 on the voltage division ratio of the voltage divider circuit 4.

[0074] Next, with reference to Figure 4, an output circuit according to yet another embodiment will be described. Figure 4 is a diagram showing the circuit configuration of an output circuit according to yet another embodiment. The output circuit 1C shown in Figure 4 mainly differs from the output circuit 1A in that it includes a voltage divider circuit 4C instead of the voltage divider circuit 4, and in the signal detected by the peak detection circuit 7.

[0075] In addition to the divided voltage signal Vdiv1, the voltage divider circuit 4C further generates a divided voltage signal Vdiv2 (second divided voltage signal) by dividing the output signal Vout. The voltage divider circuit 4C mainly differs from the voltage divider circuit 4 in that capacitor 42 includes capacitor 45 (third capacitive element) and capacitor 46 (fourth capacitive element), and capacitor 44 includes capacitor 47 (third capacitive element) and capacitor 48 (fourth capacitive element).

[0076] Specifically, capacitor 42 is composed of capacitors 45 and 46 connected in series with each other. One end of capacitor 45 is electrically connected to the other end of capacitor 41. The other end of capacitor 45 is electrically connected to one end of capacitor 46. The connection point CP3 between the other end of capacitor 45 and the one end of capacitor 46 is electrically connected to the base of transistor 71. The other end of capacitor 46 is electrically connected to the ground wire GL. In other words, capacitors 41, 45, and 46 are connected in series between the output terminal Tout1 and the ground wire GL.

[0077] Capacitor 44 is composed of capacitors 47 and 48 connected in series with each other. One end of capacitor 47 is electrically connected to the other end of capacitor 43. The other end of capacitor 47 is electrically connected to one end of capacitor 48. The connection point CP4 between the other end of capacitor 47 and the one end of capacitor 48 is electrically connected to the base of transistor 72. The other end of capacitor 48 is electrically connected to the ground wire GL. In other words, capacitors 43, 47, and 48 are connected in series between the output terminal Tout2 and the ground wire GL.

[0078] The voltage divider circuit 4C divides the positive-sequence component Voutp using the series circuit of capacitors 41 and 45 and capacitor 46 to generate the positive-sequence component Vdiv2p. The voltage divider circuit 4C outputs the positive-sequence component Vdiv2p from connection point CP3. The voltage divider circuit 4C divides the negative-sequence component Voutn using the series circuit of capacitors 43 and 47 and capacitor 48 to generate the negative-sequence component Vdiv2n. The voltage divider circuit 4C outputs the negative-sequence component Vdiv2n from connection point CP4.

[0079] At low frequencies, the voltage value (amplitude) of the voltage divider signal Vdiv2 is smaller than the voltage value (amplitude) of the detection signal Vm1. On the other hand, at high frequencies, capacitance C1, capacitance C3, capacitance C5 of capacitor 45, capacitance C6 of capacitor 46, capacitance C7 of capacitor 47, capacitance C8 of capacitor 48, resistance value of bandwidth adjustment element 5a, and resistance value of bandwidth adjustment element 5b may be set so that the voltage value (amplitude) of the voltage divider signal Vdiv2 is approximately the same as the voltage value (amplitude) of the detection signal Vm1. Here, "low frequency" refers to a frequency lower than the frequency range in which the signal component is amplified by high-frequency peaking. Here, "high frequency" refers to a frequency within the frequency range of high-frequency peaking. As a result, for example, the amplitude of the high-frequency component of the detection signal Vm1 can be made substantially equal to the amplitude of the low-frequency component, the amplitude of the low-frequency component of the voltage divider signal Vdiv2 can be made smaller than the amplitude of the low-frequency component of the detection signal Vm1, and the amplitude of the high-frequency component of the voltage divider signal Vdiv2 can be made substantially equal to the amplitude of the high-frequency component of the detection signal Vm1.

[0080] In this embodiment, the peak detection circuit 7 detects the peak voltage of the voltage divider signal Vdiv2 and outputs a peak voltage Vpeak2 according to the detection result. The peak voltage Vpeak2 is a voltage generated according to the peak voltage of the voltage divider signal Vdiv2. The peak voltage Vpeak2 is smaller than the peak voltage of the voltage divider signal Vdiv2 due, for example, the base-emitter voltage of transistors 71 and 72.

[0081] In output circuit 1C, the same effects as output circuit 1A are achieved with the same configuration as output circuit 1A. Furthermore, in output circuit 1C, the voltage divider circuit 4C divides the positive-sequence component Voutp using capacitors 41, 45 and capacitor 46 to generate the positive-sequence component Vdiv2p, and divides the negative-sequence component Voutn using capacitors 43, 47 and capacitor 48 to generate the negative-sequence component Vdiv2n. The peak detection circuit 7 outputs a peak voltage Vpeak2 corresponding to the divided voltage signal Vdiv2. Specifically, the peak detection circuit 7 detects the peak voltage of the divided voltage signal Vdiv2 and outputs a peak voltage Vpeak2 according to the detection result.

[0082] As described above, the signal strength (amplitude) of the high-frequency component of the detection signal Vm1 can be made substantially equal to the signal strength (amplitude) of the low-frequency component, and the signal strength (amplitude) of the low-frequency component of the voltage divider signal Vdiv2 can be made smaller than the signal strength (amplitude) of the low-frequency component of the detection signal Vm1, thereby making the signal strength (amplitude) of the high-frequency component of the voltage divider signal Vdiv2 substantially equal to the signal strength (amplitude) of the high-frequency component of the detection signal Vm1. As a result, the output circuit 1C can detect the peak voltage consisting of signal components from a wide frequency range from low to high frequencies of the detection signal Vm1 and output the peak voltage Vpeak1 according to the detection result, as well as detect the peak voltage of the high-frequency component of the voltage divider signal Vdiv2 and output the peak voltage Vpeak2 according to the detection result. This makes it possible to estimate the extent to which the low-frequency component of the detection signal Vm1 contributes to the peak voltage by comparing the peak voltages Vpeak1 and Vpeak2. Alternatively, for example, depending on the spectrum of the output signal Vout, one of the peak voltages Vpeak1 or Vpeak2 can be selected and used.

[0083] In output circuit 1C, in addition to peak voltage Vpeak1, peak voltage Vpeak2 can be output. Peak voltage Vpeak2 is the peak voltage corresponding to the voltage divider signal Vdiv2, and the voltage division ratio of voltage divider signal Vdiv2 with respect to the output signal Vout is smaller than the voltage division ratio of voltage divider signal Vdiv1 with respect to the output signal Vout. By comparing the results of these different peak voltages with the results of comparing the frequency characteristics of the input signals of peak detection circuit 6 and peak detection circuit 7, it is possible to estimate the contribution of signal components in a specific frequency range (e.g., high-frequency components due to high-frequency peaking) to the peak voltage, as described above. Alternatively, for example, depending on the spectrum of the output signal Vout, either peak voltage Vpeak1 or peak voltage Vpeak2 can be selected and used. For example, when an optical modulator is driven by the output signal Vout, the peak voltage may be selected considering the response characteristics (frequency characteristics) of the optical signal to the drive signal of the optical modulator.

[0084] Furthermore, by using the voltage divider circuit 4C to make the signal strength (amplitude) of the high-frequency component of the divided voltage signal Vdiv2 substantially equal to the signal strength (amplitude) of the high-frequency component of the detection signal Vm1, the voltage values ​​of the detection signal Vm1 input to transistors 61 and 62 of the peak detection circuit 6 and the voltage values ​​of the divided voltage signal Vdiv2 input to transistors 71 and 72 of the peak detection circuit 7 can be kept below a predetermined voltage. Therefore, transistors 61, 62, 71, and 72 can be operated with a margin relative to their respective allowable voltages.

[0085] Next, with reference to Figure 5, an output circuit according to yet another embodiment will be described. Figure 5 is a diagram showing the circuit configuration of an output circuit according to yet another embodiment. The output circuit 1D shown in Figure 5 mainly differs from the output circuit 1B in that it includes a voltage divider circuit 4C instead of the voltage divider circuit 4, and in the signals that are subject to bandwidth adjustment by the bandwidth adjustment elements 5c and 5d.

[0086] In this embodiment, the bandwidth adjustment elements 5c and 5d are circuit elements for adjusting the bandwidth of the voltage divider signal Vdiv2 to generate a detection signal Vm2. Specifically, the bandwidth adjustment element 5c is used to adjust the bandwidth of the positive-sequence component Vdiv2p to generate the positive-sequence component Vm2p, and the bandwidth adjustment element 5d is used to adjust the bandwidth of the negative-sequence component Vdiv2n to generate the negative-sequence component Vm2n.

[0087] The bandwidth adjustment element 5c is electrically connected between connection point CP3 and peak detection circuit 7. Specifically, one end of the bandwidth adjustment element 5c is electrically connected to connection point CP3, and the other end of the bandwidth adjustment element 5c is electrically connected to the base of transistor 71. The bandwidth adjustment element 5d is electrically connected between connection point CP4 and peak detection circuit 7. Specifically, one end of the bandwidth adjustment element 5d is electrically connected to connection point CP4, and the other end of the bandwidth adjustment element 5d is electrically connected to the base of transistor 72. The resistance values ​​of the bandwidth adjustment elements 5c and 5d may differ from the resistance values ​​of the bandwidth adjustment elements 5a and 5b. The resistance values ​​of the bandwidth adjustment elements 5c and 5d are, for example, between 5kΩ and 50kΩ.

[0088] A low-pass filter is formed by the bandwidth adjustment element 5c and the input capacitance of the peak detection circuit 7, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the positive-sequence component Vdiv2p are reduced, and the positive-sequence component Vm2p is generated. Similarly, a low-pass filter is formed by the bandwidth adjustment element 5d and the input capacitance of the peak detection circuit 7, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the negative-sequence component Vdiv2n are reduced, and the negative-sequence component Vm2n is generated.

[0089] The cutoff frequency of the low-pass filter can be increased or decreased by adjusting the resistance values ​​of the bandwidth adjustment elements 5c and 5d. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5c and 5d lowers the cutoff frequency, and decreasing the resistance values ​​of the bandwidth adjustment elements 5c and 5d raises the cutoff frequency. Therefore, adjusting the resistance values ​​of the bandwidth adjustment elements 5c and 5d increases or decreases the bandwidth of the detection signal Vm2. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5c and 5d narrows the bandwidth, suppressing the high-frequency components due to high-frequency peaking of the voltage divider signal Vdiv2, and flattening the spectrum of the detection signal Vm2. Decreasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b widens the bandwidth, resulting in a spectrum of the detection signal Vm2 that is similar to the spectrum of the voltage divider signal Vdiv2, where high-frequency components are amplified by high-frequency peaking.

[0090] In output circuit 1D, the same effects as in output circuit 1B are achieved with the same configuration as in output circuit 1B. Furthermore, in output circuit 1D, a low-pass filter is formed by the bandwidth adjustment element 5c and the input capacitance of the peak detection circuit 7, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the positive-sequence component Vdiv2p are reduced, and the positive-sequence component Vm2p is generated. Similarly, a low-pass filter is formed by the bandwidth adjustment element 5d and the input capacitance of the peak detection circuit 7, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the negative-sequence component Vdiv2n are reduced, and the negative-sequence component Vm2n is generated.

[0091] For example, the signal strength (amplitude) of the high-frequency component of the detection signal Vm1 can be made substantially equal to the signal strength (amplitude) of the low-frequency component, and the signal strength (amplitude) of the low-frequency component of the detection signal Vm2 can be made smaller than the signal strength (amplitude) of the low-frequency component of the detection signal Vm1, thereby making the signal strength (amplitude) of the high-frequency component of the detection signal Vm2 substantially equal to the signal strength (amplitude) of the high-frequency component of the detection signal Vm1. This makes it possible to detect the peak voltage consisting of signal components in a wide frequency range from low to high frequencies of the detection signal Vm1 and output a peak voltage Vpeak1 according to the detection result, as well as to detect the peak voltage consisting of the high-frequency component of the detection signal Vm2 and output a peak voltage Vpeak2 according to the detection result.

[0092] Furthermore, by setting the resistance values ​​of the bandwidth adjustment elements 5c and 5d to different values ​​from those of the bandwidth adjustment elements 5a and 5b, the spectrum of the detection signal Vm2 can be adjusted to be different from that of the detection signal Vm1. For example, while the spectrum of the detection signal Vm1 can be made broad and flat from low to high frequencies, the spectrum of the detection signal Vm2 can be made to have a larger high-frequency component than the low-frequency component (however, the spectrum of the detection signal Vm2 is flatter than that of the output signal Vout). Therefore, by comparing the peak voltage Vpeak1 and the peak voltage Vpeak2, it is possible to estimate how much the low-frequency component of the detection signal Vm1 contributes to the peak voltage. Alternatively, for example, depending on the spectrum of the output signal Vout, either the peak voltage Vpeak1 or the peak voltage Vpeak2 can be selected and used. For example, when an optical modulator is driven by the output signal Vout, the peak voltage may be selected considering the response characteristics (frequency characteristics) of the optical signal to the drive signal of the optical modulator.

[0093] Next, with reference to Figure 6, an output circuit according to yet another embodiment will be described. Figure 6 is a diagram showing the circuit configuration of an output circuit according to yet another embodiment. The output circuit 1E shown in Figure 6 mainly differs from output circuit 1 in that it includes an ESD (Electro-Static Discharge) protection circuit 8 instead of a voltage divider circuit 4, and in the signal that is subject to bandwidth adjustment by the bandwidth adjustment elements 5a and 5b.

[0094] The ESD protection circuit 8 is a circuit for protecting the internal circuitry (e.g., the amplifier circuit 2) of the output circuit 1E from static electricity. The ESD protection circuit 8 is provided, for example, between the amplifier circuit 2 and the output terminals Tout1 and Tout2. Alternatively, the ESD protection circuit 8 may be provided between the inductors 3a and 3b and the output terminals Tout1 and Tout2. The ESD protection circuit 8 includes a potential generation circuit 81, diodes 82a, 82b, 83a, 83b, 84a, and 84b, and a clamp circuit 90.

[0095] The potential generation circuit 81 is a circuit that generates an intermediate potential between output terminal Tout1 and output terminal Tout2. The potential generation circuit 81 includes resistive elements 81a and 81b. Resistive elements 81a and 81b are connected in series with each other between output terminal Tout1 and output terminal Tout2. Specifically, one end of resistive element 81a is electrically connected to output terminal Tout1. The other end of resistive element 81a is electrically connected to one end of resistive element 81b. The other end of resistive element 81b is electrically connected to output terminal Tout2. The resistance value of resistive element 81a and the resistance value of resistive element 81b are substantially equal. The resistance values ​​of resistive elements 81a and 81b are, for example, 2kΩ to 20kΩ.

[0096] The potential generation circuit 81 generates an intermediate potential between output terminal Tout1 and output terminal Tout2 at the connection point X between the other end of resistor element 81a and one end of resistor element 81b. For example, if the reference potential of the output signal Vout is set to ground potential (0V), and the voltage of the positive-sequence component Voutp of the output signal Vout is the peak voltage and the voltage of the negative-sequence component Voutn of the output signal Vout is the bottom voltage, then the voltage at connection point X will be greater than the bottom voltage and less than the peak voltage. When ESD is not occurring (when the internal circuit of output circuit 1E is in a balanced state (unmodulated state) or when modulation operation is being performed), the intermediate potential is also called the output common-mode voltage. For example, when the resistance value of resistor element 81a and the resistance value of resistor element 81b are equal, the voltage at connection point X will be the average voltage of the positive-sequence component Voutp and the negative-sequence component Voutn.

[0097] Diodes 82a, 82b, 83a, 83b, 84a, and 84b are ESD protection diodes that protect the amplifier circuit 2 from static electricity. Diodes 82a and 83a are connected in series between connection point X and output terminal Tout1. Specifically, the cathode of diode 82a is electrically connected to connection point X. The anode of diode 82a is electrically connected to the cathode of diode 83a. The anode of diode 83a is electrically connected to output terminal Tout1.

[0098] Diodes 82b and 83b are connected in series between connection point X and output terminal Tout2. Specifically, the cathode of diode 82b is electrically connected to connection point X. The anode of diode 82b is electrically connected to the cathode of diode 83b. The anode of diode 83b is electrically connected to output terminal Tout2. Diodes 82a, 82b, 83a, and 83b are, for example, PN junction diodes formed in a P-type well. Diodes 82a, 82b, 83a, and 83b serve as the discharge path when a positive ESD voltage is generated at output terminals Tout1 and Tout2.

[0099] The cathode of diode 84a is electrically connected to output terminal Tout1. The anode of diode 84a is electrically connected to the ground wire GL. The cathode of diode 84b is electrically connected to output terminal Tout2. The anode of diode 84b is electrically connected to the ground wire GL. Diodes 84a and 84b are, for example, PN junction diodes formed in an N-type well. Diodes 84a and 84b serve as discharge paths when a negative ESD voltage is generated at output terminals Tout1 and Tout2.

[0100] The clamp circuit 90 is a circuit designed to prevent dielectric breakdown of the internal circuitry within the output circuit 1E by suppressing the rise in ESD potential at output terminals Tout1 and Tout2. When a positive ESD voltage is generated at connection point X, the clamp circuit 90 connects connection point X to ground potential via grounding wiring GL. The clamp circuit 90 employs a configuration in which circuit elements are selected and the circuit design is carried out to withstand the applied voltage during ESD protection operation. The clamp circuit 90 includes a detection circuit 91 and a switching circuit 92.

[0101] The detection circuit 91 is a circuit that detects the ESD voltage based on the intermediate potential described above. The detection circuit 91 includes a resistor 93, a capacitor 94, and MOS (Metal-Oxide-Semiconductor) transistors 95 and 96. The resistor 93 and the capacitor 94 are connected in series between the connection point X and the ground wire GL, forming a low-pass filter. Specifically, one end of the resistor 93 is electrically connected to the connection point X. The other end of the resistor 93 is electrically connected to one end of the capacitor 94. The other end of the capacitor 94 is electrically connected to the ground wire GL. For example, when a step-changing voltage pulse occurs at the connection point X as the ESD voltage, a voltage substantially equal to the voltage at the connection point X is generated at the connection point Y between the other end of the resistor 93 and one end of the capacitor 94 after a delay time of approximately the time constant determined by the product of the resistance of the resistor 93 and the capacitance of the capacitor 94.

[0102] MOS transistors 95 and 96 constitute an inverter circuit (inverting circuit). MOS transistor 95 is, for example, a P-type MOS transistor. MOS transistor 96 is, for example, an N-type MOS transistor. The source of MOS transistor 95 is electrically connected to connection point X. The source of MOS transistor 96 is electrically connected to the ground wire GL. The drains of MOS transistor 95 and MOS transistor 96 are electrically connected to each other at connection point Z. The gates of MOS transistor 95 and MOS transistor 96 are electrically connected to each other and further electrically connected to connection point Y.

[0103] In this inverter circuit, when a voltage is generated at connection point X and the voltage at connection point Y is lower than the threshold voltage of the inverter circuit, the MOS transistor 95 turns on, and the output at connection point Z of the inverter circuit becomes substantially equal to the voltage at connection point X. On the other hand, when the voltage at connection point Y is higher than the threshold voltage, the MOS transistor 96 turns on, and the output of the inverter circuit becomes substantially equal to the ground potential supplied to the grounding wiring GL. In this embodiment, the inverter circuit has a single-stage configuration, but it may have an odd-numbered configuration of three or more stages.

[0104] The switching circuit 92 is a circuit that turns on and off according to the output of the inverter circuit. The switching circuit 92 includes a MOS transistor 97. The MOS transistor 97 is, for example, an N-type MOS transistor. The drain of the MOS transistor 97 is electrically connected to connection point X. The source of the MOS transistor 97 is electrically connected to the ground wire GL. The gate of the MOS transistor 97 is electrically connected to connection point Z.

[0105] When the gate-source voltage of MOS transistor 97 is higher than the threshold voltage of MOS transistor 97, MOS transistor 97 operates in an ON state, lowering its drain-source resistance. Conversely, when the gate-source voltage of MOS transistor 97 is lower than the threshold voltage of MOS transistor 97, MOS transistor 97 operates in an OFF state, increasing its drain-source resistance. With this configuration, MOS transistor 97 functions by being triggered by the potential of connection point Y and switching in response to the potential of connection point X, connecting connection point X to ground potential with low resistance when the potential of connection point X rises.

[0106] Here, each of the diodes 82a, 82b, 83a, 83b, 84a, and 84b has parasitic capacitance. Therefore, at the connection point CP5 between the anode of diode 82a and the cathode of diode 83a, the potential difference between the potential of output terminal Tout1 and the intermediate potential is divided by the parasitic capacitance of diode 82a and the parasitic capacitance of diode 83a, generating the positive-sequence component Vdiv3p. Similarly, at the connection point CP6 between the anode of diode 82b and the cathode of diode 83b, the potential difference between the potential of output terminal Tout2 and the intermediate potential is divided by the parasitic capacitance of diode 82b and the parasitic capacitance of diode 83b, generating the negative-sequence component Vdiv3n. In other words, diodes 82a, 82b, 83a, and 83b constitute a voltage divider circuit, dividing the output signal Vout to generate a divided signal Vdiv3 (first divided signal) which includes a positive-sequence component Vdiv3p and a negative-sequence component Vdiv3n.

[0107] In this embodiment, the bandwidth adjustment elements 5a and 5b are circuit elements for adjusting the bandwidth of the voltage divider signal Vdiv3 to generate the detection signal Vm1. Specifically, bandwidth adjustment element 5a is used to adjust the bandwidth of the positive-sequence component Vdiv3p to generate the positive-sequence component Vm1p, and bandwidth adjustment element 5b is used to adjust the bandwidth of the negative-sequence component Vdiv3n to generate the negative-sequence component Vm1n.

[0108] The bandwidth adjustment element 5a is electrically connected between the connection point CP5 and the peak detection circuit 6. Specifically, one end of the bandwidth adjustment element 5a is electrically connected to the connection point CP5, and the other end of the bandwidth adjustment element 5a is electrically connected to the base of the transistor 61. The bandwidth adjustment element 5b is electrically connected between the connection point CP6 and the peak detection circuit 6. Specifically, one end of the bandwidth adjustment element 5b is electrically connected to the connection point CP6, and the other end of the bandwidth adjustment element 5b is electrically connected to the base of the transistor 62. The resistance values ​​of the bandwidth adjustment elements 5a and 5b are, for example, 1kΩ to 10kΩ.

[0109] A low-pass filter is formed by the bandwidth adjustment element 5a and the input capacitance of the peak detection circuit 6, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the positive-sequence component Vdiv3p are reduced, and the positive-sequence component Vm1p is generated. Similarly, a low-pass filter is formed by the bandwidth adjustment element 5b and the input capacitance of the peak detection circuit 6, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the negative-sequence component Vdiv3n are reduced, and the negative-sequence component Vm1n is generated.

[0110] The cutoff frequency of the low-pass filter can be increased or decreased by adjusting the resistance values ​​of the bandwidth adjustment elements 5a and 5b. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b lowers the cutoff frequency, and decreasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b raises the cutoff frequency. Therefore, adjusting the resistance values ​​of the bandwidth adjustment elements 5a and 5b increases or decreases the bandwidth of the detection signal Vm1. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b narrows the bandwidth, suppressing the high-frequency components due to high-frequency peaking of the voltage divider signal Vdiv3, and flattening the spectrum of the detection signal Vm1. Decreasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b widens the bandwidth, resulting in a spectrum of the detection signal Vm1 that is similar to the spectrum of the voltage divider signal Vdiv3, whose high-frequency components are amplified by high-frequency peaking.

[0111] In output circuit 1E, the same effects as output circuit 1 are achieved with the same configuration as output circuit 1. Furthermore, in output circuit 1E, the positive-sequence component Vdiv3p is generated by diodes 82a and 83a, and the negative-sequence component Vdiv3n is generated by diodes 82b and 83b. In this configuration, the output signal Vout can be divided using diodes 82a, 82b, 83a, and 83b, which are used for ESD protection. Therefore, there is no need to provide dedicated circuit elements for the voltage divider circuit, making it possible to reduce the circuit size of output circuit 1E.

[0112] Next, with reference to Figure 7, an output circuit according to yet another embodiment will be described. Figure 7 is a diagram showing the circuit configuration of an output circuit according to yet another embodiment. The output circuit 1F shown in Figure 7 mainly differs from the output circuit 1E in that it includes an ESD protection circuit 8F instead of the ESD protection circuit 8, and in the signal subject to bandwidth adjustment by the bandwidth adjustment elements 5a and 5b. The ESD protection circuit 8F mainly differs from the ESD protection circuit 8 in that it further includes diodes 85a and 85b.

[0113] Diodes 85a and 85b are ESD protection diodes that protect the amplifier circuit 2 from static electricity. The cathode of diode 85a is electrically connected to the anode of diode 84a. The anode of diode 85a is electrically connected to the ground wire GL. In other words, diodes 84a and 85a are connected in series between the output terminal Tout1 and the ground wire GL. The cathode of diode 85b is electrically connected to the anode of diode 84b. The anode of diode 85b is electrically connected to the ground wire GL. In other words, diodes 84b and 85b are connected in series between the output terminal Tout2 and the ground wire GL.

[0114] Here, each of the diodes 84a, 84b, 85a, and 85b has parasitic capacitance. Therefore, at the connection point CP7 between the anode of diode 84a and the cathode of diode 85a, the positive-sequence component Voutp is divided by the parasitic capacitances of diode 84a and diode 85a to generate the positive-sequence component Vdiv1p. Similarly, at the connection point CP8 between the anode of diode 84b and the cathode of diode 85b, the negative-sequence component Voutn is divided by the parasitic capacitances of diode 84b and diode 85b to generate the negative-sequence component Vdiv1n. In other words, diodes 84a, 84b, 85a, and 85b constitute a voltage divider circuit, dividing the output signal Vout to generate the divided voltage signal Vdiv1.

[0115] In this embodiment, the bandwidth adjustment elements 5a and 5b are circuit elements for adjusting the bandwidth of the voltage divider signal Vdiv1 to generate a detection signal Vm1. Specifically, bandwidth adjustment element 5a is used to adjust the bandwidth of the positive-sequence component Vdiv1p to generate the positive-sequence component Vm1p, and bandwidth adjustment element 5b is used to adjust the bandwidth of the negative-sequence component Vdiv1n to generate the negative-sequence component Vm1n.

[0116] The bandwidth adjustment element 5a is electrically connected between the connection point CP7 and the peak detection circuit 6. Specifically, one end of the bandwidth adjustment element 5a is electrically connected to the connection point CP7, and the other end of the bandwidth adjustment element 5a is electrically connected to the base of the transistor 61. The bandwidth adjustment element 5b is electrically connected between the connection point CP8 and the peak detection circuit 6. Specifically, one end of the bandwidth adjustment element 5b is electrically connected to the connection point CP8, and the other end of the bandwidth adjustment element 5b is electrically connected to the base of the transistor 62. The resistance values ​​of the bandwidth adjustment elements 5a and 5b are, for example, 1kΩ to 10kΩ.

[0117] A low-pass filter is formed by the bandwidth adjustment element 5a and the input capacitance of the peak detection circuit 6, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the positive-sequence component Vdiv1p are reduced, and the positive-sequence component Vm1p is generated. Similarly, a low-pass filter is formed by the bandwidth adjustment element 5b and the input capacitance of the peak detection circuit 6, so high-frequency components with frequencies higher than the cutoff frequency of the low-pass filter of the negative-sequence component Vdiv1n are reduced, and the negative-sequence component Vm1n is generated.

[0118] The cutoff frequency of the low-pass filter can be increased or decreased by adjusting the resistance values ​​of the bandwidth adjustment elements 5a and 5b. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b lowers the cutoff frequency, and decreasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b raises the cutoff frequency. Therefore, adjusting the resistance values ​​of the bandwidth adjustment elements 5a and 5b increases or decreases the bandwidth of the detection signal Vm1. For example, increasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b narrows the bandwidth, suppressing the high-frequency components due to high-frequency peaking of the voltage divider signal Vdiv1, and flattening the spectrum of the detection signal Vm1. Decreasing the resistance values ​​of the bandwidth adjustment elements 5a and 5b widens the bandwidth, resulting in a spectrum of the detection signal Vm1 that is similar to the spectrum of the voltage divider signal Vdiv1, where high-frequency components are amplified by high-frequency peaking.

[0119] In output circuit 1F, the same effects as output circuit 1E are achieved with the same configuration as output circuit 1E. Furthermore, in output circuit 1F, the positive-sequence component Vdiv1p is generated by diodes 84a and 85a, and the negative-sequence component Vdiv1n is generated by diodes 84b and 85b. In other words, capacitors 41 and 42 in output circuit 1 correspond to diodes 84a and 85a, respectively, and capacitors 43 and 44 correspond to diodes 84b and 85b, respectively. In this configuration as well, the output signal Vout can be divided using diodes 84a, 84b, 85a, and 85b, which are used for ESD protection. Therefore, since there is no need to provide dedicated circuit elements for the voltage divider circuit, it is possible to reduce the circuit size of output circuit 1F.

[0120] The output circuit relating to this disclosure is not limited to the embodiments described above.

[0121] In the above embodiment, bipolar transistors were used as transistors 21, 22, 23, 24, 61, 62, 71, and 72 for the explanation. However, transistors 21, 22, 23, 24, 61, 62, 71, and 72 may also be field-effect transistors (FETs). In that case, the base, emitter, and collector of the bipolar transistors are replaced with the gate, source, and drain, respectively. NPN bipolar transistors are replaced with N-channel FETs. When field-effect transistors are used as transistors 21, 22, 23, and 24, the amplifier circuit 2 is referred to as an open-drain type amplifier circuit.

[0122] In the above embodiment, the amplifier circuit 2 outputs the output signal Vout via inductors 3a and 3b, but it may also output a single-phase output signal. In this case, the output circuits 1, 1A, 1B, 1C, 1D, 1E, and 1F only need to have a single-phase circuit configuration. For example, in output circuit 1, the output terminal Tout2, inductor 3b, capacitors 43 and 44, bandwidth adjustment element 5b, and transistor 62 may be omitted. In that case, in order to stabilize the operation of transistor 23, the collector of transistor 23 may be connected to the power supply wiring PL via a load resistor. The resistance value of the load resistor may be the same as the resistance value of the external termination resistor connected to the output terminal Tout1.

[0123] Capacitors 41, 42, 43, 44, 45, 46, 47, and 48 may be composed of components, or they may be metal members such as electrodes and wiring formed on a semiconductor substrate, and may be composed of two metal members facing each other with an insulating layer in between. Referring to Figure 8, an example in which capacitors 41 and 42 are each composed of two metal members will be explained.

[0124] Figure 8 shows an example of the configuration of a voltage divider circuit. When the output circuit 1 is configured as an IC, the output circuit 1 includes a semiconductor substrate 11, an insulating layer 12 provided on the semiconductor substrate 11, multilayer wiring formed on the insulating layer 12, and an electrode pad 13. The semiconductor substrate 11 is, for example, a silicon substrate. The electrode pad 13 is a flat metal member provided on the semiconductor substrate 11 and functions as an output terminal Tout1. The insulating layer 12 has a wiring layer including a connecting line 14, a wiring layer including an electrode 15 (first metal member), and a wiring layer including a shielding wiring 16 (second metal member), which are arranged in that order from the output terminal Tout1 toward the semiconductor substrate 11. The insulating layer 12 may be composed of a plurality of insulating layers stacked from the semiconductor substrate 11 toward the electrode pad 13, and the wiring layer may be formed between these plurality of insulating layers.

[0125] The connecting line 14 is, for example, a wiring pattern that connects the output terminal Tout1 and the inductor 3a. The electrode 15 is a flat metal member provided on the semiconductor substrate 11 and functions as a connection point CP1. A wiring pattern 17 is connected to the electrode 15, which connects the electrode 15 to the band adjustment element 5a. The electrode 15 outputs a voltage divider signal Vdiv1 to the band adjustment element 5a via the wiring pattern 17. The shield wiring 16 is a flat metal member provided on the semiconductor substrate 11 and functions as a ground wiring GL. In other words, the ground wiring GL includes the shield wiring 16.

[0126] In the configuration shown in Figure 8, the electrode pad 13 and the electrode 15 are positioned facing each other. Therefore, the electrode pad 13 and the electrode 15 form a capacitor 41. More specifically, the electrode 15 is positioned facing the electrode pad 13 with an insulating layer in between. Thus, the capacitor 41 is composed of the electrode pad 13, the electrode 15, and the insulating layer sandwiched between the electrode pad 13 and the electrode 15. Similarly, the electrode 15 and the shield wiring 16 are positioned facing each other. Therefore, the electrode 15 and the shield wiring 16 form a capacitor 42. More specifically, the shield wiring 16 is positioned facing the electrode 15 with an insulating layer in between. Thus, the capacitor 42 is composed of the electrode 15, the shield wiring 16, and the insulating layer sandwiched between the electrode 15 and the shield wiring 16.

[0127] The capacitance C1 of capacitor 41 is set by adjusting the area of ​​electrode pad 13, the area of ​​electrode 15, and the distance between electrode pad 13 and electrode 15. Similarly, the capacitance C2 of capacitor 42 is set by adjusting the area of ​​electrode 15, the area of ​​shield wiring 16, and the distance between electrode 15 and shield wiring 16. As shown in equation (3), the capacitance Cpad of electrode pad 13 is obtained as the combined capacitance of capacitance C1 and capacitance C2.

number

[0128] In the above configuration, capacitances C1 and C2 are both, for example, approximately 100f to 400fF. In this case, capacitance Cpad is approximately 50f to 200fF. Note that if the area of ​​electrode 15 is smaller than the area of ​​electrode pad 13, equation (3) above may not be satisfied. To reduce the effect of parasitic capacitance of the wiring pattern 17, the bandwidth adjustment element 5a may be placed near electrode 15.

[0129] In the above configuration, since capacitors 41 and 42 do not need to be configured as dedicated electronic components, it is possible to reduce the circuit size of output circuit 1.

[0130] Capacitor 41 may be formed by an electrode pad 13 and an electrode 15, and capacitor 42 may be configured as an electronic component. Alternatively, capacitor 41 may be configured as an electronic component, and capacitor 42 may be formed by an electrode 15 and a shielding wire 16. In other words, at least one of capacitors 41 and 42 may be configured by an electrode 15 and an electrode pad 13 or a shielding wire 16. Other capacitors may be configured similarly to capacitors 41 and 42. Since it is not necessary to configure at least one of the capacitors as a dedicated electronic component, the circuit size of output circuit 1 can be reduced. The same configuration can be adopted in output circuits 1A, 1B, 1C, and 1D.

[0131] Next, the frequency characteristics of each part of the output circuit 1C will be described in detail with reference to Figure 9. Figure 9 shows the frequency characteristics of each signal in the output circuit shown in Figure 4. The unit of the vertical axis is decibels, with the voltage amplitude at a frequency of 1 GHz for each signal as the reference. The frequency characteristics were calculated for each signal: output signal Vout, voltage divider signal Vdiv1, detection signal Vm1, and voltage divider signal Vdiv2. The capacitance C1 of capacitor 41 was set to approximately 10 fF, the capacitance C3 of capacitor 43 to approximately 10 fF, the capacitance C5 of capacitor 45 to approximately 25 fF, the capacitance C6 of capacitor 46 to approximately 25 fF, the capacitance C7 of capacitor 47 to approximately 25 fF, and the capacitance C8 of capacitor 48 to approximately 25 fF. The resistance value R1 of the bandwidth adjustment element 5a was set to approximately 2 kΩ, and the resistance value R2 of the bandwidth adjustment element 5b was set to approximately 2 kΩ.

[0132] As shown in Figure 9, the output signal Vout, the voltage divider signal Vdiv1, and the voltage divider signal Vdiv2 have low signal strength (voltage amplitude) in the low frequency band (e.g., below 30 GHz) and a peak value at a frequency of approximately 53 GHz. Therefore, the peak detection circuit 7, to which the voltage divider signal Vdiv2 is input, can detect the peak voltage of the high-frequency component. On the other hand, the peak detection circuit 6, to which the detection signal Vm1 is input, has a flat signal strength (voltage amplitude) over a wide frequency band from 1 GHz to 50 GHz. Therefore, it can detect a peak voltage consisting of a spectrum flattened over a wide bandwidth from low to high frequencies. [Explanation of Symbols]

[0133] 1, 1A, 1B, 1C, 1D, 1E, 1F… Output Circuit 2…Amplifier circuit 3a...Inductor 3b...Inductor 4,4C...voltage divider circuit 5a, 5b... Bandwidth adjustment elements (first bandwidth adjustment element) 5c, 5d... Bandwidth adjustment elements (second bandwidth adjustment elements) 6…Peak detection circuit (first peak detection circuit) 7…Peak detection circuit (second peak detection circuit) 8,8F…ESD protection circuit 11… Semiconductor substrates 12…Insulating layer 13… Electrode pads 14…Connecting wires 15…Electrode (first metal component) 16…Shielded wiring (second metal component) 17…Wiring Pattern 21, 22, 23, 24… Transistors 25…Current source 41…Capacitor (first capacitive element) 42…Capacitor (second capacitive element) 43…Capacitor (first capacitive element) 44…Capacitor (second capacitive element) 45…Capacitor (third capacitive element) 46…Capacitor (fourth capacitive element) 47…Capacitor (third capacitive element) 48…Capacitor (fourth capacitive element) 61… Transistor 62... Transistors 63…Current source 64…Capacitor 71… Transistor 72... Transistors 73…Current source 74…Capacitor 81...Potential generation circuit 81a... Resistor element 81b... Resistor element 82a...diode 82b... Diode 83a...diode 83b... Diode 84a...diode 84b... Diode 85a...diode 85b... Diode 90... Clamp circuit 91...Detection circuit 92…Switching circuits 93... Resistor 94… Capacitor 95…MOS transistor 96…MOS transistor 97…MOS transistor CP1…Connection point CP2…Connection point CP3…Connection point CP4…Connection point CP5…Connection point CP6…Connection point CP7…Connection point CP8…Connection point GL…Ground wiring PL…Power wiring Tb... Bias supply terminal Tout1…Output terminal Tout2…Output terminal Tp1…Output terminal Tp2…Output terminal Vdiv1…Voltage divider signal (first voltage divider signal) Vdiv1n... Reverse-phase component Vdiv1p…Positive phase component Vdiv2…Voltage divider signal (second voltage divider signal) Vdiv2n... Reverse-phase component Vdiv2p…Positive phase component Vdiv3…Voltage divider signal (first voltage divider signal) Vdiv3n... Reverse-phase component Vdiv3p…Positive phase component Vm1…Detection signal (first detection signal) Vm1n...Reverse-phase component Vm1p…Positive phase component Vm2…Detection signal (second detection signal) Vm2n... Reverse-phase component Vm2p…Positive phase component Vinn... Reverse-phase component Vinp…Positive phase component VOUT…Output signal Voutn... Reverse-phase component Voutp…Positive phase component Vpeak1…Peak voltage (first peak voltage) Vpeak2…Peak voltage (second peak voltage) X...Connection point Y...Connection point Z...Connection point

Claims

1. Inductor and An amplification circuit that outputs an output signal via the aforementioned inductor, An output terminal for outputting the aforementioned output signal to the outside, A voltage divider circuit includes a first capacitive element and a second capacitive element connected in series with respect to the inductor and the output terminal, which divides the output signal between the first capacitive element and the second capacitive element to generate a first voltage divider signal. A first band adjustment element having a resistive component and adjusting the frequency characteristics of the first voltage divider signal to generate a first detection signal, A first peak detection circuit detects the peak voltage of the first detection signal and outputs a first peak voltage according to the detection result, An output circuit equipped with this feature.

2. The output circuit according to claim 1, further comprising a second peak detection circuit that outputs a second peak voltage in response to the first voltage divider signal.

3. The output circuit according to claim 2, wherein the second peak detection circuit detects the peak voltage of the first voltage divider signal and outputs the second peak voltage according to the detection result.

4. The system further comprises a second band adjustment element having a resistive component, which adjusts the frequency characteristics of the first voltage divider signal to generate a second detection signal, The output circuit according to claim 2, wherein the second peak detection circuit detects the peak voltage of the second detection signal and outputs the second peak voltage according to the detection result.

5. It further includes a second peak detection circuit that outputs a second peak voltage, The second capacitive element includes a third capacitive element and a fourth capacitive element connected in series. The voltage divider circuit divides the output signal using the first capacitive element, the third capacitive element, and the fourth capacitive element to generate a second divided voltage signal. The output circuit according to claim 1, wherein the second peak detection circuit outputs the second peak voltage in response to the second voltage divider signal.

6. The output circuit according to claim 5, wherein the second peak detection circuit detects the peak voltage of the second voltage divider signal and outputs the second peak voltage according to the detection result.

7. The system further includes a second band adjustment element having a resistive component, which adjusts the frequency characteristics of the second voltage divider signal to generate a second detection signal. The output circuit according to claim 5, wherein the second peak detection circuit detects the peak voltage of the second detection signal and outputs the second peak voltage according to the detection result.

8. It is further equipped with grounding wiring to supply ground potential, The output circuit according to any one of claims 1 to 7, wherein the first capacitive element and the second capacitive element are connected in series with each other between the output terminal and the grounding wire.

9. The output circuit according to any one of claims 1 to 8, wherein each of the first capacitive element and the second capacitive element is composed of an ESD protection diode.

10. Semiconductor substrate and A flat plate-shaped first metal member provided on the semiconductor substrate, Furthermore, The output terminal is an electrode pad provided on the semiconductor substrate, The grounding wiring includes a flat plate-shaped second metal member, The first metal member is positioned so as to face the electrode pad, The output circuit according to claim 8, wherein the first capacitive element is composed of the electrode pad and the first metal member.

11. The second metal member is positioned facing the first metal member, The output circuit according to claim 10, wherein the second capacitive element is composed of the first metal member and the second metal member.

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