AD conversion circuit

Abstract

To suppress a time difference in a conversion completion timing of an ADC within a desired range.SOLUTION: An AD conversion circuit comprises: a ΔΣAD converter 200-1 that has a ΔΣ modulator 300-1 and a digital filter 301-1; a ΔΣAD converter 200-2 that has a ΔΣ modulator 300-2 and a digital filter 301-2; a CPU 208 that outputs a conversion start request signal START_CPU at each measurement value acquisition cycle of the ΔΣAD converter 200-2; and a control unit 210 that operates the ΔΣAD converters 200-1 and 200-2 asynchronously in a normal mode, and sets the integration period of the digital filter 301-2 so that the conversion by the ΔΣAD converter 200-1 and the conversion by the ΔΣAD converter 200-2 are synchronized with each other within the measurement value acquisition cycle in a synchronous mode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to an AD conversion circuit. [Background technology]

[0002] The pressure transmitter is equipped with various sensors, including a differential pressure (DP) sensor, a high-pressure static pressure (STH) sensor, a low-pressure static pressure (STL) sensor, and a temperature (TEMP) sensor. The measured gauge pressure / absolute pressure (PV value) is calculated by performing AD conversion on the outputs of these sensors. To avoid the effects of aliasing during sampling, a dedicated AD converter (ADC: Analog-to-Digital Converter) is required for the DP signal necessary for this calculation, and AD conversion must be performed continuously. On the other hand, since continuous sampling is not required for the remaining STH, STL, and TEMP signals, a separate ADC is provided, and the system configuration uses a total of two ADCs, switching between the three inputs of STH, STL, and TEMP to perform AD conversion.

[0003] For products requiring high reliability, such as pressure transmitters, in addition to DP measurement for calculating PV value, STH, STL, and TEMP measurements for correction, as well as measurements to detect sensor and ADC failures, must also be performed during operation. Therefore, as described above, a two-channel ADC is prepared, with channel 1 ADC performing DP measurement, and channel 2 ADC performing STH, STL, and TEMP measurements for correction, DP measurement for sensor failure diagnosis (no inter-channel synchronization required), and DP measurement for ADC failure diagnosis (inter-channel synchronization required).

[0004] To correctly diagnose an ADC failure, it is necessary to use the same ADC settings as channel 1 and measure the DP (Diagram Processing Value) using channel 2 at approximately the same timing as channel 1. For example, if the DP acquisition period for channel 1's ADC is 50ms, the ADC for channel 2 must acquire the DP value within ±2% of that period (±1ms). If this time constraint is not met, fluctuations in the DP value may lead to a false positive diagnosis of ADC failure, even if the ADC is not actually faulty.

[0005] As mentioned above, continuous sampling is essential for the ADC of channel 1 to avoid the effects of aliasing. Therefore, in order to synchronize the acquisition of ADC values ​​for channel 1 and channel 2, two commercially available ADC chips (for example, TI's ADS1248 or Analog Devices' AD7176-2) with input terminals that allow external ADC conversion start requests to be specified are used.

[0006] Then, each chip is designated as channel 1 and channel 2, and when acquiring the DP value (DP SYNC) for ADC diagnostics on channel 2, the CPU (Central Processing Unit) performs a process in which it observes the conversion completion interrupt signal from channel 1 and generates a conversion start request signal for channel 2.

[0007] Figure 14 is a block diagram showing the configuration of a conventional AD conversion circuit, and Figures 15 and 16 are timing charts explaining the operation of the AD conversion circuit. Figure 16 shows the timing from time ts onwards in Figure 15. In the example in Figures 14 to 16, the measurement acquisition period of ADC100-1 on channel 1 is 50 ms, and the measurement acquisition period of ADC100-2 on channel 2 is 180 ms.

[0008] The CPU 102 receives a 50ms period timer interrupt signal INT_TIM_CH1 for channel 1 and a 180ms period timer interrupt signal INT_TIM_CH2 for channel 2 from timers 103 and 104. In response to the timer interrupt signal INT_TIM_CH1, the CPU 102 outputs a conversion start request signal START_CH1 to the ADC 100-1 for channel 1.

[0009] The ADC100-1 on channel 1 acquires the DP signal from the DP sensor in synchronization with the conversion start request signal START_CH1, performs AD conversion, and outputs the conversion completion interrupt signal INT_CH1 when the conversion is complete. In Figures 15 and 16, ADC_CH1 shows the output of the ADC100-1 on channel 1.

[0010] Furthermore, in response to the timer interrupt signal INT_TIM_CH2, the CPU 102 outputs a conversion start request signal START_CH2 to the ADC 100-2 on channel 2. The ADC100-2 on channel 2, in synchronization with the conversion start request signal START_CH2, sequentially acquires the STH, STL, TEMP, DP, and DP SYNC signals from the STH, STL, TEMP, and DP sensors, performs AD conversion, and outputs a conversion completion interrupt signal INT_CH2 when the conversion is complete.

[0011] To switch between the STH, STL, TEMP, DP, and DP SYNC signals, the output of multiplexer 101 is switched at a 180ms cycle. In Figures 15 and 16, ADC_CH2 shows the output of ADC100-2 on channel 2.

[0012] As described above, DP signal measurement is performed twice: once for sensor fault diagnosis (no inter-channel synchronization required) and once for ADC fault diagnosis (inter-channel synchronization required). In Figures 14 to 16, the DP value obtained for ADC fault diagnosis is shown as DP SYNC.

[0013] When the CPU 102 acquires DP SYNC, it needs to look at the conversion completion interrupt signal INT_CH1 of channel 1, output the conversion start request signal START_CH2 of channel 2, and align the acquisition timing of DP SYNC with the acquisition timing of DP of channel 1.

[0014] However, considering that the pressure transmitter has strict requirements for current consumption and it is necessary to operate the CPU at a frequency of 1 MHz or less, it was difficult to suppress the conversion completion timings of channel 1 and channel 2 within a time difference of ±2% (±1 ms) by the processing of the low-speed CPU.

[0015] Also, the inventor proposed a multi-channel ADC capable of multi-channel AD conversion with different periods (see Patent Document 1). In the multi-channel ADC disclosed in Patent Document 1, although synchronization between channels is possible, there is a constraint that the output period of each channel needs to be an integer multiple of the shortest period.

Prior Art Documents

Patent Documents

[0016]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0017] The present invention has been made to solve the above problems, and an object thereof is to provide an AD conversion circuit capable of suppressing the time difference between the conversion completion timings of the first AD converter and the second AD converter within a desired range.

Means for Solving the Problems

[0018] The AD conversion circuit of the present invention is characterized by comprising: a first ΔΣAD converter having a first ΔΣ modulator and a first digital filter, configured to convert a first analog input signal into a digital signal; a second ΔΣAD converter having a second ΔΣ modulator and a second digital filter, configured to convert a second analog input signal, which is the same as or different from the first analog input signal, into a digital signal; a CPU configured to output a conversion start request signal to the second ΔΣAD converter at each measurement acquisition cycle of the second ΔΣAD converter; and a control unit configured to operate the first and second ΔΣAD converters asynchronously in normal mode, and to set the integration period of the second digital filter so that the conversion by the first ΔΣAD converter and the conversion by the second ΔΣAD converter are synchronized within the measurement acquisition cycle in synchronous mode.

[0019] Furthermore, in one example of the AD conversion circuit of the present invention, the first ΔΣ AD converter is composed of a first ΔΣ modulator configured to convert the first analog input signal into a digital signal of a first frequency, and a first digital filter configured to convert the digital signal output from the first ΔΣ modulator into a digital signal of a second frequency lower than the first frequency and output it, and the second ΔΣ AD converter is composed of a second ΔΣ modulator configured to convert the second analog input signal into a digital signal of a first frequency, and a second digital filter configured to convert the digital signal output from the second ΔΣ modulator into a digital signal of a third frequency lower than the first frequency and output it. Furthermore, in one configuration example of the AD conversion circuit of the present invention, the control unit comprises a signal generation unit configured to set the integration periods of the first and second digital filters, a first timer configured to supply a clock of a second frequency with a period equal to the integration period of the first digital filter to the first digital filter, and a second timer configured to supply a clock of a third frequency with a period equal to the integration period of the second digital filter to the second digital filter, wherein the signal generation unit sets the integration periods of the first and second digital filters to the same value in the normal mode, and sets the length and timing of the integration period of the second digital filter so that the conversion by the first ΔΣAD converter and the conversion by the second ΔΣAD converter are synchronized within the measurement value acquisition period in the synchronous mode. Furthermore, one example configuration of the AD conversion circuit of the present invention is characterized in that, in synchronous mode, the lengths of one or more integration periods of the first digital filter and the lengths of multiple integration periods of the second digital filter are substantially the same.

[0020] Furthermore, the AD conversion circuit of the present invention is characterized by comprising: a first ΔΣAD converter having a first ΔΣ modulator, a first digital filter, and a second digital filter, configured to convert a first analog input signal into a digital signal; a second ΔΣAD converter having a second ΔΣ modulator and a third digital filter, configured to convert a second analog input signal, which is the same as or different from the first analog input signal, into a digital signal; a CPU configured to output a conversion start request signal to the second ΔΣAD converter at each measurement acquisition cycle of the second ΔΣAD converter; and a control unit configured to operate the first and second ΔΣAD converters asynchronously in normal mode, and in synchronous mode to synchronize the first and second ΔΣAD converters, to set the integration period of the second and third digital filters so that the conversion by the first ΔΣ modulator and the second digital filter and the conversion by the second ΔΣ modulator and the third digital filter are synchronized within the measurement acquisition cycle.

[0021] Furthermore, in one example configuration of the AD conversion circuit of the present invention, the first ΔΣ AD converter is composed of a first ΔΣ modulator configured to convert the first analog input signal into a digital signal of a first frequency, a first digital filter configured to convert the digital signal output from the first ΔΣ modulator into a digital signal of a second frequency lower than the first frequency and output it, and a second digital filter configured to convert the digital signal output from the first ΔΣ modulator into a digital signal of a third frequency lower than the first frequency and output it; and the second ΔΣ AD converter is composed of a second ΔΣ modulator configured to convert the second analog input signal into a digital signal of a first frequency, and a third digital filter configured to convert the digital signal output from the second ΔΣ modulator into a digital signal of a fourth frequency lower than the first frequency and output it. Furthermore, in one example configuration of the AD conversion circuit of the present invention, the control unit includes a signal generation unit configured to set the integration periods of the first, second, and third digital filters; a first timer configured to supply a clock of the second frequency, whose period is the integration period of the first digital filter, to the first digital filter; a second timer configured to supply a clock of the third frequency, whose period is the integration period of the second digital filter, to the second digital filter; and a third timer configured to supply a clock of the fourth frequency, whose period is the integration period of the third digital filter, to the third digital filter. The signal generation unit is composed of a timer and a signal generator, and in the normal mode, the signal generation unit sets the integration periods of the first and third digital filters to the same value and disables the setting of the integration period of the second digital filter to stop the clock output of the second timer, and in the synchronous mode, the signal generation unit sets the integration periods of the second and third digital filters to the same value and sets the length and timing of the integration periods of the second and third digital filters so that the conversion by the first ΔΣ modulator and the second digital filter and the conversion by the second ΔΣ modulator and the third digital filter are synchronized within the measurement value acquisition cycle.

[0022] Furthermore, in one example configuration of the AD conversion circuit of the present invention, the CPU specifies either the normal mode or the synchronous mode in synchronization with the conversion start request signal, and the control unit operates in the mode specified by the CPU. Furthermore, one example configuration of the AD conversion circuit of the present invention further comprises a multiplexer configured to selectively output one of the plurality of second analog input signals to the second ΔΣ AD converter, wherein the CPU outputs a control signal that specifies to the multiplexer the selection of one of the plurality of second analog input signals in synchronization with the conversion start request signal. Furthermore, in one example configuration of the AD conversion circuit of the present invention, the CPU outputs a control signal that sequentially designates a plurality of second analog input signals, and is characterized in that it enters synchronization mode when the first and second ΔΣAD converters are in the order in which they should synchronously acquire the same analog input signal. Furthermore, in one example configuration of the AD conversion circuit of the present invention, the CPU periodically outputs the conversion start request signal to the second ΔΣAD converter, always setting the conversion start request signal to the first ΔΣAD converter to a significant value, and the first ΔΣ modulator and the first digital filter of the first ΔΣAD converter continuously perform conversion operations in accordance with the conversion start request signal output from the CPU. [Effects of the Invention]

[0023] According to the present invention, in a synchronization mode for synchronizing the first and second ΔΣAD converters, a control unit is provided that sets the integration period of the second digital filter so that the conversion by the first ΔΣAD converter and the conversion by the second ΔΣAD converter are synchronized within the measurement acquisition cycle. This makes it possible to keep the time difference in the conversion completion timing between the first AD converter and the second AD converter within a desired range, even when using a low-speed CPU. Furthermore, the present invention eliminates the constraint on the output cycle between channels.

[0024] Furthermore, in the present invention, by providing a first ΔΣAD converter having a first ΔΣ modulator, a first digital filter, and a second digital filter, a second ΔΣAD converter having a second ΔΣ modulator and a third digital filter, and a control unit that sets the integration period of the second and third digital filters so that the conversion by the first ΔΣ modulator and the second digital filter and the conversion by the second ΔΣ modulator and the third digital filter are synchronized within the measurement acquisition cycle in a synchronization mode for synchronizing the first and second ΔΣAD converters, the time difference in the conversion completion timing between the first AD converter and the second AD converter can be kept within a desired range even when using a low-speed CPU. In addition, the present invention eliminates the constraint on the output cycle between channels. [Brief explanation of the drawing]

[0025] [Figure 1] Figure 1 is a block diagram showing the configuration of an AD conversion circuit according to a first embodiment of the present invention. [Figure 2] Figure 2 is a timing chart illustrating the operation of the AD conversion circuit according to the first embodiment of the present invention. [Figure 3] Figure 3 is a timing chart illustrating the operation of the AD conversion circuit according to the first embodiment of the present invention. [Figure 4] Figure 4 is a block diagram showing an example configuration of a digital filter for a ΔΣADC according to the first embodiment of the present invention. [Figure 5] Figure 5 is a block diagram showing an example configuration of a digital filter for a ΔΣADC according to the first embodiment of the present invention. [Figure 6] Figure 6 is a block diagram showing the configuration of a reference example of an AD conversion circuit. [Figure 7] Figure 7 is a timing chart illustrating the operation of the AD conversion circuit shown in Figure 6. [Figure 8] Figure 8 is a timing chart illustrating the operation of the AD conversion circuit shown in Figure 6. [Figure 9] Figure 9 is a timing chart illustrating the operation of an AD conversion circuit according to a second embodiment of the present invention. [Figure 10] Figure 10 is a timing chart illustrating the operation of an AD conversion circuit according to a second embodiment of the present invention. [Figure 11] Figure 11 is a block diagram showing the configuration of an AD conversion circuit according to a third embodiment of the present invention. [Figure 12] Figure 12 is a timing chart illustrating the operation of an AD conversion circuit according to a third embodiment of the present invention. [Figure 13] Figure 13 is a timing chart illustrating the operation of an AD conversion circuit according to a third embodiment of the present invention. [Figure 14] Figure 14 is a block diagram showing the configuration of a conventional AD conversion circuit. [Figure 15] Figure 15 is a timing chart illustrating the operation of a conventional AD conversion circuit. [Figure 16] Figure 16 is a timing chart illustrating the operation of a conventional AD conversion circuit. [Modes for carrying out the invention]

[0026] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing the configuration of an AD conversion circuit according to a first embodiment of the present invention. The AD conversion circuit of this embodiment includes a channel 1 ΔΣADC200-1 that converts a DP signal (first analog input signal) output from a DP sensor (not shown) into a digital signal, a channel 2 ΔΣADC200-2 that converts any of the signals (second analog input signal) from an STH sensor, STL sensor, TEMP sensor, or DP sensor (not shown) into a digital signal, and a multiplexer 201 that selectively outputs any of the STH signal, STL signal, TEMP signal, or DP signal to the ΔΣADC200-2.

[0027] Furthermore, the AD conversion circuit includes an interface section (SPI_IF) 202 for connection to the CPU, a signal generation section (STATE_CTRL) 203 that outputs reset signals RST_CH1 and RST_CH2 for ΔΣADC200-1 and 200-2 and sets the integration period of the digital filters of ΔΣADC200-1 and 200-2, and a ΔΣADC that selectively selects either the conversion start request signal output from the CPU or the conversion start request signal output from STATE_CTRL203. It consists of a multiplexer 204 that outputs to 200-2, a timer 205 that supplies clock DECIM_CH1 to ΔΣADC200-1 with a period equal to the integration period of the digital filter of ΔΣADC200-1, set from STATE_CTRL203, a timer 206 that supplies clock DECIM_CH2 to ΔΣADC200-2 with a period equal to the integration period of the digital filter of ΔΣADC200-2, set from STATE_CTRL203, and an MCU (Micro Control Unit) 207.

[0028] STATE_CTRL203, multiplexer 204, and timers 205 and 206 constitute the control unit 210. The MCU207 includes a CPU208 that controls the start / stop of ΔΣADC200-1 and 200-2 and reads the conversion results of ΔΣADC200-1 and 200-2, and a timer209 that measures the start interval of channel 2. The CPU208 executes the processing of this embodiment according to a program stored in its internal memory.

[0029] Figures 2 and 3 are timing charts illustrating the operation of the AD conversion circuit in this embodiment. Figure 3 shows the timing from time ts in Figure 2 onwards. In this embodiment, SPI (Serial Peripheral Interface) is used as the serial bus connecting ΔΣADC200-1, 200-2 and MCU207, 2 Other serial buses such as C may also be used. Furthermore, if the ΔΣADC200-1, 200-2 and MCU207 are integrated into a single chip, SPI or I 2Instead of using C, you can connect using an internal bus such as AMBA (Advanced Microcontroller Bus Architecture) defined by Arm, for example.

[0030] In this embodiment, the measurement acquisition period for ΔΣADC200-1 of channel 1 is set to 50 ms, and the measurement acquisition period for ΔΣADC200-2 of channel 2 is set to 180 ms.

[0031] The ΔΣADC200-1 consists of a ΔΣ modulator 300-1 that oversamples (40.96 kHz in this embodiment) an analog DP signal and performs AD conversion, and a digital filter 301-1 that outputs a digital signal from which the quantization noise of the ΔΣ modulator 300-1 has been removed by passing only the signal frequency band of the output signal of the ΔΣ modulator 300-1.

[0032] Similarly, the ΔΣADC200-2 consists of a ΔΣ modulator 300-2 that oversamples an analog input signal (one of the STH signal, STL signal, TEMP signal, or DP signal) and performs AD conversion, and a digital filter 301-2 that outputs a digital signal from which the quantization noise of the ΔΣ modulator 300-2 has been removed by passing only the signal frequency band of the output signal of the ΔΣ modulator 300-2.

[0033] Figures 4 and 5 are block diagrams showing example configurations of the digital filter 301-1. Digital filters for ΔΣADCs are called SINC filters or CIC filters, and the configuration of a third-order SINC filter is shown in Figure 4. The configuration of a fourth-order SINC filter is shown in Figure 5.

[0034] The digital filter 301-1 receives the oversampling clock CLK (sampling frequency f) input to the ΔΣ modulator 300-1. Soperates at (f = 40.96 kHz), and an integration calculation unit 302 with a plurality of cascaded connection configurations that integrates the data IN output from the ΔΣ modulator 300-1 for each sample, and a clock (sampling frequency f D = f S / N) that operates at a frequency of 1 / N (N is an integer of 2 or more) of the clock CLK, and samples the data of the sampling frequency f S output from the integration calculation unit 302 at the final stage at the sampling frequency f D and a frequency conversion unit 303 that decimates at the sampling frequency f D and operates at the clock of the sampling frequency f

[0035] Each integration calculation unit 302 includes an addition unit 306 that adds the data of the sampling frequency f S input to the integration calculation unit 302 and the integration result from the previous sample, and a delay unit 307 that delays the integration result output from the addition unit 306 by one sample (by the period of the clock CLK of the sampling frequency f S and inputs it to the addition unit 306. Thus, each integration calculation unit 302 integrates the data input to the integration calculation unit 302 for each clock of the sampling frequency f S .

[0036] The frequency conversion unit �03 turns on in synchronization with the clock of the sampling frequency f D and decimates (downsamples) the data, thereby converting the data of the sampling frequency f S output from the integration calculation unit 302 at the final stage to the data of the sampling frequency f D .

[0037] Each difference calculation unit 304 subtracts the data of the previous sample from the data of the sampling frequency f D input to the difference calculation unit 304 for one sample (by the period of the sampling frequency f DIt consists of a delay unit 308 that delays the data by the period of the clock, and a subtraction unit 309 that subtracts the output data of the delay unit 308 from the data input to the difference calculation unit 304. In this way, each difference calculation unit 304 subtracts the data from the previous sample from the data input to the difference calculation unit 304.

[0038] A ΔΣ ADC using the digital filter described above is disclosed, for example, in the document "H. Kuribayashi and T. Kajita, “Area-Efficient Decimation Filter with 50 / 60 Hz Power-Line Noise Suppression for ΔΣ A / D Converters”, SICE Journal of Control, Measurement, and System Integration, Vol.10, No.3, pp.165-169, 2017".

[0039] Figures 4 and 5 show the configuration of digital filter 301-1, but the configuration of digital filter 301-2 is the same as that of digital filter 301-1. As shown in Figures 4 and 5, the SINC filter has a sampling frequency f D =f S There is a delay unit 308 that operates at a clock of / N. Therefore, in the case of the third-order SINC filter shown in Figure 4, the output data latency is the sampling frequency f D The result is the clock period × N × 3. In the case of the 4th-order SINC filter shown in Figure 5, the output data latency is the sampling frequency f D The result is the clock period × N × 4. A 4th-order SINC filter requires a larger circuit area, but it can provide a steeper low-pass characteristic.

[0040] In Figures 4 and 5, the oversampling clock CLK is divided by N to obtain the sampling frequency f. D =f S The configuration for generating a clock of / N is described, but as will be explained later, in this embodiment, the sampling frequency fD The clock is supplied from timers 205 and 206.

[0041] Timer 209 of MCU207 outputs a 180ms period timer interrupt signal INT_TIM for channel 2 to CPU208.

[0042] CPU208 outputs a conversion start request signal START_CH1. As shown in Figures 2 and 3, CPU208 keeps the conversion start request signal START_CH1 at a significant value, "High," at all times. By keeping the conversion start request signal START_CH1 at "High" at all times in this way, the load on CPU208 can be reduced.

[0043] The ΔΣADC200-1 continues to perform AD conversion as long as the conversion start request signal START_CH1 is "High," and stops after the currently running AD conversion is completed when the conversion start request signal START_CH1 goes "Low." Furthermore, CPU208 outputs a conversion start request signal START_CPU in response to a timer interrupt signal INT_TIM with a period of 180ms.

[0044] For the ΔΣADC200-1 on channel 1, STATE_CTRL203 sets the reset signal RST_CH1 to "High" when the conversion start request signal START_CH1 becomes "High" during the initial startup. When the reset signal RST_CH1 becomes "High", the integrator constituting the ΔΣ modulator 300-1 of the ΔΣADC200-1 is reset, and the delay section (flip-flops) 307 and 308 of the digital filter 301-1 are also reset. When the reset signal RST_CH1 becomes "Low", the ΔΣADC200-1 is released from reset mode, and data conversion becomes possible.

[0045] STATE_CTRL203 sets the integration period of the digital filter 301-1 of ΔΣADC200-1 for timer 205, starting from when the reset signal RST_CH1 becomes "Low" and ΔΣADC200-1 is released from reset mode. The longer the integration period, the steeper the low-pass filter characteristics can be obtained. Here, the integration period is the sampling frequency f mentioned above. D =f S It is the reciprocal of / N.

[0046] In this embodiment, the integration period of the digital filter 301-1 of channel 1 is set to 50ms (N=2048). As set from STATE_CTRL203, timer 205 starts sampling at frequency f every 50ms from when the reset signal RST_CH1 becomes "Low". D The clock DECIM_CH1 at (=40.96kHz / 2048) is output to ΔΣADC200-1.

[0047] In this embodiment, the third-order SINC filter shown in Figure 4 is used as the digital filter 301-1 of the ΔΣADC200-1. The output data latency of the third-order SINC filter is the sampling frequency f D The clock period is × N × 3. Therefore, ΔΣADC200-1 can output the AD conversion result from the moment the reset signal RST_CH1 goes "Low" and the third pulse of the clock DECIM_CH1 is received.

[0048] The ΔΣADC200-1 acquires a DP signal from a DP sensor (not shown), performs AD conversion on the DP signal, and outputs the result of the AD conversion in synchronization with the clock DECIM_CH1. In Figures 2 and 3, ADC_CH1[23:0] shows the 24-bit output of the ΔΣADC200-1.

[0049] STATE_CTRL203 outputs a conversion completion interrupt signal INT_CH1 to CPU208 when the conversion is complete, synchronized with the third and subsequent pulses of the clock DECIM_CH1 after the reset signal RST_CH1 goes "Low".

[0050] Furthermore, CPU208 outputs the multiplexer control signals START_SEL and MUX_SEL via SPI_IF202 so that the STH, STL, and DP signals are sequentially converted to AD in sync with the timer interrupt signal INT_TIM from timer209.

[0051] Specifically, in the Normal Mode, which is a mode in which one of the STH, STL, or DP signals is acquired, meaning that there is no need to synchronize the ΔΣADC200-1 on channel 1 and the ΔΣADC200-2 on channel 2, the CPU208 sets the multiplexer control signal START_SEL to "Low" in synchronization with the conversion start request signal START_CPU, and outputs the multiplexer control signal MUX_SEL which specifies which of STH, STL, or DP to select.

[0052] At this time, CPU208, in synchronization with the conversion start request signal START_CPU, switches the specification by the multiplexer control signal MUX_SEL in the following order: STH → STL → DP (inter-channel synchronization required) → DP (inter-channel synchronization not required) → STH → ....

[0053] If the multiplexer control signal START_SEL output from CPU208 via SPI_IF202 is "Low", the multiplexer 204 outputs the conversion start request signal START_CPU output from CPU208 as the conversion start request signal START_CH2. The ΔΣADC200-2 starts up and performs AD conversion whenever the conversion start request signal START_CH2 becomes "High", and stops after the currently running AD conversion is completed when the conversion start request signal START_CH2 becomes "Low".

[0054] The multiplexer 201 selects one of the STH, STL, or DP signals and outputs it to the ΔΣADC200-2, based on the multiplexer control signal MUX_SEL output from the CPU 208 via SPI_IF202.

[0055] For channel 2's ΔΣADC200-2, the input is switched by the multiplexer 201, so it is necessary to reset the ΔΣADC200-2 before acquiring the signal. Therefore, STATE_CTRL203 sets the reset signal RST_CH2 to "High" in response to the conversion start request signal START_CPU output from CPU208. When the reset signal RST_CH2 is "High", the integrator constituting the ΔΣ modulator 300-2 of ΔΣADC200-2 is reset, and the delay section (flip-flops) 307 and 308 of the digital filter 301-2 are also reset. When the reset signal RST_CH2 is "Low", ΔΣADC200-2 is released from reset mode, and data conversion becomes possible.

[0056] For the ΔΣADC200-1 on channel 1, since it always converts the DP signal, STATE_CTRL203 only needs to set the reset signal RST_CH1 to "High" during the initial startup, as described above. In this embodiment, the assertion period for the reset signals RST_CH1 and RST_CH2 is set to 1 ms.

[0057] STATE_CTRL203 sets the integration period of the digital filter 301-2 of ΔΣADC200-2 for timer 206, starting from when the reset signal RST_CH2 becomes "Low" and ΔΣADC200-2 is released from reset mode.

[0058] In this embodiment, the integration period of the digital filter 301-2 of channel 2 in Normal Mode is set to 50ms (N=2048). Based on the settings from STATE_CTRL203, the timer 206 starts sampling at frequency f every 50ms from the moment the reset signal RST_CH2 goes "Low". D The clock signal DECIM_CH2 (=40.96kHz / 2048) is output to ΔΣADC200-2.

[0059] In this embodiment, the third-order SINC filter shown in Figure 4 is used as the digital filter 301-2 of the ΔΣADC200-2. The output data latency of the third-order SINC filter is the sampling frequency f D The clock period is × N × 3. Therefore, the ΔΣADC200-2 can output the AD conversion result from the moment the third pulse of the clock DECIM_CH2 is received after the reset signal RST_CH2 goes "Low".

[0060] The ΔΣADC200-2 takes one of the STH, STL, or DP signals via the multiplexer 201, performs AD conversion on the signal, and outputs the result of the AD conversion synchronized with the clock DECIM_CH2. In Figures 2 and 3, ADC_CH2[23:0] shows the 24-bit output of the ΔΣADC200-2. Note that in Figure 2, for simplicity, only an example of STL signal acquisition is shown.

[0061] STATE_CTRL203 outputs a conversion completion interrupt signal INT_CH2 to CPU208 when the conversion is complete, synchronized with the third and subsequent pulses of the clock DECIM_CH2 after the reset signal RST_CH2 goes "Low".

[0062] Next, as shown in Figure 3, when the CPU 208 is in sync mode, which is the mode for acquiring DP SYNC, i.e., when it is necessary to synchronize ΔΣADC200-1 on channel 1 and ΔΣADC200-2 on channel 2, the CPU 208 sets the multiplexer control signal START_SEL to "High" in synchronization with the conversion start request signal START_CPU, and outputs the multiplexer control signal MUX_SEL which specifies DP as the target for selection.

[0063] When STATE_CTRL203 receives a conversion start request signal START_CPU from CPU208 when the multiplexer control signal START_SEL output from CPU208 via SPI_IF202 is "High", it generates a conversion start request signal START_ST in synchronization with the clock DECIM_CH1 of channel 1's ΔΣADC200-1. Since the clock DECIM_CH1 is generated by the settings from STATE_CTRL203, it is possible to set the conversion start request signal START_ST to "High" in synchronization with the clock DECIM_CH1.

[0064] When the conversion start request signal START_ST is output from STATE_CTRL203, CPU208 resets the multiplexer control signal START_SEL from "High" to "Low".

[0065] When the multiplexer control signal START_SEL is "High", STATE_CTRL203 outputs a conversion start request signal START_CPU from CPU208, and after the reset signal RST_CH2 becomes "Low", it sets the length of the integration period and timing of the digital filter 301-2 of ΔΣADC200-2 to timer 206 so that the conversion by ΔΣADC200-1 and the conversion by ΔΣADC200-2 are synchronized. STATE_CTRL203 can detect when the multiplexer control signal START_SEL has become "High" via SPI_IF202.

[0066] In this embodiment, the integration period of the digital filter 301-2 of channel 2 in Sync Mode is set to 33.3ms (N=1364). As set from STATE_CTRL203, the timer 206 starts sampling at frequency f every 33.3ms from the time the conversion start request signal START_ST becomes "High". D The clock signal DECIM_CH2 (=40.96kHz / 1364) is output to ΔΣADC200-2.

[0067] As described above, the ΔΣADC200-2 can output the AD conversion result from the moment it receives the third pulse of the clock DECIM_CH2 after the reset signal RST_CH2 has gone "Low".

[0068] If the multiplexer control signal START_SEL output from CPU208 via SPI_IF202 is "High", multiplexer204 outputs the conversion start request signal START_ST output from STATE_CTRL203 as the conversion start request signal START_CH2.

[0069] Multiplexer 201 selects a DP signal according to the multiplexer control signal MUX_SEL output from CPU 208 via SPI_IF202 and outputs it to ΔΣADC200-2.

[0070] The ΔΣADC200-2 takes in the DP signal via the multiplexer 201, performs AD conversion on the signal, and outputs the result of the AD conversion in synchronization with the clock DECIM_CH2. STATE_CTRL203 outputs a conversion completion interrupt signal INT_CH2 to CPU208 when the conversion is complete, synchronized with the third and subsequent pulses of the clock DECIM_CH2 after the reset signal RST_CH2 goes "Low".

[0071] Through the above operations, in this embodiment, the data is acquired in the order STH → STL → DP SYNC → DP → STH → ... and then converted to AD. The duration for which the multiplexer control signal MUX_SEL specifies STH and STL is 180ms each (the period of INT_TIM and START_CPU). On the other hand, since the DP signal needs to be captured twice in a row, as can be seen from Figure 3, the duration for which the multiplexer control signal MUX_SEL specifies DP is 2 × 180ms.

[0072] In pressure transmitters, high-precision acquisition of the DP signal is required, so for channel 1, this is addressed by extending the integration period of the digital filter 301-1. However, since the acquisition of the DP signal in synchronous mode is for fault diagnosis, high-precision AD conversion results are not required. Therefore, in this embodiment, the integration period of the digital filter 301-2 for channel 2 in synchronous mode is set to 33.3 ms (N=1364), and the integration period of the digital filter 301-2 in normal mode is set to 50 ms (N=2048).

[0073] This allows the output data latency of ΔΣADC200-2 in synchronous mode to be 100ms (≒33.3ms × 3). By setting the conversion start request signal START_ST to "High" in synchronization with the channel 1 clock DECIM_CH1, and outputting pulses of clock DECIM_CH2 to ΔΣADC200-2 every 33.3ms from the time the conversion start request signal START_ST is set to "High", the conversion completion timings of ΔΣADC200-1 and ΔΣADC200-2 can be synchronized in synchronous mode, as shown by the timing of the dashed line 400 in Figure 3. This allows the time difference in the conversion completion timings of ΔΣADC200-1 and ΔΣADC200-2 to be kept within a desired range (e.g., ±1ms). Furthermore, this embodiment eliminates the constraints on the output period between channels, as seen in the multi-channel ADC disclosed in Patent Document 1.

[0074] The inventor previously proposed an AD conversion circuit that can keep the time difference between the conversion completion timings of the first ADC and the second ADC within a desired range (Japanese Patent Application No. 2021-119469). The configuration of this AD conversion circuit is shown in Figure 6. Figures 7 and 8 are timing charts illustrating the operation of the AD conversion circuit in Figure 6. Figure 8 shows the timing from time ts in Figure 7 onwards.

[0075] The ADC212-1 continuously outputs the AD conversion result of the DP signal at a predetermined output data rate (50ms). Meanwhile, the ADC212-2 receives one of the STH, STL, or DP signals via the multiplexer 201 in synchronization with the conversion start request signal START_CH2 output from the multiplexer 204, and performs A / D conversion on the signal.

[0076] In the AD conversion circuit shown in Figure 6, in normal mode, the conversion start request signal START_CPU is transmitted to ADC212-2 via multiplexer 204, and in synchronous mode, the conversion start request signal START_ST is transmitted to ADC212-2 so that ADC212-1 and ADC212-2 are synchronized.

[0077] The AD conversion circuit in Figure 6 does not assume the use of a ΔΣADC, but when considering applying the AD conversion circuit to a pressure oscillator, it is desirable to adopt a ΔΣADC that can perform AD conversion with high precision. However, if ΔΣADCs are used as ADC212-1 and ADC212-2, the data output latency of the DP SYNC value becomes 200ms in the worst case, which exceeds the assumed measurement period of channel 2, which is 180ms.

[0078] For example, in the example shown in Figure 8, acquiring DP SYNC takes more than 180ms, and as shown by the dashed line 401 in Figure 8, the next conversion start request signal START_CPU is received from CPU 208 before acquiring DP SYNC. Therefore, the acquisition of DP SYNC is not completed before the AD conversion of the next DP signal begins.

[0079] On the other hand, in this embodiment, by setting the integration period of the digital filter 301-2 for channel 2 in synchronous mode to 33.3ms, the data output latency of the ΔΣADC200-2 when acquiring the DP SYNC value can be kept to 100ms. Therefore, regardless of the timing of the AD conversion request for channel 2 from the CPU 208 (START_CPU), it is possible to acquire the DP SYNC value within the acquisition period of channel 2, which is 180ms. As a result, in this embodiment, it is possible to prevent the occurrence of receiving the next conversion start request signal START_CPU while the digital filter processing for generating the DP SYNC value is being executed.

[0080] In this embodiment, we describe an example where signals are acquired and converted to AD in the order STH→STL→DP SYNC→DP→STH→..., but as with conventional technology, TEMP may be added as a target for selection in channel 2 in normal mode. In addition, if there are other signals that you would like to acquire on channel 2 besides STH, STL, TEMP, DP, and DP SYNC, you can add them as appropriate. Conversely, it is also possible to reduce the number of signals that do not need to be acquired. For example, in this embodiment, two signals, STH and STL, are acquired from the static pressure sensor, but it is also acceptable to acquire only one.

[0081] [Second Example] In the first embodiment, the data output latency of ΔΣADC200-2 when acquiring the DP SYNC value was set to 100ms by setting the integration period of the digital filter 301-2 of channel 2 in synchronous mode to 33.3ms (N=1364). However, in the configuration of the first embodiment, STATE_CTRL203 may be set to 16.6ms (N=682) for the integration period of the digital filter 301-2 in synchronous mode. This makes it possible to set the data output latency of ΔΣADC200-2 when acquiring the DP SYNC value to 50ms (≒16.6ms × 3). The operation in this case is shown in Figures 9 and 10. Figure 10 shows the timing after time ts in Figure 9.

[0082] By setting the integration period of the digital filter 301-2 in synchronous mode to 16.6ms (N=682), setting the conversion start request signal START_ST to "High" in synchronization with the channel 1 clock DECIM_CH1, and outputting pulses of the clock DECIM_CH2 to ΔΣADC200-2 every 16.6ms from the time the conversion start request signal START_ST is set to "High", the conversion completion timing of ΔΣADC200-1 and ΔΣADC200-2 can be synchronized in synchronous mode, as shown by the timing of the dashed line 402 in Figure 10.

[0083] In this embodiment, the data output latency of the ΔΣADC200-2 when acquiring DP Sync values ​​can be reduced to 100ms in the worst-case scenario. In other words, in this embodiment, the measurement acquisition cycle of the ΔΣADC200-2 for channel 2, which was set to 180ms, can be further shortened, and the number of times channel 2 can be executed can be increased.

[0084] In the first embodiment, an example is described in which the data is acquired and converted in the order of STH→STL→DP SYNC→DP→STH→·····. However, in this embodiment, the measurement acquisition period of ΔΣADC200-2 can be shortened, making it easier to add TEMP as a target for selection of channel 2 in normal mode.

[0085] Furthermore, if the measurement acquisition cycle of the ΔΣADC200-2 can be shortened, it will be possible to further increase the number of signals that can be converted by the ΔΣADC200-2 (input signals to the multiplexer 201). For example, by connecting the ADC's reference voltage as the input to the multiplexer 201 and performing AD conversion on the reference voltage, it can be used for fault diagnosis of the multiplexer 201 and the ΔΣADC200-2. In this case, since the AD conversion is performed on a reference voltage whose expected value is clear, fault diagnosis of the multiplexer 201 and the ΔΣADC200-2 can be performed by comparing the acquired AD conversion result with the expected value.

[0086] [Third embodiment] Next, a third embodiment of the present invention will be described. Figure 11 is a block diagram showing the configuration of an AD conversion circuit according to the third embodiment of the present invention. The AD conversion circuit of this embodiment consists of a ΔΣADC200a-1, a ΔΣADC200-2, a multiplexer 201, an interface unit (SPI_IF) 202, a signal generation unit (STATE_CTRL) 203a, timers 205 and 206, an MCU 207, and a timer 211 that supplies a clock DECIM_CH1_SYNC to the ΔΣADC200-1, with a period equal to the integration period of the second digital filter of the ΔΣADC200-1, based on settings from STATE_CTRL203a. STATE_CTRL203a and timers 205, 206, and 211 constitute the control unit 210a.

[0087] Figures 12 and 13 are timing charts illustrating the operation of the AD conversion circuit in this embodiment. Figure 13 shows the timing from time ts in Figure 12 onwards. The conversion start request signal START_CH2 in Figures 11 to 13 is the same signal as the conversion start request signal START_CPU described in the first embodiment.

[0088] In this embodiment, the ΔΣADC200a-1 of channel 1 includes a ΔΣ modulator 300-1 and a digital filter 301-1, as well as a digital filter 310 for synchronization acquisition. Similar to digital filter 301-1, digital filter 310 outputs a digital signal from which the quantization noise of ΔΣ modulator 300-1 has been removed by allowing only the signal frequency band of the output signal of ΔΣ modulator 300-1 to pass through. The difference from digital filter 301-1 is that it operates using the clock DECIM_CH1_SYNC supplied from timer 211 and is reset by the reset signal RST_CH2 of channel 2.

[0089] The operation of the AD conversion circuit in normal mode is the same as in the first embodiment, so a detailed explanation is omitted. However, in normal mode, STATE_CTRL203a disables the setting of the integration period of the digital filter 310 for the timer 211. Therefore, in normal mode, the clock DECIM_CH1_SYNC is not output from the timer 211, and thus the AD conversion result is not output from the digital filter 301-1.

[0090] In Figures 11 to 13, ADC_CH1_SYNC[23:0] shows the 24-bit output of digital filter 310. ADC_CH1[23:0] shows the 24-bit output of digital filter 301-1, similar to the first embodiment.

[0091] Next, STATE_CTRL203a sets the reset signal RST_CH2 to "High" in response to the conversion start request signal START_CH2 (START_CPU) output from CPU208, similar to the first embodiment. When the reset signal RST_CH2 becomes "High", the integrator constituting the ΔΣ modulator 300-2 of ΔΣADC200-2 is reset, and the delay sections (flip-flops) 307 and 308 of the digital filters 301-2 and 310 are also reset.

[0092] Then, STATE_CTRL203a sets the length of the integration period and timing of the digital filters 301-2 and 310 to timers 206 and 211 so that the conversion by the ΔΣ modulator 300-1 and digital filter 310 and the conversion by the ΔΣ modulator 300-2 and digital filter 301-2 are synchronized, starting from when the reset signal RST_CH2 becomes "Low" in synchronous mode and the digital filters 301-2 and 310 are released from reset mode. The operation of timer 205 based on the settings from STATE_CTRL203a is the same as in the first embodiment. Whether it is in synchronous mode or normal mode can be confirmed by notification from CPU 208 via SPI_IF202.

[0093] In this embodiment, the integration period for digital filters 301-1, 301-2, and 310 is set to 50ms (N=2048). Based on the settings from STATE_CTRL203a, timers 206 and 211 start sampling at frequency f every 50ms from the moment the reset signal RST_CH2 goes "Low" in synchronous mode. D The clock signals DECIM_CH2 and DECIM_CH1_SYNC (=40.96kHz / 2048) are output to digital filters 301-2 and 310.

[0094] In this embodiment, a third-order SINC filter shown in Figure 4 is used as the digital filter 310. The output data latency of the third-order SINC filter is the sampling frequency f D This is the clock period × N × 3. Therefore, the digital filter 310 can output the AD conversion result from the moment it receives the third pulse of the clock DECIM_CH1_SYNC after the reset signal RST_CH2 goes "Low".

[0095] Thus, the ΔΣADC200a-1 can, in synchronous mode, acquire the DP signal, perform AD conversion on the signal, and output the result of the AD conversion (DP of ADC_CH1[23:0]) from the digital filter 301-1 in synchronization with the clock DECIM_CH1. In addition, it can also output the result of the AD conversion (DP SYNC of ADC_CH1_SYNC[23:0]) from the digital filter 310 in synchronization with the clock DECIM_CH1_SYNC.

[0096] In the first embodiment, the integration period of the digital filter 301-2 for channel 2 in synchronous mode was set to 33.3 ms (N=1364), but in this embodiment, the integration period for channel 2 is always 50 ms (N=2048).

[0097] Furthermore, in the first embodiment, based on the settings from STATE_CTRL203, the timer 206 starts sampling at a sampling frequency f every 33.3 ms from the time the conversion start request signal START_ST becomes "High" in synchronous mode.D The clock signal DECIM_CH2 (=40.96kHz / 1364) is output to ΔΣADC200-2.

[0098] On the other hand, in this embodiment, according to the settings from STATE_CTRL203a, the timer 206 starts sampling at a sampling frequency f every 50ms from the time the reset signal RST_CH2 goes "Low" in synchronous mode. D The clock signal DECIM_CH2 (=40.96kHz / 2048) is output to ΔΣADC200-2.

[0099] The ΔΣADC200-2 can output the AD conversion result from the moment it receives the third pulse of the clock DECIM_CH2 after the reset signal RST_CH2 goes "Low". The STATE_CTRL203a outputs the conversion completion interrupt signal INT_CH2 to the CPU208 in synchronization with the third and subsequent pulses of the clock DECIM_CH2 after the reset signal RST_CH2 goes "Low" when the conversion is complete.

[0100] Thus, in this embodiment, as shown by the timing indicated by the dashed line 403 in Figure 13, the conversion completion timing of ΔΣADC200a-1 and ΔΣADC200-2 can be synchronized in synchronous mode. In the first and second embodiments, the DP value for measurement was acquired on channel 1 and the DP SYNC value for ADC diagnosis was acquired on channel 2 in synchronous mode, but in this embodiment, the DP SYNC value is acquired on channel 1 and the DP value for measurement is acquired on channel 2 in synchronous mode.

[0101] In the first and second embodiments, the operating timing of the ΔΣADC200-2 of channel 2 was controlled. However, in this embodiment, a digital filter 310 for synchronization acquisition is provided inside the ΔΣADC200a-1 of channel 1, and by operating the digital filter 310 at the same timing as channel 2, it is possible to acquire AD conversion values ​​at the same timing for both channel 1 and channel 2.

[0102] In this embodiment, an additional digital filter 310 is required, but since the integration period of the digital filter can be made the same for channel 1 and channel 2, AD conversion values ​​with equivalent accuracy can be obtained for channel 1 and channel 2.

[0103] In the first to third embodiments, third-order SINC filters are used as digital filters 301-1, 301-2, and 310, but fourth-order SINC filters may also be used. When a fourth-order SINC filter is used, the output data latency of the ΔΣADC is the sampling frequency f D It is the clock period × N × 4.

[0104] When a fourth-order SINC filter is used, digital filters 301-1, 301-2, and 310 can output the AD conversion result from the moment they receive the fourth pulse of the clock DECIM_CH1, DECIM_CH2, and DECIM_CH1_SYNC after a reset.

[0105] A fourth-order SINC filter has a steeper low-pass characteristic than a third-order SINC filter, which can improve the accuracy of AD conversion values. However, this comes at the cost of an increased digital filter area and increased output data latency.

[0106] Furthermore, although the processing of the AD conversion results output from ΔΣADC200-1,200a-1,200-2 is not described in the first to third embodiments, in the present invention, means for processing the AD conversion results are not an essential component. For example, the AD conversion results can be transferred to the CPU208 via SPI_IF202. In this case, individual IDs may be added to the AD conversion results before transfer. These processes are disclosed in Patent Document 1. Needless to say, the means for processing the AD conversion results are not limited to the configuration disclosed in Patent Document 1.

[0107] Furthermore, the present invention is not limited to pressure transmitters, but can also be applied to devices other than pressure transmitters. [Industrial applicability]

[0108] This invention can be applied to a technology for performing AD conversion of multiple channels of analog input signals. [Explanation of symbols]

[0109] 200-1, 200a-1, 200-2…ΔΣADC, 201, 204…Multiplexer, 202…Interface unit, 203, 203a…Signal generation unit, 205, 206, 209, 211…Timer, 207…MCU, 208…CPU, 210, 210a…Control unit, 300-1, 300-2…ΔΣ modulator, 301-1, 301-2, 310…Digital filter, 302…Integration calculation unit, 303…Frequency conversion unit, 304…Difference calculation unit, 306…Addition unit, 307, 308…Delay unit, 309…Subtraction unit.

Claims

1. A first ΔΣ AD converter having a first ΔΣ modulator and a first digital filter, configured to convert a first analog input signal into a digital signal, A second ΔΣ AD converter comprising a second ΔΣ modulator and a second digital filter, configured to convert a second analog input signal, which is the same as or different from the first analog input signal, into a digital signal; A CPU configured to output a conversion start request signal to the second ΔΣAD converter at each measurement acquisition cycle of the second ΔΣAD converter, An AD conversion circuit characterized by comprising a control unit configured to set the integration period of the second digital filter so that the conversion by the first ΔΣAD converter and the conversion by the second ΔΣAD converter are synchronized within the measurement value acquisition period in a normal mode in which the first and second ΔΣAD converters are operated asynchronously, and in a synchronous mode in which the first and second ΔΣAD converters are synchronized.

2. In the AD conversion circuit according to claim 1, The first ΔΣ AD converter is, A first ΔΣ modulator configured to convert the first analog input signal into a digital signal of a first frequency, It consists of a first digital filter configured to convert the digital signal output from the first ΔΣ modulator into a digital signal of a second frequency lower than the first frequency and output it, The second ΔΣ AD converter described above is The second ΔΣ modulator is configured to convert the second analog input signal into a digital signal of the first frequency, An AD conversion circuit characterized by comprising a second digital filter configured to convert the digital signal output from the second ΔΣ modulator into a digital signal of a third frequency lower than the first frequency and output it.

3. In the AD conversion circuit according to claim 2, The control unit, A signal generation unit configured to set the integration period of the first and second digital filters, A first timer configured to supply the first digital filter with a clock having a second frequency whose period is the integration period of the first digital filter, It consists of a second timer configured to supply the second digital filter with a clock having a third frequency whose period is the integration period of the second digital filter, The signal generation unit is characterized in that, in the normal mode, the integration periods of the first and second digital filters are set to the same value, and in the synchronous mode, the length and timing of the integration period of the second digital filter are set so that the conversion by the first ΔΣ AD converter and the conversion by the second ΔΣ AD converter are synchronized within the measurement value acquisition period.

4. In the AD conversion circuit according to claim 3, An AD conversion circuit characterized in that, in synchronous mode, the lengths of one or more integration periods of the first digital filter and the lengths of multiple integration periods of the second digital filter are substantially the same.

5. A first ΔΣ AD converter having a first ΔΣ modulator, a first digital filter, and a second digital filter, configured to convert a first analog input signal into a digital signal, A second ΔΣ AD converter having a second ΔΣ modulator and a third digital filter, configured to convert a second analog input signal, which is the same as or different from the first analog input signal, into a digital signal; A CPU configured to output a conversion start request signal to the second ΔΣAD converter at each measurement acquisition cycle of the second ΔΣAD converter, An AD conversion circuit characterized in that, in normal mode, the first and second ΔΣ AD converters are operated asynchronously, and in synchronous mode, the first and second ΔΣ AD converters are operated in synchronous mode, the circuit includes a control unit configured to set the integration period of the second and third digital filters so that the conversion by the first ΔΣ modulator and the second digital filter and the conversion by the second ΔΣ modulator and the third digital filter are synchronized within the measurement acquisition period.

6. In the AD conversion circuit according to claim 5, The first ΔΣ AD converter is, A first ΔΣ modulator configured to convert the first analog input signal into a digital signal of a first frequency, The first digital filter is configured to convert the digital signal output from the first ΔΣ modulator into a digital signal of a second frequency lower than the first frequency and output it, It consists of a first ΔΣ modulator and a second digital filter configured to convert the digital signal output from the first ΔΣ modulator into a digital signal of a third frequency lower than the first frequency and output it, The second ΔΣ AD converter described above is The second ΔΣ modulator is configured to convert the second analog input signal into a digital signal of the first frequency, An AD conversion circuit characterized by comprising a third digital filter configured to convert the digital signal output from the second ΔΣ modulator into a digital signal of a fourth frequency lower than the first frequency and output it.

7. In the AD conversion circuit according to claim 6, The control unit, A signal generation unit configured to set the integration period of the first, second, and third digital filters, A first timer configured to supply the first digital filter with a clock having a second frequency whose period is the integration period of the first digital filter, A second timer configured to supply the second digital filter with a clock of the third frequency having a period equal to the integration period of the second digital filter, It consists of a third timer configured to supply the third digital filter with a clock having a fourth frequency whose period is the integration period of the third digital filter, The signal generation unit is characterized in that, in the normal mode, it sets the integration periods of the first and third digital filters to the same value and disables the setting of the integration period of the second digital filter to stop the clock output of the second timer, and in the synchronous mode, it sets the integration periods of the second and third digital filters to the same value and sets the length and timing of the integration periods of the second and third digital filters so that the conversion by the first ΔΣ modulator and the second digital filter and the conversion by the second ΔΣ modulator and the third digital filter are synchronized within the measurement value acquisition cycle.

8. In the AD conversion circuit according to any one of claims 1 to 7, The CPU, in synchronization with the conversion start request signal, specifies either the normal mode or the synchronous mode. The control unit is characterized by operating in a mode specified by the CPU.

9. In the AD conversion circuit according to claim 8, The present invention further comprises a multiplexer configured to selectively output one of the multiple second analog input signals to the second ΔΣ AD converter, The AD conversion circuit is characterized in that the CPU outputs a control signal that specifies to the multiplexer the selection of one of the plurality of second analog input signals in synchronization with the conversion start request signal.

10. In the AD conversion circuit according to claim 9, The aforementioned CPU outputs a control signal that sequentially specifies a plurality of second analog input signals, and the AD conversion circuit is characterized in that it enters a synchronous mode when the first and second ΔΣ AD converters are in the order in which they should synchronously acquire the same analog input signals.

11. In the AD conversion circuit according to claim 1 or 5, The CPU periodically outputs the conversion start request signal to the second ΔΣAD converter, always setting the conversion start request signal to the first ΔΣAD converter to a significant value. The AD conversion circuit is characterized in that the first ΔΣ modulator and the first digital filter of the first ΔΣ AD converter perform a conversion operation continuously in accordance with a conversion start request signal output from the CPU.

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