Filtering techniques, analog-to-digital converters and application-specific integrated circuits

Abstract

Filter method for converting an analog input signal into a sampled digital output signal, wherein the z-transformed digital output signal Y(z) results from the z-transformed analog input signal X(z) and the z-transformed rounding error E(z) at order k as Y(z) = X(z) · z -1 + E(z) · (1- z -1 ) k , where Y r (z) = E(z) · (1-z -1 ) k the z-transform of the noise signal is characterized in that - the filter gain at the frequency limit approaches 0 to 1, - for an impulse response h i of the filter at time i for a filter length N: ∑ i = 0 N − 1 h i = 1, where the filter is set up such that the ratio of the variance of the noise signal is var(Y r ) to the variance of the rounding error var(E) yields: var ( Y r ) var ( E ) = h 0 2 + ( h 1 − h 0 ) 2 + ( h 2 − h 1 ) 2 + ⋯ + ( h N − 2 − h N − 1 ) 2 + h N − 1 2 and the variance of the noise signal var(Y r ) is minimized, where the filtering method is an infinite impulse response method.

Description

[0001] The present invention relates to a filter method, in particular for a sigma-delta analog-to-digital converter, for converting an analog input signal into a sampled digital output signal, wherein the z-transformed digital output signal Y(z) is obtained from the z-transformed analog input signal X(z) and the z-transformed rounding error E(z) at order k as Y(z) = X(z) · z -1 + E(z) · (1- z -1 ) k , where Y r (z) = E(z) · (1- z- 1 ) k the z-transform of the noise signal. The invention further relates to an analog-to-digital converter configured to perform a filtering method of this type, and to an application-specific integrated circuit comprising such an analog-to-digital converter. State of the art

[0002] Sigma-delta analog-to-digital converters (A / D converters) are described in the documents "Spectral Analysis of Quantization Noise in a Single-Loop Sigma-Delta Modulator with DC Input," "Understanding Delta-Sigma Data Converters," and "Double-Loop Sigma-Delta Modulation with DC Input." Their operating principle is based on converting a low-resolution input signal (for example, 1 to 4 bits). This process generates rounding errors of varying sizes, which accumulate. These accumulated rounding errors are subtracted from the next input signal during each A / D conversion, resulting in the average rounding errors disappearing. When considering rounding errors in the frequency domain, it can be observed that no error occurs at the limit of zero frequency (at low frequencies), but that the rounding errors also increase with increasing frequency (keyword: "noise shaping").

[0003] Typically, the sampling rate of a sigma-delta A / D converter is significantly higher than predicted by the Nyquist theorem (Nyquist: sampling rate f). a > 2*highest signal frequency). The usable signal bandwidth is therefore significantly smaller than the sampling rate f. a A low-pass filter of the data stream supplied by the sigma-delta converter ensures that the low-frequency useful signal is passed through, while the high-frequency rounding errors are largely suppressed. Depending on the dimensions of the sigma-delta converter and the subsequent filter, accuracy of, for example, 12 to 20 bits can be achieved.

[0004] However, the known solutions are unsatisfactory because they either have a limited signal-to-noise ratio at higher frequencies or require a relatively high computational effort, and are therefore not cost-effective to implement. Disclosure of the invention

[0005] According to the invention, a filter method of the type mentioned above is provided, in which the gain of the filter approaches 1 at the frequency limit of 0, for an impulse response h i of the filter at time i for a filter length N: ∑i=0N−1 h i =1, where the filter is set up such that the ratio of the variance of the noise signal is var(Y r ) to the variance of the Runduna error var(E) yields: var(Yr)var(E)=h02+(h1−h0)2+(h2−h1)2+⋯+(hN−2−hN−1)2+hN−12 and the variance of the noise signal var(Y r ) is minimized. Advantages of the invention

[0006] The invention provides a method for the optimal filtering of the data stream supplied by a k-th order sigma-delta converter (for example, in software), but alternatively also in an integrated circuit that implements the method. Optimal filtering here means that the noise signal (given a finite length of the impulse response of the FIR filter) is reduced to the absolute smallest possible level. A CIC filter (cascaded integrator-differentiator filter) of the same length, known in the prior art, does not achieve this.

[0007] The filtering method can, in principle, be of any order, i.e., k=1, 2, 3, 4,... However, first-order and second-order filtering methods are preferred.

[0008] The solution according to the invention provides reduced noise compared to known filter arrangements (for example, CIC), an improved signal-to-noise ratio (typically 1.25 dB for k=1, 3.05 dB for k=2).

[0009] In a preferred embodiment, the filter method is a finite impulse response (FIR) method. The filter can therefore be of the FIR type and linear-phase. Such an FIR filter of length N yields, given a noise spectrum, ~ sin(π·f / f). a ) k at its output the smallest possible variance, while at the same time useful signals near frequency 0 are passed through with a factor of 1.

[0010] In another embodiment, the filtering method is an infinite impulse response (IIR) method. Preferably, however, the filtering method in this embodiment implements the desired finite impulse response. Preferably, the filtering method is then implemented as a (low-computation) recursive filter. The filtering method can be implemented as an FIR filter structure, but the IIR implementations are preferred because they require significantly less computational effort per sample.

[0011] In a preferred embodiment, the filtering method is a first-order method, i.e., k = 1.

[0012] In a further preferred embodiment, the following applies to the impulse response h i of the filter at time i with a filter length N: hi=6⋅N+(N−1)⋅i−i2N⋅(N+1)⋅(N+2)

[0013] With a first-order filter method, minimal noise can be achieved with such an impulse response.

[0014] In another preferred embodiment, the filtering method is a second-order method, i.e., k = 2.

[0015] In a further preferred embodiment, the following applies to the impulse response h i of the filter at time i with a filter length N: hi=30i4−2(N−1)i3+(N2−5N−1)i2+(N−1)(3N+2)i+2N(N+1)N(N+1)(N+2)(N+3)(N+4)

[0016] With a second-order filter method, minimal noise can be achieved with such an impulse response.

[0017] One embodiment of the invention further relates to an analog-to-digital converter comprising a signal input, a signal output, a quantizer, and a noise reduction circuit arranged upstream of the quantizer in the signal direction, wherein the noise reduction circuit is configured to perform a filtering method according to one of the preceding embodiments. Such an analog-to-digital converter offers particularly high noise reduction with comparatively low computational effort, especially if the filtering method is designed as an infinite impulse response method.

[0018] Another embodiment of the invention relates to an application-specific integrated circuit (ASIC) comprising an analog-to-digital converter of the type described above, wherein the application-specific integrated circuit is configured to convert an analog input signal from a sensor into a digital output signal. Such an ASIC according to the invention is a cost-effective and reliable alternative to a software-based application of the filtering method according to the invention.

[0019] Advantageous embodiments of the invention are specified in the dependent claims and described in the description. Drawings

[0020] Exemplary embodiments of the invention are explained in more detail with reference to the drawings and the following description. The drawings show: Fig. 1 a state-of-the-art sigma-delta converter of order k=1, Fig. 2 a state-of-the-art sigma-delta converter of order k=2, Fig. 3 an embodiment of a sigma-delta filter method of order k=1 of type FIR according to the invention, Fig. 4 an embodiment of a sigma-delta filter method of order k=2 of type FIR according to the invention, Fig. 5 an embodiment of a sigma-delta filter method of order k=1 of type IIR according to the invention, and Fig. 6 an embodiment of a sigma-delta filter method of order k=2 of type IIR according to the invention, Embodiments of the invention

[0021] The Fig. 1 and Fig. Figure 2 shows two simple models of a sigma-delta converter of order k=1 and k=2, respectively, which are known in the prior art. The order indicates how the accumulation of rounding errors occurs. At k=1 ( Fig. 1) The simple error sum is subtracted from the input signal x in step 1. At k=2 ( Fig. 2) The cumulative sum of the error sum is subtracted from the input signal x in step 2. Higher-order converters (k=3...5) also exist, but these have different structures.

[0022] The analog input signal is denoted by x, the digital output signal by y. X(z) and Y(z) are the descriptions of the signals x and y using the z-transform, that is, in the frequency domain. The digital output signal in the frequency domain is then given by: Y(z)=X(z)⋅z−1+E(z)⋅(1−z−1)k,

[0023] A factor z -d This means the delay of the corresponding signal by d clock cycles of the sampling rate f. a The block labeled Q represents the quantizer of the filter. For a 1-bit quantizer, this returns the value -1 for a negative input signal, and +1 otherwise.

[0024] The rounding error e results from the difference between the quantizer output signal (+1) and the quantizer input signal. The rounding error e itself is uniformly distributed; its z-transform E(z) is a constant, meaning all frequencies are in the range 0...f. a equally represented.

[0025] As can be seen from equation (1), the output signal y or Y(z) contains both the delayed input signal x or X(z) and the rounding noise Y shaped in the frequency domain. r (z) = E(z)·(1-z -1 ) k with k=1 or 2. For the sake of simplicity, let z = exp(j·ω·f / f) be used to consider the filtered quantization noise in the frequency domain. a ) with f = frequency. The resulting noise term is then: |E(z)⋅(1−z−1)k|~sin(π⋅f / fa)k, so a noise that increases with frequency.

[0026] Since the bandwidth of the filtered signal after low-pass filtering is significantly lower than the original sampling rate f a After filtering, the sampling rate is usually reduced by a factor M, meaning that only every Mth sample is subsequently processed. Typical values ​​for M are 16, 32, 64, 128, and 256.

[0027] In the state of the art, (k+1)-fold averaging filters over M samples are most commonly used as filters for a k-th order sigma-delta converter. These are easy to implement, and reducing the sampling rate by a factor of M leads to particularly low-complexity structures (which is used especially in the aforementioned CIC filters). The transfer function H(z) of such a (k+1)-fold averaging filter is given by: H(z)=(1M∑i=0M−1z−i)k+1

[0028] The impulse response h of such a filter is symmetrical and has a triangular shape with length N = 2M - 1 for k=1, and an approximate parabolic shape with length N = 3M - 2 for k = 2.

[0029] The invention provides a method for the optimal filtering of the data stream supplied by a k-th order sigma-delta converter (for example, in software), but alternatively also in the form of a circuit (for example, an ASIC) that implements this. Optimal filtering here means that the quantization noise (given a finite length of the filter's impulse response) is reduced to the absolute smallest possible level. A prior art CIC filter of the same length does not achieve this.

[0030] The solution for a sigma-delta converter of order k=1 can be derived as follows. The noise e or E(z) caused by the quantizer is given by the noise transfer function (1-z). -1 ) kshaped and passed to the output of the sigma-delta converter. For a first-order converter (k=1), the sampled noise values ​​e i The output is passed on as follows: yr(n)=(en−en−1)⋅h0+(en−1−en−2)⋅h1+…+(en−N+2−en−N+1)⋅hN−2+(en−N+1−en−N )⋅hN−1=h0⋅en+(h1−h0)⋅en−1+(h2−h1)⋅en−2+…+(hN−1−hN−2)⋅en−N+1−hN−1⋅en−N

[0031] This involves using an FIR filter of length N with impulse response h0 ... h N-1 Assumed. y r (n) is the noise signal at the output at time n, e i the value of the quantization error at time i, h0 ... h N-1 the impulse response of the filter used.

[0032] There are now 2 requirements for the impulse response h: - the gain of the filter at frequency 0 should, for example, be = 1 (so that the low-frequency useful signal is allowed through), - the variance of the noise signal y r It should be minimal.

[0033] The first requirement implies: ∑i=0N−1hi=1

[0034] Since the noise sampling rates e i Since they are independent of each other, the variance of y can be r can be specified as follows (where var(e) = variance of the quantization noise e): var(Yr)var(E)=h02+(h1−h0)2+(h2−h1)2+⋯+(hN−2−hN−1)2+hN−12

[0035] The solution to this optimization problem for k=1 can be given in closed-form formulas. The following solution is obtained for the impulse response h (with i = 0...N-1): hi=6⋅N+(N−1)⋅i−i2N⋅(N+1)⋅(N+2)

[0036] It is a parabolic curve in i.

[0037] For a sigma-delta converter of order k=2 according to the invention, a closed-form solution for the impulse response h can also be given. It is: hi=30i4−2(N−1)i3+(N2−5N−1)i2+(N−1)(3N+2)i+2N(N+1)N(N+1)(N+2)(N+3)(N+4)

[0038] It is a 4th order polynomial in i.

[0039] The solutions for k=1 and k=2 can be directly implemented as FIR filters with N coefficients. Fig. Figures 3 (k=1) and 4 (k=2) each show an embodiment with a filter length of N=5.

[0040] In Fig. In each of steps 3, 4, 5 and 6, a sample is delayed by one further sampling clock cycle (z -1 ) and weighted error subtraction performed by the impulse response h0, h1, h2, h3, or h4 to obtain the sampled digitized output signal y or Y(z).

[0041] In Fig. In steps 7, 8, 9 and 10, a sample is delayed by one further sampling clock cycle (z -1) and error subtraction weighted by the impulse response h0, h1, h2, h3, or h4 is performed to obtain the sampled digitized output signal y or Y(z), respectively, whereas in contrast to the embodiment of the Fig. 3 an inverse order of weighting is used by the impulse response h0, h1, h2, h3, h4.

[0042] The disadvantage of these implementations is the high computational effort: for a filter length N, N multiplications and (N-1) additions must be performed per sample.

[0043] A low-effort implementation of the filter according to the invention is possible in the embodiments of the Fig. 5 and Fig. 6 shown.

[0044] The filters according to the invention can be implemented not only as FIR filters, but also as low-effort IIR filters, which is due to the special form (here: polynomials) of the impulse response h.

[0045] Fig. Figure 5 shows the inventive embodiment of the IIR filter for k=1 and filter length N. The coefficients in this filter arrangement are given by formula (7): c0=1, c1=N, c2=N-(N+1) / 2. The particular advantage of this implementation is its low complexity; only 5 multiplications and 7 additions per sample are required. The constant factor 6 / (N·(N+1)·(N+2)) from formula (7) is not included. This factor does not necessarily have to be implemented, as it only results in a uniform attenuation of signal and noise. It can be applied to y exactly or as an approximation (for example, as a power of two) if required.

[0046] In the embodiment of the Fig. In steps 11, 12, and 13, a sample is delayed by N sampling cycles (z -1 ) and error subtraction weighted by the coefficients c0, c1 or c2 is performed to obtain the sampled digitized output signal y or Y(z).

[0047] A corresponding embodiment according to the invention is also available for the case k=2 of an IIR filter. Fig. Figure 6 shows the coefficients as a function of the filter length N: c0=1,c1=N,c2=c1⋅(N+1) / 2,c3=c2⋅(N+2) / 3,c4=c3⋅(N+3) / 4, b3=2⋅N2+14⋅N+24,b4=−12⋅N−48,b5=24.

[0048] Here too, the constant factor 30 / (N·(N+1)·(N+2)·(N+3)·(N+4)) (here from formula (8)) is not taken into account.

[0049] In this embodiment, a sample delayed by N sampling cycles (z) is used in each of steps 14, 15, 16, 17 and 18. -N ) and performed using the coefficients c0, c1, c2, c3, c4 or weighted error subtraction to obtain the sampled digitized output signal y or Y(z).

Claims

[1] Filter method for converting an analog input signal into a sampled digital output signal, wherein the z-transformed digital output signal Y(z) is obtained from the z-transformed analog input signal X(z) and the z-transformed rounding error E(z) at order k as Y(z) = X(z) · z -1 + E(z) · (1- z -1 ) k , where Y r (z) = E(z) · (1-z -1 ) k the z-transform of the noise signal is, characterized by , that - the filter gain at the frequency limit approaches 0 to 1, - for an impulse response h i of the filter at time i for a filter length N: ∑i=0N−1 h i = 1, where the filter is set up such that the ratio of the variance of the noise signal is var(Y r ) to the variance of the rounding error var(E) yields: var(Yr)var(E)=h02+(h1−h0)2+(h2−h1)2+⋯+(hN−2−hN−1)2+hN−12 and the variance of the noise signal var(Y r ) is minimized, where the filtering method is an infinite impulse response method. [2] Filtering method according to any of the preceding claims, wherein the filtering method is a first-order method, i.e., k = 1. [3] Filter method according to claim 2, wherein for the impulse response h i The following applies to the filter at time i for a filter length N: hi=6⋅N+(N−1)⋅i−i2N⋅(N+1)⋅(N+2) [4] Filter method according to claim 3, wherein - in a first step (11) an error subtraction delayed by N sampling cycles and weighted by the coefficient c0=1, - in a second step (12) an error subtraction delayed by N sampling cycles and weighted by the coefficient c1=N and - in a third step (13) an error subtraction is performed, delayed by N sampling cycles and weighted by the coefficient c2= N·(N+1) / 2, to obtain Y(z). [5] Filtering method according to claim 1, wherein the filtering method is a second-order method, i.e. k = 2. [6] Filter method according to claim 5, wherein for the impulse response h i of the filter at time i for a filter length N: hi=30i4−2(N−1)i3+(N2−5N−1)i2+(N−1)(3N+2)i+2N(N+1)N(N+1)(N+2)(N+3)(N+4) [7] Filter method according to claim 6, wherein - in a first step (14) an error subtraction delayed by N sampling cycles and weighted by the coefficient c0=1, - in a second step (15) an error subtraction delayed by N sampling cycles and weighted by the coefficient c1=N, - in a third step (16) an error subtraction delayed by N sampling cycles and weighted by the coefficient c2= c1·(N+1) / 2, - in a fourth step (17) an error subtraction delayed by N sampling cycles and weighted by the coefficient c3= c2·(N+2) / 3 and - in a fifth step (18) an error subtraction is performed, delayed by N sampling cycles and weighted by the coefficient c4= c3·(N+3) / 4, to obtain Y(z). [8] Analog-to-digital converter comprising a signal input, a signal output, a quantizer and a noise reduction circuit arranged upstream of the quantizer in the direction of the signal, wherein the noise reduction circuit is configured to perform a filtering method according to any of the preceding claims. [9] Application-specific integrated circuit comprising an analog-to-digital converter according to claim 8, wherein the application-specific integrated circuit is configured to convert an analog input signal from a sensor into a digital output signal.

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