Image sensor

Abstract

To provide an image sensor with improved electric and optical characteristics.SOLUTION: An image sensor that is provided includes a semiconductor substrate having a first surface and a second surface facing each other, a first pixel separation structure provided in a first trench extending vertically from the first surface of the semiconductor substrate and defining a plurality of pixel regions, and a second pixel separation structure provided in a second trench extending vertically from the second surface of the semiconductor substrate and overlapping with the first pixel separation structure. The first pixel separation structure can include a liner semiconductor pattern that defines a gap region in the first trench and includes side wall parts and a bottom wall part that connects the side wall parts, a liner insulating pattern disposed between the liner semiconductor pattern and the semiconductor substrate, and a capping insulating pattern provided in the gap region of the liner semiconductor pattern.SELECTED DRAWING: Figure 2

Description

Technical Field

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[0003]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor having improved electrical and optical characteristics.

Background Art

[0002] An image sensor converts an optical image into an electrical signal. Recently, with the development of the computer and communication industries, the demand for image sensors with improved performance in various fields such as digital cameras, video cameras, PCS (Personal Communication System), game devices, security cameras, and medical micro cameras has been increasing.

[0003] Image sensors include charge-coupled devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors have a simple driving method and can integrate a signal processing circuit on a single chip, so the product can be miniaturized. CMOS image sensors also have very low power consumption, so they are easily applicable to products with limited battery capacity. In addition, since CMOS image sensors can use CMOS process technologies interchangeably, the manufacturing cost can be reduced. Therefore, as high resolution becomes feasible with technological development, the use of CMOS image sensors has been increasing rapidly.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem that the present invention aims to solve is to provide an image sensor with improved electrical and optical characteristics.

[0006] The problems that this invention aims to solve are not limited to those mentioned above, and other problems not mentioned should be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] To achieve the aforementioned problem, an image sensor according to one embodiment of the present invention includes a semiconductor substrate having a first surface and a second surface facing each other, a first pixel isolation structure provided in a first trench extending perpendicularly from the first surface of the semiconductor substrate and defining a plurality of pixel regions, and a second pixel isolation structure provided in a second trench extending perpendicularly from the second surface of the semiconductor substrate and superimposed on the first pixel isolation structure, wherein the first pixel isolation structure is a liner semiconductor pattern defining a gap region in the first trench, and includes a liner semiconductor pattern including sidewalls and a bottom connecting the sidewalls, a liner insulating pattern disposed between the liner semiconductor pattern and the semiconductor substrate, and a capping insulating pattern provided in the gap region of the liner semiconductor pattern.

[0008] To achieve the aforementioned problem, an image sensor according to one embodiment of the present invention may include: a semiconductor substrate having a first surface and a second surface facing each other; a first pixel isolation structure extending perpendicularly from the first surface of the semiconductor substrate and surrounding each pixel region, the first pixel isolation structure including a liner semiconductor pattern with side walls and a bottom connecting the side walls; a second pixel isolation structure extending perpendicularly from the second surface of the semiconductor substrate and superimposed on the first pixel isolation structure; and a back contact plug penetrating a part of the second pixel isolation structure and connected to the liner semiconductor pattern of the first pixel isolation structure.

[0009] To achieve the aforementioned problem, an image sensor according to one embodiment of the present invention comprises a semiconductor substrate of a first conductivity type having a first surface and a second surface facing each other, a first pixel isolation structure extending perpendicularly from the first surface of the semiconductor substrate and surrounding each of the pixel regions, the first pixel isolation structure including a liner semiconductor pattern including side walls and a bottom connecting the side walls, a liner insulating pattern between the semiconductor substrate and the liner semiconductor pattern, and a capping insulating pattern on the liner semiconductor pattern, a second pixel isolation structure extending perpendicularly from the second surface of the semiconductor substrate and superimposed on the first pixel isolation structure, and each of the pixel regions The device may include: a photoelectric conversion region provided within a semiconductor substrate and containing a second conductivity type impurity; an element isolation film adjacent to the first surface of the semiconductor substrate, defining an active portion on the first surface of the semiconductor substrate in each of the pixel regions; a transfer gate electrode disposed in the active portion of each of the pixel regions; a back contact plug penetrating a portion of the second pixel isolation structure and connected to the liner semiconductor pattern of the first pixel isolation structure; a color filter on the second surface of the semiconductor substrate corresponding to the pixel region; a lattice structure disposed between the color filters and superimposed on the second pixel isolation structure; and microlenses on the color filters. [Effects of the Invention]

[0010] According to embodiments of the present invention, the amount of conductive semiconductor material with high light absorption in the pixel isolation structure can be minimized. Therefore, the absorption of incident light by the semiconductor material of the pixel isolation structure can be reduced, and a negative voltage can be applied to the semiconductor material of the pixel isolation structure to reduce dark current due to defects at the interface between the semiconductor substrate and the pixel isolation structure. Thus, the electrical and optical characteristics of the image sensor can be improved simultaneously. [Brief explanation of the drawing]

[0011] [Figure 1]This is a plan view showing a part of an image sensor according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view of an image sensor according to an embodiment of the present invention, showing a cross-section taken along the line I-I' in Figure 1. [Figure 3A] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3B] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3C] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3D] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3E] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3F] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3G] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3H] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 3I] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of the P1 portion in Figure 2. [Figure 4] This is an enlarged view of a part of an image sensor according to various embodiments of the present invention, and is an enlarged view of portion P2 in Figure 2. [Figure 5]A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 6] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 7] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 8] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 9] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 10] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 11] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 12] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 13] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 14] A drawing for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, showing a cross section cut along the line I-I' of FIG. 1. [Figure 15] A schematic plan view of an image sensor including a semiconductor device according to an embodiment of the present invention. [Figure 16] A cross-sectional view of an image sensor according to an embodiment of the present invention, showing a cross section cut along the line of FIG. 15. [Figure 17] This is a cross-sectional view of an image sensor according to an embodiment of the present invention, showing a cross-section cut along the line in Figure 15. [Modes for carrying out the invention]

[0012] Hereinafter, an image sensor according to an embodiment of the present invention and a method for manufacturing the same will be described in detail with reference to the drawings.

[0013] Figure 1 is a plan view showing a part of an image sensor according to an embodiment of the present invention. Figure 2 is a cross-sectional view of an image sensor according to an embodiment of the present invention, showing a cross-section taken along the line I-I' in Figure 1. Figures 3A to 3I are enlarged views of parts of an image sensor according to various embodiments of the present invention, specifically enlarged views of portion P1 in Figure 2. Figure 4 is an enlarged view of a part of an image sensor according to various embodiments of the present invention, specifically enlarged views of portion P2 in Figure 2.

[0014] Referring to Figures 1 and 2, an image sensor according to an embodiment of the present invention may include, from a vertical viewpoint, a photoelectric conversion layer 10, a readout circuit layer 20, and a light transmission layer 30.

[0015] The photoelectric conversion layer 10 can be positioned between the readout circuit layer 20 and the light transmission layer 30 from a vertical perspective. Light incident from the outside can be converted into an electrical signal in the photoelectric conversion region PD. The photoelectric conversion layer 10 may include a semiconductor substrate 101, first and second pixel isolation structures PIS1 and PIS2, and the photoelectric conversion region PD.

[0016] In detail, the semiconductor substrate 101 may have a first surface 100a (or front surface) and a second surface 100b (or back surface) that face each other. The semiconductor substrate 101 is a substrate on which a first conductivity type (e.g., p-type) bulk silicon substrate has a first conductivity type epitaxial layer formed on it, and in the manufacturing process of the image sensor, the bulk silicon substrate may be removed and only the p-type epitaxial layer remains. Alternatively, the semiconductor substrate 101 may be a bulk semiconductor substrate 101 containing wells of the first conductivity type.

[0017] The semiconductor substrate 101 may include a central region CR and an edge region ER surrounding the central region CR. The central region may include a plurality of pixel regions PR defined by first and second pixel separation structures PIS1 and PIS2, and the edge region may include a plurality of dummy pixel regions DPR defined by first and second pixel separation structures PIS1 and PIS2.

[0018] The element isolation film 105 can be positioned adjacent to the first surface 100a of the semiconductor substrate 101 in each pixel region PR. The element isolation film 105 can be provided within a first trench T1 formed by recessing the first surface 100a of the semiconductor substrate 101. The element isolation film 105 can be composed of an insulating material. As an example, the element isolation film 105 may include a liner oxide film and a liner nitride film conformally covering the surface of the first trench T1, and a burying oxide film filling the first trench T1 in which the liner oxide film and liner nitride film are formed. The element isolation film 105 can define an active area on the first surface 100a of the semiconductor substrate 101.

[0019] The first pixel isolation structure PIS1 can be provided within the semiconductor substrate 101 by extending perpendicularly (i.e., in the third direction D3) to the first surface 100a of the semiconductor substrate 101. The first pixel isolation structure PIS1 can be provided within a second trench T2 recessed from the first surface 100a of the semiconductor substrate 101.

[0020] The first pixel separation structure PIS1 can penetrate a portion of the element separation film 105. The first pixel separation structure PIS1 can define multiple pixel regions PR in the central region CR and multiple dummy pixel regions DPR in the edge region ER. Here, the first pixel separation structure PIS1 may include a first portion that extends parallel to each other along a first direction D1 and a second portion that extends parallel to each other along a second direction D2 across the first portion. The first pixel separation structure PIS1 can extend continuously from the central region CR to the edge region ER along the first and second directions.

[0021] The first pixel separation structure PIS1 can enclose each of the pixel regions PR and each of the dummy pixel regions DPR in a planar view. The pixel regions PR can be separated from each other in the first direction D1 and the second direction D2 by the first and second pixel separation structures PIS1 and PIS2 in the central region CR. The dummy pixel regions DPR can be separated from each other in the first direction D1 and the second direction D2 by the first and second pixel separation structures PIS1 and PIS2 in the edge region ER. That is, the pixel regions PR and the dummy pixel regions DPR can be arranged two-dimensionally along the first direction D1 and the second direction D2.

[0022] The upper surface of the first pixel isolation structure PIS1 can be substantially coplanar with the first surface 100a of the semiconductor substrate 101. The upper surface of the first pixel isolation structure PIS1 can be substantially coplanar with the upper surface of the element isolation film 105.

[0023] The first pixel isolation structure PIS1 may have a bottom surface between the first surface 100a and the second surface 100b of the semiconductor substrate 101. The first pixel isolation structure PIS1 may be separated from the second surface 100b of the semiconductor substrate 101. The first pixel isolation structure PIS1 may have a first upper width on the first surface 100a of the semiconductor substrate 101 and a first lower width at its bottom surface. The first lower width may be smaller than or substantially the same as the first upper width. As an example, the width of the first pixel isolation structure PIS1 may gradually decrease from the first surface 100a to the second surface 100b of the semiconductor substrate 101. The first pixel isolation structure PIS1 may have a first length in a direction perpendicular to the surface of the semiconductor substrate 101 (i.e., a third direction D3).

[0024] According to one embodiment, the first pixel isolation structure PIS1 may include a liner insulating pattern 111, a liner semiconductor pattern 113, and a capping insulating pattern 115.

[0025] Referring in detail to Figure 3A, the liner insulating pattern 111 can conformally cover the inner wall of the second trench T2 recessed from the first surface 100a of the semiconductor substrate 101. The liner insulating pattern 111 can be provided between the liner semiconductor pattern 113 and the semiconductor substrate 101. The liner insulating pattern 111 can be in direct contact with the semiconductor substrate 101. The bottom surface of the liner insulating pattern 111 can be in contact with the second pixel isolation structure PIS2. The bottom surface of the liner insulating pattern 111 may be in contact with a portion of the second pixel isolation structure PIS2.

[0026] The liner insulating pattern 111 may include a material having a lower refractive index than the semiconductor substrate 101. The liner insulating pattern 111 may include, for example, silicon-based insulating materials (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or high dielectric materials (e.g., hafnium oxide and / or aluminum oxide). As another example, the liner insulating pattern 111 may include multiple layers, the layers of which may contain other materials.

[0027] The liner semiconductor pattern 113 can fill a portion of the second trench T2 provided by the liner insulating pattern 111. The liner semiconductor pattern 113 can conformally cover a portion of the liner insulating pattern 111. That is, the liner semiconductor pattern 113 does not have to be provided on the upper sidewall of the liner insulating pattern 111.

[0028] The liner semiconductor pattern 113 may include sidewalls and a bottom connecting the sidewalls, and a gap region may be defined within the second trench T2 by the sidewalls and the bottom. The bottom of the liner semiconductor pattern 113 may be adjacent to the second surface 100b of the semiconductor substrate 101. The upper surface of the sidewalls of the liner semiconductor pattern 113 may be perpendicularly separated from the first surface 100a of the semiconductor substrate 101. As an example, as shown in Figure 3A, the upper surface of the sidewalls of the liner semiconductor pattern 113 may be located at a lower level than the bottom surface of the element isolation film 105 with respect to the first surface 100a of the semiconductor substrate 101. As another example, as shown in Figures 3H and 3I, the upper surface of the sidewalls of the liner semiconductor pattern 113 may be located at a higher level than the bottom surface of the element isolation film 105 with respect to the first surface 100a of the semiconductor substrate 101.

[0029] According to the embodiment, the sidewall portion of the liner semiconductor pattern 113 may have a first thickness D1 on the liner insulating pattern 111. Furthermore, the upper portion of the sidewall portion of the liner semiconductor pattern 113 may have a thickness that decreases as it approaches the first surface 100a of the semiconductor substrate 101. That is, the upper part of the sidewall portion of the liner semiconductor pattern 113 may have a sharp spacer shape.

[0030] The bottom of the liner semiconductor pattern 113 may have a second thickness D2 on the liner insulating pattern 111. Here, the second thickness D2 may be substantially the same as or smaller than the first thickness D1. On the other hand, according to the embodiment shown in Figure 3B, the bottom of the liner semiconductor pattern 113 may have a second thickness D2 that is greater than the first thickness D1 of the side wall.

[0031] The bottom of the liner semiconductor pattern 113 can be in contact with the liner insulating pattern 111. That is, a portion of the liner insulating pattern 111 can be positioned between the bottom of the liner semiconductor pattern 113 and the second pixel isolation structure PIS2. Alternatively, as shown in Figure 3C, the bottom of the liner semiconductor pattern 113 may be in contact with the second pixel isolation structure PIS2.

[0032] As another example, according to the embodiment shown in Figure 3E, the first pixel isolation structure PIS1 can be separated perpendicularly from the second pixel isolation structure PIS2. Therefore, the bottom portion of the liner insulation pattern 111 can be in contact with the semiconductor substrate 101. That is, a portion of the semiconductor substrate 101 can exist between the bottom surface of the liner insulation pattern 111 and the second pixel isolation structure PIS2.

[0033] The liner semiconductor pattern 113 may include an undoped polysilicon film or an impurity-doped polysilicon film. The impurities in the liner semiconductor pattern 113 may have the same conductivity type as the semiconductor substrate 101. The impurities in the liner semiconductor pattern 113 may include at least one of the following: boron (B), phosphorus (P), arsenic (As), gallium (Ga), indium (In), antimony (Sb), and aluminum (Al).

[0034] The liner semiconductor pattern 113 can be separated from the semiconductor substrate 101 by the liner insulating pattern 111. Therefore, when the image sensor is operating, the liner semiconductor pattern 113 can be electrically isolated from the semiconductor substrate 101.

[0035] The liner semiconductor pattern 113 may have a single body that is provided across the entire pixel array region. That is, the liner semiconductor pattern 113 may have a single body that is provided in common to both the central region and the edge region.

[0036] The liner semiconductor pattern 113 can be connected to the back contact plug PLG in the edge region ER. A negative bias can be applied to the liner semiconductor pattern 113 through the contact pattern CT and the back contact plug PLG. Therefore, the dark current generated at the boundary between the first pixel isolation structure PIS1 and the semiconductor substrate 101 can be reduced.

[0037] The capping insulating pattern 115 can be positioned within the gap region defined by the liner semiconductor pattern 113. The capping insulating pattern 115 can cover the liner semiconductor pattern 113 and cover the upper sidewall of the liner insulating pattern 111. The capping insulating pattern 115 can have an upper surface at substantially the same level as the upper surface of the element isolation film 105. The capping insulating pattern 115 may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0038] In addition, a potential barrier region (PBR) containing a second conductivity type impurity can be provided within the semiconductor substrate 101 adjacent to the sidewall of the first pixel isolation structure PIS1. The potential barrier region (PBR) can contain impurities of the same conductivity type (e.g., p-type) as the semiconductor substrate 101. The concentration of impurities doped into the potential barrier region (PBR) can be higher than the concentration of impurities in the semiconductor substrate 101. When the potential barrier region (PBR) forms the second trench T2, it can reduce the generation of dark current due to electron-hole pairs (EHPs) generated by surface defects in the second trench T2.

[0039] According to the embodiments illustrated in Figures 3F, 3G, and 3I, the first pixel isolation structure PIS1 may further include an air gap AG or void defined within the gap region of the liner semiconductor pattern 113.

[0040] Referring in detail to Figure 3F, the bottom surface of the capping insulating pattern 115 is perpendicularly separated from the bottom of the liner semiconductor pattern 113, allowing an air gap AG to be defined within the gap region of the liner semiconductor pattern 113. That is, a portion of the sidewall and the bottom of the liner semiconductor pattern 113 can define the air gap AG. The bottom surface of the capping insulating pattern 115 can be located at a lower or higher level than the upper surface of the sidewall of the liner semiconductor pattern 113, relative to the first surface 100a of the semiconductor substrate 101. Furthermore, the bottom surface of the capping insulating pattern 115 can be rounded.

[0041] Referring to Figure 3G, the capping insulating pattern 115 can cover the liner semiconductor pattern 113 with a non-uniform thickness, and an air gap AG surrounded by the capping insulating pattern 115 can be defined within the gap region of the liner semiconductor pattern 113.

[0042] Referring again to Figures 1 and 2, the second pixel isolation structure PIS2 can be provided within the semiconductor substrate 101 by extending vertically D3 from the second surface 100b of the semiconductor substrate 101. The second pixel isolation structure PIS2 can also be provided within a third trench T3 recessed from the second surface 100b of the semiconductor substrate 101.

[0043] The second pixel separation structure PIS2 may have a bottom surface between the first surface 100a and the second surface 100b of the semiconductor substrate 101. That is, the second pixel separation structure PIS2 may be separated from the first surface 100a of the semiconductor substrate 101. The second pixel separation structure PIS2 may be in contact with the first pixel separation structure PIS1.

[0044] The second pixel separation structure PIS2 may have a second upper width on the second surface 100b of the semiconductor substrate 101 and a second lower width on its bottom surface. The second lower width may be smaller than or substantially the same as the second upper width. The width of the second pixel separation structure PIS2 may gradually decrease from the second surface 100b of the semiconductor substrate 101 to the first surface 100a.

[0045] The second pixel separation structure PIS2 may have a planar structure substantially identical to that of the first pixel separation structure PIS1. The second pixel separation structure PIS2 may be superimposed on the first pixel separation structure PIS1 in a planar view. That is, the second pixel separation structure PIS2 may include a first portion extending in a first direction D1 and a second portion intersecting the first portion and extending along a second direction D2.

[0046] The second pixel separation structure PIS2 may have a second length in the vertical direction D3, and this second length may differ from the first length of the first pixel separation structure PIS1. In one example, the second length of the second pixel separation structure PIS2 may be smaller than or substantially the same as the first length.

[0047] The second pixel separation structure PIS2 can be composed of at least one high-dielectric film having a higher dielectric constant than the silicon oxide film. As an example, the second pixel separation structure PIS2 may include a surface dielectric film 121 and a gap fill dielectric film 123.

[0048] The surface dielectric film 121 can cover the inner wall of the third trench T3 and the second surface 100b of the semiconductor substrate 101 with a uniform thickness. The gap fill insulating film 123 can fill the third trench T3 on which the surface dielectric film 121 is formed and can have a substantially flat upper surface on the second surface of the semiconductor substrate 101. The surface and gap fill dielectric films 121 and 123 may include a metal oxide or metal fluoride containing at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanide (La). For example, the surface dielectric film 121 may include an aluminum oxide film, and the gap fill dielectric film 123 may include a hafnium oxide film.

[0049] Referring to Figures 3A and 3B, the surface dielectric film 121 of the second pixel separation structure PIS2 can come into contact with the liner insulating pattern 111 of the first pixel separation structure PIS1.

[0050] Referring to Figure 3C, the surface dielectric film 121 of the second pixel separation structure PIS2 may be in contact with the bottom of the liner semiconductor pattern 113 of the first pixel separation structure PIS1.

[0051] Referring to Figure 3D, the second pixel separation structure PIS2 can be positioned offset from the first pixel separation structure PIS1. In this case, the second pixel separation structure PIS2 can come into contact with a portion of the bottom surface of the first pixel separation structure PIS1.

[0052] Referring to Figure 3E, the second pixel separation structure PIS2 can be superimposed on the first pixel separation structure PIS1 and separated vertically. That is, a portion of the semiconductor substrate 101 can exist between the first pixel separation structure PIS1 and the second pixel separation structure PIS2.

[0053] Referring again to Figures 1 and 2, a photoelectric conversion region PD can be provided within the semiconductor substrate 101 of each pixel region PR. The photoelectric conversion region PD generates photocharge in proportion to the intensity of incident light. The photoelectric conversion region PD can be formed by ion implantation of an impurity having a second conductivity type opposite to that of the semiconductor substrate 101 into the semiconductor substrate 101. A photodiode can be formed by the junction between the semiconductor substrate 101 of the first conductivity type and the photoelectric conversion region of the second conductivity type.

[0054] According to some embodiments, the photoelectric conversion region PD may have an impurity concentration difference between a region adjacent to the first surface 100a and a region adjacent to the second surface 100b, such that the photoelectric conversion region PD has a potential gradient between the first surface 100a and the second surface 100b of the semiconductor substrate 101. For example, the photoelectric conversion region PD may include a plurality of vertically stacked impurity regions.

[0055] A transfer gate electrode TG can be positioned on the first surface 100a of the semiconductor substrate 101 in each pixel region PR and dummy pixel region DPR. The transfer gate electrode TG can be located in the center of each pixel region PR in a plan view. A portion of the transfer gate electrode TG can be positioned within the semiconductor substrate 101, and a gate insulating film GIL can be interposed between the transfer gate electrode TG and the semiconductor substrate 101.

[0056] A floating diffusion region (FD) can be provided within the semiconductor substrate 101 on one side of the transfer gate electrode TG. The floating diffusion region (FD) can be formed by ion implantation of an impurity opposite to that of the semiconductor substrate 101. For example, the floating diffusion region (FD) may be an n-type impurity region.

[0057] The readout circuit layer 20 can be placed on the first surface 100a of the semiconductor substrate 101. The readout circuit layer 20 may include a readout circuit connected to the photoelectric conversion layer 10. The electrical signals converted by the photoelectric conversion layer 10 can be processed by the readout circuit layer 20.

[0058] In detail, the readout circuit layer 20 may include MOS transistors (e.g., a reset transistor, a source follower transistor, and a selection transistor).

[0059] The interlayer insulating film 210 can be laminated on the first surface 100a of the semiconductor substrate 101, and the interlayer insulating film 210 can cover the MOS transistors and transfer gate electrodes TG that constitute the readout circuit. The interlayer insulating film 210 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0060] Wiring structures 221 and 222 connected to the readout circuit can be arranged within the interlayer insulating film 210. The wiring structures 221 and 222 may include metal wiring 222 and contact plugs 221 connecting them.

[0061] The light-transmitting layer 30 can be placed on the second surface 100b of the semiconductor substrate 101. The light-transmitting layer 30 may include a lattice structure 310, a protective film 320, a color filter 330, a microlens 340, and a passivation film 350 in the central region CR. The light-transmitting layer 30 may include a light-shielding pattern OBP, a back contact plug PLG, a contact pattern CT, an organic film 345, and a passivation film 350 in the edge region ER.

[0062] In detail, in the central region CR, the lattice structure 310 can be positioned on the upper surface of the gap fill insulating film 123. The lattice structure 310, like the first and second pixel separation structures PIS1 and PIS2, may have a lattice shape in plan view. The lattice structure 310 may be superimposed on the first and second pixel separation structures PIS1 and PIS2 in plan view. That is, the lattice structure 310 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2 across the first portion. The width of the lattice structure 310 may be substantially the same as, or smaller than, the minimum width of the first and second pixel separation structures PIS1 and PIS2.

[0063] The lattice structure 310 may include a conductive pattern and / or a low-refractive-index pattern. The conductive pattern may include a metallic material such as titanium, tantalum, or tungsten. The low-refractive-index pattern may be composed of a material having a lower refractive index than the conductive pattern. The low-refractive-index pattern may be composed of an organic material and may have a refractive index of about 1.1 to 1.3. For example, the lattice structure may be a polymer layer containing silica nanoparticles.

[0064] In the central region CR, the protective film 320 can cover the surface of the lattice structure 320 with a substantially uniform thickness on the upper surface of the gap fill insulating film 123. The protective film 320 may include at least one single or multiple film, for example, an aluminum oxide film and a silicon carbide oxide film.

[0065] In the central region CR, the color filter 330 can be provided on the protective film 320 corresponding to each of the pixel regions PR. The color filter 330 may include blue, red, and green color filters. As another example, the color filter 330 may include magenta, cyan, and yellow color filters. As yet another example, some of the color filters 330 may include white color filters or infrared filters.

[0066] The microlenses 340 can be positioned on the color filter 330, corresponding to each of the pixel regions PR. As another example, at least one of the microlenses 340 can be positioned on at least two color filters.

[0067] The microlenses 340 can be arranged two-dimensionally along first and second directions D1 and D2 that intersect each other. The microlenses 340 have an upward-curving shape and can have a predetermined radius of curvature. The microlenses 340 can focus light by changing the path of light incident on the image sensor. The microlenses 340 can be formed from a light-transmitting resin.

[0068] The passivation film 350 can conformally cover the upper surface of the microlens 340. The passivation film 350 can be formed from, for example, an inorganic oxide.

[0069] In the edge region ER, the back contact plug PLG can penetrate a portion of the second pixel isolation structure PIS2 and a portion of the semiconductor substrate 101, and be connected to the liner semiconductor pattern 113 of the first pixel isolation structure PIS1. When the image sensor is operating, a negative bias voltage can be applied to the back contact plug PLG.

[0070] The back contact plug PLG can have a width greater than the width of the second pixel separation structure PIS2. The back contact plug PLG can penetrate a portion of the first and second intersecting parts of the second pixel separation structure PIS2. The bottom surface of the back contact plug PLG can be spaced further away from the second surface 100b of the semiconductor substrate 101 than the bottom surface of the second pixel separation structure PIS2. That is, with respect to the second surface 100b of the semiconductor substrate 101, the bottom surface of the back contact plug PLG can be located at a lower level than the bottom surface of the second pixel separation structure PIS2.

[0071] The back contact plug PLG may contain metal and / or metal nitride. For example, the back contact plug may contain titanium and / or titanium nitride.

[0072] More specifically, referring to Figure 4, the back contact plug PLG can conformally cover the inner wall of the contact hole formed by recessing the second surface 100b of the semiconductor substrate 101. The back contact plug PLG can contact the side wall portion of the liner semiconductor pattern 113. Furthermore, if the first pixel separation structure PIS1 includes an air gap AG, a portion of the back contact plug PLG can be inserted into a portion of the gap region of the liner semiconductor pattern. Thus, it can contact a portion of the inner wall portion of the side wall portion of the liner semiconductor pattern 113.

[0073] The contact pattern CT can be embedded within the contact hole where the back contact plug PLG is formed. The contact pattern CT may contain a different material from the back contact plug PLG. For example, the contact pattern CT may contain aluminum (Al).

[0074] The contact pattern CT can be electrically connected to the liner semiconductor pattern 113 of the first pixel isolation structure PIS1. A negative bias can be applied to the semiconductor pattern of the first pixel isolation structure PIS1 through the contact pattern CT, and the negative bias can be transmitted from the edge region ER to the central region CR.

[0075] In the edge region ER, the light-shielding pattern OBP can be continuously extended from the back contact plug PLG and positioned on the upper surface of the gap fill insulating film 123 of the second pixel separation structure PIS2. That is, the light-shielding pattern OBP can contain the same material as the back contact plug PLG. The light-shielding pattern OBP can contain metal and / or metal nitride. For example, the light-shielding pattern OBP can contain titanium and / or titanium nitride. The light-shielding pattern OBP does not necessarily have to be extended to the central region ER of the pixel array.

[0076] The protective film 320 can cover the upper surface of the light-shielding pattern OBP and the upper surface of the contact pattern CT.

[0077] The organic film 345 and the passivation film can be provided on the protective film 320 in the edge region ER. The organic film 345 may contain the same material as the microlens 340.

[0078] Figures 5 to 14 are diagrams illustrating a method for manufacturing an image sensor according to an embodiment of the present invention, and show a cross-section taken along the line I-I' in Figure 1.

[0079] Referring to Figures 1 and 5, a semiconductor substrate 101 of a first conductivity type (e.g., p-type) can be provided. The semiconductor substrate 101 may have a first surface 100a and a second surface 100b facing each other. The semiconductor substrate 101 may include a first conductivity type epitaxial layer formed on a first conductivity type bulk silicon substrate 100. Alternatively, the semiconductor substrate 101 may be a bulk semiconductor substrate containing wells of the first conductivity type. As another example, the semiconductor substrate 101 may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate.

[0080] The semiconductor substrate 101, i.e., the epitaxial layer, can be formed by selective epitaxial growth (SEG) using the bulk silicon substrate 100 as a seed, and a first-type impurity can be doped during the epitaxial growth process. For example, the epitaxial layer may contain p-type impurities.

[0081] The first trench T1 can be formed by patterning the first surface 100a of the semiconductor substrate 101. The first trench T1 can define active areas in each pixel region PR and dummy pixel region DPR.

[0082] The first trench T1 can be formed by forming a buffer film BFL and a first mask pattern MP1 on the first surface 100a of the semiconductor substrate 101, and then using the first mask pattern MP1 as an etching mask to anisotropically etch the semiconductor substrate 101.

[0083] The buffer film BFL can be formed on the first surface 100a of the semiconductor substrate 101 by performing a deposition process or a thermal oxidation process. The buffer film BFL may include a silicon oxide film. The first mask pattern MP1 may include a silicon nitride film or a silicon oxynitride film. The bottom surface of the first trench T1 may be separated from the first impurity region 110a.

[0084] Next, an embedded insulating film 103 that fills the first trench T1 can be formed. The embedded insulating film 103 can be formed by depositing a thick insulating material onto the semiconductor substrate 101 on which the first trench T1 is formed. The embedded insulating film 103 can fill the first trench T1 and cover the first mask pattern MP1.

[0085] Referring to Figures 1 and 6, a second trench T2 can be formed that defines the pixel region PR and the dummy pixel region DPR. The second trench T2 can be formed by patterning the embedded insulating film 103 and the first surface 100a of the semiconductor substrate 101.

[0086] In detail, a second mask pattern MP2 can be formed on the embedded insulating film 103, and the second trench T2 can be formed by using the second mask pattern MP2 as an etching mask to anisotropically etch the semiconductor substrate 101.

[0087] The second trench T2 extends perpendicularly from the first surface 100a of the semiconductor substrate 101 to the second surface 100b, exposing the sidewall of the epitaxial layer. The second trench T2 can be formed deeper than the first trench T1 and can penetrate a portion of the first trench T1.

[0088] The second trench T2 may include a plurality of first regions having a uniform width and extending in a first direction D1 in a plan view, and a plurality of second regions having a uniform width and extending in a second direction D2 that intersects with the first direction D1.

[0089] By performing an anisotropic etching process to form a second trench T2, the width of the second trench T2 can gradually decrease from the first surface 100a of the semiconductor substrate 101 towards the second surface 100b. That is, the second trench T2 can have inclined sidewalls. The bottom surface of the second trench T2 can be separated from the second surface 100b of the semiconductor substrate 101.

[0090] After forming the second trench T2, the second mask pattern MP2 can be removed. In addition, after forming the second trench T2, a potential barrier region (see PBR in Figure 3A) containing impurities of the first conductivity type can be formed along the inner wall of the second trench T2. For example, the potential barrier region may contain p-type impurities.

[0091] Referring to Figures 1 and 7, a liner insulating film 110 can be formed that conformally covers the inner wall of the second trench T2. The liner insulating film 110 can conformally cover the upper surface of the embedded insulating film 103. The liner insulating film 110 can be deposited using a deposition method that has excellent step coverage characteristics. The liner insulating film 110 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0092] Referring to Figures 1 and 8, a liner semiconductor pattern 113 can be formed on the liner insulating film 110. Forming the liner semiconductor pattern 113 may include carrying out the liner semiconductor film deposition process and the liner semiconductor film etching process in situ.

[0093] Liner semiconductor films can be formed using at least one of the following techniques: low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD).

[0094] According to one embodiment, a source gas containing a first conductivity type impurity can be used during the deposition process of a liner semiconductor film. The source gas may include a first gas containing a silane compound and a second gas containing the impurity, for example, a compound containing boron (B). The first and second gases chemically react to form a liner semiconductor film. The liner semiconductor film thus formed can have a uniform impurity concentration regardless of position. The liner semiconductor film may include polycrystalline silicon or amorphous silicon containing a first conductivity type impurity.

[0095] For example, in the deposition process of a liner semiconductor film, SiH4 (or Si2H6) and BCl3 (or B2H6) can be used, and the deposition process can be carried out at a low temperature of approximately 300 to 530°C.

[0096] During the etching process of the liner semiconductor film, an etchant gas containing chlorine can be used. During the etching process of the liner semiconductor film, the etching speed can be made faster on the first surface 100a of the semiconductor substrate 101 than on the inner wall of the second trench T2. Therefore, the liner semiconductor film can be etched on the first surface 100a of the semiconductor substrate 101, exposing the liner insulating film 110, while the liner semiconductor film can remain in the second trench T2.

[0097] The liner semiconductor film deposition and etching process can be repeated until the upper surface of the liner semiconductor pattern 113 is positioned at a level lower than the bottom surface of the first trench T1. Alternatively, the liner semiconductor film deposition and etching process can be repeated so that the upper surface of the liner semiconductor pattern 113 is positioned at a level lower than the first surface 100a of the semiconductor substrate 101 and higher than the bottom surface of the first trench T1.

[0098] The liner semiconductor pattern 113 formed in this manner may include a side wall portion on the inner wall of the second trench T2 and a bottom portion on the bottom surface of the second trench T2. Furthermore, the side wall portion of the liner semiconductor pattern 113 may have a sharper spacer shape as it approaches the first surface 100a of the semiconductor substrate 101.

[0099] Referring to Figures 1 and 9, a capping insulating film 114 can be formed that fills the second trench T2 on which the liner semiconductor pattern 113 is formed.

[0100] The capping insulating film 114 can cover the liner insulating film 110 on the first surface 100a of the semiconductor substrate 101. The capping insulating film 114 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0101] The capping insulating film 114 can be formed using film formation techniques that have excellent step coverage properties, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In such cases, the capping insulating film 114 can cover the side walls and bottom of the liner semiconductor pattern 113 within the second trench T2.

[0102] In contrast, it can be formed using a deposition method with poor step-coating properties. For example, the capping insulating film 114 can be formed using a physical vapor deposition method. In such a case, as shown in Figures 3F and 3G, the capping insulating film 114 may be separated from the bottom of the liner semiconductor pattern 113 in the second trench T2, forming an air gap in the second trench T2. By using a deposition process with poor step-coating properties, the bottom and a portion of the sidewall of the liner semiconductor pattern 113 can be exposed in the air gap, as shown in Figure 3F.

[0103] Next, the liner insulating film 110 and the capping insulating film 114 are flattened so that the upper surface of the first mask pattern MP1 is exposed, and the liner insulating pattern 111, the liner semiconductor pattern 113, and the capping insulating pattern 115 can be formed in the second trench T2, as shown in Figure 10. Thus, the first pixel separation structure PIS1 can be formed in the second trench T2.

[0104] After forming the first pixel isolation structure PIS1, the first mask pattern MP1 can be removed, and the embedded insulating film 103 can be planarized so that the first surface 100a of the semiconductor substrate 101 is exposed, thereby forming the element isolation film 105 in the first trench T1. The planarization step that exposes the first surface 100a of the semiconductor substrate 101 allows the upper surface of the first pixel isolation structure PIS1 and the upper surface of the element isolation film 105 to be substantially coplane.

[0105] Next, referring to Figure 10, MOS transistors constituting a readout circuit can be formed on the first surface 100a of the semiconductor substrate 101.

[0106] In detail, a transfer gate electrode TG can be formed in the pixel region PR and the dummy pixel region DPR, respectively. Forming the transfer gate electrode TG includes patterning the semiconductor substrate 101 to form gate recess regions in each of the pixel region PR and the dummy pixel region DPR, forming a gate insulating film conformally covering the inner wall of the gate recess region, forming a gate conductive film filling the gate recess region, and patterning the gate conductive film.

[0107] Furthermore, when patterning the gate conductive film to form the transfer gate electrode TG, the gate electrodes of the readout transistors can be formed together in each of the pixel regions PR.

[0108] After forming the transfer gate electrode TG, a floating diffusion region FD can be formed within the semiconductor substrate 101 on one side of the transfer gate electrode TG. The floating diffusion region FD can be formed by ion implantation of impurities of a second conductivity type. Furthermore, when forming the floating diffusion region FD, the source / drain impurity region of the readout transistor can be formed.

[0109] An interlayer insulating film 210, a contact plug 221, and connecting wiring 223 can be formed on the first surface 100a of the semiconductor substrate 101.

[0110] The interlayer insulating film 210 can cover the transfer gate electrode TG and the first surface 100a of the semiconductor substrate 101. The interlayer insulating film 210 is formed from a material with excellent gap-fill properties and is formed so that the top surface is flattened. For example, the interlayer insulating film 210 can be made of HDP (High Density Plasma), TOSZ (Tonen SilaZene), SOG (Spin On Glass), USG (Undoped Silica Glass), etc.

[0111] A floating diffusion region FD or a contact plug 221 connected to a readout transistor can be formed within the interlayer insulating film 210. Connecting wiring 223 can be formed between the interlayer insulating films 210. Wiring for the electrical connection of the readout transistor can be arranged without positional constraints. The contact plug 221 and connecting wiring 223 can be formed from, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), and alloys composed of combinations thereof.

[0112] Referring to Figures 1 and 11, the vertical thickness of the semiconductor substrate 101 can be reduced by performing a thinning process to remove a portion of the semiconductor substrate 101. The thinning process includes grinding or polishing the second surface 100b of the semiconductor substrate 101 and anisotropic and isotropic etching. The semiconductor substrate 101 can be inverted to thin the semiconductor substrate 101. A portion of the semiconductor substrate 101 can be removed by the grinding or polishing process, and then anisotropic or isotropic etching can be performed to remove any remaining surface defects of the semiconductor substrate 101.

[0113] As an example, by performing a thin-film deposition process on the semiconductor substrate 101, the bulk silicon substrate 100 can be removed, leaving behind a p-type epitaxial layer. In this embodiment, the thickness of the semiconductor substrate 101 remaining after the thin-film deposition process may be approximately 8 μm to 15 μm.

[0114] Next, the second surface 100b of the semiconductor substrate 101 can be patterned to form the third trench T3.

[0115] The third trench T3 can be formed by forming a buffer film BFL and a third mask pattern MP3 on the second surface 100b of the semiconductor substrate 101, and then using the third mask pattern MP3 as an etching mask to anisotropically etch the semiconductor substrate 101.

[0116] The buffer film BFL can be formed on the third surface 300a of the semiconductor substrate 101 by performing a deposition process or a thermal oxidation process. The buffer film BFL may include a silicon oxide film. The third mask pattern MP3 may include a silicon nitride film or a silicon oxynitride film.

[0117] The third trench T3 can expose the first pixel isolation structure PIS1. The third trench T3 can expose the liner insulating film 110 or the liner semiconductor pattern 113 of the first pixel isolation structure PIS1.

[0118] Referring to Figures 1 and 12, the surface dielectric film 121 and the gap fill dielectric film 123 can be sequentially stacked within the third trench T3. By forming the surface dielectric film 121 and the gap fill dielectric film 123, the second pixel separation structure PIS2 can be formed within the third trench T3.

[0119] The surface dielectric film 121 can be conformally deposited on the surface of the third trench T3 and on the second surface 100b of the semiconductor substrate 101. The surface dielectric film and the gap fill dielectric films 121 and 123 can be formed by performing an atomic layer deposition (ALD) process. The gap fill dielectric film 123 can fill the third trench T3 on which the surface dielectric film 121 is formed and can have a substantially flat upper surface on the second surface 100b of the semiconductor substrate 101. The surface and gap fill dielectric films 121 and 123 can contain metal oxides such as aluminum oxide and / or hafnium oxide. Furthermore, in the pad region R2, the surface and gap fill dielectric films 121 and 123 can conformally cover the inner wall of the pad trench PT.

[0120] Referring to Figures 1 and 13, in the edge region ER, a contact hole can be formed that penetrates a part of the semiconductor substrate 101 and a part of the second pixel isolation structure, exposing a part of the semiconductor pattern of the first pixel isolation structure PIS1.

[0121] A conductive film can be deposited on the inner wall of the contact hole and on the upper surface of the gap fill dielectric film 123. After depositing the conductive film, a patterning process can be performed on the conductive film to remove it in the central region CR. Thus, a light-shielding pattern OBP and a back contact plug PLG can be formed in the edge region ER. The conductive film may include metals such as copper, tungsten, aluminum, titanium, tantalum, or alloys thereof.

[0122] Next, a contact pattern CT can be filled into the contact hole where the back contact plug PLG is formed. The contact pattern CT can contain a different conductive material from the back contact plug PLG. For example, the contact pattern CT can contain aluminum.

[0123] Referring to Figures 1 and 14, a lattice structure 310 can be formed on the upper surface of the gap fill dielectric film 123. The lattice structure 310 can extend in a first direction D1 and a second direction D2 and have a lattice shape. The lattice structure 310 can be formed by sequentially depositing a conductive film and a low refractive index film and then patterning them. The lattice structure 310 can include a conductive pattern and / or a low refractive index pattern. The conductive pattern can include a metallic material such as titanium, tantalum, or tungsten. The low refractive index pattern can be composed of a material having a lower refractive index than the conductive pattern.

[0124] The protective film 320 can be formed on the upper surface of the gap fill dielectric film 123 to cover the surface of the lattice structure 310 with a substantially uniform thickness. The protective film 320 can extend from the central region CR to the edge region ER, and in the edge region ER it can cover the upper surface of the light-shielding pattern OBP and the upper surface of the contact pattern CT. The protective film 320 can include at least one single or multiple film among, for example, an aluminum oxide film and a silicon carbide oxide film.

[0125] After forming the protective film 320, a color filter 340 can be formed corresponding to each of the pixel regions PR. The color filter 340 may include blue, red, and green color filters.

[0126] Next, referring again to Figure 2, microlenses 340 can be formed on the color filter 330. The microlenses 340 have a convex shape and can have a predetermined radius of curvature. The microlenses 340 can be formed from a light-transmitting resin.

[0127] After forming the microlens 340, a passivation film 350 can be formed to conformally cover the upper surface of the microlens 340. The passivation film 350 can be formed from, for example, an inorganic oxide.

[0128] Figure 15 is a schematic plan view of an image sensor including a semiconductor device according to an embodiment of the present invention. Figures 16 and 17 are cross-sectional views of the image sensor according to an embodiment of the present invention, showing a cross-section cut along the line in Figure 15.

[0129] Referring to Figures 15 and 16, the image sensor can include a sensor chip 1 and a logic chip 2. Sensor chip 1 can include a pixel array area R1 and a pad area R2.

[0130] The pixel array region R1 may include a plurality of unit pixels P arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect each other. Each unit pixel P may include a photoelectric conversion element and a readout element. An electrical signal generated by incident light can be output from each unit pixel P in the pixel array region R1.

[0131] The pixel array region R1 may include a light-receiving region AR and a light-shielding region OB. The light-shielding region OB may surround the light-receiving region AR in a plan view. In other words, the light-shielding region OB may be positioned above, below, and to the left and right of the light-receiving region AR in a plan view. The light-shielding region OB is provided with reference pixels that are not incident on, and the size of the electrical signal sensed by a unit pixel P can be calculated by comparing the amount of charge sensed by a unit pixel P in the light-receiving region AR with a reference amount of charge generated at the reference pixel P.

[0132] Multiple conductive pads CP can be arranged in the pad region R2 for inputting and outputting control signals and photoelectric signals. The pad region R2 can surround the pixel array region R1 in a plan view to facilitate electrical connection with external elements. The conductive pads CP can input and output electrical signals generated at a unit pixel P to an external device.

[0133] As previously described, the sensor chip 1 may include a photoelectric conversion layer 10 in the vertical direction between the readout circuit layer 20 and the light transmission layer 30.

[0134] The photoelectric conversion layer 10 of the sensor chip 1 may include, as previously described, a semiconductor substrate 101, first and second pixel isolation structures PIS1 and PIS2 that define pixel regions, and a photoelectric conversion region PD provided within the pixel region. Here, the semiconductor substrate 101 may correspond to the epitaxial layer of the previously described embodiment.

[0135] In the light-receiving area AR, sensor chip 1 can include the same technical features as the image sensor described earlier.

[0136] The first and second pixel separation structures PIS1 and PIS2 can be arranged within the semiconductor substrate 101 in the light-shielding region OB. A portion of the first pixel separation structure PIS1 can be connected to a contact plug PLG in the light-shielding region OB.

[0137] The gap fill dielectric film 123 can be extended from the light-receiving region AR to the light-shielding region OB and the pad region R2.

[0138] In the light-shielding region OB, a light-shielding pattern OBP can be placed on the gap-fill dielectric film 123. The light-shielding pattern OBP can block light from entering the photoelectric conversion region PD provided in the light-shielding region OB. In the reference pixel region of the light-shielding region OB, the photoelectric conversion region PD may not output a photoelectric signal but may output a noise signal. The noise signal may be generated by electrons produced by heat generation or dark current, etc. The light-shielding pattern OBP may include a metal such as tungsten, copper, aluminum, or an alloy thereof.

[0139] The protective film 320 can be extended from the active pixel sensor array region R1 to the pad region R2. The protective film 320 can cover the upper surface of the light-shielding pattern OBP.

[0140] The filtering film FL can cover the protective film 320 in the light-shielding region OB. The filtering film FL can block light of different wavelengths than the color filter 330. For example, the filtering film FL can block infrared light. The filtering film FL may, but is not limited to, a blue color filter.

[0141] In the light-shielding region OB, the first through-conductive pattern 510 can penetrate the semiconductor substrate 101 and be electrically connected to the metal wiring 221 of the readout circuit layer 20 and the wiring structure 1111 of the logic chip 2. The first through-conductive pattern 510 may have a first bottom surface and a second bottom surface located at different levels from each other. A first embedded pattern 511 may be provided inside the first through-conductive pattern 510. The first embedded pattern 511 may contain a low refractive index material and have insulating properties.

[0142] In the pad region R2, a conductive pad CP can be provided on the second surface 100b of the semiconductor substrate 101. The conductive pad CP can be embedded within the second surface 100b of the semiconductor substrate 101. As an example, the conductive pad CP can be provided within a pad trench formed in the second surface 100b of the semiconductor substrate 101 in the pad region R2. The conductive pad CP can include metals such as aluminum, copper, tungsten, titanium, tantalum, or alloys thereof. In the image sensor mounting process, a bonding wire can be bonded to the conductive pad CP. The conductive pad CP can be electrically connected to an external device through the bonding wire.

[0143] In the pad region R2, the second through-conductive pattern 520 can penetrate the semiconductor substrate 101 and be electrically connected to the wiring structure 1111 of the logic chip 2. The second through-conductive pattern 520 can extend onto the second surface 100b of the semiconductor substrate 101 and be electrically connected to the conductive pad CP. A portion of the second through-conductive pattern 520 can cover the bottom surface and side walls of the conductive pad CP. A second embedding pattern 521 can be provided inside the second through-conductive pattern 520. The second embedding pattern 521 may contain a low refractive index material and have insulating properties. In the pad region R2, first and second pixel isolation structures PIS1 and PIS2 can be provided around the second through-conductive pattern 520.

[0144] The logic chip 2 may include a logic semiconductor substrate 1000, a logic circuit TR, a wiring structure 1111 connected to the logic circuit, and a logic interlayer insulating film 1100. The uppermost layer of the logic interlayer insulating film 1100 may be bonded to the read circuit layer 20 of the sensor chip 1. The logic chip 2 may be electrically connected to the sensor chip 1 through a first through-conductive pattern 510 and a second through-conductive pattern 520.

[0145] In one example, the sensor chip 1 and the logic chip 2 are described as being electrically connected to each other through first and second through-hole conductive patterns, but the present invention is not limited thereto.

[0146] According to the embodiment shown in Figure 17, the first and second through-conductive patterns shown in Figure 16 can be omitted, and the sensor chip and logic chip may be electrically connected by directly bonding the bonding pads provided on the uppermost metal layers of the sensor chip and logic chip to each other.

[0147] In detail, the image sensor's sensor chip 1 may include a first bonding pad BP1 provided on the top metal layer of the readout circuit layer 20, and the logic chip 2 may include a second bonding pad BP2 provided on the top metal layer of the wiring structure 111. The first and second bonding pads BP1 and BP2 may include at least one of the following materials: tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0148] The first bonding pad BP1 of sensor chip 1 and the second bonding pad BP2 of logic chip 2 can be directly electrically bonded to each other using a hybrid bonding method. Hybrid bonding refers to bonding in which two components containing the same material fuse at their interface. For example, if the first and second bonding pads BP1 and BP2 are made of copper (Cu), they can be physically and electrically bonded by copper (Cu)-copper (Cu) bonding. Alternatively, the insulating film surface of sensor chip 1 and the insulating film surface of logic chip 2 can be joined by dielectric-dielectric bonding.

[0149] While embodiments of the present invention have been described above with reference to the attached drawings, those with ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without altering its technical idea or essential features. Therefore, the embodiments described above should be understood to be illustrative and not limiting in all respects. [Explanation of Symbols]

[0150] 10 Photoelectric conversion layer 20 Readout circuit layer 30 Light transmission layer 101 Semiconductor substrate 105 Element Separation Membrane 310 Lattice structure 320 Protective film 330 Color Filters 340 Microlens 350 Passivation membrane 350 AG Air Gap CR center area DPR dummy pixel area ER edge region FD floating diffusion region GIL Gate Insulator PD (Photoelectric Transformation) Region PIS1, PIS2 Pixel Separation Structures PR Pixel Area TG Transfer Terminal

Claims

1. A substrate having a first surface and a second surface facing each other, A first isolation structure is provided within a first trench that extends perpendicularly from the first surface of the substrate and defines a plurality of pixel regions, The second separation structure is provided in a second trench extending perpendicularly from the second surface of the substrate and superimposed on the first separation structure in a first direction perpendicular to the first surface of the substrate, The first separation structure is, A first liner pattern that defines a gap region within the first trench, the first liner pattern including a side wall portion and a bottom portion connecting the side wall portion in a first direction perpendicular to the first surface of the substrate, A second liner pattern is disposed between the first liner pattern and the substrate, The first liner pattern includes a capping insulating pattern provided within the gap region of the first liner pattern, An image sensor in which the upper surface of the side wall portion of the first liner pattern is spaced perpendicularly from the first surface of the substrate.

2. The image sensor according to claim 1, wherein the first separation structure further includes an air gap defined within the gap region by the capping insulation pattern.

3. The first separation structure includes a plurality of first parts extending along a second direction in a plan view and a plurality of second parts intersecting the first parts in a plan view and extending along a third direction in a plan view. The image sensor according to claim 1 or 2, wherein the first liner pattern is continuously extended along the second and third directions.

4. The image sensor according to any one of claims 1 to 3, wherein the thickness of the bottom portion of the first liner pattern is substantially the same as or greater than the thickness of the side wall portion.

5. The bottom portion of the first liner pattern is adjacent to the second separation structure, The image sensor according to any one of claims 1 to 4, wherein the upper portion of the side wall of the first liner pattern has a thickness that decreases as it is adjacent to the first surface.

6. Each of the pixel regions further includes an element isolation film adjacent to the first surface of the substrate, The image sensor according to any one of claims 1 to 5, wherein the upper surface of the side wall portion of the first liner pattern is located at the level between the bottom surface of the element isolation film and the second isolation structure.

7. Each of the pixel regions further includes an element isolation film adjacent to the first surface of the substrate, The image sensor according to any one of claims 1 to 5, wherein the upper surface of the side wall portion of the first liner pattern is located at the level between the bottom surface of the element isolation film and the first surface of the substrate.

8. The image sensor according to any one of claims 1 to 7, wherein the first liner pattern contains impurities of the same first conductivity type as the substrate.

9. Each of the aforementioned pixel regions is provided and further comprises a photoelectric conversion region containing a second type of conductivity impurity, The image sensor according to any one of claims 1 to 8, wherein the side wall portion of the first liner pattern surrounds each of the photoelectric conversion regions in a plan view.

10. The bottom portion of the first liner pattern is adjacent to the second separation structure, The image sensor according to any one of claims 1 to 9, further comprising a back contact plug that penetrates a portion of the second separation structure and connects to the first liner pattern.

11. The image sensor according to any one of claims 1 to 10, wherein a portion of the second liner pattern is disposed between the second separation structure and the bottom of the first liner pattern.

12. The first separation structure has its maximum width on the first surface of the substrate in the second direction. The image sensor according to any one of claims 1 to 11, wherein the second separation structure has its maximum width on the second surface of the substrate in the second direction.

13. The image sensor according to any one of claims 1 to 12, wherein the first vertical length of the first separation structure in the first direction is greater than or substantially the same as the second vertical length of the second separation structure in the first direction.

14. A substrate having a first surface and a second surface facing each other, A first separation structure that extends perpendicularly from the first surface of the substrate and surrounds each of the pixel regions, the first separation structure includes a first liner pattern including side walls and a bottom portion connecting the side walls, A second separation structure extends perpendicularly from the second surface of the substrate and is superimposed on the first separation structure in a first direction perpendicular to the first surface of the substrate, Includes a back contact plug that penetrates a portion of the second separation structure and connects to the first liner pattern of the first separation structure, An image sensor in which the upper surface of the side wall portion of the first liner pattern is spaced perpendicularly from the first surface of the substrate.

15. The image sensor according to claim 14, wherein the rear contact plug contacts the side wall portion of the first liner pattern.

16. The image sensor according to claim 14 or 15, wherein the rear contact plug has a width in the second direction that is greater than the maximum width of the second separation structure in the second direction perpendicular to the first direction.

17. The first separation structure further includes a second liner pattern provided between the first liner pattern and the substrate, and a capping insulating pattern that fills the gap region defined by the bottom and sidewalls of the first liner pattern. The image sensor according to any one of claims 14 to 16, wherein a portion of the second liner pattern is disposed between the second separation structure and the bottom of the first liner pattern.

18. Each of the pixel regions further includes an element isolation film adjacent to the first surface of the substrate, The image sensor according to any one of claims 14 to 17, wherein the upper surface of the side wall portion of the first liner pattern is perpendicularly separated from the bottom surface of the element isolation film.

19. The first separation structure includes a plurality of first parts extending along a second direction in a plan view and a plurality of second parts intersecting the first parts in a plan view and extending along a third direction in a plan view. The image sensor according to any one of claims 14 to 18, wherein the first liner pattern is continuously extended along the second and third directions.

20. A first-conductivity substrate having a first surface and a second surface facing each other, A first separation structure extending perpendicularly from the first surface of the substrate and surrounding each of the pixel regions, the first separation structure including a first liner pattern including side walls and a bottom connecting the side walls, a second liner pattern between the substrate and the first liner pattern, and a capping insulating pattern on the first liner pattern, A second separation structure extends vertically from the second surface of the substrate and is superimposed on the first separation structure, A photoelectric conversion region containing a second-conductivity impurity is provided within the substrate of each of the aforementioned pixel regions, An active portion is defined on the first surface of the substrate in each of the aforementioned pixel regions, and an element isolation film adjacent to the first surface of the substrate, A transfer gate electrode is disposed in each of the active parts of the pixel region, A back contact plug that penetrates a portion of the second separation structure and connects to the first liner pattern of the first separation structure, A color filter corresponding to the pixel region is provided on the second surface of the substrate, A grid structure is placed between the color filters and superimposed on the second separation structure, The color filter includes a microlens, An image sensor in which the upper surface of the side wall portion of the first liner pattern is spaced perpendicularly from the first surface of the substrate.

Images