Chip-type electronic components

Abstract

Provided is a chip-type electronic component that is less likely to cause separation of a spacer and a mounting substrate. A chip-type electronic component 1 of the present invention comprises a multilayered ceramic capacitor 1A and spacers 10. The multilayered ceramic capacitor 1A comprises: a stack 2 that includes internal electrode layers 5 and dielectric layers 4 that are alternately disposed; and external electrodes 3. When the two surfaces of the stack 2 opposing each other in the multilayered direction are capacitor main surfaces A, the two surfaces thereof opposing each other in the width direction are capacitor side surfaces B, and the two surfaces thereof opposing each other in the length direction are capacitor end surfaces C, the external electrodes 3 are respectively provided on the capacitor end surfaces C. The spacers 10 are disposed on both sides in the length direction of the capacitor main surface A on the mounting substrate side of the multilayered ceramic capacitor 1A. When the two surfaces opposing each other in the multilayered direction of each of the spacers 10 are spacer main surfaces AS, a recess 11 is formed in the surface of the spacer main surface AS on the mounting substrate side.

Description

Technical Field

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[0001] The present invention relates to chip-type electronic components.

Background Art

[0002] A multilayer ceramic capacitor includes a laminate having an inner layer portion in which dielectric layers and internal electrodes are alternately stacked, and external electrodes provided on both end faces in the longitudinal direction of the laminate. Here, when a voltage is applied to the multilayer ceramic capacitor, the dielectric layer may be polarized and the multilayer ceramic capacitor may vibrate in the polarization direction. Then, this vibration may be transmitted to the mounting substrate, and cracks may occur in the mounting substrate. For this reason, conventionally, there is a technique in which a spacer is disposed on the mounting surface side of the multilayer ceramic capacitor to form a chip-type electronic component, and the spacer buffers the vibration to suppress the vibration transmitted to the mounting substrate (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, for example, when a high dielectric constant material is used as a component of the dielectric layer, the vibration becomes large. Therefore, if the bonding force between the mounting substrate and the spacer is weak, the spacer may peel off from the mounting substrate. [[ID=�6]]

[0005] An object of the present invention is to provide a chip-type electronic component in which a spacer and a mounting substrate are difficult to peel off.

Means for Solving the Problems

[0006] To solve the above problems, the present invention provides a chip-type electronic component comprising: a laminate including a plurality of internal electrode layers and a plurality of internal dielectric layers arranged alternately to each other; an external electrode provided on each of the capacitor end faces, when the laminate has two faces facing each other in the stacking direction as capacitor main faces, two faces facing each other in the width direction intersecting the stacking direction as capacitor side faces, and two faces facing each other in the length direction intersecting the stacking direction and the width direction as capacitor end faces; and spacers arranged on both sides in the length direction of the capacitor main face on the mounting substrate side of the multilayer ceramic capacitor, wherein, when the two faces of the spacer facing each other in the stacking direction are designated as spacer main faces, recesses are formed on the surface of the spacer main faces on the mounting substrate side. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a chip-type electronic component in which the spacer and the mounting substrate are less likely to separate. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic perspective view of a chip-type electronic component 1 according to an embodiment. [Figure 2] This is a partial cross-sectional view of chip-type electronic component 1 along the line II-II in Figure 1. [Figure 3] This is a cross-sectional view of chip-type electronic component 1 along the line III-III in Figure 1. [Figure 4] This is a diagram showing the second main surface AS2 of spacer 10 facing upwards. [Figure 5] This is a flowchart illustrating the manufacturing method of chip-type electronic component 1. [Figure 6] This is a modified form of a partial cross-sectional view of chip-type electronic component 1. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below. Figure 1 is a schematic perspective view of a chip-type electronic component 1 according to an embodiment. Figure 2 is a partial cross-sectional view of the chip-type electronic component 1 along line II-II in Figure 1. Figure 3 is a cross-sectional view of the chip-type electronic component 1 along line III-III in Figure 1. Figures 1, 2, and 3 show the components bonded to a mounting substrate 210.

[0010] The chip-type electronic component 1 comprises a multilayer ceramic capacitor 1A having a substantially rectangular parallelepiped-shaped laminate 2 and a pair of external electrodes 3 provided at both ends of the laminate 2, and a spacer 10 attached to the multilayer ceramic capacitor 1A. The laminate 2 also includes an inner layer portion 6 which comprises multiple sets of dielectric layers 4 and internal electrode layers 5.

[0011] In the following description, the orientation of the chip-type electronic component 1 is described as follows: the direction in which the pair of external electrodes 3 are provided is defined as the length direction L. The direction in which the dielectric layer 4 and the internal electrode layer 5 are stacked is defined as the stacking direction T. The direction that intersects both the length direction L and the stacking direction T is defined as the width direction W. In this embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0012] Furthermore, of the six outer surfaces of the laminate 2, a pair of outer surfaces facing the stacking direction T are designated as the first capacitor main surface A1 and the second capacitor main surface A2, a pair of outer surfaces facing the width direction W are designated as the first capacitor side surface B1 and the second capacitor side surface B2, and a pair of outer surfaces facing the length direction L are designated as the first capacitor end surface C1 and the second capacitor end surface C2.

[0013] Furthermore, when there is no need to distinguish between the first capacitor main surface A1 and the second capacitor main surface A2, they will be collectively referred to as capacitor main surface A; when there is no need to distinguish between the first capacitor side surface B1 and the second capacitor side surface B2, they will be collectively referred to as capacitor side surface B; and when there is no need to distinguish between the first capacitor end surface C1 and the second capacitor end surface C2, they will be collectively referred to as capacitor end surface C.

[0014] (Laminate 2) The laminate 2 includes an inner layer portion 6, an outer layer portion 7 disposed on the capacitor main surface A side of the inner layer portion 6, and a side gap portion 8. The laminate 2 is preferably rounded at the ridge line portion R. The ridge line portion R is a portion where two surfaces of the laminate 2, that is, the capacitor main surface A and the capacitor side surface B, the capacitor main surface A and the capacitor end surface C, or the capacitor side surface B and the capacitor end surface C intersect, and includes the corner portion where the capacitor main surface A, the capacitor side surface B, and the capacitor end surface C intersect.

[0015] (Inner layer portion 6) The inner layer portion 6 includes a plurality of sets of dielectric layers 4 and internal electrode layers 5 laminated alternately along the lamination direction T.

[0016] (Dielectric layer 4) The dielectric layer 4 is made of a ceramic material. As the ceramic material, for example, a dielectric ceramic mainly composed of BaTiO3 is used. Also, as the ceramic material, a material obtained by adding at least one of sub-components such as Mn compound, Fe compound, Cr compound, Co compound, nickel compound, etc. to these main components may be used.

[0017] (Internal electrode layer 5) The internal electrode layer 5 is preferably formed of a metal material typified by, for example, nickel, Cu, Ag, Pd, Ag-Pd alloy, Au, etc.

[0018] The internal electrode layer 5 includes a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layer 5A and the second internal electrode layer 5B are arranged alternately. When there is no need to particularly distinguish and explain the first internal electrode layer 5A and the second internal electrode layer 5B, they are collectively described as the internal electrode layer 5.

[0019] The internal electrode layer 5 includes a facing portion 52 that faces each other between the first internal electrode layer 5A and the second internal electrode layer 5B, and a lead-out portion 51 that does not face each other between the first internal electrode layer 5A and the second internal electrode layer 5B and is drawn out from the facing portion 52 to one capacitor end face C side. The end of the lead-out portion 51 is exposed on the capacitor end face C and is electrically connected to the external electrode 3. The direction in which the lead-out portion 51 extends is different between the first internal electrode layer 5A and the second internal electrode layer 5B, and is alternately drawn out to the first capacitor end face C1 side and the second capacitor end face C2 side. Then, charges are accumulated between the facing portions 52 of the first internal electrode layer 5A and the second internal electrode layer 5B adjacent to each other in the stacking direction T, and it functions as a capacitor.

[0020] (Outer layer portion 7) The outer layer portion 7 is disposed on both capacitor main surface A sides of the inner layer portion 6 and is made of the same material as the dielectric layer 4 of the inner layer portion 6.

[0021] (Side gap portion 8) The side gap portion 8 is provided on both capacitor side surface B sides of the inner layer portion 6 in the laminate 2. The side gap portion 8 is integrally manufactured with the same material as the dielectric layer 4.

[0022] (External electrode 3) The external electrode 3 is provided on both capacitor end faces C of the laminate 2. That is, the first external electrode 3A is formed on the first capacitor end face C1, and the second external electrode 3B is formed on the second capacitor end face C2. The external electrode 3 covers not only the capacitor end face C but also a part of the capacitor main surface A and the capacitor side surface B on the capacitor end face C side. The external electrode 3 includes a base electrode layer 30 and a plating layer 31 formed on the outer periphery of the base electrode layer 30.

[0023] (Base electrode layer 30) The base electrode layer 30 is electrically connected to the end of the lead portion 51 of the internal electrode layer 5 exposed on the capacitor end face C. In this embodiment, the base electrode layer 30 is a so-called baked electrode, which is made by firing a conductive paste containing a conductive metal such as copper, nickel, silver, palladium, silver-palladium alloy, or gold. The baked electrode contains a glass component and a metal. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The baked electrode is made by applying a conductive paste containing glass and metal to the laminate 2 and baking it. It may be baked simultaneously with the internal electrode layer 5 and the dielectric layer 4, or it may be baked after the internal electrode layer 5 has been baked. When baking simultaneously with the internal electrode layer 5 and the dielectric layer 4, it is preferable to add a dielectric material instead of a glass component to form the baked electrode.

[0024] (Plating layer 31) The plating layer 31 includes a Ni plating layer 31a disposed on the outer periphery of the base electrode layer 30 so as to cover the base electrode layer 30, and a Sn plating layer 31b disposed on the outer periphery of the Ni plating layer 31a so as to cover the Ni plating layer 31a. The Ni plating layer 31a can prevent the base electrode layer 30 from being corroded by solder when mounting ceramic electronic components, and the Sn plating layer 31b improves the wettability of solder when mounting the multilayer ceramic capacitor 1A, making mounting easier. The Ni plating layer 31a consists of plating of nickel or a nickel-containing alloy. The Sn plating layer 31b consists of plating of Sn or a Sn-containing alloy. In addition to the above metals, the plating layer 31 may also contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0025] (Spacer 10) The spacer 10 comprises a pair of two spacers, a first spacer 10A and a second spacer 10B. Hereafter, unless it is necessary to distinguish between the first spacer 10A and the second spacer 10B, they will be described simply as spacer 10. On the second capacitor main surface A2 side of the multilayer ceramic capacitor 1A, the first spacer 10A is positioned on one side in the length direction L, and the second spacer 10B is positioned on the other side. The first spacer 10A and the second spacer 10B are substantially rectangular and identical in shape, facing each other and positioned at a certain distance apart.

[0026] The spacer 10 is a roughly rectangular parallelepiped, with six outer surfaces, a pair of outer surfaces facing the stacking direction T designated as the first spacer main surface AS1 and the second spacer main surface AS2, a pair of outer surfaces facing the width direction W designated as the first spacer side surface BS1 and the second spacer side surface BS2, and a pair of outer surfaces facing the length direction L designated as the first spacer end surface CS1 and the second spacer end surface CS2.

[0027] The first spacer main surface AS1 is the surface facing the laminate 2, and the second spacer main surface AS2 is the mounting surface that is mounted on the mounting substrate 210. The first spacer main surface AS1 of the first spacer 10A is formed on the first capacitor end face C1. 1 outside part electrode 3A The first spacer main surface AS1 of the second spacer 10B is in contact with the second capacitor main surface A2, and the second spacer main surface AS1 of the second spacer 10B is formed on the second capacitor end surface C2. 2 external electrode 3B It is in contact with the main surface A2 side of the second capacitor.

[0028] The cross-sectional shape of the spacer 10 perpendicular to the stacking direction T is a rectangle in which the side extending in the length direction L is the shorter side and the side extending in the width direction W is the longer side. The first spacer side surface BS1 and the second spacer side surface BS2 are surfaces along the shorter side of the spacer 10, and the first spacer end surface CS1 and the second spacer end surface CS2 are surfaces of the spacer 10 Long side It is a surface that follows a specific direction. The first spacer end face CS1 of the first spacer 10A is formed on the side of the first capacitor end face C1 of the first external electrode 3A, and the second spacer end face CS2 of the second spacer 10B is formed on the side of the second capacitor end face C2 of the second external electrode 3B.

[0029] Furthermore, when there is no need to distinguish between the first spacer main surface AS1 and the second spacer main surface AS2, they will be collectively referred to as the spacer main surface AS; when there is no need to distinguish between the first spacer side surface BS1 and the second spacer side surface BS2, they will be collectively referred to as the spacer side surface BS; and when there is no need to distinguish between the first spacer end surface CS1 and the second spacer end surface CS2, they will be collectively referred to as the spacer end surface CS.

[0030] The spacer 10 is not limited to a rectangular parallelepiped shape; it may also be a hexahedron shape in which the area of ​​the first spacer main surface AS1 is larger than that of the second spacer main surface AS2. Furthermore, the spacer side surface BS and the spacer end surface CS do not have to be perpendicular to the second spacer main surface AS2, which is the mounting surface. In addition, for example, the first spacer side surface BS1, the second spacer side surface BS2, the first spacer end surface CS1, and the second spacer end surface CS2 may be curved surfaces.

[0031] Spacer 10 is manufactured using so-called high-temperature solder, which mainly consists of an intermetallic compound containing a high-melting-point metal and a low-melting-point metal. In this specification, "main component" means that the content is 50% or more. When an intermetallic compound is the main component, the reaction rate is fast and the shape changes little.

[0032] The high-melting-point metal contains at least one of Cu or Ni, and the low-melting-point metal contains Sn. When an intermetallic compound containing a high-melting-point metal containing at least one of Cu or Ni and a low-melting-point metal containing Sn is used as the main component, it has a melting point that does not melt even at soldering temperatures, and it is possible to arrange it while maintaining the desired shape during soldering. Furthermore, the intermetallic compound is preferably an intermetallic compound produced by the reaction of Sn and a Cu-Ni alloy. In addition, Ag may be further included as the high-melting-point metal constituting the intermetallic compound.

[0033] (Conductive resin) Furthermore, the spacer 10 may be made of a conductive resin. The conductive resin includes a metal and a thermosetting resin. When the spacer 10 is made of a conductive resin, it is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste, because it contains resin.

[0034] (Metal in conductive resin) The metals that can be included in the conductive resin are Ag, Cu, or alloys thereof. Alternatively, metal powders coated with Ag can be used. When using metal powders coated with Ag, it is preferable to use Cu or Ni as the metal powder. Cu treated with an anti-oxidation treatment can also be used. The metal in the conductive resin is preferably present in an amount of 35 vol% to 75 vol% of the total volume of the conductive resin. The metal in the conductive resin can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders. The average particle size of the metal in the conductive resin is not particularly limited. The average particle size of the conductive filler may be, for example, 0.3 μm to 10 μm. The metal in the conductive resin is primarily responsible for the conductivity of the conductive resin. Specifically, conductive paths are formed inside the conductive resin by the contact between the conductive fillers.

[0035] (Resin of conductive resin) Various known thermosetting resins such as epoxy resins, phenolic resins, urethane resins, silicone resins, and polyimide resins can be used as the resin included in the conductive resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. The resin included in the conductive resin is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin. Furthermore, it is preferable that the conductive resin contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, and imidazole compounds can be used as the curing agent for the epoxy resin.

[0036] (Surface shape) The spacer 10 has recesses 11 formed on the surface of the second spacer main surface AS2, which is the mounting surface. Multiple recesses 11 are formed. Figure 4 is a view of the spacer 10 with the second spacer main surface AS2 facing upwards. According to this embodiment, because the recesses 11 are formed on the surface on the second spacer main surface AS2 side, when mounting the chip-type electronic component 1 onto the mounting substrate 210, the solder 240 can enter the recesses 11, and the fixing force between the solder 240 and the spacer 10 can be improved by the anchoring effect.

[0037] (Total opening area of ​​recess 11) The total opening area of ​​the recess 11 is preferably 25% to 75% of the surface area of ​​the second spacer main surface AS2. The reason is that if the total opening area of ​​the recess 11 is greater than 75% of the area of ​​the second spacer main surface AS2, much of the solder 240 will be trapped in the recess 11, making it difficult for the solder 240 to flow to the spacer end face CS and spacer side surface BS of the spacer 10, thus weakening the bonding strength between the spacer 10 and the mounting substrate 210. If the total opening area of ​​the recess 11 is less than 25% of the total area of ​​the second spacer main surface AS2, the bonding area between the solder 240 and the spacer 10 will decrease, and therefore the anchoring effect with the solder 240 will not be sufficiently obtained. The total opening area of ​​the recess 11 of the spacer 10 is the sum of the areas of the openings of the recess 11 when viewed from the second spacer main surface AS2 side.

[0038] (Definition of recess 11) The second main surface AS2 of spacer 10 is not flat but has irregularities. Here, the thickness of spacer 10 is defined as the distance T in the stacking direction between the most protruding position on the second main surface AS2 of spacer 10, i.e., the top of the convex part, and the first main surface AS1. When the second main surface AS2 is brought into contact with a flat surface, the flat surface comes into contact with the top of the convex part of the second main surface AS2. From this position of the flat surface, i.e., the top of the convex part, toward the first main surface AS1, the portion within 1% of the thickness of spacer 10 is considered to be included in the flat surface of the second main surface AS2, and the portion that is recessed by more than 1% of the thickness of spacer 10 is defined as a recess 11.

[0039] (Opening area of ​​one recess 11) The opening area of ​​one recess 11 is preferably 0.1% to 70% of the surface area of ​​the second spacer main surface AS2. The reason is that if the opening area of ​​one recess 11 is greater than 70% of the area of ​​the second spacer main surface AS2, too much solder 240 will be trapped in the recess 11, making it difficult for the solder 240 to flow to the spacer end face CS and spacer side surface BS of the spacer 10, which may result in a lower bonding strength between the spacer 10 and the mounting substrate 210. If the opening area of ​​one recess 11 is less than 0.1% of the area of ​​the second spacer main surface AS2, the solder 240 will not be able to penetrate sufficiently into the recess 11 of the spacer 10, and therefore will not be able to fully benefit from the anchoring effect. Furthermore, the opening area of ​​one recess 11 is more preferably 0.5% to 65% of the area of ​​the second spacer main surface AS2, even more preferably 1% to 60%, and particularly preferably 5% to 50%.

[0040] (Number of recesses 11) The number of recesses 11 is appropriately selected to satisfy the conditions of the total opening area of ​​the recesses 11 and the opening area of ​​a single recess 11.

[0041] (Internal shape of recess 11) The internal shape of the recess 11 is not particularly limited. For example, it may be a tapered shape that narrows as it approaches the first spacer main surface AS1 from the second spacer main surface AS2, or it may be an octopus pot shape where the interior is larger than the opening.

[0042] (Depth of recess 11) The depth of the recess 11 is preferably 1% to 50% of the thickness of the spacer 10 in the stacking direction T. The stacking direction T is the direction in which the dielectric layer 4 and the internal electrode layer 5 are stacked in the multilayer ceramic capacitor 1A described above, and in the case of the spacer 10, it is the direction connecting the first spacer main surface AS1 and the second spacer main surface AS2. The "depth" refers to the length from the opening of the recess 11 to the bottom, in the direction of the stacking direction T.

[0043] The reason why it is preferable for the depth of the recess 11 to be 1% or more of the thickness of the spacer 10 in the stacking direction T is that if the depth of the recess 11 is less than 1%, the surface becomes smooth, making it difficult to obtain the anchoring effect described later.

[0044] The reason why it is preferable that the depth of the recess 11 be 50% or less of the thickness of the spacer 10 in the stacking direction T is that if the depth of the recess 11 is greater than 50%, the length of the portion of the spacer 10 in the stacking direction T where the recess 11 is provided will be shortened, which may reduce the mechanical strength of the spacer 10.

[0045] In this embodiment, the recesses 11 consist of a mixture of recesses 11 that are 1% or more but less than 5% and recesses 11 that are 5% or more. Furthermore, the average depth of the recesses 11 that are 5% or more is more preferably 5% or more but 35% or less of the thickness of the spacer 10 in the stacking direction T, and even more preferably 10% or more but 20% or less. It is preferable that the recesses 11 consist of a mixture of recesses 11 that are 1% or more but less than 5% and recesses 11 that are 5% or more. The recesses 11 may consist only of recesses 11 that are 1% or more but less than 5% and may consist only of recesses 11 that are 5% or more.

[0046] (Side and end faces) It is preferable that recesses 11 are also formed on the surfaces of two spacer end faces CS that face each other in the length direction L of the spacer 10. It is also preferable that recesses 11 are also formed on the surfaces of two spacer side faces BS that face each other in the width direction W of the spacer 10. In this way, when recesses 11 are also placed on the surface of the spacer end face CS and the surface of the spacer side BS, the solder 240 wets the surface of the spacer end face CS and the spacer side BS, thereby improving the adhesion force between the solder 240 and the external electrode 3.

[0047] However, the recess 11 of the spacer 10 does not need to be on any other surface as long as it is provided on the second spacer main surface AS2. Also, if it is provided on other surfaces, it may be placed on some surfaces, not all surfaces. Some surfaces can be any surface. For example, the recess 11 may be located on both sides of the spacer side BS or on one side, as long as it is provided on the second spacer main surface AS2, and may be located on both sides of the spacer end surface CS or on one side. When positioned on one side, it is more preferable that the recess 11 be formed on the end face CS1 of the first spacer 10A and the end face CS2 of the second spacer 10B. Solder 240 attempting to wet the end faces CS1 and CS2 of the first spacer is absorbed by the recess 11 of the end face CS1 of the first spacer 10A and the recess 11 of the end face CS2 of the second spacer 10B, thereby suppressing excessive fillet formation. Furthermore, the recess 11 of the spacer 10 may be positioned on different faces of the first spacer 10A and the second spacer 10B, as long as it is provided on the main surface AS2 of the second spacer.

[0048] (Mounting board 210) A lands 230 are arranged on the mounting substrate 210 on which the chip-type electronic component 1 is mounted. The lands 230 have a first land 230A and a second land 230B. A first spacer 10A is connected to the first land 230A, and a second spacer 10B is connected to the second land 230B, both by solder 240.

[0049] Here, a recess 11 is formed on the surface of the second spacer main surface AS2, and solder 240 enters this recess 11. Therefore, the chip-type electronic component 1 and the mounting substrate 210 are joined with a high bonding force due to the anchoring effect.

[0050] (Manufacturing method for chip-type electronic component 1) Next, a method for manufacturing the chip-type electronic component 1 according to the embodiment will be described. Figure 5 is a flowchart illustrating the method for manufacturing the chip-type electronic component 1. The manufacturing process for the chip-type electronic component 1 comprises a laminate manufacturing process S1, an external electrode formation process S2, a spacer placement process S3, and a recess formation process S4.

[0051] (Laminate manufacturing process S1) First, in the laminate manufacturing process S1, a material sheet is prepared in which the pattern of the internal electrode layer 5 is printed with conductive paste on a ceramic green sheet for lamination, which is formed from a ceramic slurry into a sheet. Then, multiple material sheets are stacked so that the internal electrode patterns are offset by half a pitch in the length direction between adjacent material sheets. Furthermore, outer layer ceramic green sheets are stacked on both sides of the multiple stacked material sheets and heat-pressed together to form a mother block member. Multiple laminates 2 are manufactured by dividing the mother block member along cutting lines corresponding to the dimensions of the laminate.

[0052] (External electrode formation process S2) Next, in the external electrode formation step S2, external electrodes 3 are formed on both ends of the laminate 2. First, the base electrode layer 30 is formed by applying a conductive paste containing, for example, a conductive metal and glass to both ends of the laminate 2 and baking it. As shown in Figure 2, the base electrode layer 30 extends not only to the capacitor end faces C on both sides of the laminate 2, but also to the capacitor main surface A, and is formed to cover a part of the capacitor main surface A on the side of the capacitor end faces C. Next, a Ni plating layer 31a is formed on the outer periphery of the base electrode layer 30 so as to cover the base electrode layer 30. Then, a Sn plating layer 31b is formed on the outer periphery of the Ni plating layer 31a so as to cover the Ni plating layer 31a. Through these steps, a multilayer ceramic capacitor 1A with external electrodes 3 formed on the laminate 2 is manufactured.

[0053] (Spacer placement process S3) In the spacer placement step S3, an intermetallic compound paste, which is the material for the spacer 10, is placed on the outer circumference of the external electrode 3 on the second capacitor main surface A2 side of the multilayer ceramic capacitor 1A.

[0054] Intermetallic compound paste is a so-called high-temperature solder whose main component is an intermetallic compound containing at least one of Cu or Ni as a high-melting-point metal and Sn as a low-melting-point metal. Such intermetallic compound pastes are placed on the surface of the Sn plating layer 31b in a liquid state, which is initially melted at a temperature of 200°C or higher. High-temperature solder has a melting point that does not melt even at typical soldering temperatures, and it is possible to position components while maintaining their desired shape during soldering.

[0055] (Concave formation step S4) Before the high-temperature solder hardens, an intermetallic compound paste is bonded to a plate that does not bond to the high-temperature solder, such as an alumina plate, from the second main surface side, to create a plate with the desired uneven surface. After the intermetallic compound paste hardens, the alumina plate is removed. This allows the recess 11 to be formed on the second spacer main surface AS2 of the spacer 10. The recesses 11 in the spacer end face CS and the spacer side surface BS can be formed by arranging the alumina plate so that it wraps around the end face and side surface, etc. The area and depth of the recesses 11 can be adjusted by adjusting the area, height, and depth of the irregularities formed on the alumina plate.

[0056] Furthermore, when forming a recess 11 with a depth of 5% or more of the thickness of the spacer 10 in the stacking direction T, a method of contacting such an alumina plate is preferable. Also, when the depth of the recess 11 is 1% or more but less than 5% of the thickness of the spacer 10 in the stacking direction T, a method of forming the recess 11 by sandblasting or the like is preferable. However, the recess 11 may be formed by any method, regardless of its depth.

[0057] The method for forming the recess 11 is not limited to this, and other methods may be used. For example, after the intermetallic compound paste has hardened, the recess may be formed by roughening the hardened surface with a file or the like, or the recess may be formed by a chemical method such as etching. Through the above process, a chip-type electronic component 1 is manufactured.

[0058] As described above, according to the chip-type electronic component 1 of this embodiment, since a recess 11 is formed on the surface on the second spacer main surface AS2 side, when the chip-type electronic component 1 is mounted on the mounting substrate 210, the solder 240 enters the recess 11, and the fixing force between the solder 240 and the spacer 10 can be improved by the anchoring effect.

[0059] Furthermore, the solder 240 may be positioned between the spacer 10 and the land 230 as shown in Figure 2, or it may cover the spacer 10 and extend to the side surface of the external electrode 3 as shown in Figure 6. In this embodiment, the spacer 10 has recesses 11 formed on the surface of the spacer end face CS and the surface of the spacer side surface BS. Therefore, when the solder 240 covers the spacer 10 and extends to the side surface of the external electrode 3 as shown in Figure 6, the solder 240 penetrates into the surface recesses 11 of the spacer end face CS and the spacer side surface BS, thereby further improving the bonding force between the solder 240 and the spacer 10 through a stronger anchoring effect.

[0060] Although preferred embodiments of the present invention have been described above, the present invention includes the following combinations. <1> A chip-type electronic component comprising: a laminate including a plurality of internal electrode layers and a plurality of internal dielectric layers arranged alternately to each other; an external electrode provided on each of the capacitor end faces when the laminate has two faces facing each other in the stacking direction as capacitor main faces, two faces facing each other in the width direction intersecting the stacking direction as capacitor side faces, and two faces facing each other in the length direction intersecting the stacking direction and the width direction as capacitor end faces; and spacers arranged on both sides in the length direction of the capacitor main face on the mounting substrate side of the multilayer ceramic capacitor, wherein when the two faces of the spacer facing each other in the stacking direction are designated as spacer main faces, recesses are formed on the surface of the spacer main faces on the mounting substrate side.

[0061] <2> The spacer is mainly composed of an intermetallic compound containing a high-melting-point metal and a low-melting-point metal. <1> The chip-type electronic component described above.

[0062] <3> The high-melting-point metal includes at least one of Cu or Ni, and the low-melting-point metal includes Sn. <2> The chip-type electronic component described above.

[0063] <4> The aforementioned spacer is made of conductive resin. <1> The chip-type electronic component described above.

[0064] <5> The total opening area of ​​the recess of the spacer is 25% to 75% of the surface area of ​​the main surface of the spacer on the mounting substrate side. <1> from <4> A chip-type electronic component as described in any of the following.

[0065] <6> The opening area of ​​one of the recesses of the spacer is 0.1% or more and 70% or less of the surface area of ​​the main surface of the spacer on the mounting substrate side. <1> from <5> A chip-type electronic component as described in any of the following.

[0066] <7> The depth of the recess in the stacking direction is 1% or more and 50% or less of the thickness of the spacer in the stacking direction. <1> from <6> A chip-type electronic component as described in any of the following.

[0067] <8> The spacer has recesses formed on the surfaces of two spacer end faces CS that are opposite to each other in the longitudinal direction. <1> from <7> A chip-type electronic component as described in any of the following.

[0068] <9> The spacer has recesses formed on the surfaces of two spacer sides that face each other in the width direction. <1> from <8> A chip-type electronic component as described in any of the following.

[0069] In the laminate, one of the two capacitor end faces is designated as the first capacitor end face and the other as the second capacitor end face, and the side of the two capacitor main faces that is on the spacer side is designated as the second capacitor main face, and in each of the spacers, one of the two spacer end faces that are opposite to each other in the longitudinal direction is designated as the first spacer end face and the other as the second spacer end face, the spacer has a first spacer that contacts the portion of the first external electrode, which is located on the side of the first capacitor end face, that extends toward the side of the second capacitor main face, and a second spacer that contacts the portion of the second external electrode, which is located on the side of the second capacitor end face, that extends toward the side of the second capacitor main face, and a recess is formed on the first spacer end face, which is the side of the first capacitor end face, and a recess is formed on the second spacer end face, which is the side of the second capacitor end face <1> from <9> A chip-type electronic component as described in any of the following. [Explanation of Symbols]

[0070] A Capacitor main surface B Capacitor side C Capacitor end face AS Spacer Main Surface AS1 First Spacer Main Surface AS2 Second Spacer Main Surface BS Spacer Side CS Spacer End Face 1. Chip-type electronic component 1A Multilayer Ceramic Capacitor 2 Laminate 3 External electrode 4. Dielectric layer 5 Internal electrode layer 10 Spacers 10A 1st Spacer 10B Second Spacer 11 recess 210 Mounting board 230 Rand 230A 1st Land 230B Second Round 240 Handa

Claims

1. A laminate comprising multiple internal electrode layers and multiple internal dielectric layers arranged alternately with respect to each other, and The laminated body, Two surfaces that face each other in the stacking direction are called the main capacitor surfaces. Two surfaces facing each other in the width direction intersecting the aforementioned stacking direction are the capacitor sides, A multilayer ceramic capacitor comprising two surfaces facing each other in the longitudinal direction intersecting the stacking direction and the width direction, defined as capacitor end faces, and external electrodes provided on each of the capacitor end faces, A chip-type electronic component comprising spacers arranged on both sides in the longitudinal direction of the main surface of the multilayer ceramic capacitor on the mounting substrate side of the capacitor, In the spacer, when two surfaces facing each other in the stacking direction are defined as the main surfaces of the spacer, a recess is formed on the surface of the main surface of the spacer on the mounting substrate side. Chip-type electronic components.

2. The spacer is mainly composed of an intermetallic compound containing a high-melting-point metal and a low-melting-point metal. The chip-type electronic component according to claim 1.

3. The aforementioned high-melting-point metal includes at least one of Cu or Ni. The low melting point metal includes Sn, The chip-type electronic component according to claim 2.

4. The aforementioned spacer is made of conductive resin. The chip-type electronic component according to claim 1.

5. The total opening area of ​​the recess of the spacer is 25% to 75% of the surface area of ​​the main surface of the spacer on the mounting substrate side. The chip-type electronic component according to claim 1.

6. The opening area of ​​one of the recesses of the spacer is 0.1% or more and 70% or less of the surface area of ​​the main surface of the spacer on the mounting substrate side. The chip-type electronic component according to claim 1.

7. The depth of the recess in the stacking direction is 1% or more and 50% or less of the thickness of the spacer in the stacking direction. The chip-type electronic component according to claim 1.

8. The spacer has recesses formed on the surfaces of two spacer end faces that face each other in the longitudinal direction. The chip-type electronic component according to claim 1.

9. The spacer has recesses formed on the surfaces of two spacer sides that face each other in the width direction. The chip-type electronic component according to claim 1.

10. In the laminate, one of the two capacitor end faces is designated as the first capacitor end face, the other as the second capacitor end face, and the side of the two capacitor main faces that is on the spacer side is designated as the second capacitor main face. When, in each of the spacers, one of the two spacer end faces that face each other in the longitudinal direction is designated as the first spacer end face and the other as the second spacer end face, The previous spacer is A first spacer that contacts the portion of the first external electrode, which is positioned on the end face side of the first capacitor, that extends toward the main face side of the second capacitor, The external electrodes include a second spacer that contacts the portion of the second external electrode, which is positioned on the end face side of the second capacitor, that extends toward the main face side of the second capacitor, A recess is formed on the first spacer end face, which is the side of the first capacitor end face of the first spacer. A recess is formed on the second spacer end face, which is the side of the second capacitor end face of the second spacer. The chip-type electronic component according to claim 1.

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