Multilayer capacitor and its mounting substrate

Abstract

To provide a multilayer capacitor in which margins of a capacitor body are optimized, and a mounting board thereof.SOLUTION: The present invention provides a multilayer capacitor and a mounting board thereof. The multilayer capacitor includes: a capacitor body including a dielectric layer and a plurality of first and second internal electrodes; and first and second external electrodes disposed on both ends of the capacitor body, respectively and connected to exposed portions of the first and second internal electrodes, respectively. When the thickness of the dielectric layer is defined as A, and an average length of margins of the capacitor body in a length direction is defined as B, A is 1 μm or less, and A / B satisfies 0.0016≤A / B<1.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a multilayer capacitor and its mounting substrate.

Background Art

[0002] A multilayer capacitor (MLCC: Multi-Layer Ceramic Capacitor) is one of the passive component parts and plays a role in controlling electrical signals on a circuit.

[0003] The main role of the multilayer capacitor is to accumulate electric charges in the electrodes, block DC signals, and act as a filter that allows AC signals to pass through.

[0004] That is, it can be said that the multilayer capacitor plays a role in bypassing and removing the AC noise on the power line and stabilizing the operation of the IC.

[0005] For such high-capacitance of MLCC, various methods have been tried. For example, methods such as increasing the dielectric constant of the dielectric, thinning the thickness of the dielectric, or increasing the overlapping area of the internal electrodes have been disclosed.

[0006] However, when increasing the overlapping area of the internal electrodes, the margin in the length direction or width direction of the product decreases. If the amount of margin reduction is too large, there may be a problem that the electric field characteristics become weak.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] The object of the present invention is to provide a multilayer capacitor and its mounting substrate in which the margin of the capacitor body is optimized so as to increase the overlap area of ​​the internal electrodes without degrading the electric field characteristics. [Means for solving the problem]

[0009] One aspect of the present invention provides a multilayer capacitor comprising a capacitor body including a dielectric layer and a plurality of first and second internal electrodes, and first and second external electrodes arranged at both ends of the capacitor body and connected to the exposed portions of the first and second internal electrodes, respectively, wherein when the thickness of the dielectric layer is defined as A and the average length of the margin in the longitudinal direction of the capacitor body is defined as B, A is 1 μm or less and A / B satisfies 0.0016 ≤ A / B < 1.

[0010] In one embodiment of the present invention, the thickness of the first and second internal electrodes may be 0.4 μm or less.

[0011] In one embodiment of the present invention, the capacitor body includes first and second surfaces facing each other, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces, and the first and second internal electrodes can be arranged such that one end is alternately exposed to the third and fourth surfaces of the capacitor body with a dielectric layer in between.

[0012] In one embodiment of the present invention, the first and second external electrodes may each include first and second connecting portions formed on the third and fourth surfaces of the capacitor body and connected to the exposed portion of the internal electrode, and first and second band portions extending from the first and second connecting portions to a part of the first surface of the capacitor body.

[0013] In one embodiment of the present invention, the present invention further includes a plating layer formed to cover the first and second external electrodes, wherein the plating layer may consist of a nickel plating layer and a tin plating layer.

[0014] In one embodiment of the present invention, the thickness of the dielectric layer is 1 μm, and A / B can satisfy 0.002 ≤ A / B ≤ 0.2.

[0015] In one embodiment of the present invention, the thickness of the dielectric layer is 0.4 μm, and A / B can satisfy 0.0016 ≤ A / B ≤ 0.5.

[0016] In one embodiment of the present invention, the average length of the margin in the longitudinal direction of the capacitor body may be 0.8 to 500 μm.

[0017] Another aspect of the present invention provides a mounting substrate for a multilayer capacitor, which includes a substrate having first and second electrode pads on one surface, and a multilayer capacitor mounted such that first and second external electrodes are connected to the first and second electrode pads, respectively. [Effects of the Invention]

[0018] According to one embodiment of the present invention, by limiting the thickness of the dielectric layer relative to the length of the margin in the length direction of the capacitor body, the overlap area of ​​the internal electrodes is increased, thereby increasing the capacitance of the multilayer capacitor while preventing electric field distortion of the multilayer capacitor. This reduces the electric field value, thereby preventing breakdown voltage (BDV) failures of the multilayer capacitor. [Brief explanation of the drawing]

[0019] [Figure 1] This is a schematic perspective view of a multilayer capacitor according to one embodiment of the present invention. [Figure 2] (a) and (b) are plan views showing the first and second internal electrodes applied to the multilayer capacitor in Figure 1, respectively. [Figure 3] This is a cross-sectional view along the line I-I' in Figure 1. [Figure 4] Figure 3 is a cross-sectional view showing that an additional plating layer has been formed on the external electrode. [Figure 5] It is a cross-sectional view of a capacitor body for explaining the position where an electric field is measured during an electric field measurement test. [Figure 6] It is a cross-sectional view schematically showing a state where the multilayer capacitor of FIG. 4 is mounted on a substrate.

Embodiments for Carrying out the Invention

[0020] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to those having average knowledge in the relevant technical field. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or emphasized or simplified) for clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0021] Also, throughout the specification, when a certain component is described as "including", it means that other components can be further included, rather than excluding other components, unless otherwise stated to the contrary.

[0022] In order to clearly explain the embodiments of the present invention, when defining the direction of the capacitor body 110, X, Y, and Z shown in the drawings indicate the length direction, width direction, and thickness direction of the capacitor body 110, respectively. Also, in the present embodiment, the Z direction can be used with the same concept as the stacking direction in which the dielectric layers are stacked.

[0023] FIG. 1 is a perspective view schematically showing a multilayer capacitor according to an embodiment of the present invention, FIGS. 2(a) and (b) are plan views respectively showing the first and second internal electrodes applied to the multilayer capacitor of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line I-I' of FIG. 1.

[0024] Referring to Figures 1 to 3, the stacked capacitor 100 according to this embodiment includes a capacitor body 110 which includes a dielectric layer 111 and a plurality of first and second internal electrodes 121 and 122, and first and second external electrodes 131 and 141 which are arranged at both ends of the capacitor body 110 and connected to the exposed portions of the first and second internal electrodes 121 and 122, respectively.

[0025] In this case, when the thickness of the dielectric layer 111 is defined as A and the length of the margin of the capacitor body 110 in the X direction as B, A is 1 μm or less, and the ratio of the thickness of the dielectric layer to the length of the margin of the capacitor body in the X direction, A / B, can satisfy 0.0016 ≤ A / B < 1.

[0026] The capacitor body 110 is formed by stacking multiple dielectric layers 111 in the Z direction and then firing them. The boundaries between adjacent dielectric layers 111 of the capacitor body 110 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0027] In this case, the capacitor body 110 may be generally hexahedral, but the present invention is not limited thereto.

[0028] Furthermore, the shape, dimensions, and number of dielectric layers 111 of the capacitor body 110 are not limited to those shown in the drawings of this embodiment.

[0029] In this embodiment, for the sake of explanation, the two surfaces of the capacitor body 110 that face each other in the Z direction are defined as the first and second surfaces 1 and 2, the two surfaces that face each other in the X direction are defined as the third and fourth surfaces 3 and 4, the two surfaces that face each other in the Y direction are defined as the fifth and sixth surfaces 5 and 6, the two surfaces that face each other in the Y direction are defined as the fifth and sixth surfaces 5 and 6.

[0030] Furthermore, in this embodiment, the mounting surface of the multilayer capacitor 100 may be the first surface 1 of the capacitor body 110.

[0031] The dielectric layer 111 may include a ceramic material with a high dielectric constant, such as barium titanate (BaTiO3) or strontium titanate (SrTiO3) ceramic powder, but the present invention is not limited thereto as long as sufficient capacitance can be obtained.

[0032] Furthermore, ceramic additives, organic solvents, plasticizers, binders, and dispersants may be added to the dielectric layer 111 along with the ceramic powder.

[0033] Examples of ceramic additives that can be used include transition metal oxides or transition metal carbides, rare earth elements, magnesium (Mg), or aluminum (Al).

[0034] Such a capacitor body 110 may include an active region that contributes to the formation of the capacitor's capacitance, and upper and lower covers 112 and 113 formed above and below the active region in the Z direction as upper and lower margin portions.

[0035] The upper and lower covers 112 and 113 may have the same material and configuration as the dielectric layer 111, except that they do not include internal electrodes.

[0036] Such upper and lower covers 112 and 113 can be formed by stacking a single dielectric layer or two or more dielectric layers in the Z direction on the upper and lower surfaces of the active region, respectively, and can essentially serve to prevent damage to the first and second internal electrodes 121 and 122 due to physical or chemical stress.

[0037] The first and second internal electrodes 121 and 122 are electrodes to which different polarities are applied, and are arranged alternately along the Z direction with a dielectric layer 111 in between, with one end of each electrode exposed on the third and fourth surfaces 3 and 4 of the capacitor body 110, respectively.

[0038] In this case, the first and second internal electrodes 121 and 122 can be electrically insulated from each other by the dielectric layer 111 placed in between them.

[0039] In this manner, the ends of the first and second internal electrodes 121 and 122, which are alternately exposed on the third and fourth surfaces 3 and 4 of the capacitor body 110, can be electrically connected to the first and second external electrodes 130 and 140, respectively, which are arranged on the third and fourth surfaces 3 and 4 of the capacitor body 110, as described later.

[0040] With the above configuration, when a predetermined voltage is applied to the first and second external electrodes 130 and 140, charge is accumulated between the first and second internal electrodes 121 and 122.

[0041] In this case, the capacitance of the multilayer capacitor 100 becomes proportional to the overlapping area of ​​the first and second internal electrodes 121 and 122 that overlap each other along the Z direction in the active region.

[0042] Furthermore, the materials used to form the first and second internal electrodes 121 and 122 are not particularly limited and can be formed using, for example, a conductive paste made of precious metal materials such as platinum (Pt), palladium (Pd), palladium-silver (Pd-Ag) alloys, and one or more substances selected from nickel (Ni) and copper (Cu).

[0043] In this case, the printing method for the conductive paste can be screen printing or gravure printing, but the present invention is not limited thereto.

[0044] Furthermore, in this embodiment, the thickness of the first and second internal electrodes 121 and 122 may be 0.4 μm or less.

[0045] If the thickness of the first and second internal electrodes 121 and 122 exceeds 0.4 μm, a problem may arise in which it is difficult to secure sufficient capacitance as designed.

[0046] Recently, multilayer capacitors have tended to be manufactured with smaller size and higher capacitance. Therefore, in order to achieve this miniaturization and higher capacitance of multilayer capacitors, it is preferable that the thickness of the internal electrodes be 0.4 μm or less.

[0047] The first and second external electrodes 131 and 141 are supplied with voltages of opposite polarity. The first and second external electrodes 131 and 141 are located at both ends of the capacitor body 110 in the X direction and can be electrically connected to the exposed portions of the first and second internal electrodes 121 and 122, respectively.

[0048] The first external electrode 131 may include a first connection portion 131a and a first band portion 131b.

[0049] The first connection portion 131a is formed on the third surface 3 of the capacitor body 110 and is connected to the exposed portion of the first internal electrode 121, and the first band portion 131b is an extension from the first connection portion 131a to a part of the first surface 1 of the capacitor body 110.

[0050] In this case, the first band portion 131b can be extended to parts of the fifth and sixth surfaces 5 and 6 and part of the second surface 2 of the capacitor body 110 in order to improve the fixing strength, etc.

[0051] The second external electrode 141 may include a second connecting portion 141a and a second band portion 141b.

[0052] The second connection portion 141a is formed on the fourth surface 4 of the capacitor body 110 and is connected to the exposed portion of the second internal electrode 122, and the second band portion 141b is a portion that extends from the second connection portion 141a to a part of the first surface 1 of the capacitor body 110.

[0053] In this case, the second band portion 141b can be further extended to parts of the fifth and sixth surfaces 5 and 6 and part of the second surface 2 of the capacitor body 110 in order to improve the fixing strength, etc.

[0054] Furthermore, as shown in Figure 4, the material may further include first and second plating layers formed to cover the first and second external electrodes 131 and 141, respectively.

[0055] In this case, the first and second plating layers may include first and second nickel plating layers 132, 142 formed on the surfaces of the first and second external electrodes 131, 141, respectively, and first and second tin plating layers 133, 143 covering the first and second nickel plating layers 132, 142, respectively.

[0056] In this embodiment, when the thickness of the dielectric layer is defined as A and the average length of the margin in the longitudinal direction of the capacitor body is defined as B, A / B satisfies 0.0016 ≤ A / B < 1.

[0057] When the electric field behavior was examined within this range of A / B values, depending on the margin length in the X direction, it was found that the electric field characteristics did not deteriorate.

[0058] Therefore, within the range of the above A / B values, it is possible to maximize the overlap area between the first and second internal electrodes, thereby providing a multilayer capacitor with high capacitance without generating electric field distortion.

[0059] When the electric field distortion of a multilayer capacitor is reduced or prevented in this way, and the electric field value of the multilayer capacitor becomes smaller, it is possible to prevent the breakdown voltage (BDV) failure of the multilayer capacitor.

[0060] Furthermore, the thickness (A) of the dielectric layer is preferably 1 μm or less. In other words, the multilayer capacitor of this embodiment may be a small, high-capacitance product in which the thickness (A) of the dielectric layer is 1 μm or less.

[0061] Recently, multilayer capacitors have tended to be manufactured with miniaturization and high capacitance. Therefore, in order to achieve miniaturization and high capacitance in such multilayer capacitors, it is preferable that the thickness of the dielectric layer be 1 μm or less.

[0062] Table 1 below shows the maximum electric field measured for changes in the A / B ratio of a multilayer capacitor using Ansys Maxwell 2D Simulation.

[0063] As shown in Figure 5, the electric field was measured at the observation line (OL) drawn perpendicularly to the point where the distance (g) from the tip of the internal electrode was 0.5 μm.

[0064] Here, g is the result of simulating by sampling only a portion of the multilayer capacitor.

[0065] In this study, the dielectric layer thickness (A) was set to 1 μm or 0.4 μm, and the distribution of the electric field in the multilayer capacitor was observed while varying the X-direction margin (B) of the capacitor body in the multilayer capacitor.

[0066] [Table 1]

[0067] Table 1 shows the case where the dielectric layer thickness is 1 μm. Referring to Table 1, it can be confirmed that for cases #1 to #5 where the A / B value is between 0.002 and 0.2, the maximum electric field is maintained without significant difference at levels ranging from 13.18 to 13.20 V / μm.

[0068] On the other hand, in the case of #6, where the A / B value is 1.0, the maximum electric field was shown to be 14.25 V / μm, which is approximately 7.35% higher than that of #1 to #5, while electric field distortion occurred.

[0069] Furthermore, in the case of #7, where the A / B value is 1.25, the electric field distortion was greater than in #6, while the maximum electric field was shown to be 15.48 V / μm, which is approximately 14.72% higher than in #1 to #5.

[0070] [Table 2]

[0071] Table 2 shows the case where the dielectric layer thickness is 0.4 μm. Referring to Table 2, it can be confirmed that for #8 to #12, where the A / B value is between 0.0016 and 0.5, the maximum electric field is maintained without significant difference at levels ranging from 32.95 to 33.00 V / μm.

[0072] On the other hand, in the case of #13, where the A / B value is 1.0, the maximum electric field was shown to be 35.62 V / μm, which is approximately 7.35% higher than that of #8 to #12, while electric field distortion occurred.

[0073] Furthermore, in the case of #14, where the A / B value is 1.25, the electric field distortion was greater than in #13, while the maximum electric field was shown to be 38.76 V / μm, which is approximately 14.86% higher than in #8 to #12.

[0074] Therefore, the multilayer capacitor of this embodiment has the characteristics of a small, high-capacitance product with a thin dielectric layer, and by making the A / B value less than 1.0, it is possible to provide a multilayer capacitor with stable electric field characteristics while preventing a decrease in the capacitance of the multilayer capacitor and suppressing the generation of electric field distortion.

[0075] Furthermore, if the A / B value is less than 0.0016, the overlapping area of ​​adjacent internal electrodes decreases, accompanied by a decrease in capacitance. Therefore, it is preferable to set the A / B value to 0.0016 or greater.

[0076] Referring to Figure 6, the mounting substrate for the multilayer electronic component according to this embodiment includes a substrate 210 having first and second electrode pads 221 and 222 on one surface, and a multilayer capacitor 100 mounted on the upper surface of the substrate 210 such that the first and second tin plating layers 133 and 143 of the first and second external electrodes 131 and 141 are connected to the first and second electrode pads 221 and 222, respectively.

[0077] In this embodiment, the multilayer capacitor 100 is shown and described in relation to how it is mounted on the substrate 210 using solder 231 and 232, but conductive paste can be used instead of solder if necessary.

[0078] Although embodiments of the present invention have been described in detail above, it will be clear to those with ordinary skill in the art that the scope of the present invention is not limited thereto, and that various modifications and variations are possible within the scope of the technical idea of ​​the present invention as described in the claims. [Explanation of Symbols]

[0079] 100 Multilayer Capacitors 110 Capacitor body 111 Dielectric layer 112, 113 Cover 121, 122 First and second internal electrodes 131, 141 First and second external electrodes 132, 142 First and second nickel plating layers 133, 143 First and second tin plating layers 210 circuit boards 221, 222 First and second pads 231, 232 solder

Claims

1. A capacitor body including a dielectric layer and a plurality of first and second internal electrodes, The capacitor body includes first and second external electrodes, which are respectively positioned at both ends and connected to the exposed portions of the first and second internal electrodes, When the thickness of the dielectric layer is defined as A and the average length of the margin in the longitudinal direction of the capacitor body is defined as B, then A is 1 μm or less and A / B satisfies 0.04 ≤ A / B < 1. The thickness of the first and second internal electrodes is 0.4 μm or less. Multilayer capacitor.

2. The capacitor body includes first and second surfaces facing each other, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces, The multilayer capacitor according to claim 1, wherein the first and second internal electrodes are arranged such that one end of each electrode is alternately exposed on the third and fourth surfaces of the capacitor body, with a dielectric layer in between.

3. The first and second external electrodes are, First and second connection parts are formed on the third and fourth surfaces of the capacitor body, respectively, and are connected to the exposed portion of the internal electrode. A multilayer capacitor according to claim 1 or 2, comprising, respectively, first and second band portions extending from the first and second connection portions to a part of the first surface of the capacitor body.

4. The plating layer further includes a layer formed to cover the first and second external electrodes, The multilayer capacitor according to any one of claims 1 to 3, wherein the plating layer comprises a nickel plating layer and a tin plating layer.

5. The multilayer capacitor according to any one of claims 1 to 4, wherein the thickness of the dielectric layer is 1 μm and A / B satisfies 0.04 ≤ A / B ≤ 0.

2.

6. The multilayer capacitor according to any one of claims 1 to 4, wherein the thickness of the dielectric layer is 0.4 μm and A / B satisfies 0.04 ≤ A / B ≤ 0.

5.

7. A substrate having first and second electrode pads on one surface, A mounting substrate for a multilayer capacitor, comprising a multilayer capacitor according to any one of claims 1 to 6, wherein the first and second external electrodes are mounted on the first and second electrode pads, respectively.

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