Electronic component, circuit board device, and method of manufacturing an electronic component

Abstract

This invention relates to electronic components, circuit board assemblies, and methods of manufacturing electronic components. The electronic component includes a component body and at least one external electrode thereon. The component body includes a dielectric and an internal electrode. Each external electrode includes a base layer connected to the internal electrode. The base layer is formed on multiple surfaces of the component body and comprises a metal and a first comaterial mixed with the metal. Each external electrode also includes a plating layer formed on at least one surface of the base layer. Each external electrode further includes an oxide layer formed on one or more surfaces of the base layer other than the surface on which the plating layer is formed. The oxide layer has a surface layer formed of an oxide film of the metal of the base layer and a second comaterial.

Description

Technical Field

[0001] The present invention relates to an electronic component, a circuit board assembly, and a method for manufacturing the electronic component. Background Technology

[0002] When there is a need to reduce the size of electronic devices, external electrodes are typically formed on the component body, which contains internal electrodes, to reduce the mounting area of ​​electronic components. These external electrodes are then soldered to a circuit board, allowing the electronic components to be mounted onto the board.

[0003] External electrodes can be formed not only on the mounting surface of the component body, but also on the side and top surfaces of the component body. In this configuration, wet solder may move upwards along the side of the external electrodes, resulting in an increased mounting area.

[0004] To prevent wet solder from moving upwards along the side of the terminal electrode, JP-2014-53599A discloses a structure in which the side portions of the first and second terminal electrodes formed on the side of the electronic component are covered with an oxide film. Summary of the Invention

[0005] However, if the side portion of the terminal electrode is covered by an oxide film, and mechanical stress is applied to the oxide film, the oxide film may peel off along the interface between the terminal electrode and the oxide film. The oxide film may suddenly peel off over a large area of ​​the terminal electrode.

[0006] One object of the present invention is to provide an electronic component in which an oxide layer formed on an external electrode is difficult to peel off from the external electrode. Another object of the present invention is to provide a method for manufacturing such an electronic component. Yet another object of the present invention is to provide a circuit board assembly in which an oxide layer formed on the external electrode of an electronic component mounted on a circuit board is difficult to peel off from the external electrode.

[0007] According to a first aspect of the present invention, an electronic component is provided, comprising a component body and at least one external electrode. The component body has a dielectric and an internal electrode. Each external electrode includes a base layer connected to the internal electrode. The base layer is formed on a plurality of surfaces of the component body and comprises a metal and a first comaterial mixed with the metal. Each external electrode further includes a plating layer formed on at least one surface of the base layer. Each external electrode further includes an oxide layer formed on one or more surfaces of the base layer other than the surface on which the plating layer is formed. The oxide layer has a surface layer formed of an oxide film of the metal of the base layer and a second comaterial.

[0008] The first common material contained in the base layer and the second common material contained in the oxide layer can have the same composition.

[0009] The main component of the dielectric can be oxide ceramic.

[0010] The first comaterial contained in the substrate layer and the second comaterial contained in the oxide layer may have the same composition as the main components of the dielectric.

[0011] From the base layer to the oxide layer, the first comaterial can extend to the second comaterial, and the first and second comaterials can have a continuous crystalline or amorphous structure.

[0012] The metal in the base layer can exist in the form of crystalline or amorphous particles, and the first comaterial can also exist in the form of crystalline or amorphous particles, so that the particles of the metal in the base layer and the particles of the first comaterial exist mixed together.

[0013] The main component of the dielectric can be barium titanate.

[0014] An oxide layer can be formed on at least a portion of the side surface of the substrate and on the surface opposite to the surface on which the coating is formed.

[0015] The ratio of the second common material on the surface of the oxide layer can be in the range of 20 at% to 75 at%.

[0016] The base layer metal may be a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au and Sn.

[0017] The first co-material may be selected from at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, and titanium oxide.

[0018] From the surface of the oxide layer, the oxide layer may include nickel oxide and barium titanate.

[0019] From the surface of the oxide layer, it can also contain compounds containing nickel, magnesium, and oxygen.

[0020] The component body may have a laminate, wherein at least one first internal electrode layer and at least one second internal electrode layer are alternately laminated separated by a dielectric. The at least one external electrode may include a first external electrode and a second external electrode, disposed on opposite sides of the laminate, such that the first external electrode is spaced apart from the second external electrode. The first internal electrode layer may be connected to the first external electrode, and the second internal electrode layer may be connected to the second external electrode.

[0021] The coating can be formed on one of the surfaces of the base layer, the surface extending perpendicular to the stacking direction of the first internal electrode layer, the second internal electrode layer and the dielectric.

[0022] According to a second aspect of the invention, a circuit board apparatus is provided, wherein the aforementioned electronic components are mounted on a circuit board, and the electronic components are connected to the circuit board via a solder layer attached to a plating layer on the electronic components.

[0023] According to a third aspect of the invention, a method for manufacturing an electronic component is provided. The method includes forming a component body comprising a dielectric and internal electrodes. The method further includes applying a mixed material obtained by mixing a co-material with a metal-containing electrode material to two opposing sides of the component body and an edge surface of adjacent sides of the component body. The method further includes sintering the mixed material and forming a base layer on the opposing sides of the component body and the edge surface of the component body where the metal and co-material are mixed. The method further includes oxidizing the metal of the base layer and forming an oxide film of the metal on a plurality of faces of the base layer. The method further includes removing the oxide film from at least one of the plurality of faces of the base layer while leaving the oxide film on at least a portion of the edge surface of the component body. The method further includes forming a plating layer on at least one of the plurality of faces of the base layer where the oxide film has been removed.

[0024] The step of removing oxide film from at least one of a plurality of surfaces of a substrate may include: sandblasting oxide film from at least one of a plurality of surfaces of a substrate to polish the surface of the substrate.

[0025] The steps of forming the component body may include: forming a sheet containing dielectric ceramic as the main component; and applying a conductive paste containing a base layer of metal onto the sheet. The component body may be sintered in the step of sintering the mixed materials.

[0026] According to one aspect of the invention, the oxide layer formed on each external electrode is difficult to peel off from the external electrode. Attached Figure Description

[0027] Figure 1 This is a perspective view showing the structure of a multilayer ceramic capacitor according to a first embodiment of the present invention.

[0028] Figure 2 By longitudinal cutting Figure 1 The cross-sectional view obtained from the multilayer ceramic capacitor.

[0029] Figure 3A yes Figure 2 Enlarged cross-sectional view of the EA section of the external electrode.

[0030] Figure 3B yes Figure 2 Enlarged cross-sectional view of the EB portion of the external electrode.

[0031] Figure 4 It is shown Figure 2A schematic diagram of an exemplary composition of the surface of the oxide layer of the external electrode shown.

[0032] Figure 5 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to a second embodiment of the present invention.

[0033] Figure 6A This is a cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0034] Figure 6B This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0035] Figure 6C This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0036] Figure 6D This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0037] Figure 6E This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0038] Figure 6F This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0039] Figure 6G This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0040] Figure 6H This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0041] Figure 6I This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0042] Figure 6J This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0043] Figure 7A It is shown Figure 6I A floor plan of an exemplary process.

[0044] Figure 7B By longitudinal cutting Figure 7A The cross-sectional view was obtained from the structure.

[0045] Figure 8This is a cross-sectional view showing the construction of a circuit board assembly for mounting multilayer ceramic capacitors on a circuit board according to a third embodiment.

[0046] Figure 9 This is a cross-sectional view showing the construction of a multilayer ceramic capacitor according to the fourth embodiment.

[0047] Figure 10 This is a perspective view showing the structure of the electronic component according to the fifth embodiment.

[0048] Figure 11 This is a perspective view showing the structure of the electronic component according to the sixth embodiment. Detailed Implementation

[0049] Embodiments of the invention will now be described with reference to the accompanying drawings. These embodiments are not intended to limit the invention. Combinations of all features described in each embodiment are not always necessary for the invention. The construction of each embodiment can be modified and / or changed according to the design, specifications, and various conditions (usage conditions, usage environment, etc.) of the devices and apparatus to which the invention is applied. The scope of the invention is defined by the appended claims and is not limited to the following embodiments. Furthermore, for the purpose of easier understanding of the parts, components, and elements, the parts, components, and elements shown in the drawings used in conjunction with the following description may differ in structure, proportion, and shape from actual parts, components, and elements.

[0050] First Embodiment

[0051] Figure 1 This is a perspective view showing the structure of a multilayer ceramic capacitor 1A according to a first embodiment of the present invention. Figure 2 Is Figure 1 The longitudinal acquisition of a 1A multilayer ceramic capacitor. Figure 1 Cross-sectional view of a 1A multilayer ceramic capacitor.

[0052] exist Figure 1 and Figure 2 In this multilayer ceramic capacitor 1A, there is a component body (component assembly) 2, an external electrode (outer electrode) 6A, and another external electrode (outer electrode) 6B. The component body 2 has a stack (or layer) 2A, a lower cover layer 5A, and an upper cover layer 5B. The stack 2A has multiple internal electrode layers 3A, multiple other internal electrode layers 3B, and multiple dielectric layers 4.

[0053] The bottom layer of the stack 2A is covered by a lower cover layer 5A, and the top layer of the stack 2A is covered by an upper cover layer 5B. Multiple internal electrode layers 3A and 3B are alternately stacked, separated by multiple dielectric layers 4. The shape of the component body 2 can be a substantially rectangular parallelepiped shape, and the shape of the stack 2A can also be a substantially rectangular parallelepiped shape. The component body 2 can be chamfered along its edges. In the following description, the direction in which the two sides of the component body 2 face each other can be referred to as the longitudinal direction DL, the direction in which the front and rear surfaces of the component body 2 face each other can be referred to as the width direction DW, and the direction in which the top and bottom surfaces of the component body 2 face each other can be referred to as the stacking direction DS.

[0054] External electrodes 6A and 6B are located on opposite sides of the element body 2. External electrodes 6A and 6B are spaced apart from each other. Each of external electrodes 6A and 6B extends continuously from the side of the element body 2 to the front and rear surfaces, as well as the top and bottom surfaces.

[0055] Along the longitudinal direction DL, internal electrode layers 3A and 3B are alternately arranged at different positions within the laminate 2A. Internal electrode layer 3A may be arranged on one side of the component body 2 relative to internal electrode layer 3B, and internal electrode layer 3B may be arranged on the opposite side of the component body 2 relative to internal electrode layer 3A. The end of internal electrode layer 3A is led out to the left end of the corresponding dielectric layer 4 on one side (right side) of the component body 2 along the longitudinal direction DL and is connected to the external electrode 6A. The end of internal electrode layer 3B is led out to the right end of the dielectric layer 4 on the other side of the component body 2 along the longitudinal direction DL and is connected to the external electrode 6B.

[0056] On the other hand, in a direction perpendicular to the direction (length direction DL) opposite to the sides of the component body 2 (width direction DW), the ends of the internal electrode layers 3A and 3B are covered by the dielectric layer 4. In the width direction DW, the position of the end of the internal electrode layer 3A can be aligned with the position of the end of the internal electrode layer 3B.

[0057] The external dimensions of the multilayer ceramic capacitor 1A have, for example, the following values: a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm. The thickness of each of the internal electrode layer 3A, the internal electrode layer 3B, and the dielectric layer 4 in the stacking direction DS can be in the range of 0.05 μm to 5 μm, for example, 0.3 μm.

[0058] The materials of the internal electrode layers 3A and 3B can be selected from metals such as Cu (copper), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), and can be alloys containing these metals.

[0059] The main component of the dielectric layer 4 is, for example, a ceramic material with a perovskite structure. The content of the main component can be 50 at% or more. The ceramic material of the dielectric layer 4 can be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, and titanium oxide.

[0060] The main components of the materials of the lower cover layer 5A and the upper cover layer 5B can be, for example, ceramic materials. The main components of the ceramic materials of the lower cover layer 5A and the upper cover layer 5B can be the same as the main components of the ceramic material of the dielectric layer 4.

[0061] like Figure 1 and Figure 2 As shown, external electrodes 6A and 6B are spaced apart from each other in the length direction DL and are formed on multiple surfaces of the component body 2. Each of the external electrodes 6A and 6B has a mounting surface M1 and a top surface M3 facing each other in the stacking direction DS, a side surface M2, a front surface M4 and a rear surface M4 facing each other in the width direction DW. Each of the external electrodes 6A and 6B includes a base layer (bottom layer) 7 and a plating layer 9 on the mounting surface M1. The side surface M2 of the external electrode 6A faces the side surface M2 of the external electrode 6B in the length direction DL. The mounting surface M1 is the surface facing the circuit board on which the multilayer ceramic capacitor 1A is mounted. The mounting surface M1 is provided on the lower surface of the component body 2. The thickness of each of the external electrodes 6A and 6B on the mounting surface M1 in the stacking direction DS is, for example, in the range of 10 μm to 40 μm.

[0062] A substrate layer 7 is formed on each of the external electrodes 6A and 6B, excluding the mounting surface M1 (i.e., side surface M2, top surface M3, front surface M4, and rear surface M4), and an oxide layer 8 is formed on the surface of the substrate layer 7. The substrate layer 7 is continuously formed on the element body 2, such that the substrate layer 7 exists on the side surface M2 and extends from the side surface M2 to the mounting surface M1. The substrate layer 7 also extends from the side surface M2 to the top surface M3, front surface M4, and rear surface M4.

[0063] The substrate layer 7 comprises a metal as a conductive material. For example, the metal of the substrate layer 7 includes at least one metal or an alloy thereof selected from the group consisting of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn as its main component. The substrate layer 7 also includes particles of a co-material. The co-material reduces the difference in the coefficients of thermal expansion between the device body 2 and the substrate layer 7 and alleviates the stress applied to the substrate layer 7. The co-material is, for example, a ceramic component that is the main component of the dielectric layer 4. The substrate layer 7 may contain a glass component. The glass component is used for densification of the substrate layer 7, etc. The glass component is, for example, an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron). The substrate layer 7 is electrically connected to a plurality of internal electrode layers that are led out to the sides of the device body.

[0064] The oxide layer 8 comprises an oxide film of a metal used as the conductive material of the substrate layer 7 and a co-material used as the substrate layer 7. The co-material of the substrate layer 7 may have the same composition as the dielectric layer 4, such as barium titanate. The metal used as the conductive material of the substrate layer 7 is, for example, nickel. The oxide film of the metal used as the conductive material of the substrate layer 7 is, for example, nickel oxide, and its thickness is, for example, in the range of 0.05 μm to 3 μm.

[0065] Each of the substrate layer 7 and the oxide layer 8 may have a metallic component contained in the element body 2. The metallic component contained in the element body 2 may include at least one of Mg, Ni, Cr, Sr, Al, Na, and Fe. For example, the metallic component contained in the element body 2 is Mg. If the metallic component is Mg, then each of the substrate layer 7 and the oxide layer 8 may include a metal used as a conductive material for the substrate layer 7, a metal contained in the element body 2, and a compound of oxygen. For example, the compound contained in each of the substrate layer 7 and the oxide layer 8 may include Ni, Mg, and O.

[0066] The main component of the coating 9 is, for example, a metal, such as Cu, Ni, Al, Zn, and Sn, or an alloy containing at least two of Cu, Ni, Al, Zn, and Sn. The coating 9 can be a coating of a single metal component, or it can include multiple coatings of different metal components. For example, as... Figure 2As shown, plating layer 9 can have a three-layer structure, namely, plating layer 9 can include a Cu plating layer 9A formed on the base layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. Cu plating layer 9A can improve the adhesion between plating layer 9 and the base layer 7. Ni plating layer 9B can improve the heat resistance of external electrodes 6A and 6B during soldering. Sn plating layer 9C can improve the wettability of solder on plating layer 9. Plating layer 9 is formed on a portion of the base layer 7, such that plating layer 9 is electrically connected to the internal electrode layer. For example, plating layer 9 can be formed on a surface of the base layer 7 extending in a direction perpendicular to the stacking direction DS. Furthermore, plating layer 9 is electrically connected to the terminals of the circuit board via solder. Incidentally, when the metal composition of the base layer 7 is Cu, Cu plating layer 9A may not be formed. If the Cu coating 9A is not formed, the coating 9 can have a two-layer structure, that is, the coating 9 can include a Ni coating 9B and a Sn coating 9C formed on the Ni coating 9B.

[0067] Figure 3A It is shown Figure 2 The enlarged cross-sectional view of the EA portion of the external electrode 6B shown. Figure 3B It is shown Figure 2 A cross-sectional view showing an enlarged view of the EB portion of the external electrode 6B. External electrode 6A has the same structure as external electrode 6B.

[0068] like Figure 3A and Figure 3B As shown, conductor 12 and co-material 11 exist in a mixed manner in the substrate layer 7. The main component of conductor 12 is a metal or alloy thereof including at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au and Sn. Co-material 11 is, for example, an oxide ceramic that is the main component of dielectric layer 4.

[0069] like Figure 3A As shown, an oxide film 8A is coated on the surface of the conductor 12 of the base layer 7 on the side surface M2, upper surface M3, front surface M4, and rear surface M4 of each external electrode 6A and 6B. The oxide film 8A is an oxide film of the metal or alloy used in the conductor 12. The oxide film 8A is segmented by co-material particles 11 present up to the surface of the base layer 7. The oxide layer 8 can be configured to include the oxide film 8A and a surface layer defined by the co-material particles 11.

[0070] on the other hand, Figure 3B A base layer 7 on the mounting surface M1 is shown, which is manufactured by the method described below. Figure 3BAs shown, an oxide film 8A is not formed on the surface of the conductor 12 exposed from the substrate layer 7 on the mounting surface M1 of the external electrodes 6A and 6B. Instead, a plating layer 9 is formed on the substrate layer 7. Thus, the conductor 12 and the plating layer 9 are connected to each other, ensuring the conductivity of the mounting surface M1 of the external electrodes 6A and 6B.

[0071] exist Figure 3A In this process, a nickel oxide film 8A is formed on the conductor 12. In the depth direction of the substrate layer 7, co-material particles 11 and the conductor 12 are mixed in an immersion pattern. The co-material particles 11 are distributed in the form of irregular islands within the conductor 12. The co-material 11 exists continuously from the oxide layer 8 to the substrate layer 7 and can have a continuous crystalline or amorphous structure. Similarly, the conductor 12 exists continuously from the oxide layer 8 to the substrate layer 7 and can have a continuous crystalline or amorphous structure.

[0072] Figure 4 schematically shown Figure 2 An exemplary composition of the surface of the oxide layer 8. Figure 4 An example is shown where the metal for conductor 12 in substrate 7 is Ni, the oxide ceramic for common material 11 is barium titanate (BaTiO3), and the oxide film 8A is nickel oxide.

[0073] exist Figure 4 In this process, co-material 11 and oxide film 8A are mixed on the surface of oxide layer 8. Co-material 11 and oxide film 8A exist in the form of crystalline or amorphous particles, such that the particles of co-material 11 are dispersed within the particles of oxide film 8A. The co-material particles 11 are distributed in the form of islands across the entire surface of oxide layer 8. Along the long axis, the size (length) of a single particle of co-material 11 ranges from 0.1 μm to 8 μm. Compound 13 of Mg, Ni, and O is separated as particles on the surface of oxide layer 8. When... Figure 4 As shown, when observing oxide layer 8 from the surface, the ratio of co-material to the overall composition ranges from 20 at% to 75 at%. This can be confirmed, for example, by surface analysis of a sufficiently large area using EDX (energy-dispersive X-ray spectroscopy). The area is large enough to represent the surface composition of oxide layer 8.

[0074] The co-material 11 extends from the surface of the oxide layer 8 through the substrate layer 7 into the device body 2. The co-material 11 is made of multiple particles aggregated to a size of approximately 1 μm to 40 μm and can be distributed along the depth direction. Therefore, even when mechanical stress is applied to the oxide layer 8, the co-material 11 exposed on the surface of the oxide layer 8 hardly peels off. When mechanical stress is applied to the oxide layer 8, the co-material 11 can act as a support for penetrating into the oxide layer 8 and supporting the oxide layer 8 on the substrate layer 7.

[0075] The common material 11 is exposed on the surface of the oxide layer 8 and splits the oxide film 8A made of nickel oxide. Therefore, even when mechanical stress is applied to the oxide layer 8 and the oxide film 8A made of nickel oxide is peeled off from the conductor 12, the peeling process of the oxide film 8A is prevented at the location of the common material 11 exposed on the surface of the oxide layer 8.

[0076] Therefore, even when mechanical stress is applied to the oxide layer 8, the possibility of the entire oxide layer 8 breaking immediately can be reduced, and the possibility of the oxide film 8A (oxide layer 8) peeling off from the external electrodes 6A and 6B can be reduced.

[0077] Since the oxide layer 8 comprises particulate compounds 13 of Mg, Ni, and O, the adhesion strength between the oxide layer 8 and the substrate layer 7 can be improved. Therefore, the possibility of the oxide layer 8 peeling off from the external electrodes 6A and 6B can be further reduced.

[0078] According to the first embodiment described above, the oxide layer 8 comprises an oxide film of a metal used as the conductive material of the base layer 7 and a common material of the base layer 7. Therefore, it is possible to suppress the oxide layer 8 from peeling off from each of the external electrodes 6A and 6B. Since the multilayer ceramic capacitor 1A has a nearly non-peeling oxide layer 8 on the surfaces of the side surface M2, upper surface M3, front surface M4, and rear surface M4 of each of the external electrodes 6A and 6B, wet solder will not move upwards onto the surfaces of the external electrodes 6A and 6B other than the mounting surface M1, and the mounting of the capacitor 1A (electronic component) by soldering can be performed in a stable manner.

[0079] Second Embodiment

[0080] Figure 5 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor. The method for manufacturing a multilayer ceramic capacitor will be described as a second embodiment of the present invention. Figures 6A to 6J These are a series of cross-sectional views illustrating an exemplary method of manufacturing a multilayer ceramic capacitor according to a second embodiment. Incidentally, for illustrative purposes, Figures 6C to 6J Only two internal electrode layers 3A and two internal electrode layers 3B are shown, which are alternately stacked with a dielectric layer 4 in between.

[0081] exist Figure 5In step S1, an organic binder and an organic solvent, acting as dispersants and molding aids, are added to the dielectric material powder, which is then pulverized and mixed to produce a slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may include one or more additives. Additives may be, for example, oxides of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si, or glass. The organic binder is, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0082] Next, as Figure 5 Step S2 is shown and as follows Figure 6A As shown, green sheets 24 are manufactured. Specifically, a slurry containing ceramic powder is applied in sheet form onto a carrier film and dried to manufacture green sheets 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The slurry is applied, for example, by a doctor blade method, a die coating machine method, or a gravure coating machine method. Step S2 is repeated to prepare multiple green sheets 24.

[0083] Then, as Figure 5 Step S3 is shown and as follows Figure 6B As shown, the conductive paste, which will become the internal electrode, is applied in a predetermined pattern to each of the green sheets 24 prepared in step S1, and the conductive paste will form Figure 1 The internal electrode layers 3A and 3B are shown to form a plurality of internal electrode patterns 23 on the green sheet 24. In step S3, a plurality of internal electrode patterns 23 can be formed on a single green sheet 24 such that the internal electrode patterns 23 are separated from each other in the longitudinal direction of the green sheet 24. The conductive paste for the internal electrodes includes metal powder used as the material for the internal electrode layers 3A and 3B. For example, if the metal used as the material for the internal electrode layers 3A and 3B is Ni, then the conductive paste for the internal electrodes includes Ni powder. In addition, the conductive paste for the internal electrodes includes a binder, a solvent, and (if necessary) auxiliary agents. The conductive paste for the internal electrodes may include a ceramic material as a co-material, which is a major component of the dielectric layer 4. The application of the conductive paste for the internal electrodes can be carried out by a screen printing method, an inkjet printing method, or a gravure printing method. Therefore, step S3 can be referred to as a printing step. In this way, a plurality of green sheets 24 having internal electrode patterns 23 thereon are prepared.

[0084] Next, as Figure 5 Step S4 is shown and as follows Figure 6CAs shown, a green sheet 24 having an internal electrode pattern 23 formed thereon and a green sheet 24A without an internal electrode pattern 23 formed thereon are stacked in a predetermined order to form a block 25 of green sheet 24. The green sheet 24A without an internal electrode pattern 23 formed thereon serves as an outer layer. In step S4, the green sheets 24 having internal electrode patterns 23 are divided into two groups, namely, green sheets 24 having internal electrode patterns 23A and green sheets 24 having internal electrode patterns 23B. Then, the green sheets 24 having internal electrode patterns 23A and green sheets 24 having internal electrode patterns 23B are stacked alternately along the stacking direction, such that the internal electrode patterns 23A on the green sheet 24 and the internal electrode patterns 23B on the next or adjacent green sheet 24 alternately change along the longitudinal direction of the green sheet 24. In addition, three types of portions are defined in the green sheet block 25. Specifically, the following are defined in the green sheet block 25: a portion in which only the internal electrode pattern 23A is stacked in the stacking direction, a portion in which the internal electrode patterns 23A and 23B are stacked alternately in the stacking direction, and a portion in which only the internal electrode pattern 23B is stacked in the stacking direction.

[0085] Next, as Figure 5 Step S5 is shown and Figure 6D As shown, suppressed in Figure 5 The laminate 25 obtained in step S4 causes the green sheet 24 to be pressed together. The pressing of the laminate 25 can be carried out, for example, by sandwiching the laminate 25 between resin films and applying hydrostatic pressure to the laminate 25.

[0086] Then, as Figure 5 Step S6 is shown and Figure 6E As shown, the pressed stacked block 25 is cut, separating it into multiple component bodies, each component body having a rectangular parallelepiped shape. Each component body has six faces. As indicated by the multiple vertical dashed lines 27, the cutting of the stacked block 25 is performed at portions where only the internal electrode pattern 23A exists in the stacking direction and portions where only the internal electrode pattern 23B exists in the stacking direction. The cutting of the stacked block 25 is performed, for example, by blade cutting or a similar method. The resulting component body 2 is as follows. Figure 6F As shown.

[0087] like Figure 6F As shown, in each of the component bodies 2, internal electrode layers 3A and 3B are alternately stacked with a dielectric layer 4 in between. Internal electrode layer 3A is exposed on one side of each component body 2, and internal electrode layer 3B is exposed on the other side of each component body 2.

[0088] Next, as Figure 5 As shown in step S7, remove in Figure 5The adhesive contained in each component body 2 obtained in step S6. For example, the adhesive is removed by heating the component body 2 in a N2 atmosphere at approximately 350°C.

[0089] Next, as Figure 5 As shown in step S8, the conductive paste for the substrate (bottom layer) 7 is applied to the substrate. Figure 5 In step S7, the adhesive is removed from the two sides of each component body 2, as well as the edges of the remaining four sides of the component body 2 adjacent to these two sides. Then, the conductive paste is dried. The conductive paste for the substrate layer 7 includes metal powder or filler used as the conductive material of the substrate layer 7. For example, when the metal used as the conductive material of the substrate layer 7 is Ni, the conductive paste for the substrate layer includes Ni powder or filler. Furthermore, the conductive paste for the substrate layer includes, for example, a ceramic component as a major component of the dielectric layer 4 as a co-material. For example, oxide ceramic particles (D50 particle size of 0.8 μm to 4 μm) with barium titanate as the main component are mixed in the conductive paste for the substrate layer in the range of 10 wt% to 40 wt%. Additionally, the conductive paste for the substrate layer includes an adhesive and a solvent.

[0090] Next, as Figure 5 Step S9 is shown and as follows Figure 6G As shown, on it at Figure 5 In step S8, the component body 2, to which conductive paste for the substrate layer is applied, undergoes a sintering process, such that in each component body 2, the internal electrode layers 3A and 3B are integrated with the dielectric layer 4, and the substrate layer 7 is formed and integrated with the component body 2. The sintering of the component body 2 is carried out, for example, in a firing furnace at a temperature range of 1000°C to 1350°C for 10 minutes to 2 hours. If a base metal such as Ni or Cu is used as the material for the internal electrode layers 3A and 3B, the sintering process can be carried out in a firing furnace while the interior of the firing furnace is maintained in a reducing atmosphere to prevent oxidation of the internal electrode layers 3A and 3B.

[0091] Next, as Figure 5 Step S10 is shown and as follows Figure 6H As shown, the metal exposed on the surface of each substrate layer 7 is oxidized to form an oxide layer 8 on the surface of the substrate layer 7, which includes an oxide film of the metal and the common material of the substrate layer 7. In the oxidation of the metal exposed on the surface of each substrate layer 7, a re-oxidation process can be performed, for example, in a N2 atmosphere at 600°C to 1000°C. Incidentally, to ensure that the oxide film of the metal exposed on the surface of each substrate layer 7 forms to a sufficient thickness, oxygen can be added to the atmosphere gas of the re-oxidation process.

[0092] Next, as Figure 5As shown in step S11, the four surfaces (i.e., side surface M2, top surface M3, front surface M4, and rear surface M4) of each substrate layer 7, excluding the mounting surface M1, are coated with an anti-corrosion resin. The coating of the anti-corrosion resin is performed, for example, by applying the anti-corrosion resin with a transfer roller and then heat-curing the anti-corrosion resin.

[0093] Next, as Figure 5 Step S12 is shown and as follows Figure 6I As shown, the oxide film is removed from the mounting surface M1 of each substrate layer 7 by sandblasting (sandblasting polishing) to expose the metal contained in the mounting surface M1 of the substrate layer 7. During sandblasting, the component body 2 is placed in the sandblasting apparatus with the mounting surface M1 facing upwards, and then the sandblasting medium is applied to the mounting surface M1 from directly above the component body 2. The sandblasting medium applied from directly above the component body 2 surrounds the sides of the component body 2, but the sides M2, top surface M3, front surface M4, and rear surface M4 of each of the two substrate layers 7 are covered with resist resin. Therefore, the oxide film can be retained on the sides M2, top surface M3, front surface M4, and rear surface M4 of each substrate layer 7. After sandblasting, the resist resin is removed with solvents or the like.

[0094] Next, as Figure 5 Step S13 is shown and as follows Figure 6J As shown, a plating layer 9 is formed on the mounting surface M1 of each substrate layer 7. During the formation of the plating layer 9, for example, Cu, Ni, and Sn plating can be performed sequentially. In this process, the component body 2, with the oxide film removed from the mounting surface M1 of each substrate layer 7, is placed in a tank along with the plating solution, and power is supplied to the tank while it is rotating, thereby forming the plating layer 9. During this process, the oxide film is present on the side surface M2, top surface M3, front surface M4, and rear surface M4 of each substrate layer 7, therefore no plating layer is formed on these surfaces.

[0095] Figure 7A It is shown Figure 6I A floor plan of an exemplary process. Figure 7B It is achieved by cutting along the length direction DL. Figure 7A The obtained cross-sectional view.

[0096] exist Figure 7A and Figure 7B In this process, multiple component bodies 2 are placed on a substrate 31, each component body 2 including an oxide film 8 formed on the surface of each substrate layer 7. When the component body 2 is placed on the substrate 31, the upper surface M3 of each component body 2 is attached to the substrate 31 by a fixing strap 32, such that the mounting surface M1 of each component body 2 faces upward. Then, a blasting medium 34 is applied (blasted) to the component body 2 from a nozzle 33 mounted above the component body 2. The blasting medium 34 is, for example, particles made of zircon or alumina.

[0097] The main settings for sandblasting conditions are sandblasting speed, sandblasting volume, and sandblasting area. The sandblasting speed is adjusted by the pressure and path of the sandblasting medium 34. The sandblasting volume is adjusted based on the medium circulation and sandblasting time. The sandblasting area is adjusted by the shape of the nozzle 33 and the distance between the component body 2 and the nozzle 33.

[0098] During the sandblasting process, the side surface M2, top surface M3, front surface M4, and rear surface M4 of each substrate layer 7 are coated with anti-corrosion resin. Therefore, even when the sandblasting medium 34 ejected from the nozzle 33 wraps around the side surface of each component body 2, an oxide film remains on the side surface M2 and top surface M3 of each substrate layer 7, while the oxide film is removed from the mounting surface M1 of each substrate layer 7. Incidentally, the amount of oxide film removed (sandblasted) from the mounting surface M1 of the substrate layer 7 can be set to a value or range that allows a coating 9 to be formed on the mounting surface M1 of the substrate layer 7.

[0099] According to the second embodiment described above, the ceramic component, which is the main component of the dielectric layer 4, is mixed in the conductive paste used for the substrate layer. Therefore, an oxide film comprising a metal serving as the conductive material of the substrate layer 7 and an oxide layer 8 comprising an oxide of a metal serving as the common material of the substrate layer 7 can be formed on each substrate layer 7. Thus, a multilayer ceramic capacitor 1A can be manufactured that reduces or eliminates the possibility of the oxide layer 8 peeling off from the external electrodes 6A and 6B, while suppressing an increase in the number of manufacturing steps.

[0100] It should be noted that although the method of removing the oxide layer 8 on the mounting surface M1 of the external electrodes 6A and 6B by sandblasting has been described in the above embodiments, isotropic dry etching such as plasma etching can also be used instead of sandblasting, or chemical polishing (such as wet etching) can be used instead of sandblasting.

[0101] Third Embodiment

[0102] Figure 8 This is a cross-sectional view showing a circuit board assembly according to a third embodiment of the present invention. The circuit board assembly includes a circuit board 41 and a multilayer ceramic capacitor 1A mounted on the circuit board 41.

[0103] exist Figure 8In this circuit board 41, ground electrodes 42A and 42B are formed. Multilayer ceramic capacitor 1A is connected to ground electrodes 42A and 42B via solder layers 43A and 43B, which are respectively attached to tin plating layers 9C and 9C. An oxide layer 8 prevents the solder layer 43A from wetting (moving upwards) the side surface M2, top surface M3, front surface M4, and rear surface M4 of the external electrode 6A. Similarly, an oxide layer 8 prevents the solder layer 43B from wetting the side surface M2, top surface M3, front surface M4, and rear surface M4 of the external electrode 6B. Therefore, it is possible to prevent a decrease in the spacing between electronic components due to the solder layers 43A and 43B wetting the side surface M2 of the external electrodes 6A and 6B. This allows for an increase in the mounting density of electronic components on the circuit board 41.

[0104] Even when solder mounting on circuit board 41 is performed in a reducing atmosphere in a reflow oven, and the oxides of the metals exposed on the surface of each oxide layer 8 are reduced to metal, the co-material of each base layer 7 retains its state on the surface of the oxide layer 8. Therefore, it is possible to prevent the wet solder layer 43A from moving upward to the side M2 ​​and top surface M3 of the external electrode 6A, and to prevent the wet solder layer 43B from moving upward to the side M2 ​​and top surface M3 of the external electrode 6B.

[0105] Since the oxide layer 8 contains the same material as the base layer 7, its heat resistance is improved. Furthermore, since the same material as the base layer 7 is present from the base layer 7 to the surface of the oxide layer 8, its resistance to thermal history is improved.

[0106] According to the third embodiment described above, the oxide layer 8 is disposed on the side surface M2, the top surface M3, the front surface M4, and the rear surface M4 of each external electrode 6A and 6B. Therefore, the reliability of the multilayer ceramic capacitor 1A mounted on the circuit board 41 can be improved, while increasing the mounting density of electronic components on the circuit board 41.

[0107] Fourth embodiment

[0108] Figure 9 This is a cross-sectional view showing the structure of the multilayer ceramic capacitor 1B according to a fourth embodiment of the present invention. Figure 9 In the process, the multilayer ceramic capacitor 1B includes a component body 2 and two external electrodes 56A and 56B.

[0109] External electrodes 56A and 56B are located on opposite sides of the component body 2 and are separated from each other. Each of the external electrodes 56A and 56B extends from the side of the component body 2 to the front, rear, upper, and lower surfaces of the component body 2.

[0110] Each of the external electrodes 56A and 56B includes a base layer 7 and three plating layers 59A, 59B, and 59C. Each of the external electrodes 56A and 56B has a mounting surface M1, a side surface M2, a top surface M3, a front surface M4, and a rear surface M4. The mounting surface M1 is the surface facing the circuit board (41) on which the multilayer ceramic capacitor 1B is mounted. The top surface M3 is the surface opposite to the mounting surface M1. Although in Figure 9 Not shown in the text, but as Figure 8 As shown in the diagram, the multilayer ceramic capacitor 1B is mounted on the ground electrodes 42A and 42B on the circuit board 41.

[0111] The surface of each of the external electrodes 56A and 56B other than the mounting surface M1, side surface M2, front surface M4, and rear surface M4 (i.e., the upper surface M3) is coated with an oxide layer 58. The material of the oxide layer 58 is similar to... Figure 1 The oxide layer 8 shown is made of the same material. A Cu plating layer 59A, a Ni plating layer 59B, and a Sn plating layer 59C are sequentially formed on the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of the base layer 7 of each external electrode 56A and 56B.

[0112] According to the fourth embodiment described above, the top surface M3 of each of the external electrodes 56A and 56B is coated with an oxide layer 58. Furthermore, plating layers 59A, 59B, and 59C are formed on the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of each of the external electrodes 56A and 56B. Therefore, when in… Figure 8 When mounting the multilayer ceramic capacitor 1B on the circuit board 41, wet solder can be allowed to move upward (extend) along the side M2 ​​of each external electrode 56A and 56B, while preventing wet solder from moving upward onto the upper surface M3 of each external electrode 56A and 56B. Therefore, even when excessive solder is applied to the ground electrodes 42A and 42B, it is possible to suppress or prevent solder from extending outward (laterally) from the ground electrodes 42A and 42B, while preventing the total height of the circuit board 41 and the multilayer ceramic capacitor 1B mounted on the circuit board 41 from exceeding the design value. Therefore, the distance between electronic components mounted on the circuit board 41 can be reduced, while decreasing the possibility of short circuits between electronic components mounted on the circuit board 41. This enables the high-density mounting of electronic components.

[0113] Fifth embodiment

[0114] Figure 10 This is a perspective view showing the structure of an electronic component according to a fifth embodiment of the present invention. Figure 10 A chip inductor 61 is shown as an example of an electronic component.

[0115] exist Figure 10In this chip inductor 61, a component body 62 and two external electrodes 66A and 66B are included. The component body 62 has a coil pattern 63, internal electrode layers 63A and 63B, and magnetic material 64. The shape of the component body 62 may be a substantially rectangular parallelepiped shape. The external electrodes 66A and 66B are located on opposite sides of the component body 62 and are separated from each other. Each of the external electrodes 66A and 66B extends from the corresponding side of the component body 62 toward the front, rear, upper, and lower surfaces of the component body.

[0116] The coil pattern 63 and the internal electrode layers 63A and 63B are covered by magnetic material 64. However, the end of the internal electrode layer 63A protrudes from the magnetic material 64 on one side of the element body 62 and connects to the external electrode 66A. The end of the internal electrode layer 63B protrudes from the magnetic material 64 on the other side of the element body 62 and connects to the external electrode 66B.

[0117] The materials for coil pattern 63, internal electrode layer 63A, and internal electrode layer 63B can be metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or alloys containing these metals. Magnetic material 64 is, for example, ferrite.

[0118] Each of the external electrodes 66A and 66B includes a base layer 67 and a plating layer 69. Each of the external electrodes 66A and 66B has a mounting surface M1, a side surface M2, a top surface M3, a front surface M4, and a rear surface M4. The mounting surface M1 is the surface facing the circuit board on which the chip inductor 61 is mounted. The top surface M3 is the surface opposite to the mounting surface M1.

[0119] The main component of the conductive material of the substrate 67 may be, for example, a metal or alloy thereof including at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The substrate 67 includes a commensal material. The commensal material is, for example, a ceramic component that is the main component of the magnetic material 64. The substrate 67 may contain a glass component. For example, the glass component is an oxide of Ba, Sr, Ca, Zn, Al, Si, or B.

[0120] An oxide layer 68 is coated on all surfaces except the mounting surface M1 of each external electrode 66A and 66B (i.e., side surface M2, top surface M3, front surface M4, and rear surface M4). The oxide layer 68 comprises an oxide film of a metal serving as the conductive material of the substrate layer 67 and an oxide of a metal containing the common material of the substrate layer 67. A plating layer 69 is formed on the mounting surface M1 of the substrate layer 67 of each external electrode 66A and 66B. The substrate layer 67, oxide layer 68, and plating layer 69 can be respectively coated with… Figure 1 The base layer 7, oxide layer 8, and coating layer 9 are constructed in a similar manner.

[0121] According to the fifth embodiment described above, the oxide layer 68 comprises an oxide film of a metal serving as the conductive material of the base layer 67 and an oxide containing a metal serving as the common material of the base layer 67. Therefore, it is possible to prevent wet solder from moving upwards to the surfaces of the external electrodes 66A and 66B on which the oxide layer 68 is formed. Furthermore, it is possible to suppress or prevent the oxide layer 68 from peeling off from the external electrodes 66A and 66B.

[0122] Sixth Embodiment

[0123] Figure 11 This is a perspective view showing the structure of an electronic component according to a sixth embodiment of the present invention. Figure 11 A chip resistor 71 is shown as an example of an electronic component.

[0124] exist Figure 11 In this embodiment, the chip resistor 71 includes a component body 72, two external electrodes 76A and 76B, and a protective film 75. The component body 72 has a resistor 73, an internal electrode layer 73B, and a substrate 74. The component body 72 may have a substantially rectangular parallelepiped shape. The external electrodes 76A and 76B are arranged on opposite sides of the component body 72 and are separated from each other. Each of the external electrodes 76A and 76B extends from the corresponding side of the component body 72 to the upper and lower surfaces of the component body 72.

[0125] Resistor 73 and internal electrode layer 73B are disposed on substrate 74 and covered by protective film 75. One end of resistor 73 is connected to internal electrode layer 73B on substrate 74. Internal electrode layer 73B extends to one side of component body 72 and is connected to external electrode 76B. Another internal electrode layer (not shown), connected to the other end of resistor 73, extends to the other side of component body 72 and is connected to external electrode 76A.

[0126] The material of resistor 73 can be selected from metals, such as Ag and Pd, or alloys containing these metals. Alternatively, the material of resistor 73 can be a metal oxide, such as ruthenium oxide. The material of the inner electrode layer 73B can be a metal selected from Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or alloys containing these metals. The material of substrate 74 is, for example, an oxide ceramic such as alumina. The material of protective film 75 is, for example, glass or resin.

[0127] Each of the external electrodes 76A and 76B includes a base layer 77 and a plating layer 79. Each of the external electrodes 76A and 76B has a mounting surface M1, a side surface M2, and a top surface M3. The mounting surface M1 is the surface facing the circuit board on which the chip resistor 71 is mounted. The top surface M3 is the surface opposite to the mounting surface M1.

[0128] The conductive material of the substrate 77 may primarily consist of, for example, a metal comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or an alloy comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The substrate 77 includes a common material. This common material may be, for example, a ceramic composition, which is a major component of the substrate 74. The substrate 77 may also include a glass composition. For example, the glass composition may be an oxide of Ba, Sr, Ca, Zn, Al, Si, or B.

[0129] The surfaces (side surface M2 and top surface M3) of each of the external electrodes 76A and 76B, excluding the mounting surface M1, are coated with an oxide layer 78. The oxide layer 78 comprises an oxide film of a metal serving as the conductive material of the substrate layer 77 and an oxide containing a metal serving as the common material of the substrate layer 77. A plating layer 79 is formed on the mounting surface M1 of the substrate layer 77 of each of the external electrodes 76A and 76B. The substrate layer 77, oxide layer 78, and plating layer 79 can be respectively similar to... Figure 1 It is constructed using the base layer 7, oxide layer 8, and coating layer 9 shown.

[0130] According to the sixth embodiment described above, the oxide layer 78 comprises an oxide film of a metal serving as the conductive material of the base layer 77 and an oxide containing a metal serving as the common material of the base layer 77. Therefore, it is possible to prevent wet solder from moving upwards to the surfaces of the external electrodes 76A and 76B on which the oxide layer 78 is formed, and to reduce the likelihood of the oxide layer 78 peeling off from the external electrodes 76A and 76B.

[0131] It should be noted that although the electronic components described in each of the above embodiments have two terminals, electronic components may have three or more terminals, such as transistors or transformers.

[0132] This application is based on and claims priority to Japanese Patent Application No. 2020-95332 (filed on June 1, 2020), the entire contents of which are incorporated herein by reference.

Claims

1. An electronic component, comprising: The component body includes a dielectric and at least one internal electrode; as well as At least one external electrode, Each of the at least one external electrode includes: A substrate layer, connected to one or more of the at least one internal electrode, comprising a metal and a first common material mixed with the metal, the substrate layer being formed on and extending from a side of the element body to cover one or more adjacent surfaces of the element body, such that the substrate layer has multiple faces facing different directions. A coating, said coating being formed on at least one surface of the substrate layer, An oxide layer is formed on one or more surfaces of the substrate layer other than at least one surface of the substrate layer. The oxide layer has a surface layer composed of a variety of oxides, including an oxide film of the metal of the substrate layer and oxide ceramics. The oxide ceramics are distributed in the form of islands on the entire surface of the oxide layer, exposed on the surface of the oxide layer, and pierce the oxide film to reach the substrate layer, thereby serving as pillars to pierce the oxide layer and support the oxide layer on the substrate layer.

2. The electronic component according to claim 1, wherein, The first common material contained in the base layer and the oxide ceramic contained in the oxide layer have the same composition.

3. The electronic component of claim 1, wherein, The main component of the dielectric is oxide ceramic.

4. The electronic component according to claim 1, wherein, The first common material contained in the substrate layer and the oxide ceramic contained in the oxide layer have the same composition as the main components of the dielectric.

5. The electronic component according to claim 1, in, At least a portion of the oxide ceramic in the oxide layer is part of a first comaterial in the substrate layer extending to the oxide layer, thereby having a continuous structure from the substrate layer to the oxide layer, and The first common material and the oxide ceramic have a single crystal structure, a polycrystalline structure, or an amorphous structure.

6. The electronic component according to claim 1, wherein, The metal in the substrate layer exists in the form of crystalline or amorphous particles, and the first co-material also exists in the form of crystalline or amorphous particles, such that the particles of the metal in the substrate layer and the particles of the first co-material exist mixed together.

7. The electronic component according to claim 1, wherein, The main component of the dielectric is barium titanate.

8. The electronic component according to claim 1, wherein, The coating is formed at least on the bottom surface of the substrate layer, and the oxide layer is disposed on one surface of the substrate layer, which is located on the element body and on at least a portion of the top surface of the substrate layer opposite to the bottom surface on which the coating is formed.

9. The electronic component according to claim 1, wherein, The ratio of the oxide ceramic to the surface of the oxide layer is in the range of 20 at% to 75 at%.

10. The electronic component according to claim 1, wherein, The metal of the base layer is a metal or alloy containing at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au and Sn.

11. The electronic component according to claim 1, wherein, The first common material includes at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, and titanium oxide.

12. The electronic component according to claim 1, wherein, At the surface of the oxide layer, the oxide layer comprises nickel oxide and barium titanate.

13. The electronic component according to claim 12, wherein, At the surface of the oxide layer, the oxide layer also contains a compound containing nickel, magnesium and oxygen.

14. The electronic component according to claim 1, wherein, The component body has a laminate, wherein, as the at least one internal electrode, at least one first internal electrode layer and at least one second internal electrode layer are alternately laminated in the laminate, separated by the dielectric. The at least one external electrode includes a first external electrode and a second external electrode, which are disposed on opposite sides of the laminate, such that the first external electrode and the second external electrode are spaced apart. The at least one first internal electrode layer is connected to the first external electrode, and The at least one second inner electrode layer is connected to the second outer electrode.

15. The electronic component according to claim 14, wherein, The coating is formed on the bottom surface of the substrate layer, and the at least one first internal electrode layer and the at least one second internal electrode layer are alternately stacked in a direction perpendicular to the bottom surface of the substrate layer in which the coating is formed.

16. A circuit board assembly, comprising: Circuit board; as well as An electronic component according to any one of claims 1-15, mounted on the circuit board, the electronic component being connected to the circuit board via a solder layer attached to the plating.

17. A method for manufacturing an electronic component, the method comprising the following steps: Forming a component body including a dielectric and internal electrodes; The mixed material, obtained by mixing the common material with the metal-containing electrode material, is applied to two opposite sides of the element body and the edge surface of the element body adjacent to the sides. The mixed material is sintered, and a base layer in which the metal and the co-material are mixed is formed on opposite sides of the component body and on the edge surface of the component body. The base layer is formed on the side of the component body and extends from the side to cover one or more adjacent surfaces of the component body, such that the base layer has multiple faces facing different directions. The metal of the substrate layer is oxidized to form an oxide layer, the oxide layer comprising an oxide film of the metal on the surface of the substrate layer, and the oxide layer further comprising a co-material of the substrate layer, the co-material and the oxide film being mixed in the form of crystalline or amorphous particles, such that the particles of the co-material are dispersed in the particles of the oxide film, and the co-material particles are distributed in the form of islands on the entire surface of the oxide layer. The oxide film is removed from at least one of the plurality of faces of the substrate layer, while leaving the oxide film on at least a portion of the edge surface of the element body; as well as A coating is formed on at least one of the multiple faces of the substrate layer on which the oxide film has been removed.

18. The method of manufacturing an electronic component according to claim 17, wherein, The step of removing the oxide film from at least one of the plurality of faces of the substrate layer includes: sandblasting the oxide film from at least one of the plurality of faces of the substrate layer to polish at least one of the plurality of faces of the substrate layer.

19. The method of manufacturing an electronic component according to claim 17 or 18, wherein, The steps for forming the component body include: Forming a sheet material containing dielectric ceramic as the main component; and A conductive paste containing the metal of the substrate layer is applied to the sheet, and The component body is sintered during the sintering of the mixed material.

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