A new type of chip multilayer ceramic capacitor

Abstract

The utility model discloses a novel sheet type multilayer ceramic capacitor relates to capacitor technical field, including two end electrodes, the inside electrode subassembly is arranged between one side of two end electrodes, the inside electrode subassembly includes a plurality of first base plate, second base plate and ceramic dielectric layer, a plurality of ceramic dielectric layer is arranged between one side of two end electrodes, and a plurality of ceramic dielectric layer is all provided with first base plate or second base plate between two two, first base plate and second base plate are staggered distribution, the top one side of first base plate and second base plate all embeds and is installed with the conducting strip. The utility model discloses through carrying out three -dimensional interdigital electrode design, shortens the current path, reduces equivalent series inductance to 0.05nH below, adapts 5G / 6G high frequency communication scene, reduces signal reflection and energy loss, in addition still improved the heat dissipation capacity under high frequency, and reduced the fracture risk.

Description

Technical Field

[0001] This utility model relates to the field of capacitor technology, specifically to a novel chip-type multilayer ceramic capacitor. Background Technology

[0002] Surface mount capacitors are a type of capacitor material. The full name of a surface mount capacitor is: multilayer (stacked) ceramic chip capacitor (MLCC), also known as chip capacitor or chip capacitor. MLCC stores charge through the dielectric properties of the ceramic dielectric layer. During charging, the charge is stored in the ceramic dielectric; during discharging, the charge is released through the internal and external electrodes. They are used in various electronic fields across industries.

[0003] The existing MLCC uses a linear electrode design, which has a high equivalent series inductance (ESL). At high frequencies (such as the 5G millimeter wave band), it is prone to signal delay and energy loss, resulting in a decrease in circuit efficiency. In view of this, in-depth research was conducted to address the above problems, which led to this case. Utility Model Content

[0004] The purpose of this invention is to provide a novel chip-type multilayer ceramic capacitor to solve the problems of high equivalent series inductance and insufficient high-frequency performance mentioned in the background art.

[0005] To achieve the above objectives, this utility model provides the following technical solution: A novel chip-type multilayer ceramic capacitor includes two terminal electrodes. An internal electrode assembly is disposed between one side of the two terminal electrodes. The internal electrode assembly includes a plurality of first substrates, second substrates, and ceramic dielectric layers. The plurality of ceramic dielectric layers are disposed between one side of the two terminal electrodes, and a first substrate or a second substrate is disposed between each pair of the plurality of ceramic dielectric layers. The first substrates and the second substrates are staggered. A conductive strip is embedded on one side of the top of each of the first substrates and the second substrate. One end of the conductive strip at the top of the first substrate and the conductive strip at the top of the second substrate are respectively connected to different terminal electrodes. A plurality of electrode fingers are installed on one side of each conductive strip, and the electrode fingers are serrated. A plurality of heat dissipation holes are penetrated through the interior of the first substrate, the second substrate, and the ceramic dielectric layers, and the interior of each heat dissipation hole is filled with a filling material.

[0006] Preferably, the pore size of the heat dissipation hole is 1-5 μm, and the filling material can be graphene or boron nitride.

[0007] Preferably, the connection between the conductive strip and the electrode finger has an arc-shaped transition with a radius of curvature ≥10μm.

[0008] Preferably, the dielectric constant of the ceramic dielectric layer increases in a gradient, with a gradient difference of 2000-5000.

[0009] Preferably, the end electrode is formed into a Cu-Ni alloy layer using a three-dimensional sputtering process, with a surface roughness Ra≤0.5μm.

[0010] Preferably, the outer sides of the end electrodes and the internal electrode assembly are covered with a protective film, and each end electrode has a pin fixed on one side, with one end of the pin extending to the outside of the protective film.

[0011] Compared with the prior art, the beneficial effects of this utility model are:

[0012] 1. The multi-layer sawtooth electrode fingers are interleaved to form a three-dimensional interdigitated electrode, which shortens the current path and reduces the equivalent series inductance to below 0.05nH, making it suitable for 5G / 6G high-frequency communication scenarios and reducing signal reflection and energy loss. At the same time, the gradient-distributed ceramic dielectric layer optimizes the electric field distribution through the gradient change of dielectric constant, further reducing high-frequency dielectric loss. The interleaved conductive strips maximize the effective area of ​​the electrode, increasing the capacitance per unit volume by more than 40%.

[0013] 2. The through-hole heat dissipation is filled with high thermal conductivity material, which vertically penetrates the electrode and the dielectric layer to form a rapid heat conduction channel, improving heat dissipation efficiency by more than 30% and ensuring the stable operation of the capacitor under high temperature conditions.

[0014] 3. The sawtooth electrode disperses thermal expansion stress through its angled design. Compared with the traditional straight electrode, the risk of breakage is reduced by more than 50%, and the radius of curvature to withstand mechanical bending is ≤3mm. Attached Figure Description

[0015] Figure 1 This is a frontal cross-sectional view of the present invention.

[0016] Figure 2 This is a top view of the structure of the first substrate of this utility model;

[0017] Figure 3 This is a top view of the structure of the second substrate of this utility model;

[0018] Figure 4 This is a partially enlarged front view of the internal motor assembly of this utility model.

[0019] In the diagram: 1. Terminal electrode; 2. Protective film; 3. Internal electrode assembly; 31. First substrate; 32. Second substrate; 33. Ceramic dielectric layer; 4. Conductive strip; 5. Heat dissipation hole; 6. Filler material; 7. Electrode finger; 8. Lead Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] Example: Please refer to Figure 1-4 A novel chip-type multilayer ceramic capacitor includes two terminal electrodes 1. An internal electrode assembly 3 is disposed between one side of the two terminal electrodes 1. The internal electrode assembly 3 includes several first substrates 31, second substrates 32, and ceramic dielectric layers 33. The multiple ceramic dielectric layers 33 are disposed between one side of the two terminal electrodes 1, and each pair of multiple ceramic dielectric layers 33 is provided with either a first substrate 31 or a second substrate 32. The first substrates 31 and the second substrates 32 are staggered. A conductive strip 4 is embedded on one side of the top of each of the first substrates 31 and the second substrate 32. One end of the conductive strip 4 at the top of the first substrate 31 and the top of the conductive strip 4 at the top of the second substrate 32 are respectively connected to different terminal electrodes 1. Multiple electrode fingers 7 are installed on one side of each conductive strip 4, and the electrode fingers 7 are serrated. Multiple heat dissipation holes 5 penetrate the interior of the first substrate 31, the second substrate 32, and the ceramic dielectric layer 33, and each heat dissipation hole 5 is filled with a filling material 6.

[0022] The connection between the conductive strip 4 and the electrode finger 7 is an arc-shaped transition with a radius of curvature ≥10μm;

[0023] The outer sides of the end electrode 1 and the internal electrode assembly 3 are covered with a protective film 2. A pin 8 is fixed on one side of the end electrode 1, and one end of the pin 8 extends to the outside of the protective film 2.

[0024] Specifically, such as Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the electrode fingers 7 at different positions of the device are interleaved and can be made of Ag-Pd alloy or Cu-Ni alloy. Their distribution forms a three-dimensional interdigitated electrode, which shortens the current path and reduces the equivalent series inductance (ESL) to below 0.05nH. This makes it suitable for 5G / 6G high-frequency communication scenarios, reduces signal reflection and energy loss, and the total number of electrode fingers 7 is greater than 1000 layers. The interlayer alignment accuracy is preferably ±0.1μm.

[0025] The pore size of the heat dissipation hole 5 is 1-5μm, and the filling material 6 can be graphene or boron nitride;

[0026] Specifically, such as Figure 2 and Figure 3As shown, the heat dissipation hole 5 is filled with a high thermal conductivity material, which penetrates vertically through the electrode and the dielectric layer to form a rapid heat conduction channel, improving the heat dissipation efficiency by more than 30% and ensuring the stable operation of the capacitor under high temperature conditions (-55℃~200℃).

[0027] The dielectric constant of the ceramic dielectric layer 33 increases gradually, with a gradient difference of 2000-5000.

[0028] Specifically, such as Figure 1 and Figure 4 As shown, the ceramic dielectric layer 33 and the terminal electrode 1 can achieve dense bonding through low-temperature co-firing, reducing interlayer defects. The gradient change of the dielectric constant of the ceramic dielectric layer 33 reduces the risk of local breakdown.

[0029] The terminal electrode 1 is formed with a Cu-Ni alloy layer by a three-dimensional sputtering process, and the surface roughness Ra≤0.5μm;

[0030] Specifically, such as Figure 1 As shown, sputtering and electroplating processes form three-dimensional terminal electrodes, enhancing the mechanical bond and conductivity with PCB pads.

[0031] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A novel multilayer ceramic chip capacitor, comprising two terminal electrodes (1), characterized in that: An internal electrode assembly (3) is disposed between one side of the two terminal electrodes (1). The internal electrode assembly (3) includes a plurality of first substrates (31), second substrates (32), and ceramic dielectric layers (33). The plurality of ceramic dielectric layers (33) are disposed between one side of the two terminal electrodes (1), and a first substrate (31) or a second substrate (32) is disposed between each pair of the plurality of ceramic dielectric layers (33). The first substrates (31) and the second substrates (32) are staggered. (32) has a conductive strip (4) embedded on one side of its top end. One end of the conductive strip (4) at the top of the first substrate (31) and the conductive strip (4) at the top of the second substrate (32) are connected to different end electrodes (1). Multiple electrode fingers (7) are installed on one side of each conductive strip (4). The electrode fingers (7) are serrated. Multiple heat dissipation holes (5) are penetrating the interior of the first substrate (31), the second substrate (32) and the ceramic dielectric layer (33). Filling material (6) is provided inside each heat dissipation hole (5).

2. The novel multilayer ceramic chip capacitor according to claim 1, characterized in that: The pore size of the heat dissipation hole (5) is 1-5 μm, and the filling material (6) can be graphene or boron nitride.

3. A novel multilayer ceramic chip capacitor according to claim 1, characterized in that: The connection between the conductive strip (4) and the electrode finger (7) is an arc-shaped transition with a radius of curvature ≥10μm.

4. A novel multilayer ceramic chip capacitor according to claim 1, characterized in that: The dielectric constant of the ceramic dielectric layer (33) increases gradually, with a gradient difference of 2000-5000.

5. A novel multilayer ceramic chip capacitor according to claim 1, characterized in that: The terminal electrode (1) is formed with a Cu-Ni alloy layer by a three-dimensional sputtering process, and the surface roughness Ra≤0.5μm.

6. A novel multilayer ceramic chip capacitor according to claim 1, characterized in that: The outer side of the end electrode (1) and the inner electrode assembly (3) is covered with a protective film (2). A pin (8) is fixed on one side of the end electrode (1), and one end of the pin (8) extends to the outside of the protective film (2).

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