Storage system

Abstract

To spread a load of overlap rejection in a storage system.SOLUTION: A storage system includes: a central processing device; a main memory; first management information which correlates a hash value of received data and an address in a volume; and an IO processing package. The IO processing package includes an IO processor and an IO memory. The IO processor executes a protocol process. The IO processor executes at least a part of a search process of an address correlated with the hash value of first received data in the first management information. The central processing device controls execution of an overlapping rejection process for the first received data on the basis of data of the address correlated with the hash value of the first received data.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a storage system.

Background Art

[0002] A storage device mainly consists of a storage controller (hereinafter referred to as a controller) and a drive. The controller provides a storage service to a host connected via a SAN. The storage service refers to storing data in a drive in response to a data write request from the host and retrieving the data from the drive in response to a data read request from the host.

[0003] In order to maximize the utilization of limited drive capacity and keep drive costs low, a function may be implemented to detect that the same data has been written to the controller from the host multiple times and store those data together as a single data in the drive. This is called a deduplication function.

[0004] The deduplication function may be implemented using a certain hash function. The data written from the host is divided into fixed-length or variable-length chunks, and by inputting the data of each chunk into the hash function, a hash value corresponding to the data is obtained. This hash value is specifically called a Fingerprint Key (hereinafter referred to as FPK).

[0005] Also, the FPK corresponding to each chunk of the drive-stored data to be deduplicated is stored in a dedicated hash table. This table is specifically called a Fingerprint Table (hereinafter referred to as FPT). Search for the FPK calculated from the write data from the host in the FPT. If a matching FPK is found, the data pointed to by those FPKs is likely to be duplicate of each other.

[0006] The FPK-matched data is read from the drive and compared with the data written from the host. If the contents match, they are considered duplicate data, and instead of storing the data written from the host on the drive, a reference to the data already stored on the drive is added.

[0007] Patent Document 1 discloses a data deduplication method and a storage device based thereon. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] International Publication No. 2018 / 061161 [Overview of the project] [Problems that the invention aims to solve]

[0009] In the deduplication method disclosed in Patent Document 1, the FPT search is performed by the controller, particularly the central processing unit (CPU) within the controller. This presents a problem in that the processing load related to the FPT search increases depending on the volume of data written from the host, leading to a decrease in I / O performance. [Means for solving the problem]

[0010] This applicationA typical example of a storage system includes a central processing unit, main memory including a program area and a work area of ​​the central processing unit, first management information associating the hash value of received data with an address in a volume, and an I / O processing package. The I / O processing package includes an I / O processor and I / O memory including a program area and a work area of ​​the I / O processor. The central processing unit controls read and write operations for user data. The I / O processor performs protocol processing. The I / O processor performs at least part of the address lookup process associated with the hash value of the first received data in the first management information. The central processing unit controls the execution of deduplication processing for the first received data based on the address data associated with the hash value of the first received data. [Effects of the Invention]

[0011] According to one aspect of the present invention, the performance of a storage system can be improved.

[0012] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0013] [Figure 1] Block diagram showing an example of the information system configuration in the embodiment. [Figure 2A] Block diagram of the IPU program area related to the embodiment [Figure 2B] Block diagram of the CPU program area related to the embodiment [Figure 3A] Block diagram of the IPU work area related to the embodiment [Figure 3B] Block diagram of the CPU work area in the embodiment [Figure 4] Block diagrams of CPU and IPU I / O areas in the embodiment [Figure 5] Example of the overall FPT configuration [Figure 6] Example of VFPTD construction using a trie [Figure 7A] Configuration example of SQ [Figure 7B] Configuration example of CQ [Figure 8] Configuration example of FPRDT [Figure 9A] Configuration example of the IPU load information table in load distribution based on FPRDT in the embodiment [Figure 9B] Configuration example of the FPT search load information table in load distribution based on FPRDT in the embodiment [Figure 9C] Configuration example of the updated FPRDT in load distribution based on FPRDT in the embodiment [Figure 10] FPT search flow in the embodiment [Figure 11] FPT search request flow in the embodiment [Figure 12] VFPTD search flow in the embodiment [Figure 13] FPMQ search flow in the embodiment [Figure 14] VFPBL update flow in the embodiment [Figure 15] VFPTD update request flow in the embodiment [Figure 16] FPT update flow in the embodiment [Figure 17] IPU load acquisition flow in the embodiment [Figure 18] FPRDT update flow in the embodiment<000B0105> [Figure 19] VFPBL release flow in the embodiment<0000!07 [Figure 20] VFPTD update flow in the embodiment

Modes for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described based on the drawings.

[0015] The following description and drawings are illustrative examples for explaining the present invention, and have been omitted and simplified as appropriate for clarity of explanation. The present invention can be implemented in various other forms, and unless otherwise specified, each component may be singular or plural.

[0016] Furthermore, the embodiments described below are not intended to limit the invention as defined in the claims, and not all combinations of elements described in the embodiments are necessarily essential to the solution of the invention.

[0017] The terminology used in the following explanation is as follows:

[0018] Firstly, regarding I / O with peripheral devices equipped with a cache mechanism, it may be stated that the device directly requests I / O, but in such cases, it is assumed that the cache mechanism operates properly and that I / O from the cache is performed as appropriate. However, this does not apply if the presence or absence of cache intervention is explicitly stated.

[0019] Secondly, while it is sometimes mentioned that memory and storage devices are freed, depending on the device's structure and the implementation of its control software, such as if the storage device is composed of an SSD (Solid State Drive), the actual freeing process may be suspended, and the area may only be recorded as logically freed.

[0020] Thirdly, while the description of the processing procedure may specify that the process should terminate without releasing the memory area used during processing, the release of used memory areas shall be handled appropriately by mechanisms such as GC (Garbage Collection).

[0021] Fourthly, while processing may sometimes be described using "program" as the subject, in such cases, the processor executing the program shall issue I / O to storage and other peripheral devices as appropriate, according to the processing content defined within the program. If the processor executing the program is not specified, the appropriate processor for the execution environment shall execute the program.

[0022] The following describes FPT (Fingerprint Table) searching for data deduplication in storage systems. Increased CPU processing load within the controller due to FPT searching can lead to a decrease in I / O performance. The CPU load can be reduced by offloading high-load processing to dedicated search hardware within the controller, separate from the CPU. For example, a coprocessor or FPGA dedicated to performing FPT searches can be installed, and the FPT search can be offloaded to these.

[0023] Integrating dedicated hardware within the controller solely for the purpose of offloading FPT search can present challenges in terms of cost, footprint, power supply capacity, and heat generation. One embodiment of this specification focuses on the surplus resources of a coprocessor installed in the controller for purposes other than FPT search, and proposes offloading at least a portion of the FPT search process.

[0024] An example of a coprocessor installed in a controller for purposes other than FPT search is one installed in a controller to offload the processing load of network protocols from the CPU, in order to support high-speed network standards such as 100 Gigabit Ethernet (hereinafter referred to as 100GbE) in SANs (Storage Area Networks). Such a coprocessor is called an IPU (I / O Processing Unit).

[0025] The IPU (Internet Processing Unit) is equipped with a processor for network protocol processing, memory that acts as a buffer for protocol data, and a DMA engine for reading and writing to the controller's memory. Depending on the load on the host interface to which the IPU is connected, these resources may not be fully utilized, resulting in surplus resources.

[0026] For example, in a configuration where multiple IPUs supporting high-speed network standards such as 100GbE are installed on the same controller, it is entirely possible for a single IPU to saturate the entire controller's I / O bandwidth during migration operations, in which case the other IPUs become surplus resources.

[0027] By utilizing these surplus IPU resources to offload FPT searches, it becomes possible to improve the performance of storage devices without installing dedicated hardware.

[0028] However, the IPU is primarily a coprocessor designed to handle I / O processing with the host, and it is essential to avoid any impact on I / O processing performance due to the processing load of offloaded FPT searches. Furthermore, since the I / O processing load with the host fluctuates depending on the operation of the host application, the amount of resources available for FPT searches also fluctuates. Therefore, instead of constantly offloading FPT searches, the controller should monitor the IPU's I / O processing load and make appropriate decisions on whether or not to offload it.

[0029] Furthermore, if multiple IPUs are installed, load balancing among them can also become a challenge. It is unlikely that the I / O load will be evenly distributed among the IPUs. For example, if load balancing is implemented by changing the offload destination using a round-robin method for each FPK, the impact on I / O performance may be greater for IPUs with high I / O loads. Therefore, it is conceivable to concentrate FPT searches on the IPU with the lowest I / O load among the multiple installed IPUs.

[0030] In the embodiments described herein, load balancing based on FPK is proposed to address the challenges associated with FPT search offloading. In one embodiment described herein, it is not assumed that a specific hash function is used for FPK calculation, but rather that the hash function used for this purpose has sufficient uniformity and randomness. This means that even if the input data is biased towards a particular pattern, the FPK output by the hash function can be considered a uniformly random number.

[0031] Therefore, in an implementation that assigns a specific range of FPK values ​​to each IPU and requests each IPU to search only for FPKs within that assigned range, it is possible to adjust the search load on each IPU by adjusting the FPK assignment range.

[0032] In the embodiments described herein, the processor load, memory load, and DMA load of each IPU are aggregated at regular time intervals, and the FPK value allocation range for each IPU is determined based on these loads.

[0033] The embodiments described herein enable the offloading of duplicate data detection processing in a storage device to the surplus resources of an IPU, thereby improving the performance of the storage device without the need for dedicated hardware. Furthermore, at least a portion of the FPT search can be offloaded to an IPU that performs protocol processing for communication with a different network or a different host device than the SAN.

[0034] Figure 1 shows a block diagram illustrating an example of the configuration of an information processing system according to one embodiment of this specification.

[0035] An information processing system in one embodiment of this specification includes a storage system 34 and a host computer 37, which are connected by a SAN 111.

[0036] The host computer 37 is a computer device equipped with a CPU (Central Processing Unit) 70, memory 73, and peripheral devices necessary for executing the application 40. The host computer 37 issues write and read commands to the connected storage system 34 in response to requests from the application 40.

[0037] The storage system 34 comprises a CPU 64 and main memory 76. The main memory 76 includes a CPU program area 47, a work area 45, and an I / O area 108. The CPU 64 executes various programs located in the CPU program area 47. Based on the various programs in the CPU program area 47, the CPU 64 provides storage services to the host computer 37 by controlling the reading and writing (read and write) of data in the volume 49, and also controls the entire storage system 34. The physical storage area of ​​the volume is provided by one or more storage drives (not shown).

[0038] Furthermore, the storage system 34 includes an IPU package (IPPK) 104 equipped with an IPU (I / O Processing Unit) 55 and IPU memory 79. The IPU package 104 is connected to the CPU 64 via a bus 117, such as PCI Express, and can communicate with each other. The IPU memory 79 includes an IPU program area 92, an IPU work area 95, and an IPU I / O area 84. The main role of the IPU 55 is to relay communication between the host computer 37 and the CPU 64 based on various programs placed in the IPU program area 92.

[0039] The IPU55 is equipped with a DMA (Direct Memory Access) controller 114 (DMA114), which allows the IPU55 to read and write to the 76-space main memory area via the DMA114.

[0040] Figure 2A shows a block diagram of the IPU program area 92 according to this embodiment. Figure 2B shows a block diagram of the CPU program area 43.

[0041] The IPU program area 92 contains a VFPTD (Finger Print Table Directory) search routine 18, a VFPTD update routine 24, and an IPU load acquisition routine 30. The VFPTD search routine 18 and the VFPTD update routine 24 are always-on routines that wait for commands from the CPU 64. The IPU load acquisition routine 30 is a periodic routine that acquires IPU load information at regular intervals.

[0042] In addition, the IPU program area 92 stores the FPMQ (Finger Print Match Queue) search routine 21 as a subroutine of the above routine. This routine is not called directly from any other routine.

[0043] The CPU program area 47 includes an FPT search routine 42, an FPT update routine 48, an FPRDT update routine 54, and a VFPBL (Virtual Fingerprint Block List) release routine 62. The FPT search routine 42 is called to search for matching data when data is written from the host computer 37 and deduplication is performed.

[0044] The FPT update routine 48 is called when the deduplication process is complete and new data entries are registered in the FPT, or data is deleted. The FPRDT update routine 54 is a continuously running routine based on an infinite loop. The VFPBL release routine 62 is called when the VFPBL and FPMQ need to be released due to reasons such as the CPU work area 45 being exhausted.

[0045] In addition, the CPU program area 47 includes the FPT search request routine 44 and the VFPTD update request routine 60 as subroutines of the above routine. These routines are not called directly from any other routine.

[0046] Figure 3A shows a block diagram of the IPU work area 95. The IPU work area 95 stores VFPTD63. Figure 3B shows a block diagram of the CPU work area 45. The CPU work area 45 stores VFPBL43 and FPMQ46. The IPU I / O area 84 does not contain any data structures in particular.

[0047] Figure 4 shows a block diagram of the CPU I / O area 108. The CPU I / O area 108 stores one pair of SQ (Submission Queue) 20 and CQ (Completion Queue) 23 for exchanging commands and responses with each IPU 55.

[0048] Figure 5 shows an example of the overall configuration of the FPT according to this embodiment. In this embodiment, the FPT includes three types of tables: VFPTD63, VFPBL43, and FPMQ46.

[0049] VFPTD63 is permanently located in the IPU work area 95 and uses the upper bits of the FPK as an index to provide the address of the corresponding VFPBL43. Figure 5 shows an example of VFPTD63 that provides a 32-bit VFPBL address from the upper 12 bits of the FPK, but there is no limit to the number of bits in the FPK that can be used as an index for VFPTD63, nor is there a limit to the bit width of the VFPBL address.

[0050] The capacity of the IPU memory 79 is generally smaller than the capacity of the main memory 76. Depending on the number of bits in the FPK used as the index, the size of VFPTD63 can become large and may put pressure on the IPU work area 95. Therefore, VFPTD63 may be implemented using a sparse data structure such as a trie instead of a linear array. The implementation method of VFPTD63 using a trie is described in Figure 6.

[0051] VFPTD63 can take a special value as an invalid VFPBL address to indicate that the VFPBL43 corresponding to the index FPK does not exist on the CPU work area 45. Figure 5 shows an example where -1 is reserved as the invalid address, but other values ​​may be used as the invalid address depending on the system's memory address scheme.

[0052] Based on an FPT lookup request from CPU64, IPU55 consults VFPTD63 from FPK and, if a valid VFPBL address is obtained, IPU55 uses DMA114 to read the corresponding VFPBL43 from CPU work area 45 into IPU work area 95. By reading only the necessary VFPBL43, the pressure on IPU work area 95 can be reduced.

[0053] On the other hand, if the address obtained from VFPTD63 is an invalid VFPBL address, IPU55 requests CPU64 to allocate VFPBL43. CPU64 reads FPMQ46 from volume 49, creates VFPBL43 from the address of the read FPMQ46, and requests IPU55 to update and re-look up VFPTD63 using the address of the newly created VFPBL43.

[0054] If the CPU work area 45 becomes exhausted due to an increase in the data cache or other reasons, it may be necessary to free up VFPBL43 and FPMQ46 to make space. In that case, all IPUs 55 are requested to delete the address to the corresponding VFPBL43 from VFPTD63 in each IPU work area 95 and replace it with an invalid address. After that, VFPBL43 and FPMQ46 are freed.

[0055] VFPBL43 is an array of FPMQ addresses located on the CPU work area 45. A single VFPBL43 stores the addresses of all FPMQ46 corresponding to the same entry on VFPTD63, and the IPU55 can obtain the addresses of each FPMQ46 on the CPU work area 45 by referencing the VFPBL43 on the CPU work area 45 via DMA114.

[0056] Note that while Figure 5 shows an example of storing a 32-bit FPMQ address, the bit width of the FPMQ address is not limited to 32 bits.

[0057] FPMQ46 is an array located on the CPU work area 45, and each entry in FPMQ46 consists of a pair of FPK and LA. Based on the FPMQ address obtained by referencing VFPBL43, the IPU55 reads FPMQ46 from the CPU work area 45 to the IPU work area 95 and searches for an FPMQ entry containing an FPK that matches the FPK to be searched. If an FPK match is detected, the IPU55 notifies the CPU64 of the LA stored in the matched entry. It is possible to find matches in multiple entries in a single search, in which case the LAs of all matched entries are notified to the CPU64.

[0058] As mentioned earlier, FPMQ46 may be released from main memory 76 if the CPU work area 45 is exhausted. Subsequently, if access to FPMQ46 is requested again, the CPU 64 will reallocate it on main memory 76 by reading from volume 49.

[0059] Figure 5 shows an example where 32-bit values ​​are used for both FPK and LA, but the bit width of these values ​​is not limited to 32 bits.

[0060] Figure 6 shows an example of a trie-based configuration of VFPTD63 according to this embodiment.

[0061] As mentioned above, if VFPTD63 is configured as a linear array or the like, the capacity of the IPU work area 95 may become strained. Therefore, VFPTD63 may be configured as a trie consisting of one or more root nodes 53, an arbitrary number of intermediate nodes 52, and an arbitrary number of leaf nodes 55. In this case, each node of VFPTD63 has a table 61 containing the child node addresses corresponding to each value of the corresponding digit.

[0062] Table 61 of leaf node 55 points to VFPBL43 instead of a node in VFPTD63.

[0063] For example, in Figure 6, if the upper 12 bits of the FPK (the upper 3 digits in the hexadecimal trie) are 245, then the root node 53 first reads the intermediate node 52 by referencing the child node address 0x25E27E6D, which corresponds to the most significant digit value of 2. Next, the leaf node 55 is read by referencing the child node address 0x5B74E72B, which corresponds to the second digit value of 4, in the table 61 of the read intermediate node 52. Finally, the VFPBL43 corresponding to 245 is read by referencing the VFPBL43 address 0x1C34062C, which corresponds to the third digit value of 5. Note that the address stored in the leaf node 55 points to a memory location on the CPU work area 45, not the IPU work area 95.

[0064] Note that Figure 6 shows an example of VFPTD63 being constructed as a hexadecimal trie with a maximum depth of 3, but the radix of the trie does not have to be 16, and the depth of the trie does not have to be 3.

[0065] Figure 7A shows an example configuration of SQ20 according to this embodiment. Figure 7B shows an example configuration of CQ23 according to this embodiment.

[0066] SQ20 is located on the CPU I / O area 108 and functions as an area that passes command 23 from CPU64 to IPU55.

[0067] SQ20 is implemented as a FIFO-type ring buffer. Command 23, sent from CPU64 to IPU55, is added to the beginning of SQ20, and P-index32, which indicates the starting position of SQ, is incremented. IPU55 retrieves command 23 from the end of SQ20 and notifies CPU64 of receipt of command 23 by incrementing C-index29, which indicates the ending position of SQ.

[0068] CQ23 is located on the CPU I / O area 108 and functions as an area that passes response 59 from IPU55 to CPU64.

[0069] CQ23 is implemented as a FIFO-type ring buffer, similar to SQ20. Response 59, sent from IPU55 to CPU64, is added to the beginning of CQ23, and P-index32, which indicates the starting position of the CQ, is incremented. CPU64 retrieves response 59 from the end of the CQ and increments C-index29, which indicates the ending position of the CQ, thereby notifying IPU55 that response 59 has been received.

[0070] Figure 8 shows an example configuration of the FPRDT (Fingerprint Range Dispatch Table) 15 according to this embodiment.

[0071] FPRDT15 is a table containing two columns: FPK range 9 and assignment ID 12. FPK range 9 contains the FPK intervals, and assignment ID 12 stores the assigned IPU numbers for FPT searches for each FPK within each FPK interval.

[0072] For example, in Figure 8, if the upper 4 bits of the FPK are 0x2456, then the FPK falls within the range of 0x2000-0x2FFF, and the search request will be sent to IPU number 0.

[0073] Furthermore, by storing -1 as a special value in the assigned ID12 column, the search is not requested from any IPU, and the search is specified to be performed on CPU64. This enables load balancing, including CPU64. CPU64 can perform the FPT search process in the same manner as the FPT search process performed by IPU55 described herein.

[0074] Note that Figure 8 shows an example where a 16-bit FPK is divided equally into 16 intervals, but the size of the FPK is not limited to 16 bits, and the number of divisions of the FPK is not limited to 16. Also, the division of the FPK into intervals does not need to be equal.

[0075] By determining the allocation amount for FTP search processing through FPK segmentation, the probability of reusing the reference data for search processing cached in IPU package 104 increases, thereby improving the overall efficiency of FTP search processing.

[0076] Figures 9A to 9C show an example of load balancing based on FPRDT15 according to this embodiment.

[0077] In this embodiment, for example, load information for each IPU 55 at each time point is stored in the IPU load information table 31. Figure 9A shows an example of the configuration of the IPU load information table 31. The IPU load information table 31 shows the maximum processing capacity, current IPU load rate, current memory load rate, and current DMA load rate for each of the multiple IPUs. The load rate indicates the utilization rate of the performance of each component. For example, the IPU load rate may be determined based on the amount of computation per unit of time, the memory load rate may be determined based on the amount of access per unit of time, and the DMA load rate may be determined based on the amount of data transferred per unit of time.

[0078] The processing power of the IPU and the processing power and load rate of its components have the following relationship: The maximum processing power of the CPU, memory, and DMA is equal to the maximum processing power of the IPU. In the example in Figure 9A, the maximum processing power of all IPUs is 5, and the maximum processing power of each of its components is also 5. The processing power that each component is exerting (using) is the product of its load rate and its maximum processing power. The surplus processing power is the current used processing power multiplied by the maximum processing power. Subtracted This is the value. Note that the maximum processing power may differ between IPUs.

[0079] Based on the information from the response sent by the IPU load acquisition routine 30 (described later), the CPU 64 acquires the IPU load rate, memory load rate, and DMA load rate for each IPU 55 and stores them in the corresponding columns of the IPU load information table 31. The IPU load information table 31 may be stored in the CPU work area 45.

[0080] Meanwhile, the CPU 64 acquires the FPT search load at each time point and records it in the FPT search load information table 28. Figure 9B shows an example of the configuration of the FPT search load information table 28. The FPT search load information table 28 can be stored in the CPU work area 45.

[0081] The FPT search load information table 28 shows the load of the FPT search process to be performed at each time point, and the load ratio of the CPU, memory, and DMA in the FPT search process. In the example in Figure 9B, the load of the FPT search process to be performed at the current time is 10. The IPU processing capacity required for this process is 10. Also, the load ratio related to the CPU, memory, and DMA in the FPT search process is 100:150:75. In other words, the memory load is the highest and the DMA load is the lowest. In this example, it is assumed that the load ratio is the same for all IPUs, but the load ratio may differ between IPUs.

[0082] CPU64 updates FPRDT15 to maximize the utilization efficiency of IPU resources at each time point by comparing the information in IPU load information table 31 with the information in FPT search load information table 28. Figure 9C shows an example of the updated FPRDT15 configuration.

[0083] For example, in the example shown in Figures 9A to 9C, IPU 0 has a maximum processing capacity of 5, and the current IPU load is 60%, the memory load is 70%, and the DMA load is 50%. Therefore, the surplus processing capacity available for FPT search is 2 (5 * 0.4) for the CPU, 1.5 (5 * 0.3) for memory, and 2.5 (5 * 0.5) for DMA.

[0084] In this example, as shown in Figure 9B, FPT search places the highest memory load on the system. Therefore, the amount of FPT search processing that can be offloaded to IPU 0 is 1 out of the total 10. Note that the FPT search processing is offloaded in units of 1. In this case, FPRDT15 is allocated less than one-tenth of the total FPT search processing to IPU 0.

[0085] CPU64 similarly determines the amount of offloading to IPUs 1 through 3. For the remaining processing, setting an invalid IPU number such as -1 in FPRDT15 and having CPU64 handle it allows for improved FPT search performance by making maximum use of IPU55's surplus resources without affecting I / O processing performance of IPU55.

[0086] Figure 10 shows the FPT search flow according to this embodiment.

[0087] In step S0101, the FPT search routine 42 calls the FPT search request routine 44.

[0088] In step S0102, the FPT search routine 42 receives the search result from the FPT search request routine 44 via CQ23.

[0089] In step S0103, the FPT search routine 42 checks whether the search result of the FPT search request routine 44 received in step S0102 is a read request response for VFPBL43 due to an invalid address being set for VFPTD63.

[0090] In step S0103, if the search result of the received FPT search request routine 44 is a VFPBL request response, in step S0105, the FPT search routine 42 calls the VFPBL update routine 56 to load the VFPBL 43 and all FPMQ 46 indicated by the VFPBL from volume 49 onto the CPU work area 45 and notify the IPU 55 of the result. Then, the process returns to step S0101 and requests the IPU 55 to perform the FPT search again.

[0091] In step S0104, the FPT search routine 42 determines whether an FPK match was detected in the search results received from the IPU 55 in step S0102.

[0092] If an FPK match is detected in step S0104, in step S0106, the FPT search routine 42 calls a deduplication process, passes one or more LAs received from the IPU 55, and initiates the process. Any method can be used for the deduplication process, and the details are omitted in this paper.

[0093] Figure 11 shows the FPT search request flow according to this embodiment.

[0094] In step S0201, the FPT search request routine 44 calculates the FPK of the data to be searched. The FPK is calculated by applying a hash function to the data. The type of hash function used here is not specified in this embodiment, but any hash function with sufficient uniformity and randomness to properly distribute the load can be used.

[0095] Furthermore, when applying a hash function to the FPK and calculating the FPK, you may use the accelerator installed in the CPU64 or IPU55.

[0096] In step S0202, the FPT search request routine 44 loads the FPT allocation range table 15 into memory.

[0097] In step S0203, the FPT search request routine 44 uses the FPK value calculated in step S0101 to look up the FPT allocation range table 15 read in step S0202 and determine the IPU number to be searched.

[0098] In step S0204, the FPT search request routine 44 determines the FPT search destination based on the IPU search destination ID read from the FPT allocation range table 15 in step S0203.

[0099] In step S0204, if the FPT search request ID matches any of the IPUs, in step S0205, the FPT search request routine 44 creates a command to request an FPT search from IPU 55.

[0100] In step S0206, the FPT search request routine 44 sends the command by storing the FPT search request command created in step S0205 in SQ20 of the requesting IPU. Upon receiving the FPT search request command, the IPU 55 starts the VFPTD search routine 18.

[0101] On the other hand, if in step S0204 the FPT search request ID does not match any IPU, in step S0207 the FPT search request routine 44 calls a routine to execute the FPT search on the CPU 64 instead of requesting the FPT search from the IPU 55. Details of this routine are omitted in this paper.

[0102] Figure 12 shows the VFPTD search flow according to this embodiment.

[0103] In step S0300, the VFPTD search routine 18 receives an FPT search request command from CPU 64.

[0104] In step S0301, the VFPTD lookup routine 18 uses the higher bits of the FPK to refer to VFPTD63 and obtain the VFPBL address.

[0105] In step S0302, the VFPTD lookup routine 18 determines whether the VFPBL address read in step S0301 is a valid address that points to a memory location within the CPU work area 45. In this example, if the VFPBL address is "-1", then that address is invalid.

[0106] If the determination result in step S0302 is not a valid VFPBL address, the CPU 64 needs to allocate VFPBL 43. Therefore, in step S0303, the VFPTD search routine 18 creates a VFPBL request response that requests the CPU 64 to allocate VFPBL 43.

[0107] In step S0304, the VFPTD search routine 18 stores the VFPBL request response created in step S0303 in CQ23 and sends the response to CPU64. Then it returns to step S0300 and waits for the next command.

[0108] If the result of the determination in step S0302 is a valid VFPBL address, in step S0305, the VFPTD search routine 18 calls the FPMQ search routine 21 with that address as a parameter. Then, it returns to step S0300 and waits for the next command.

[0109] Figure 13 shows the FPMQ search flow according to this embodiment.

[0110] In step S0400, the FPMQ search routine 21 reads the VFPBL 43 located in the CPU work area 45 into the IPU work area 95 via DMA 114.

[0111] In step S0401, the FPMQ lookup routine 21 reads the FPMQ46 located in the CPU work area 45 into the IPU work area 95 via DMA 114, based on the contents of VFPBL43 read in step S0400. For example, all FPMQ46 addresses indicated by VFPBL43 are read. Alternatively, the FPMQ46s indicated by VFPBL43 may be read sequentially, and the processing described below may be executed for each FPMQ46. If the FPMQ46 is divided and arranged in multiple discontinuous regions on the CPU work area 45, all of these regions shall be treated as a single FPMQ46. When reading the FPMQ46 distributed in these discontinuous regions on the CPU work area 45 into the IPU work area 95 using DMA114, functions that speed up the transfer of data divided into multiple regions, such as the DMA gather function, may be used.

[0112] In step S0402, the FPMQ search routine 21 retrieves the first entry of the FPMQ46 that was loaded into the IPU work area 95 in step S0401.

[0113] In step S0403, the FPMQ search routine 21 compares the FPK of the retrieved FPMQ entry with the FPK to be searched.

[0114] If, in step S0403, the FPK of the FPMQ entry does not match the FPK being searched, then in step S0404, the FPMQ search routine 21 determines whether the current FPMQ entry is the last entry in the FPMQ. If it is the last entry, the routine terminates.

[0115] In step S0404, if the current FPMQ entry is not the last entry in the FPMQ, in step S0405, the FPMQ lookup routine 21 reads the next FPMQ entry in FPMQ 46 and returns to step S0403.

[0116] In step S0403, if the FPK in the FPMQ entry matches the searched FPK, in step S0406, the FPMQ search routine 21 creates an FPK match detection response to notify the CPU 64 of the FPK detection. The FPK match detection response includes the LA associated with each of the one or more matching FPKs.

[0117] In step S0, the FPMQ search routine 21 stores the FPK match detection response created in step S0406 in CQ23 and sends it to the CPU 64. Then, the process proceeds to step S0404. For example, the VFPTD search may be offloaded to the IPU 55, and the FPMQ search may be performed by the CPU 64. The retrieved VFPBL address is passed from the IPU 55 to the CPU 64.

[0118] Figure 14 shows the VFPBL update flow according to this embodiment.

[0119] In step S0501, the VFPBL update routine 56 reads the VFPBL 43 from volume 49 (drive) into the CPU work area 45 based on the FPK instructed by the caller. If the VFPBL 43 is stored in multiple discontinuous areas on volume 49, all of those areas are treated together as a single VFPBL 43.

[0120] In step S0502, the VFPBL update routine 56 loads the FPMQ 46 into the CPU work area 45 based on the VFPBL 43 loaded into the CPU work area 45 in step S0501.

[0121] In step S0503, the VFPBL update routine 56 calls the VFPTD update request routine 60 and requests each IPU 55 to add the address of VFPBL 43, which was read onto the CPU work area 45 in step S0501, to VFPTD 63.

[0122] Figure 15 shows the VFPTD update request flow according to this embodiment.

[0123] In step S0601, the VFPTD update request routine 60 calculates the FPK of the FPT update target data. The same method as in the FPT search request routine 44 is used for FPK calculation.

[0124] In step S0602, the VFPTD update request routine 60 creates an FPT update request command using the FPK calculated in step S0601.

[0125] In step S0603, the VFPTD update request routine 60 resets the IPU ID counter to 0.

[0126] In step S0604, the VFPTD update request routine 60 determines whether the value of the IPU ID counter exceeds the maximum value of the IPU ID.

[0127] In step S0604, if the value of the IPU ID counter does not exceed the maximum value of the IPU ID, in step S0605, the VFPTD update request routine 60 sends a VFPTD update request command to the IPU 55 indicated by the value of the IPU ID counter. Upon receiving the VFPTD update request command, the IPU 55 sets the address of the target VFPBL 43 in the entry corresponding to the FPK in the VFPTD 63 within the IPU work area 95.

[0128] In step S0606, the VFPTD update request routine 60 increments the value of the IPU ID counter and returns to step S0604.

[0129] In step S0604, if the value of the IPU ID counter exceeds the maximum value of the IPU ID, the VFPTD update request routine 60 terminates processing.

[0130] Figure 16 shows the FPT update flow according to this embodiment.

[0131] In step S0701, the FPT update routine 48 calculates the FPK of the data to be updated. The calculation of the FPK is the same as that of the FPT search routine 42.

[0132] In step S0702, the FPT update routine 48 calls the VFPTD update request routine 60, requesting each IPU 55 to invalidate the VFPTD entries corresponding to the FPK calculated in step S0701. This is a measure to prevent invalid data from being read to the IPU 55 when the IPU 55 refers to these data structures during subsequent update operations of the FPMQ 46 and VFPBL 43.

[0133] In step S0703, the FPT update routine 48 updates FPMQ46 based on the FPK calculated in step S0701. The update of FPMQ46 is assumed to refer to a table managed independently by the CPU64, for example, and the details are omitted in this paper.

[0134] In step S0704, the FPT update routine 48 updates VFPBL43 based on the FPK calculated in step S0701.

[0135] In step S0705, the FPT update routine 48 uses the updated VFPBL address to call the VFPTD update request routine 60 again, and reflects the updated VFPBL address in the VFPTD 63 held in the work area 95 of each IPU 55.

[0136] Figure 17 shows the IPU load acquisition flow according to this embodiment.

[0137] In step S0801, the IPU load acquisition routine 30 acquires the processor load of IPU 55.

[0138] In step S0802, the IPU load acquisition routine 30 acquires the memory load of IPU 55.

[0139] In step S0803, the IPU load acquisition routine 30 acquires the DMA load of IPU 55.

[0140] In step S0804, the IPU load acquisition routine 30 creates an IPU load notification response that notifies the CPU 64 of the IPU load based on the load information acquired in steps S0801, S0802, and S0803.

[0141] In step S0805, the IPU load acquisition routine 30 stores the IPU load notification response created in step S0804 in CQ23 and sends it to the CPU 64.

[0142] In step S0806, the IPU load acquisition routine 30 waits for a certain period of time and returns to step S0801.

[0143] Figure 18 shows the FPRDT update flow according to this embodiment.

[0144] In step S0901, the FPRDT update routine 54 receives an IPU load notification response from one of the IPUs 55. This response contains information on processor load, memory load, and DMA load obtained by the IPU load acquisition routine 30.

[0145] In step S0902, the FPRDT update routine 54 updates the FPRDT 15 based on the information from the response received from the IPU 55 in step S0901. The update of the FPRDT 15 is as described with reference to Figures 9A to 9C. The FPRDT update routine then returns to step S0901 and waits for the next response.

[0146] Figure 19 shows the VFPBL release flow according to this embodiment.

[0147] In step S1001, the VFPBL release routine 62 calls the VFPTD update request routine 60, requesting each IPU 55 to remove the reference to the VFPBL 43 corresponding to the FPK in the FPTD and replace it with an invalid address.

[0148] In step S1002, the VFPBL release routine 62 releases VFPBL 43 from the CPU work area 45.

[0149] In step S1003, the VFPBL release routine 62 releases FPMQ46 from the CPU work area 45.

[0150] Figure 20 shows the VFPTD update flow according to this embodiment.

[0151] In step S1101, the VFPTD update routine 24 receives a VFPTD update request command from the CPU 64.

[0152] In step S1102, the VFPTD update routine 24 updates the VFPTD 63 located in the IPU work area 95 based on the FPK included in the VFPTD update request command received from the CPU 64 in step S1101 and its corresponding VFPBL address. The routine then returns to step S1101 to wait for the next VFPTD update request command.

[0153] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations.

[0154] Furthermore, each of the above-mentioned configurations, functions, and processing units may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above-mentioned configurations and functions may be implemented in software by having the processor interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card or SD card.

[0155] Furthermore, the control lines and information lines shown are those deemed necessary for explanatory purposes, and not all control lines and information lines are necessarily shown in the actual product. In practice, it is reasonable to assume that almost all components are interconnected. [Explanation of Symbols]

[0156] 55 I / O processors 64 CPU 76 Main Memory 79 IPU memory 84 Storage Systems 104 IPU package 114 DMA

Claims

1. It is a storage system, Central processing unit and The main memory of the central processing unit includes the program area and the work area, First management information that associates the hash value of the received data with the address in the volume, I / O processing package, The aforementioned I / O processing package is: I / O processor, The I / O memory includes the program area and work area of ​​the I / O processor, The central processing unit controls the read and write operations of user data. The I / O processor executes protocol processing, The I / O processor performs at least a portion of the address lookup process associated with the hash value of the first received data in the first management information, The central processing unit controls the execution of the deduplication process for the first received data based on the address data associated with the hash value of the first received data. The storage system includes a plurality of I / O processing packages, including the I / O processing package. The central processing unit is a storage system that determines the amount of the first management information search processing to be allocated to each of the multiple I / O processing packages based on the load of the multiple I / O processing packages.

2. The storage system according to Claim 1, The central processing unit is a storage system that determines the amount of the first management information search processing to be allocated to each of the multiple I / O processing packages based on the load of the I / O processor and I / O memory of each of the multiple I / O processing packages.

3. The storage system according to Claim 2, Each of the aforementioned multiple I / O processing packages further includes a DMA controller, The central processing unit is a storage system that determines the amount of the first management information search processing to be allocated to each of the multiple I / O processing packages based on the load of the I / O processor, I / O memory, and DMA controller of each of the multiple I / O processing packages.

4. A storage system, Central processing unit and The main memory of the central processing unit includes the program area and the work area, First management information that associates the hash value of the received data with the address in the volume, I / O processing package, The aforementioned I / O processing package is: I / O processor, The I / O memory includes the program area and work area of ​​the I / O processor, The central processing unit controls the read and write operations of user data. The I / O processor executes protocol processing, The I / O processor performs at least a portion of the address lookup process associated with the hash value of the first received data in the first management information, The central processing unit controls the execution of the deduplication process for the first received data based on the address data associated with the hash value of the first received data. The aforementioned storage system, Multiple I / O processing packages including the aforementioned I / O processing package, The system includes a range of hash values ​​for received data and a second management information that associates at least a portion of the assignment destinations for the search process in the first management information, The central processing unit determines the I / O processor to which at least a portion of the search process is assigned, based on the hash value of the first received data and the second management information, as a storage system.

5. A storage system, Central processing unit and The main memory of the central processing unit includes the program area and the work area, First management information that associates the hash value of the received data with the address in the volume, I / O processing package, The aforementioned I / O processing package is: I / O processor, The I / O memory includes the program area and work area of ​​the I / O processor, The central processing unit controls the read and write operations of user data. The I / O processor executes protocol processing, The I / O processor performs at least a portion of the address lookup process associated with the hash value of the first received data in the first management information, The central processing unit controls the execution of the deduplication process for the first received data based on the address data associated with the hash value of the first received data. The storage system includes second management information that associates a range of hash values ​​of received data with at least a portion of the allocation destinations for the search process in the first management information, The aforementioned allocation includes the I / O processor and the central processing unit, The central processing unit is a storage system that determines the allocation destination for at least a portion of the search process in the first management information for the second received data, based on the hash value of the second received data and the second management information.

6. A storage system, Central processing unit and The main memory of the central processing unit includes the program area and the work area, First management information that associates the hash value of the received data with the address in the volume, I / O processing package, The aforementioned I / O processing package is: I / O processor, The I / O memory includes the program area and work area of ​​the I / O processor, The central processing unit controls the read and write operations of user data. The I / O processor executes protocol processing, The I / O processor performs at least a portion of the address lookup process associated with the hash value of the first received data in the first management information, The central processing unit controls the execution of the deduplication process for the first received data based on the address data associated with the hash value of the first received data. The I / O memory holds the first partial information within the first management information, The first partial information associates the hash value of the received data with the address in the main memory of the second partial information within the first management information, The aforementioned I / O processor is Based on the hash value of the first received data, the first address in the main memory is obtained from the first partial information. A storage system that reads the second portion of the first address from the main memory into the I / O memory.

7. A storage system according to any one of claims 1, 4, 5, or 6, The aforementioned I / O processing package is a storage system that performs protocol processing in communication with the host.

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