Local cache for memory device

Abstract

A system and technique for buffering data locally within a memory device to allow access to data associated with a plurality of different rows within the memory device. The memory device includes a storage bank circuit having memory cells and a sense amplifier circuit coupled to the storage bank circuit. The memory device also includes a buffer circuit coupled to an output of the sense amplifier circuit. In addition, the memory device includes a selection circuit. The selection circuit receives a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit and outputs a selected one of the first data signal and the second data signal.

Description

Technical Field

[0001] The examples in this disclosure generally relate to locally buffering data within a memory device to allow access to data associated with multiple different rows within that memory device. Background Technology

[0002] In modern computer architectures, memory devices comprising multiple memory cells are used. An example memory device is Dynamic Random Access Memory (DRAM). A memory device contains a multi-level metric array of memory cells arranged in multiple memory banks. The memory cells are arranged in rows and columns within this array. A memory controller coupled to the memory cells provides memory commands to the memory device, indicating which memory cells to activate for reading from them (e.g., a read command) or writing to them (e.g., a write command). In one example, accessing a row of memory cells for a read command involves pre-charging the previously accessed row and activating the new target row. Data within the memory cells of the activated row is received by a sense amplifier and output to the memory controller. Summary of the Invention

[0003] In one example, a memory device includes: a memory bank circuit having memory cells; and a sense amplifier circuit coupled to the memory bank circuit. The memory device also includes a buffer circuit coupled to the output of the sense amplifier circuit. Additionally, the memory device includes a selection circuit. The selection circuit receives a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit, and outputs a selected one of the first data signal and the second data signal.

[0004] In one example, a method includes outputting a first data signal from a sense amplifier circuit of a memory device based on a first command. The first data signal corresponds to one or more first memory cells of the memory device. The method further includes outputting a second data signal from a buffer circuit of the memory device. The second data signal corresponds to a second command. The second data signal corresponds to one or more second memory cells in the memory device. Additionally, the method includes outputting a selected one of the first and second data signals from a selection circuit of the memory device.

[0005] In one example, a computing system includes: a memory controller configured to output a first command and a second command; and a memory device. The memory device includes: a sense amplifier circuit; a buffer circuit; and a selection circuit. The sense amplifier circuit outputs a first data signal based on the first command and a second data signal associated with the second command. The buffer circuit stores the second data signal based on receiving the second command. The selection circuit receives the first data signal from the sense amplifier circuit and the second data signal from the buffer circuit, and outputs a selected one of the first and second data signals.

[0006] These and other aspects can be understood by referring to the following detailed description. Attached Figure Description

[0007] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting the scope of the description.

[0008] Figure 1 A block diagram of the computing system is shown.

[0009] Figure 2 A block diagram of a memory system is shown.

[0010] Figure 3 A block diagram illustrating a portion of a memory system is shown.

[0011] Figure 4 A block diagram illustrating a portion of a memory system is shown.

[0012] Figure 5 A flowchart illustrating a method for executing a read command within a memory device is provided.

[0013] Figure 6 A flowchart illustrating a method for operating a memory device is provided.

[0014] Figure 7 A flowchart illustrating a method for operating a memory device is provided.

[0015] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0016] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the features, nor as a limitation on the scope of the claims. Furthermore, the illustrated examples do not necessarily possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0017] Computing systems use memory devices for data storage. A memory device comprises multiple memory cells that store values ​​(e.g., bits of data). Memory cells are arranged within an array. In one example, memory cells are arranged in rows and columns. In other examples, memory cells are arranged in different configurations. Memory cells store data as voltage values. Additionally, memory cells are connected to word lines and bit lines. In one example, each row of memory cells is connected to a corresponding word line (or two or more word lines). Word lines are driven to select the corresponding memory cell to be written to or read from. Word lines are coupled to row selection circuitry that drives the corresponding word line. Bit lines are driven to write values ​​to one or more selected memory cells (or multiple selected memory cells) or are electrically floated to read values ​​from one or more selected memory cells (or multiple selected memory cells). Bit lines are coupled to sense amplifier circuitry. The sense amplifier circuitry controls the voltage value of the bit lines to drive data to or read from selected memory cells within the memory cells.

[0018] In one example, two or more memory cells are grouped together to form a memory bank. In one or more examples, a memory bank includes one or more rows and / or one or more columns of memory cells.

[0019] A memory cell comprises one or more transistors and one or more capacitors. A memory cell may be referred to as a bit cell. Transistors are coupled to word lines and bit lines to control the selection, writing to, and reading from memory cells. One or more capacitors store the value (or bits) of the memory cell. Writing to a memory cell updates the voltage value of one or more capacitors.

[0020] In one example, to read from a row of a memory cell, the previously accessed row is precharged, and the target row is activated. Precharging the row closes the current row, restores the value read from the capacitor of the memory cell, and prepares the sensing amplifier to read another row of the memory cell.

[0021] Precharging the currently active row of a memory cell to activate another row of the memory cell is known as a row or page conflict. Row or page conflicts use a large number of cycles, thereby increasing the latency of the memory device. The memory device described below includes: a buffer circuit that stores data associated with a first active row of the memory cell; and a sense amplifier circuit that reads data associated with a second row of the memory cell. The first row of the memory cell is deactivated (e.g., precharged), while the second row of the memory cell is activated. The data associated with the first row of the memory cell remains in the buffer circuit, while the data associated with the second row of the memory cell is activated. Therefore, data associated with multiple rows of the memory cell can be accessed without row or page conflicts. Thus, the latency of the memory device is reduced, thereby improving the performance of the memory device.

[0022] Figure 1 An example is illustrated of a computing system 100 including a memory device 110 coupled to a host device 120. The host device 120 includes a memory controller 122 and a processing device 124. The processing device 124 is a central processing unit (CPU) or a graphics processing unit (GPU), etc.

[0023] In one example, memory device 110 is a double data rate (DDR) memory device. In one or more examples, memory device 110 is DDR1, DDR2, DDR3, DDR4, or DDR5, or another type of DDR memory. In other examples, memory device 110 is another type of memory. In one or more examples, memory device 110 is a dual in-line memory module (DIMM). In one or more examples, memory device 110 is a multi-rank buffered (MR) DIMM.

[0024] Memory device 110 includes row control circuitry 112, read / write circuitry 114, memory cells 116, bit lines 117, and word lines 118. Memory cells 116 are configured as an array. For example, memory cells 116 are configured as rows and columns. In other examples, the memory cells are configured in other ways. In one example, a row (or another group) of memory cells 116 is coupled to a common word line 118 or two or more word lines 118. In one or more examples, at least one word line 118 is coupled to two or more rows (or other groups) of memory cells 116. In one or more examples, a column (or other group) of memory cells 116 is coupled to a common bit line 117 or two or more bit lines 117. In one or more examples, at least one bit line 117 is coupled to two or more columns (or other groups) of memory cells 116.

[0025] Memory cell 116 includes one or more transistors and one or more capacitors. The transistors of memory cell 116 are connected to one or more word lines 116 and one or more bit lines 117. The transistors control the activation or deactivation of the corresponding memory cell 116 based on the voltage values ​​of the one or more word lines 118 and the one or more bit lines 117. The one or more capacitors of memory cell 116 store the value of memory cell 116. In one example, the value is updated or read from the one or more capacitors of the activated memory cell 116.

[0026] The row control circuit 112 is connected to the word line 118. The row control circuit 112 is coupled to the memory cell 116 via the word line 118.

[0027] The row control circuit 112 controls the activation and deactivation of memory cells 116 by controlling how the corresponding word lines 118 are driven. In one example, one or more memory cells 116 are activated for updating by driving one or more predetermined voltage levels on the corresponding word lines 118.

[0028] In one example, row control circuitry 112 receives one or more signals (e.g., address signals, control signals, and / or data signals, etc.) indicating which of the word lines 118 to drive to activate one or more corresponding memory cells in memory cell 116.

[0029] Read / write circuitry 114 is connected to bit line 117. In one example, read / write circuitry 114 is connected to memory cell 116 via bit line 117. In one example, read / write circuitry 114 drives one or more bit lines in bit line 117 to update the value of the corresponding memory cell 116 and / or read the value from the corresponding memory cell 116. In one example, read / write circuitry 114 includes a sense amplifier circuit connected to bit line 117 and configured to receive signals from memory cell 116 via bit line 117 and / or write values ​​to memory cell 116 via bit line 117.

[0030] In one example, read / write circuitry 114 receives one or more signals (e.g., address signals, control signals, and / or data signals, etc.) that indicate which of the bit lines 117 should be driven to activate a corresponding memory cell or more in memory cell 116 for updating or reading from it.

[0031] The memory controller 122 transmits address signals, control signals, and data signals to the memory device 110. The processing device 124 provides data signals to the memory controller 122. The memory controller 122 generates control and address signals associated with the data signals. The memory controller 122 receives data signals from the memory device 110. The memory device 110 generates data signals based on the address and / or control signals generated and output by the memory controller 122.

[0032] Figure 2 An example of memory device 210 is shown. Memory device 210 and... Figure 1 The memory device 110 is similarly configured. The memory device 210 includes memory bank circuitry 250, sense amplifier circuitry 220, buffer circuitry 230, and select circuitry 240. Each memory bank circuit in the memory bank circuitry 250 includes one or more memory cells (e.g., ...). Figure 1 (One or more memory cells in memory cell 116). In one example, each memory bank circuit in memory bank circuit 250 includes different one or more memory cells (e.g., Figure 1 (One or more different memory cells in memory cell 116). Sensing amplifier circuit 220 is included in the read / write circuit (e.g., Figure 1 The read / write circuit 114 is included within the read / write circuit. In one example, a buffer circuit 230 is included within the read / write circuit (e.g., Figure 1 The read / write circuit 114 is located within the read / write circuitry of the memory device 210, or is located in a circuit element outside the read / write circuitry. In one example, the selection circuitry 240 is included in the read / write circuitry (e.g., ...). Figure 1 The read / write circuit 114 is located within the read / write circuitry of the memory device 210 or in circuitry elements outside the read / write circuitry. In one or more examples, the sense amplifier circuitry 220, the buffer circuitry 230, and the selection circuitry 240 are included in the read / write circuitry (e.g., the read / write circuitry 114). Figure 1 The read / write circuit 114 is included within the read / write circuit. In another example, one or more of the sense amplifier circuit 220, buffer circuit 230, and selection circuit 240 are included in the read / write circuit (e.g., Figure 1 The read / write circuit 114 is included within the memory device 210, and one or more of the sense amplifier circuit 220, buffer circuit 230, and selection circuit 240 are included in the read / write circuit (e.g., Figure 1 The read / write circuit 114) is located in the external circuit elements.

[0033] Memory device 210 includes memory circuits 2501 to 2501. NN is a number of two or greater. Each memory bank circuit 250 is coupled to a corresponding sense amplifier circuit 220 and a corresponding buffer circuit 230. For example, memory bank circuit 2501 is coupled to sense amplifier circuit 2201 and buffer circuit 2301. Sense amplifier circuit 2201 and buffer circuit 2301 are coupled to selection circuit 2401. Memory bank circuit 2502 is coupled to sense amplifier circuit 2202 and buffer circuit 2302. Sense amplifier circuit 2202 and buffer circuit 2302 are coupled to selection circuit 2402. Memory bank circuit 250 N Coupled to the sense amplifier circuit 220 N and buffer circuit 230 N Sensing amplifier circuit 220 N and buffer circuit 230 N Coupled to selection circuit 240 N .

[0034] As in Figure 3 As illustrated in the example, memory bank circuitry 250 includes memory cells 310 arranged in columns 320 and rows 330. Memory cells 310 and... Figure 1 The memory cell 116 is similarly configured. The memory bank circuit 250 includes two or more columns and / or two or more rows 330 (or other configurations of the memory cells). Additionally, the memory bank circuit 250 includes two or more memory cells 310. Each row 330 includes two or more memory cells 310. Each column includes two or more memory cells 310.

[0035] The memory circuit 250 also includes a row control circuit 340 and a column control circuit 350. The row control circuit 340 and... Figure 1 The row control circuit 112 is similarly configured. The row control circuit 340 is connected to row 330. Each row 330 is connected via word lines (e.g., Figure 1 The word line 118 is connected to the row control circuit 340. The row control circuit 340 selects and activates the memory cell 310 of row 330 based on control and / or address signals received from the host device 120. The column control circuit 350 is connected via bit lines (e.g., Figure 1 The bit line 117 is coupled to column 320. Column control circuit 350 controls the selection of column 320 by driving the bit line with a voltage signal. The bit line is associated with column 320.

[0036] Column 320 is coupled to sense amplifier circuit 220 via column control circuit 350. For example, memory cell 310 of column 320 is coupled to sense amplifier circuit 220 via bit lines. In one example, sense amplifier circuit 220 receives data from memory cell 310 via bit lines.

[0037] Each sense amplifier circuit in sense amplifier circuit 220 includes one or more sense amplifiers. Memory device 210 includes sense amplifier circuits 2201 to 220. M N is a number of two or greater. In one example, M equals N. In other examples, M is greater than or less than N. The sensing amplifier circuit 220 includes sensing amplifiers that sense memory cells (e.g., Figure 3 The voltage corresponding to the data on the memory cell (310), the voltage of the amplified memory cell, and / or the memory cell precharged to disable these memory cells. Memory cell (e.g., Figure 3 The memory cell 310 includes one or more transistors and one or more capacitors. The transistors are coupled to bit lines and word lines to control the selection of the memory cell, and the one or more capacitors store voltage values ​​associated with data stored in the memory cell. The sense amplifier circuit 220 senses and amplifies the voltage on the memory cell and outputs the voltage to the selection circuit 240.

[0038] The output of each sense amplifier circuit 220 is coupled to a corresponding circuit in the buffer circuit 230 and the selection circuit 240. The memory device 210 includes buffer circuits 2301 to 230. P P is a number of two or greater. P is greater than or less than M and / or N. Additionally, memory device 210 includes selection circuits 2401 to 240. Q Q is a number of two or greater. Q is greater than or less than M, N, and / or P.

[0039] In one example, memory device 210 includes a single buffer circuit 230. In this example, each sense amplifier circuit in sense amplifier circuit 220 is coupled to the same buffer circuit 230. In other examples, N is greater than P. In this example, two or more sense amplifier circuits in sense amplifier circuit 220 are coupled to the same buffer circuit 230.

[0040] In one or more examples, the output of the sensing amplifier circuit 2201 is coupled to the buffer circuit 2301 and the selection circuit 2401, and the output of the sensing amplifier circuit 2202 is coupled to the buffer circuit 2302 and the selection circuit 2401. M And sensing amplifier circuit 220 M The output is coupled to the buffer circuit 230. P and selection circuit 240 Q .

[0041] The sense amplifier circuit 220 outputs a data signal to the buffer circuit 230, and the buffer circuit 230 stores the data of the data signal. The data signal is associated with an active row 330. Each buffer circuit 230 includes one or more latches and / or one or more flip-flops. In other examples, the buffer circuit 230 includes a sense amplifier and is configured similarly to the sense amplifier circuit 220. In other examples, the buffer circuit 230 includes other types of memory elements. In one example, the buffer circuit 230 is configured to store data associated with a row (e.g., row 330) of the memory bank circuit 250.

[0042] Buffer circuit 230 is configured to store one or more bits of a page. A page corresponds to one or more memory cells of memory bank circuit 250. In one example, a page corresponds to a row of memory cells. In one example, buffer circuit 230 is configured to store a small portion of a page (e.g., 1 / 2, 1 / 4, 1 / 8, or 1 / T, where T is greater than 8).

[0043] In one or more examples, one or more buffer circuits 230 store multiple rows of memory cells (e.g., Figure 3 The data associated with row 330. For example... Figure 3 As illustrated, buffer circuit 230 includes a plurality of row buffer circuits 360. In one example, buffer circuit 230 includes row buffer circuits 3501 to 350. S S is a number of two or greater. Each row buffer circuit is configured to store data associated with one or more rows 330 of the memory unit 310.

[0044] Selection circuit 240 is a multiplexer (MUX). In other examples, the selection circuit is a different type of selection circuit. Selection circuit 240 has a first input coupled to the output of the corresponding sense amplifier circuit 220 and the output of the corresponding buffer circuit 230. For example, the first input of selection circuit 2401 is coupled to the output of sense amplifier circuit 2201, and the second input of selection circuit 2401 is coupled to the output of buffer circuit 2301. Additionally, the first input of selection circuit 2402 is coupled to the output of sense amplifier circuit 2202, and the second input of selection circuit 2402 is coupled to the output of buffer circuit 2302.

[0045] Selection circuit 240 receives a first data signal from corresponding sense amplifier circuit 220 and a second data signal from corresponding buffer circuit 230, and outputs one of the first and second data signals based on a control signal. The control signal is provided by a memory controller (e.g., Figure 1 The memory controller 122 is provided.

[0046] In one example, memory device 210 receives one or more command signals from a host device (e.g., host device 120). The command signals may be read command signals (e.g., a read operation) or write command signals (a write operation). Additionally, the command signals may indicate an address within memory bank circuitry 250, which is the target address to which data is written or read. In one example, the command signals may be decoded to indicate the columns 320 and rows 330 of a particular memory bank circuitry 250 to be activated to execute the command signals.

[0047] In one example, the command signal includes an indication (e.g., one or more values) for determining whether data is selected and output from sense amplifier circuit 220 or buffer circuit 230. For example, the command signal may include an encoded value decoded by memory device 210. The decoded value is provided to selection circuit 240 to determine whether one or more values ​​read from memory circuit 250 are selected and output from one of the buffer circuits, sense amplifier circuit 220 or buffer circuit 230. The decoded value is provided to selection circuit 240 as a control signal. In one example, the command signal is a Command Address Strobe (CAS) command signal, which includes an encoded value indicating whether one or more values ​​received from sense amplifier circuit 220 or buffer circuit 230 are selected and output.

[0048] The output of the selection circuit 240 is coupled to the host device 120. For example, the output of the selection circuit 240 is coupled to the memory controller 122 and outputs a data signal to the memory controller 122. In one example, the output of the selection circuit 240 is coupled to a first-in-first-out (FIFO) buffer circuit within the read data path circuit of the memory device. The FIFO buffer circuit is coupled to the memory controller 122. In one example, a driver circuit is used to drive the data signal to the memory controller 122.

[0049] Figure 4 A memory device 400 is illustrated. The memory device 400 includes input / output (I / O) circuitry 410, read data path circuitry 420, write data path circuitry 430, and memory bank circuitry 250. The I / O circuitry 410 is coupled to the memory bank circuitry 250 via the read data path circuitry 420 and the write data path circuitry 430. The I / O circuitry 410 is connected to a memory controller (e.g., Figure 1 The memory controller 122 receives data to be written to the memory bank circuit 250 and provides the data to the memory bank circuit 250 via the write data path circuit 430. The write data path circuit 430 includes a deserializer circuit, one or more flip-flops, and alignment circuitry, etc. In one example, a write driver circuit coupled to the memory bank circuit 250 receives a data signal and drives the data signal to an active memory cell to update the memory cell.

[0050] The memory circuit 250 outputs data to the I / O circuit 410 via the data path circuit 420, which in turn outputs the data to the memory controller (e.g., ...). Figure 1 The memory controller 122). In one example, the sense amplifier circuit (e.g., sense amplifier circuit 220) draws from one or more memory cells (e.g., memory controller 122). Figure 3 The memory cell 310 obtains data. The sense amplifier circuit outputs the data to the I / O circuit 410 via the data read path circuit 420.

[0051] In one example, the read data path circuit 420 includes a read buffer circuit 422 and a driver circuit 424. The read buffer circuit 422 receives a data signal from the sense amplifier circuit and transmits the data signal to the driver circuit 424, which outputs the data signal to the I / O circuit 410. In one example, the driver circuit 424 is a serializer circuit.

[0052] In one example, buffer circuit 422 includes buffer circuit 440, buffer circuit 442, and selection circuit 444. Buffer circuit 440 and buffer circuit 442 are connected to... Figure 2 The buffer circuit 230 functions similarly and is configured similarly. For example, buffer circuits 440 and 442 each store data associated with one or more rows of the memory bank circuit 250. In one example, buffer circuit 440 stores data associated with a first row, and buffer circuit 442 stores data associated with a second row. The first row corresponds to the currently active row within the memory bank circuit 250, and the second row corresponds to an inactive row (e.g., a previously active row that is now deactivated). The outputs of buffer circuits 440 and 442 are connected to selection circuit 444. Selection circuit 444 is configured similarly to selection circuit 240. In one example, selection circuit 444 outputs a data signal from one of the buffer circuits 440 and 442 based on a control signal provided by a memory controller (e.g., memory controller 122). Therefore, in this configuration, data corresponding to the currently active row of the memory cell and data corresponding to the previously active row of the memory cell can be output to a host device (e.g., Figure 1 (The host device 120).

[0053] Figure 5 A flowchart illustrating a method 500 for accessing a memory device according to one or more examples is shown. Method 500 comprises a memory device 210 and a host device (e.g., Figure 1The host device 120 performs the operation. At operation 510, a first command signal associated with the first row is received from a memory controller (e.g., memory controller 122). In one example, memory controller 122 generates the command signal based on control signals received from processing device 124. The command signal may be an activation command signal. The activation command signal is part of a read or write memory operation. The activation command is a row access command. In one example, the activation command activates (e.g., opens or selects) a row (e.g., row 330) and outputs (e.g., pulls) data (e.g., charge) to sense amplifier circuit 220. The data may be output from sense amplifier circuit 220 to buffer circuit 230. In another example, the activation command activates a row (e.g., row 330), and data is pulled to sense amplifier circuit 220. A read command is used to output data from sense amplifier circuit 220 to buffer circuit 230.

[0054] In one example, the command signal includes multiple bits indicating a target address within memory device 210 and one or more control values. The control values ​​are indicated via one or more bits. The one or more bits can be used to determine whether data will be stored in buffer circuit 230 and / or selected and output from sense amplifier circuit 220 or buffer circuit 230. In one example, the one or more control bits may indicate which of the buffer circuits 230 should store data. In one example, in addition to the command signal, memory controller 122 also outputs one or more control signals with one or more bits. The one or more bits indicate whether the data associated with the command signal will be stored... Figure 2 The buffer circuit 230 contains controls for the selection circuit 240. In one example, one or more bits can indicate which of the buffer circuits 230 should store data.

[0055] In one example, buffer circuit 230 is a small fraction of the page size (e.g., a small fraction capable of storing one or more rows of memory). In this example, one or more bits include an indication of the number of bits to be stored within buffer circuit 230 regarding the page (or row). In one or more examples, one or more bits indicate loading multiple bits starting from the first or last bit associated with the command signal.

[0056] In one example, one or more bits indicate a specific portion of a page (or row) to be stored within buffer circuit 230. For example, a page within memory bank circuit 250 is divided into multiple portions. One or more bits indicate which of these portions should be stored within buffer circuit 230. In one example, the portion of a page to be stored within buffer circuit 230 corresponds to the portion of the page in which address information associated with a command signal is stored. For example, the address information associated with a command signal is stored in the third portion (e.g., the third 1 / 8) of a page in the memory bank. In this example, the third portion of the page is stored within buffer circuit 230.

[0057] Memory device 210 receives a command signal and activates a first row 330 within first memory bank circuitry 250 associated with the address of the read command. Sensing amplifier circuitry 220 generates and outputs a data signal from the voltage within the activated row or a corresponding portion of the activated row. In one example, the active row is referred to as the first row.

[0058] In one example, the memory controller 122 maintains a page table that indicates data stored in rows or portions of rows within the buffer circuit 230. Additionally, in one or more examples, the memory controller 122 reorders commands such that commands for common rows occur sequentially. The memory controller 122 generates control signals based on the target row of the command and the data stored in the buffer circuit 230. For example, based on a determination of whether data associated with the target row is stored in the buffer circuit 230. Based on data being stored in the buffer circuit 230, the memory controller 122 generates a control signal that provides an indication to the selection circuit to select the output of the buffer circuit 230 for output. Based on data not being stored in the buffer circuit 230, the memory controller 122 generates a control signal that provides an indication to the selection circuit 240 to output the data signal from the sense amplifier circuit 220. The memory controller 122 may additionally generate one or more bits of a command signal or control signal that provides an indication to the buffer circuit 230 to store the data signal or not store the data signal. In one example, data is not stored in buffer circuit 230 to maintain the current data in buffer circuit 230 as the target of subsequent memory commands. In an example where buffer circuit 230 includes multiple row buffer circuits 360, one or more bits or control signals may indicate from which row buffer circuit 360 data should be output and / or in which row buffer circuit 360 data should be stored.

[0059] In one example, an indication (e.g., one or more values) is included within one or more bits of a command or control signal. This indication is used to determine whether data is selected and output from the sense amplifier circuit 220 or the buffer circuit 230.

[0060] At operation 520, a data signal associated with the first row of the memory cell is stored in a buffer circuit, and a data signal is output from a selection circuit. In one example, one or more control signals are transmitted from memory controller 122 to memory device 210 along with a read command. The one or more control signals include one or more bits providing an indication to buffer circuit 230 to store the data signal associated with the first row. The one or more control signals are received by buffer circuit 230. Buffer circuit 230 determines whether to store the data signal received from sense amplifier circuit 220. In one example, buffer circuit 230 receives the data signal from sense amplifier circuit as well as the control signal, and stores the data signal within buffer circuit 230 based on the value of the bit in the control signal. The data signal includes data (e.g., the voltage value of a bit) associated with an entire page (row) or a portion of a page. In one or more examples, storing the data signal within buffer circuit 230 includes storing the data signal within row buffer circuit 3601 of buffer circuit 230.

[0061] The data signal associated with the first row (or a portion thereof) is further output to selection circuitry 240. Selection circuitry 240 outputs the data signal to memory controller 122 via a read data path and / or other output circuitry of memory device 210. In one example, one or more control signals are further received by selection circuitry 240 from memory controller 122. The one or more control signals provide selection circuitry 240 with an indication of whether to select and output the data signal received from sense amplifier circuitry 220 or the data signal received from buffer circuitry 230. The value of the one or more control signals determines which data signal is output by selection circuitry 240.

[0062] At operation 530, a second command associated with the second row is received from the memory controller. For example, memory device 110 receives the second command. Additionally, one or more second control signals are output from memory controller 122 to memory device 110. In one or more examples, memory bank circuitry 250 selects and activates the second row 330 of memory cell 310 based on the second command. The first row is pre-charged and deactivated, making the second row selectable and activated. Sensing amplifier circuitry 220 generates a second data signal based on data within the memory cells of the second row. The second data signal is output from sensing amplifier circuitry 220. In one example, at operation 530 of method 500, upon receiving data associated with the second command and in the source amplifier circuitry, data associated with the first row of memory cells and stored in buffer circuitry 230 is accessible.

[0063] In one or more examples, at least a portion of operations 520 and 530 of method 500 may occur during periods that at least partially overlap. In one example, at least a portion of operations 520 and 530 of method 500 occur in parallel. In other words, in one or more examples, first data can be read from buffer circuit 230 at operation 520 of method 500, while second data is loaded into sense amplifier circuit 220 at operation 530 of method 500. In one or more examples, operations 520 and 530 of method 500 occur during non-overlapping periods.

[0064] Buffer circuit 230 receives a second or more control signals and determines whether to store data associated with the second data signal. In one example, based on the value of a bit in the second or more control signals, buffer circuit 230 determines not to store data associated with the second data signal. In this example, memory controller 122 generates a control signal indicating that data associated with the second data signal should not be stored because a pending read command targets data associated with the first data signal. Therefore, when the pending command is executed, data associated with the first data signal can be read from buffer circuit 230.

[0065] In one example, buffer circuit 230 stores the second data signal in second row buffer circuit 3302 based on a second or more control signals.

[0066] At operation 540, the selection circuit selects the output data signal associated with the second row of the memory cell. In one example, the selection circuit 240 receives a second data signal from the sense amplifier circuit 220, a first data signal from the buffer circuit 230, and one or more second control signals. Based on the values ​​of the second or more control signals, the selection circuit 240 selects and outputs one of the second and first data signals. In one example, the control signals are associated with a second command; therefore, the selection circuit 240 selects and outputs the second data signal from the sense amplifier circuit 220, since the second data signal includes data associated with the second row 330, which is the target of the second read command.

[0067] At operation 550, a third command associated with the first row is received from the memory controller. The memory controller 122 outputs the third command to the memory device, which includes one or more third control signals. The third or more third control signals include an indication to the selection circuit to select the data signal output from the buffer circuit 230. In addition, the third or more third control signals provide an indication to the memory bank circuit 250 and the sense amplifier circuit 220 to maintain the currently active second row as the active row.

[0068] At operation 560, the selection circuit selects and outputs the data associated with the first row of the memory cell, which is output by the buffer circuit. The selection circuit 240 receives a data signal from the sense amplifier circuit 220, a data signal from the buffer circuit 230, and a third or more control signals. Based on the value of the control signal, the selection circuit 240 selects and outputs the data signal received from the buffer circuit 230.

[0069] In one example, buffer circuit 230 receives a third or more control signals and selects and outputs data from a row buffer circuit 360 associated with the received read command.

[0070] At operation 570, a fourth command associated with the second row of memory cells is received from the memory controller. The memory bank circuit 250 receives the fourth command and deactivates the second row of memory cells by pre-charging it based on a control signal received from the memory controller 122. Additionally, the third row is activated. The sense amplifier circuit 220 receives data associated with the memory cells in the third row and generates a data signal.

[0071] At operation 580, data associated with the third row of the memory cell is stored in a buffer circuit and output from a selection circuit. In one example, buffer circuit 230 receives a control signal from memory controller 122 and a data signal from buffer circuit 230, and stores the data of the data signal in buffer circuit 230. In one or more examples, buffer circuit 230 overwrites the data in buffer circuit 230 with the data of the data signal associated with the third row. In one example, buffer circuit 230 stores the data of the data signal in row buffer circuit 360 based on a third or more control signals. Additionally, the selection circuit selects and outputs the data signal output from sense amplifier circuit 220 based on a third or more control signals received by memory controller 122.

[0072] In one example, a page hit is determined when the memory controller 122 determines that the data for the target row of a read command is within the sense amplifier circuit 220 and / or the buffer circuit 230. A page hit allows data associated with the target row of the read command to be output from the memory device without pre-charging (deactivating) the row and activating a new row. Therefore, the latency of this memory device is reduced compared to a memory device without buffer circuitry. In one example, the memory controller 122 reorders pending read commands based on data stored in the buffer circuit 230.

[0073] While the above description pertains to executing read commands, in other examples, buffer circuit 230 can be used to execute write commands. In one example, data signals are maintained within buffer circuit 230 while data signals are written to and updated in one or more rows 330 of memory cell 310. In one example, when a row 330 in memory bank circuit 250 is written and the data associated with that row is stored in buffer circuit 230, buffer circuit 230 evicts the data and the row is updated in memory bank circuit 250. Control signals provided by memory controller 122 can provide indication for buffer circuit 230 to evict the data associated with the row. In another example, the write command includes updating the data associated with the target row of the write command within buffer circuit 230. Data is then written from buffer circuit 230 to memory cell 310 of memory bank circuit 250. Control signals provided by memory controller 122 are used to control the writing of data to buffer circuit 230 and the writing of data from buffer circuit 230 to memory cell 310.

[0074] Figure 6 Examples are given for operating memory devices (e.g., Figure 1 The memory device 110 and / or Figure 2 A flowchart of method 600 for a memory device 210. Method 600 includes operation 510, namely, receiving a first read command associated with a first row of memory cells from a memory controller. (The above refers to...) Figure 5 Operation 510 is described in more detail. Additionally, method 600 includes operation 520, which involves storing data associated with the first row of the memory cell in a buffer circuit and outputting a data signal from the selection circuit. The above refers to... Figure 5 Operation 520 is described in more detail. Method 600 also includes operation 610, which refreshes one or more cells of the memory device. For example, refreshing... Figure 1 One or more memory cells in memory cell 116. Refreshing a memory cell involves refreshing the data (e.g., values) stored within the memory cell. In one or more examples, the memory cell experiences leakage (e.g., charge leakage corresponding to a capacitor). Over time, leakage may lead to the loss of data within the memory cell. During the refresh process, one or more memory cells 116 are selected via row control circuitry 112 and read / write circuitry 114 and driven with the original values ​​stored within the memory cells, thereby refreshing the value of the selected memory cell 116. Reference Figure 2 The memory refresh process can be applied to one or more memory bank circuits in memory bank circuit 250. In other examples, the memory refresh process is applied to one or more rank circuits of the memory device.

[0075] At operation 620 of method 600, output the data associated with the first row. For example, refer to... Figure 2 The selection circuit 240 selects the data to be output from the buffer circuit 230. While the selection circuit 240 selects the data to be output from the buffer circuit 230, the sense amplifier circuit 220 can be used to refresh the memory circuit 250 (e.g., refresh...). Figure 1 One or more memory cells 116). Therefore, one or more memory cells 250 can be refreshed while selecting and outputting data from buffer circuit 230. In one example, one or more memory cells 250 are refreshed via sense amplifier circuit 220 (or Figure 1 One or more memory cells 116), and during at least partially overlapping time periods, data is selected and output from one or more buffer circuits in buffer circuit 230 via selection circuit 240. In one example, one or more memory circuits in memory circuit 250 are refreshed via sense amplifier circuit 220 (or Figure 1 One or more memory cells 116), and concurrently select and output data from one or more buffer circuits in buffer circuit 230 via selection circuit 240. Thus, during a period that at least partially overlaps with the period of refreshing one or more memory cells and / or rows of a memory device (e.g., memory device 210), data according to one or more memory cells and / or rows of the memory device is output based on read commands from buffer circuit 230.

[0076] In one example, operations 610 and 620 of method 600 occur during a period that at least partially overlaps. In another example, operations 610 and 620 occur in parallel with each other. In examples where operations 610 and 620 occur during a period that at least partially overlaps or in parallel with each other, data can be read from buffer circuitry 230 when the corresponding memory circuitry is refreshed via a refresh cycle in which data access is normally blocked. In other examples, operation 610 may occur before or after operation 620.

[0077] Figure 7 Examples are given for operating memory devices (e.g., Figure 1 The memory device 110 and / or Figure 2 A flowchart of method 700 for the memory device 210. At operation 710 of method 700, a first data signal is output from the sense amplifier circuit based on a first read command. (See also...) Figure 1Based on a first command, the sense amplifier circuit 220 outputs a first data signal based on a first or more memory cells in the memory cells of the memory bank circuit 250. The first data signal is output to the selection circuit 240. Outputting the first data signal includes activating one or more word lines and driving one or more bit lines, as described in more detail above, to select one or more memory cells of the memory bank circuit 250, and to receive data from the selected one or more memory cells. The first command corresponds to a first address.

[0078] At operation 720 of method 700, a second data signal is output from the buffer circuit based on the second command. (See reference) Figure 2 Based on the second command, buffer circuit 230 outputs a second data signal based on a second or more memory cells in the memory cells of memory bank circuit 250. The second data signal is output to selection circuit 240. In one example, the second data was previously output from sense amplifier circuit 220 and loaded (stored) in buffer circuit 230, as described above.

[0079] At operation 730 of method 700, a selected one of a first data signal and a second data signal is output from a selection circuit. For example, selection circuit 240 selects either the first data signal output from sense amplifier circuit 220 or the second data signal output from buffer circuit 230, and outputs the selected data signal. Selection circuit 240 receives a control signal indicating which data signal to select. The control signal is associated with a command. For example, if the data associated with the command is stored in the buffer circuit, the control signal indicates that the second data signal output from the buffer circuit is to be output. If the data associated with the command is stored in the sense amplifier circuit, the control signal indicates that the first data signal output from the sense amplifier circuit is to be output. The data signal is output from selection circuit 240 and provided to a host device (e.g., Figure 1 The host device 120), as described in more detail above.

[0080] Row or page collisions involve recharging a currently active memory cell in a memory device to activate other memory cells. These collisions utilize numerous cycles, increasing the latency of the memory device. As described above, row or page collisions can be mitigated by including buffer circuitry within the memory device. The buffer circuitry is capable of storing data associated with a first active memory cell, while a sense amplifier circuitry reads data associated with a second memory cell. When the second memory cell is activated, the memory cells are deactivated (e.g., pre-charged). The data associated with the first memory cell remains in the buffer circuitry, while the data associated with the second memory cell is activated. Therefore, data associated with multiple memory cells can be accessed without row or page collisions. This reduces the latency of the memory device, thereby improving its performance.

[0081] The techniques described above may be partially embodied in the following non-limiting embodiments.

[0082] Example 1. A memory device, the memory device comprising: a memory bank circuit including memory cells; a sense amplifier circuit coupled to the memory bank circuit; a buffer circuit coupled to an output of the sense amplifier circuit; and a selection circuit configured to receive a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit, and to output a selected one of the first data signal and the second data signal.

[0083] Example 2. The memory device according to Example 1, wherein the first data signal is associated with a first or more memory cells in the memory cell, and the second data signal is associated with a second or more memory cells in the memory cell.

[0084] Example 3. The memory device according to Example 2, wherein the sense amplifier circuit is configured to store data associated with a second or more memory cells in the memory cells within the buffer circuit.

[0085] Example 4. The memory device according to Example 2, wherein the first data signal is associated with a first read command and the second data signal is associated with a second read command.

[0086] Example 5. The memory device according to Example 1, wherein the sensing amplifier circuit is configured to store data associated with a third read command within the buffer circuit.

[0087] Example 6. The memory device according to Example 1, wherein the buffer circuit includes row buffer circuits, each of the row buffer circuits is configured to store data associated with a data signal, and wherein the buffer circuit is configured to output a data signal from one of the row buffer circuits based on a read command.

[0088] Example 7. The memory device according to Example 1, wherein the sensing amplifier circuit is configured to refresh one or more memory cells in the memory cells, and the selection circuit is configured to output the second data signal from the buffer circuit during at least partially overlapping time periods.

[0089] Example 8. The memory device according to Example 1, wherein the buffer circuit is configured to store a number of bits less than the number of bits in a page of the memory device.

[0090] Example 9. A method comprising: outputting a first data signal from a sense amplifier circuit of a memory device based on a first command, wherein the first data signal corresponds to a first or more memory cells of the memory device; outputting a second data signal from a buffer circuit of the memory device, wherein the second data signal corresponds to a second command and wherein the second data signal corresponds to a second or more memory cells of the memory devices; and outputting a selected one of the first data signal and the second data signal from a selection circuit of the memory device.

[0091] Example 10. The method according to Example 9, the method further includes: receiving the first command; and outputting the first data signal from the selection circuit based on receiving the first command.

[0092] 11. The method according to Embodiment 9, the method further comprising: receiving the second command; and outputting the second data signal from the selection circuit based on receiving the second command.

[0093] Example 12. The method according to Example 9, the method further comprising: receiving a third command, wherein the target of the third command is a third or more memory cells in the memory cells of the memory device; outputting a third data signal associated with the third or more memory cells in the memory cells from the sense amplifier circuit; storing the third data signal in the buffer circuit; and outputting the third data signal from the selection circuit.

[0094] Example 13. According to the method of Example 12, the method further includes selecting one of the second data signal and the third data signal to output from the buffer circuit.

[0095] Example 14. The method according to Example 9, the method further comprising: receiving a fourth command, wherein the target of the fourth command is a fourth or more memory cells in the memory cells of the memory device; outputting a fourth data signal associated with the fourth or more memory cells in the memory cells from the sense amplifier circuit; receiving a second data signal from the buffer circuit and the fourth data signal from the sense amplifier circuit at the selection circuit; and outputting the fourth data signal from the selection circuit based on receiving the fourth command.

[0096] Example 15. The method according to Example 9, the method further comprising refreshing one or more memory cells in the memory cells via the sensing amplifier circuit, and outputting the second data signal from the buffer circuit via the selection circuit during at least partially overlapping time periods.

[0097] Example 16. A computing system comprising: a memory controller configured to output a first command and a second command; and a memory device comprising: a sense amplifier circuit configured to output a first data signal based on the first command and a second data signal associated with the second command; a buffer circuit configured to store the second data signal based on receiving the second command; and a selection circuit configured to receive the first data signal from the sense amplifier circuit and the second data signal from the buffer circuit, and output a selected one of the first data signal and the second data signal.

[0098] Example 17. The computing system according to Example 16, wherein the sensing amplifier circuit is configured to store data of one or more memory cells of the memory device in the buffer circuit.

[0099] Example 18. The computing system according to Example 16, wherein the sensing amplifier circuit is configured to store data associated with a third or more memory cells in the memory cells of the memory device and based on a third command within the buffer circuit.

[0100] Example 19. The computing system according to Example 16, wherein the sensing amplifier circuit is configured to refresh one or more memory cells of the memory device, and the selection circuit is configured to output the second data signal from the buffer circuit during at least partially overlapping time periods.

[0101] Example 20. The computing system according to Example 16, wherein the buffer circuit is configured to store a number of bits less than the number of bits in a page of the memory device.

[0102] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. A memory device, the memory device comprising: A storage circuit, the storage circuit including a memory unit; A sensing amplifier circuit, the sensing amplifier circuit being coupled to the memory circuit; A buffer circuit, which is coupled to the output of the sensing amplifier circuit; and The selection circuit is configured to receive a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit, and output a selected one of the first data signal and the second data signal.

2. The memory device of claim 1, wherein the first data signal is associated with a first or more memory cells in the memory cell, and the second data signal is associated with a second or more memory cells in the memory cell.

3. The memory device of claim 2, wherein the sensing amplifier circuit is configured to store data associated with a second or more memory cells in the memory cells within the buffer circuit.

4. The memory device of claim 2, wherein the first data signal is associated with a first read command, and the second data signal is associated with a second read command.

5. The memory device of claim 1, wherein the sensing amplifier circuit is configured to store the data associated with the third read command within the buffer circuit.

6. The memory device of claim 1, wherein the buffer circuitry includes row buffer circuitry, each row buffer circuitry being configured to store data associated with a data signal, and wherein the buffer circuitry is configured to output a data signal from one of the row buffer circuitry based on a read command.

7. The memory device of claim 1, wherein the sensing amplifier circuit is configured to refresh one or more memory cells in the memory cells, and the selection circuit is configured to output the second data signal from the buffer circuit during at least partially overlapping time periods.

8. The memory device of claim 1, wherein the buffer circuit is configured to store a number of bits less than the number of bits within a page of the memory device.

9. A method, the method comprising: Based on a first command, a first data signal is output from the sensing amplifier circuit of the memory device, wherein the first data signal corresponds to a first or more memory cells of the memory device; A second data signal is output from the buffer circuit of the memory device, wherein the second data signal corresponds to a second command, and wherein the second data signal corresponds to a second or more memory cells in the memory cells of the memory device; as well as The selection circuit of the memory device outputs a selected one of the first data signal and the second data signal.

10. The method according to claim 9, further comprising: Receive a third command, wherein the target of the third command is a third or more memory cells in the memory cells of the memory device; A third data signal associated with the third or more memory cells in the memory cell is output from the sensing amplifier circuit; The third data signal is stored in the buffer circuit; as well as The third data signal is output from the selection circuit.

11. A computing system, the computing system comprising: A memory controller configured to output a first command and a second command; and The memory device includes: A sensing amplifier circuit configured to output a first data signal based on the first command and a second data signal associated with the second command; A buffer circuit, configured to store the second data signal based on receiving the second command; and A selection circuit is configured to receive a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit, and to output a selected one of the first data signal and the second data signal.

12. The computing system of claim 11, wherein the sensing amplifier circuit is configured to store data of one or more memory cells of the memory device within the buffer circuit.

13. The computing system of claim 11, wherein the sensing amplifier circuit is configured to store data associated with a third or more memory cells in the memory cells of the memory device and based on a third command within the buffer circuit.

14. The computing system of claim 11, wherein the sensing amplifier circuit is configured to refresh one or more memory cells of the memory device, and the selection circuit is configured to output the second data signal from the buffer circuit during at least partially overlapping time periods.

15. The computing system of claim 11, wherein the buffer circuit is configured to store a number of bits less than the number of bits within a page of the memory device.

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