Semiconductor equipment

Abstract

To provide a semiconductor device that is robust to changes of a process, a supply voltage, and a temperature.SOLUTION: A semiconductor device 100A comprises: power supply terminals 3, 4; a hall element 10 having first to fourth terminals 11-14; current sources 20, 21; a reference voltage source 50; a transistor 30N including a drain connected to a second terminal 212, a gate connected to a second terminal 12, and a source; a transistor 31N including a drain connected to the second terminal 212, a gate connected to the fourth terminal 14, and a source; a reference voltage source 50; an operational amplifier 60 including an inverted input terminal to which the reference voltage source 50 is connected, a non-inverted input terminal to which a voltage based on the voltage at a connection point of the source of the transistor 30N and the source of the transistor 31N is inputted, and an output terminal 61; and a third transistor including a drain connected to the third terminal 13, a gate connected to the output terminal 61, and a source connected to the power supply terminal 4.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In a driving circuit of a Hall element, a Hall element in-phase feedback circuit has been proposed that applies a bias to the in-phase voltage output from the Hall element and feeds it back (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When using the Hall element in-phase feedback circuit as described above, the in-phase voltage output from the Hall element is fixed to a predetermined reference voltage value. On the other hand, the threshold voltage of the transistor to which the in-phase voltage output from the Hall element is input is affected by fluctuations in the process, power supply voltage, and temperature (PVT fluctuations; Process, Voltage, Temperature). In the Hall element in-phase feedback circuit as described above, even when affected by PVT fluctuations, the in-phase voltage output from the Hall element cannot be adjusted to a fixed value. Therefore, when the in-phase input range of the subsequent-stage amplifier to which the in-phase voltage output from the Hall element is input is narrow, it may deviate from the in-phase input range due to the influence of PVT fluctuations. When the in-phase voltage of the subsequent-stage amplifier to be input deviates from the in-phase input range, the amplification operation cannot be performed normally, and the detection sensitivity of the magnetic sensor circuit decreases.

[0005] When using the Hall element common-mode feedback circuit described above, feedback is applied by comparing the common-mode voltage with a predetermined reference voltage. Therefore, according to the conventional technology, the value of the common-mode voltage remains constant even when the temperature changes. On the other hand, the threshold voltage of the input transistor to which the common-mode voltage is input is affected by temperature. Therefore, according to the conventional technology, even if the threshold voltage of the input transistor changes due to temperature changes, the common-mode voltage does not change, so the margin becomes small depending on the temperature. Specifically, as the temperature decreases, the threshold voltage increases, so the lower limit of the common-mode voltage also increases, and the lower limit margin becomes small. This is especially noticeable when the threshold voltage is in the process corner (Hi corner) than when it is the Typ value.

[0006] This invention has been made in view of these circumstances and aims to provide a semiconductor device that is robust against fluctuations in process, power supply voltage, and temperature. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention is a semiconductor device including a semiconductor substrate, comprising: a first power terminal to which a first power voltage is supplied; a second power terminal to which a second power voltage is supplied; a Hall element formed on the semiconductor substrate having first to fourth terminals; a first current source including a first end connected to the first power terminal and a second end connected to the first terminal of the Hall element; a second current source including a first end connected to the first power terminal and a second end; a drain connected to the second end of the second current source; a gate connected to the second terminal of the Hall element and a source; and the second end of the second current source and The device comprises: a second transistor having a drain connected to the drain of the first transistor, a gate connected to the fourth terminal of the Hall element, and a source connected to the source of the first transistor; an operational amplifier having a reference voltage source, an inverting input terminal to which the reference voltage source is connected, a non-inverting input terminal to which a voltage based on the voltage at the connection point between the source of the first transistor and the source of the second transistor is input, and an output terminal; and a third transistor having a drain connected to the third terminal of the Hall element, a gate connected to the output terminal of the operational amplifier, and a source connected to the second power supply terminal. [Effects of the Invention]

[0008] According to the present invention, a semiconductor device that is robust against fluctuations in process, power supply voltage, and temperature can be provided. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example of the configuration of a semiconductor device according to the embodiment. [Figure 2] This figure shows a first modified example of the configuration of a semiconductor device according to the embodiment. [Figure 3] This diagram illustrates the common-mode input range of an amplifier provided in a semiconductor device according to an embodiment. [Figure 4]This figure illustrates the upper limit margin MGNP and lower limit margin MGNN of the common-mode voltage range of a semiconductor device according to an embodiment. [Figure 5] This figure illustrates the change in the margin of the common-mode voltage range for each temperature in the semiconductor device according to the embodiment (when the threshold voltage VTH of the level shifter and amplifier input transistor is the Typ value). [Figure 6] This figure illustrates the change in the margin of the common-mode voltage range for each temperature in the semiconductor device according to the embodiment (when the threshold voltage VTH of the level shifter and amplifier input transistor is at the process corner). [Figure 7] This figure illustrates a method for adjusting the bleeder voltage division ratio in a semiconductor device according to an embodiment. [Figure 8] This figure shows the configuration of a second modified example of the semiconductor device according to the embodiment. [Figure 9] This diagram shows the configuration of a third modified example of the semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0010] A preferred embodiment of the semiconductor device according to the present invention will be described in detail below with reference to the attached drawings.

[0011] [Circuit configuration of semiconductor device] Figure 1 is a diagram showing an example of the configuration of a semiconductor device according to an embodiment. An example of the configuration of the semiconductor device 100A will be described with reference to the same figure. The semiconductor device 100A includes a semiconductor substrate 2. A magnetic sensor circuit 1A is formed on the semiconductor substrate 2 by a semiconductor manufacturing process. The magnetic sensor circuit 1A comprises a Hall element 10, a level shifter 110, an amplification circuit 130, a transistor 32N, a current source 20, a current source 21, and a differential amplifier 70A.

[0012] The semiconductor device 100A includes a power terminal 3 as a first power terminal, a power terminal 4 as a second power terminal, and an output terminal To. A first power supply voltage is supplied to power terminal 3. In Figure 1, the first power supply voltage is shown as voltage VDD. A second power supply voltage is supplied to power terminal 4. In Figure 1, the second power supply voltage is shown as voltage VSS. The output terminal To is connected to the output terminal of the differential amplifier 70A. The connection point between output terminal To and the output terminal of the differential amplifier 70A corresponds to the output terminal of the magnetic sensor circuit 1A.

[0013] The Hall element 10 includes a detection unit for detecting linked magnetic fields and is formed on the semiconductor substrate 2. The Hall element 10 is a so-called horizontal Hall element (lateral Hall element) that includes a detection unit for detecting a magnetic field linked along a direction perpendicular to the surface of the semiconductor substrate 2. A horizontal Hall element can detect a magnetic field perpendicular to the surface of the semiconductor substrate 2. The Hall element 10 exemplified in Figure 1, etc., is a horizontal Hall element, but is not limited to a horizontal Hall element. It may also be a so-called vertical Hall element (vertical Hall element) that includes a detection unit for detecting a magnetic field linked along a direction parallel to the surface of the semiconductor substrate 2. In other words, the Hall element 10 is either a horizontal Hall element or a vertical Hall element.

[0014] The Hall element 10 outputs differential output signals corresponding to the detected magnetic field strength as output voltage 101 and output voltage 102. When the nearby magnetic field is weak, the Hall element 10 outputs in-phase voltages to output voltages 101 and 102, and when the nearby magnetic field is strong, it outputs out-of-phase voltages to output voltages 101 and 102. In the following description, the in-phase voltage output by the Hall element 10 will be referred to as the output common-mode voltage VCM.

[0015] The voltage signal output from the Hall element 10 is a weak voltage signal of several tens of μV to several mV. Therefore, it is difficult to ensure the signal-to-noise power (S / N) ratio of the magnetic sensor circuit. In addition, the voltage signal output from the Hall element 10 increases or decreases depending on the temperature change. Further, when the Hall element 10 is driven by a constant current source, the output common-mode voltage (common-mode output voltage) of the voltage signal output from the Hall element changes depending on the temperature change. This is because the signal output from the Hall element is a voltage signal, and the output common-mode voltage of this voltage signal changes greatly depending on the temperature change. The semiconductor device 100A is configured as described below to reduce the influence of these fluctuations.

[0016] The Hall element 10 has a terminal 11 as a first terminal, a terminal 12 as a second terminal, a terminal 13 as a third terminal, and a terminal 14 as a fourth terminal. The terminal 12 outputs an output voltage 101, and the terminal 14 outputs an output voltage 102, thereby outputting a differential output signal. The terminal 12 and the terminal 14 are respectively connected to the input terminals of the differential amplifier 70A. The terminal 11 is connected to the current source 20, and the terminal 13 is connected to the drain of the transistor 32N.

[0017] The current source 20 as a first current source has a first end 201 and a second end 202. The first end 201 of the current source 20 is connected to the power supply terminal 3. The second end 202 of the current source 20 is connected to the terminal 11 of the Hall element 10. The current source 21 as a second current source has a first end 211 and a second end 212. The first end 211 of the current source 21 is connected to the power supply terminal 3. The second end 212 of the current source 21 is connected to the level shifter 110, more specifically, to the drains of the transistor 30N and the transistor 31N described later.

[0018] The level shifter 110 has a transistor 30N as the first transistor and a transistor 31N as the second transistor. Both the transistor 30N and the transistor 31N are N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The drain of the transistor 30N is connected to the second terminal 212 of the current source 21 and the drain of the transistor 31N. The gate of the transistor 30N is connected to the terminal 12 of the Hall element 10. The source of the transistor 30N is connected to the non-inverting input terminal of the operational amplifier 60 and the source of the transistor 31N. The drain of the transistor 31N is connected to the second terminal 212 of the current source 21 and the drain of the transistor 30N. The gate of the transistor 31N is connected to the terminal 14 of the Hall element 10. The source of the transistor 31N is connected to the non-inverting input terminal of the operational amplifier 60 and the source of the transistor 30N.

[0019] The transistor 30N and the transistor 31N share a common source. The connection point of the source of the transistor 30N and the source of the transistor 31N is also referred to as a common source 104. A level shift voltage (hereinafter referred to as "voltage VS"), which is a voltage (=VCM - VTH) that is the difference between the output common-mode voltage VCM of the Hall element 10 and the threshold voltage VTH of the transistors 30N and 31N, is output to the common source 104. That is, the transistors 30N and 31N function as a level shifter 110 that shifts the output voltage of the Hall element 10 by the threshold voltage VTH.

[0020] The amplification circuit 130 comprises a reference voltage source 50 and an operational amplifier 60. The reference voltage source 50 is a DC voltage source capable of outputting a predetermined reference voltage VREF. The positive terminal of the reference voltage source 50 is connected to the inverting input terminal of the operational amplifier 60, and the negative terminal is connected to the power supply terminal 4. The operational amplifier 60 comprises an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal 61. The positive terminal of the reference voltage source 50 is connected to the inverting input terminal of the operational amplifier 60. A voltage based on the voltage of the common source 104, which is the connection point between the source of transistor 30N and the source of transistor 31N, is input to the non-inverting input terminal of the operational amplifier 60. In the example shown in Figure 1, the sources of transistor 30N and transistor 31N are directly connected to the non-inverting input terminal of the operational amplifier 60. The output terminal 61 of the operational amplifier 60 is connected to the gate of transistor 32N.

[0021] The third transistor, transistor 32N, is an N-channel MOSFET. The drain of transistor 32N is connected to terminal 13 of the Hall element 10. The gate of transistor 32N is connected to output terminal 61 of the operational amplifier 60. The source of transistor 32N is connected to power supply terminal 4.

[0022] The differential amplifier 70A comprises an input transistor 71N as a first input transistor and an input transistor 72N as a second input transistor. Both input transistors 71N and 72N are N-channel type MOSFETs. The gate of input transistor 71N is connected to the connection point between the gate of transistor 31N and terminal 12 of the Hall element 10. The gate of input transistor 72N is connected to the connection point between the gate of transistor 32N and terminal 14 of the Hall element 10.

[0023] [Operation of the magnetic sensor circuit] Next, we will explain the operation of the magnetic sensor circuit 1A. The Hall element 10 is driven by a constant current from the current source 20. The current source 21, transistor 30N, and transistor 31N form a source follower circuit. The source follower circuit functions as a level shifter that outputs a voltage VS. The voltage VS is the difference between the common-mode output voltage VCM of the Hall element 10 and the threshold voltage VTH of transistors 30N and 31N. Specifically, the voltage VS is expressed by the following equation (1).

[0024] VS = VCM - VTH …(1)

[0025] A voltage VS is input to the non-inverting input terminal of the operational amplifier 60, and a reference voltage VREF is input to the inverting input terminal. The operational amplifier 60 applies negative feedback so that the voltage VS and the reference voltage VREF are equal. In other words, in the magnetic sensor circuit 1A, the voltage VS is used as the feedback voltage VFB. As a result of the negative feedback applied by the operational amplifier 60, the output common-mode voltage VCM is maintained at the voltage expressed by the following equation (2). In other words, the magnetic sensor circuit 1A operates to maintain the output common-mode voltage VCM of the Hall element 10 at a predetermined voltage.

[0026] VCM = VREF + VTH …(2)

[0027] Furthermore, in order to link the output common-mode voltage VCM with the input common-mode range ICMR of the differential amplifier 70A, it is preferable that the input transistors 71N, 72N, 30N, and 31N are of the same type or have equivalent electrical characteristics. Moreover, in order for these transistors to have equivalent electrical characteristics, it is preferable that they share a common manufacturing process. Here, the electrical characteristics of a transistor include the threshold voltage. That is, the input transistors 71N, 72N, 30N, and 31N each have the same threshold voltage.

[0028] Furthermore, it is preferable that the input transistors 71N, 72N, 30N, and 31N each have equal current densities and equal overdrive voltages. That is, the current densities of transistors 30N and 31N drain - The current density of the current flowing between the sources and input transistors 71N and 72N drain - It is preferable that the current density of the current flowing between the sources be equal to the current density of the current flowing between the sources. Furthermore, in order to equalize the overdrive voltage, it is preferable to design the circuit so that the current density per w / l (channel size ratio) is equal.

[0029] [First variation] Figure 2 shows a first modified example of the configuration of a semiconductor device according to the embodiment. An example of the configuration of semiconductor device 100B will be described with reference to this figure. Semiconductor device 100B differs from semiconductor device 100A in that a magnetic sensor circuit 1B is formed on the semiconductor substrate 2 instead of the magnetic sensor circuit 1A. The magnetic sensor circuit 1B also differs from the magnetic sensor circuit 1A in that it further includes a voltage divider circuit 120. In the description of semiconductor device 100B, components similar to those of semiconductor device 100A may be denoted by the same reference numerals and their description may be omitted.

[0030] The voltage divider circuit 120 comprises a resistor 40 as a first resistor and a resistor 41 as a second resistor. Resistor 40 has a first terminal 401 and a second terminal 402. The first terminal 401 of resistor 40 is connected to a common source 104. The second terminal 402 of resistor 40 is connected to the first terminal 411 of resistor 41 and the positive input terminal of the operational amplifier 60. Resistor 41 has a first terminal 411 and a second terminal 412. The first terminal 411 of resistor 41 is connected to the second terminal 402 of resistor 40. The second terminal 412 of resistor 41 is connected to the power supply terminal 4. The voltage divider circuit 120 is a bleeder resistor circuit that flows a bleeder current between the common source 104 and the power supply terminal 4.

[0031] The source of transistor 30N is connected to the first terminal 401 of resistor 40 and the source of transistor 31N. The source of transistor 31N is connected to the first terminal 401 of resistor 40 and the source of transistor 30N. The non-inverting input terminal of operational amplifier 60 is connected to the connection point between the second terminal 402 of resistor 40 and the first terminal 411 of resistor 41, i.e., node N1.

[0032] The non-inverting input terminal of the operational amplifier 60 receives a voltage based on the voltage VS, which is the voltage obtained by dividing the voltage VS by resistors 40 and 41, i.e., the voltage at node N1. The inverting input terminal of the operational amplifier 60 receives a reference voltage VREF. The operational amplifier 60 applies negative feedback so that the voltage at node N1 and the reference voltage VREF are equal. In the magnetic sensor circuit 1B, the voltage at node N1 is used as the feedback voltage VFB. As a result of the negative feedback applied by the operational amplifier 60, the output common-mode voltage VCM is maintained at the voltage expressed by the following equation (3). That is, the magnetic sensor circuit 1B operates to maintain the output common-mode voltage VCM of the Hall element 10 at a predetermined voltage. The bleeder voltage division ratio α is the ratio of the voltage at node N1 to the voltage VS, where 0 < α ≤ 1.

[0033] VCM = VREF / α + VTH …(3)

[0034] Here, the reference voltage VREF, which is the output voltage of the reference voltage source 50, may vary. This variation in the reference voltage VREF can be adjusted by changing the bleeder voltage division ratio α. In the example shown in Figure 2, the resistance value of resistor 40 is variable, and the bleeder voltage division ratio α can be changed by changing the resistance value of resistor 40. Note that resistor 41 may be a variable resistor, or resistors 40 and 41 may be variable resistors. In other words, if at least one of resistors 40 or 41 is a variable resistor, the bleeder voltage division ratio α can be adjusted within the range of 0 < α ≤ 1.

[0035] The resistance value of resistor 40 is variable and may be determined based on the subsequent circuit. In the example shown in Figures 1 and 2, the subsequent circuit is the input transistor 71N and input transistor 72N of the differential amplifier 70A. The timing for determining the resistance value of resistor 40 may be, for example, before factory shipment. Specifically, the resistance value of resistor 40 may be varied by performing a predetermined measurement before packaging the semiconductor device 100B and performing a trimming process based on the measured results. Alternatively, a switch SW (not shown) may be provided in parallel with resistors 40 and 41 to switch the bleeder voltage division ratio α of the voltage division circuit 120. The bleeder voltage division ratio α may be switched adaptively, for example, depending on the temperature.

[0036] [Common-mode input range of the amplifier] Figure 3 is a diagram illustrating the common-mode input range of the amplifier provided in the semiconductor device according to this embodiment. First, an example of the circuit configuration of the differential amplifier 70A will be described with reference to this figure. The differential amplifier 70A comprises an input transistor 71N, an input transistor 72N, a load transistor 73P, a load transistor 74P, and a tail current source 75.

[0037] The gates of input transistors 71N and 72N are connected to the common-mode output voltage VCM. Specifically, the gate of input transistor 71N is connected to terminal 12 of the Hall element 10, and the gate of input transistor 72N is connected to terminal 14. The sources of input transistors 71N and 72N are connected to each other. The drain of input transistor 71N is connected to the drain and gate of load transistor 73P. The drain of input transistor 72N is connected to the drain of load transistor 74P and the output terminal 76 of differential amplifier 70A. That is, the drain voltages of input transistor 72N and load transistor 74P are supplied to the output terminal 76 as the output voltage of differential amplifier 70A.

[0038] Load transistors 73P and 74P are both P-channel MOSFETs. The source of load transistor 73P and the source of load transistor 74P are connected to each other, and this connection point is connected to power supply terminal 3. The gate of load transistor 73P and the gate of load transistor 74P are connected to each other, and this connection point is connected to the connection point between the drain of load transistor 73P and the drain of input transistor 71N. The drain of load transistor 73P is connected to the drain of input transistor 71N and the gate of load transistor 73P. The drain of load transistor 74P is connected to the drain of input transistor 72N and the output terminal 76 of differential amplifier 70A.

[0039] The tail current source 75 has one end connected to the connection point between the sources of input transistor 71N and input transistor 72N, and the other end connected to the power supply terminal 4. The potential at the connection point between the sources of input transistor 71N and input transistor 72N is denoted as voltage VTAIL. The minimum potential difference across the ends required for the tail current source 75 to operate in the saturation region is voltage VDSAT.

[0040] Next, we will explain the common-mode input range of the differential amplifier 70A. In an amplifier composed of a typical N-channel input differential pair, the conditions for saturation region operation without gain reduction are shown in equations (4) to (7) below.

[0041] VDSAT=VCM-VTAIL-VTHN<VGP-VTAIL …(4) VTAIL> VDSAT …(5) VDD-VGP-|VTHP| <VDD-VGP …(6) VTAIL=VCM-VTHN-VDSAT …(7)

[0042] Here, equation (4) represents the saturation condition for the input transistor 71N. Equation (5) represents the saturation condition for the tail current source 75. Equation (6) represents the saturation condition for the load transistor 73P. Since the absolute threshold voltage |VTHP| of the load transistor 73P is positive (|VTHP|>0), it is clear that equation (6) is satisfied.

[0043] Substituting the voltage VTAIL from equation (7) into equation (5), we obtain the following equation (8). Furthermore, by rearranging equation (8), we obtain the following equation (9).

[0044] VCM-VTHN-VDSAT>VDSAT …(8) VCM>VTHN+2VDSAT …(9)

[0045] In other words, the common-mode voltage limit ICMRN can be defined as shown in equation (10) below.

[0046] ICMRN = VTHN + 2VDSAT …(10)

[0047] Furthermore, equation (4) can be transformed to obtain equation (11), and equation (12) can be obtained from equations (11) and (6). In addition, the voltage dVT, which is the difference between the threshold voltage VTHN of an N-channel transistor and the absolute value of the threshold voltage |VTHP| of a P-channel transistor, is expressed by the following equation (13).

[0048] VCM <VGP-VTAIL+VTAIL+VTHN …(11) VCM <VDD-|VTHP|-VDSAT+VTHN …(12) dVT = VTHN - |VTHP| …(13)

[0049] Therefore, from equations (12) and (13), the common-mode voltage limit ICMRP can be defined as shown in equation (14) below.

[0050] ICMRP=VDD-|VTHP|-VDSAT+VTHN=VDD-VDSAT+dVT …(14)

[0051] Comparing the common-mode voltage lower limit ICMRN and common-mode voltage upper limit ICMRP calculated above, it can be seen that the common-mode voltage lower limit ICMRN is a function of voltage VTHN, regardless of the voltage VDD at power terminal 3. On the other hand, it can be seen that the common-mode voltage upper limit ICMRP is a function of voltage VDD and voltage dVT at power terminal 3. In other words, the degree of narrowing from the power line is more pronounced for the common-mode voltage lower limit ICMRN. To put it another way, there is less margin on the lower limit side than on the upper limit side. However, according to the present invention, by linking the output common-mode voltage VCM with the common-mode voltage lower limit ICMRN, it is possible to secure a lower limit margin MGNN against variations in the threshold voltage VTH.

[0052] [Common-mode voltage range margin] Next, we will explain the margin of the common-mode voltage range with reference to Figures 4 to 6. Since the case of semiconductor device 100A corresponds to the case where the bleeder voltage division ratio α=1, we will explain using the case of semiconductor device 100B, which includes the case where the bleeder voltage division ratio α=1, as an example.

[0053] Figure 4 is a diagram illustrating the upper limit margin MGNP and lower limit margin MGNN of the common-mode voltage range of the semiconductor device according to the embodiment. First, the margin of the common-mode voltage input to the differential amplifier 70A will be explained with reference to this figure. The horizontal axis of the figure represents the power supply voltage of the differential amplifier 70A, and the vertical axis represents the common-mode voltage. The power supply voltage of the differential amplifier 70A is the voltage VDD supplied to the power supply terminal 3. The figure shows the common-mode voltage range in which saturation region operation is possible.

[0054] The common-mode voltage range in which saturation region operation is defined as the voltage range of output voltages 101 and 102 in which input transistors 71N and 72N can operate in the saturation region. The output common-mode voltage VCM, which is the average voltage of output voltages 101 and 102, and the common-mode voltage upper limit ICMRP are determined by equations (3) and (14) described above, respectively.

[0055] The common-mode voltage limit ICMRP increases in conjunction with the power supply voltage of the differential amplifier 70A, as shown by the dashed line in Figure 4. Since the output common-mode voltage VCM is constant in the voltage range above the minimum operating voltage VDDmin and does not depend on the power supply voltage of the differential amplifier 70A, the upper limit margin MGNP increases as the power supply voltage of the differential amplifier 70A increases.

[0056] On the other hand, the common-mode voltage limit ICMRN is determined by equation (10) described above. As shown by the dashed line in the figure, the common-mode voltage limit ICMRN does not depend on the power supply voltage of the differential amplifier 70A, so even if the power supply voltage of the differential amplifier 70A increases, the lower limit margin MGNN remains constant.

[0057] Next, the change in the margin of the common-mode voltage range for each temperature will be explained with reference to Figures 5 and 6. Figure 5 shows an example when the threshold voltage VTH of transistors 30N, 31N, input transistor 71N, and input transistor 72N is the typical value. In the explanation of this figure, the horizontal axis represents temperature and the vertical axis represents common-mode voltage.

[0058] In the magnetic sensor circuit 1A, the output voltage VS obtained by level-shifting (stepping down) the output voltage of the Hall element 10 by the threshold voltage VTH of transistors 30N and 31N is compared with the reference voltage VREF. That is, the output common-mode voltage VCM is expressed by equation (3) above, and as the temperature Ta decreases, the threshold voltage VTH increases, so as the temperature Ta decreases, the output common-mode voltage VCM also increases. On the other hand, the common-mode voltage lower limit ICMRN is determined by equation (10) above, so as the temperature Ta decreases, the common-mode voltage lower limit ICMRN also increases. Thus, with the magnetic sensor circuit 1A, even if the common-mode voltage lower limit ICMRN changes in response to temperature changes, the lower limit margin MGNN does not decrease.

[0059] Figure 6 shows an example where the threshold voltage VTH of transistors 30N, 31N, input transistors 71N, and 72N is at the process corner (Hi corner). In the explanation of this figure, the horizontal axis represents temperature and the vertical axis represents common-mode voltage. When the threshold voltage VTH of transistors 30N, 31N, input transistors 71N, and 72N is at the process corner, the upper limit margin MGNP is smaller compared to the case of the Typ value (see Figure 5). The upper limit of the common-mode voltage ICMRP is determined by equation (14) described above and is therefore greater than the voltage VDD at power supply terminal 3. Therefore, even if the upper limit margin MGNP decreases as the temperature Ta decreases, the output common-mode voltage VCM will not exceed the upper limit of the common-mode voltage ICMRP.

[0060] Furthermore, the lower limit margin MGNN is larger compared to the Typ value. In the case of process corners, as with the Typ value, even if the common-mode voltage lower limit ICMRN increases, the output common-mode voltage VCM also increases in conjunction with the common-mode voltage lower limit ICMRN, thus maintaining the lower limit margin MGNN. Therefore, according to this embodiment, it is not necessary to set a high design value for the reference voltage VREF, and thus the upper limit margin MGNP can be maintained. Also, even if the common-mode voltage lower limit ICMRN increases, the output common-mode voltage VCM also increases in conjunction with the common-mode voltage lower limit ICMRN, thus maintaining the lower limit margin MGNN.

[0061] [Methods for adjusting semiconductor devices] Figure 7 is a diagram illustrating a method for adjusting the bleeder voltage division ratio in a semiconductor device according to an embodiment. The method for adjusting the bleeder voltage division ratio α will be explained with reference to this figure. In this figure, the horizontal axis represents the reference voltage VREF, which is the output voltage of the reference voltage source 50, and the vertical axis represents the output common-mode voltage VCM.

[0062] In conventional technology, the reference voltage VREF and the output common-mode voltage VCM were proportional, so the relationship between the reference voltage VREF and the output common-mode voltage VCM was a straight line L1. That is, as the reference voltage VREF increased, the output common-mode voltage VCM also increased. In this case, if the reference voltage VREF fluctuated due to PVT fluctuations, etc., it may exceed the range from the upper limit of the common-mode voltage ICMRP to the lower limit of the common-mode voltage ICMRN. Specifically, if the reference voltage VREF is smaller than the intersection of the reference voltage VREF shown by the straight line L1 and the lower limit of the common-mode voltage ICMRN shown by the dashed line, the lower limit margin MGNN becomes a negative value, which may cause a malfunction.

[0063] On the other hand, according to this embodiment, the value of the output common-mode voltage VCM can be adjusted by adjusting the bleeder voltage division ratio α. Specifically, the bleeder voltage division ratio α is adjusted so that VREF / α is a constant value. If VREF / α is a constant value, the output common-mode voltage VCM is as shown in equation (3), and therefore the output common-mode voltage VCM is also a constant value. Note that the threshold voltage VTH does not need to be adjusted because it is linked to the common-mode voltage lower limit ICMRN.

[0064] According to this embodiment, even if the reference voltage VREF, which is the output value of the reference voltage source 50, fluctuates due to PVT fluctuations or the like, the output common-mode voltage VCM can be adjusted by adjusting the bleeder voltage division ratio α, thereby maintaining the upper limit margin MGNP and the lower limit margin MGNN at or above a certain value.

[0065] By substituting equation (13) into equation (14), we can obtain the following equation (18).

[0066] ICMRP=VDD-|VTHP|-VDSAT+VTHN …(18)

[0067] Therefore, the upper limit margin MGNP is expressed by the following equation (19). On the other hand, the lower limit margin MGNN is expressed by the following equation (20).

[0068] MGNP=(ICMRP)-VCM=VDD-|VTHP|-VDSAT-VREF / α …(19) MGNN=VCM-(ICMRN)=VREF / α-2VDSAT…(20)

[0069] Since both equation (19) representing the upper limit margin MGNP and equation (20) representing the lower limit margin MGNN include the term "VREF / α", it is possible to adjust the upper limit margin MGNP and the lower limit margin MGNN by adjusting the bleeder voltage division ratio α. Therefore, by adjusting the bleeder voltage division ratio α according to the variation in the reference voltage VREF, it is possible to balance the upper limit margin MGNP and the lower limit margin MGNN.

[0070] [Summary of Embodiments] According to the embodiment described above, the semiconductor device 100A is equipped with transistors 30N and 31N to level-shift the output common-mode voltage VCM of the Hall element 10 by a threshold voltage VTH. Furthermore, the semiconductor device 100A is equipped with a reference voltage source 50, an operational amplifier 60, and a transistor 32N to compare a predetermined reference voltage VREF with the level-shifted voltage VS and apply negative feedback. According to this embodiment, since the output common-mode voltage VCM is level-shifted by a source follower circuit, the output common-mode voltage VCM depends on the threshold voltage VTH. Since the threshold voltage VTH is easily affected by PVT fluctuations, the output common-mode voltage VCM is also affected by PVT fluctuations. Therefore, even if the common-mode input range of the differential amplifier 70A connected to the subsequent stage (terminals 12 and 14 of the Hall element 10) is affected by PVT fluctuations, the output common-mode voltage VCM is similarly affected by PVT fluctuations. Therefore, according to this embodiment, the semiconductor device 100A can perform amplification operations normally regardless of PVT fluctuations. In other words, a semiconductor device 100A that is robust to PVT fluctuations can be provided. Furthermore, according to this embodiment, since the level shifter 110 is configured using a source follower circuit, the common-mode voltage VCM of the Hall element's 10 output can be linked to the common-mode input range of the next-stage differential amplifier 70A with a relatively simple configuration. Therefore, the common-mode input range specifications of the differential amplifier 70A can be relaxed without complicating the circuit configuration.

[0071] Furthermore, according to the embodiment described above, the semiconductor device 100A further comprises a differential amplifier 70A, and the differential amplifier 70A comprises input transistors 71N and 72N. Therefore, even if input transistors 71N and 72N are affected by PVT fluctuations, transistors 30N and 31N are similarly affected by PVT fluctuations, and thus the output common-mode voltage VCM is also similarly affected by PVT fluctuations. Accordingly, according to this embodiment, the semiconductor device 100A can perform amplification operations normally regardless of PVT fluctuations.

[0072] Furthermore, according to the embodiment described above, transistors 30N, 31N, input transistor 71N, and input transistor 72N all have the same threshold voltage VTH. Therefore, if the common-mode input range of input transistors 71N and 72N shifts due to the influence of PVT fluctuations, the output common-mode voltage VCM of the Hall element 10 also shifts due to the influence of PVT fluctuations, as it is also a function of the threshold voltage VTH. Thus, according to this embodiment, the semiconductor device 100A can perform amplification operations normally regardless of PVT fluctuations.

[0073] Furthermore, according to the above-described embodiment, transistor 30N, transistor 31N, input transistor 71N and input transistor 72N are drain -The current density of the current flowing between the sources is designed to be equal. That is, transistors 30N and 31N and input transistors 71N and 72N are, drain-The current density of the current flowing between the sources is made equal, so that the overdrive voltage is also equal. Therefore, if the common-mode input range of input transistors 71N and 72N is shifted due to the influence of PVT fluctuations, the output common-mode voltage VCM of the Hall element 10 is also shifted due to the influence of PVT fluctuations. According to this embodiment, the semiconductor device 100A can perform amplification operations normally regardless of PVT fluctuations.

[0074] Furthermore, according to the above-described embodiment, the semiconductor device 100B further includes a voltage divider circuit 120, which inputs a feedback voltage VFB, obtained by dividing the voltage VS by a bleeder voltage divider ratio α, to the non-inverting input terminal of the operational amplifier 60. With the semiconductor device equipped with the voltage divider circuit 120, the bleeder voltage divider ratio α can be adjusted, so even if affected by PVT fluctuations, the value of the output common-mode voltage VCM can be adjusted to match the common-mode input range of the differential amplifier 70A by adjusting the bleeder voltage divider ratio α. In other words, a semiconductor device 100B that is robust against PVT fluctuations can be provided.

[0075] Furthermore, according to the embodiment described above, at least one of the resistors 40 and 41 constituting the voltage divider circuit 120 is a variable resistor whose resistance value can be adjusted. Therefore, according to this embodiment, if necessary due to predetermined measurements performed before packaging the semiconductor device 100B, the bleeder voltage divider ratio α can be adjusted by changing the resistance value of the variable resistor by trimming or the like.

[0076] Furthermore, according to the embodiment described above, the Hall element 10 is either a horizontal Hall element that detects a magnetic field perpendicular to the surface of the semiconductor substrate 2, or a vertical Hall element that detects a magnetic field parallel to the surface of the semiconductor substrate 2. In other words, the Hall element 10 may be either a horizontal Hall element or a vertical Hall element. Therefore, according to this embodiment, the semiconductor device 100A can detect magnetic fields perpendicular to the surface of the semiconductor substrate 2, or magnetic fields parallel to the surface of the semiconductor substrate 2.

[0077] [Second variation] Figure 8 shows the configuration of a second modified example of the semiconductor device according to the embodiment. An example of the configuration of semiconductor device 100C will be described with reference to this figure. Semiconductor device 100C differs from semiconductor device 100B in that a magnetic sensor circuit 1C is formed on the semiconductor substrate 2 instead of the magnetic sensor circuit 1B. The magnetic sensor circuit 1C has a complementary relationship with the magnetic sensor circuit 1B. That is, while the magnetic sensor circuit 1B is configured using an N-channel type MOSFET, the magnetic sensor circuit 1C is configured using a P-channel type MOSFET. In the description of semiconductor device 100C, components similar to those of semiconductor device 100B may be denoted by the same reference numerals and their explanation may be omitted.

[0078] As a second modification, a semiconductor device 100C having a voltage divider circuit 120C will be used as an example for explanation. However, as with the case where an N-channel MOSFET is used, a configuration without a voltage divider circuit 120C may also be adopted.

[0079] Magnetic sensor circuit 1C differs from magnetic sensor circuit 1B in that it includes a level shifter 110C instead of a level shifter 110. Level shifter 110C includes transistors 30P and 31P. Both transistors 30P and 31P are P-channel type MOSFETs. The drain of transistor 30P is connected to the second terminal 212 of the current source 21 and the drain of transistor 31P. The gate of transistor 30P is connected to terminal 12 of the Hall element 10. The source of transistor 30P is connected to the resistor 40C and the source of transistor 31P. The drain of transistor 31P is connected to the second terminal 212 of the current source 21 and the drain of transistor 30P. The gate of transistor 31P is connected to terminal 14 of the Hall element 10. The source of transistor 31P is connected to the resistor 40C and the source of transistor 30P.

[0080] Furthermore, the magnetic sensor circuit 1C differs from the magnetic sensor circuit 1B in that it includes a voltage divider circuit 120C instead of the voltage divider circuit 120. The voltage divider circuit 120C includes a resistor 40C and a resistor 41C. The resistor 40C has a first terminal 401C and a second terminal 402C. The first terminal 401C of the resistor 40C is connected to the common source 104C. The second terminal 402C of the resistor 40C is connected to the first terminal 411C of the resistor 41C and to the positive input terminal of the operational amplifier 60. The resistor 41C has a first terminal 411C and a second terminal 412C. The first terminal 411C of the resistor 41C is connected to the second terminal 402C of the resistor 40C. The second terminal 412C of the resistor 41C is connected to the power supply terminal 3. The voltage divider circuit 120C is a bleeder resistor circuit that allows a bleeder current to flow between the common source 104C and the power supply terminal 3.

[0081] Furthermore, the magnetic sensor circuit 1C differs from the magnetic sensor circuit 1B in that it includes a reference voltage source 50C instead of the reference voltage source 50. The reference voltage source 50C is a DC voltage source capable of outputting a predetermined voltage. The positive terminal of the reference voltage source 50C is connected to the power supply terminal 3, and the negative terminal of the reference voltage source 50C is connected to the non-inverting input terminal of the operational amplifier 60.

[0082] Furthermore, magnetic sensor circuit 1C differs from magnetic sensor circuit 1B in that it includes transistor 32P instead of transistor 32N. Transistor 32P is a P-channel MOSFET. The drain of transistor 32P is connected to terminal 13 of the Hall element 10. The gate of transistor 32P is connected to output terminal 61 of the operational amplifier 60. The source of transistor 32P is connected to power supply terminal 3.

[0083] Furthermore, magnetic sensor circuit 1C differs from magnetic sensor circuit 1B in that it includes a differential amplifier 70C instead of differential amplifier 70A. Differential amplifier 70C includes input transistor 71P and input transistor 72P. Both input transistors 71P and 72P are P-channel type MOSFETs. The gate of input transistor 71P is connected to the connection point between the gate of transistor 31P and terminal 12 of Hall element 10. The gate of input transistor 72P is connected to the connection point between the gate of transistor 32P and terminal 14 of Hall element 10.

[0084] Detailed circuit diagrams for differential amplifier 70C will be omitted from this explanation. The configuration of differential amplifier 70C is complementary to the configuration of differential amplifier 70A, which was explained with reference to Figure 3.

[0085] [Third variation] Figure 9 is a diagram showing the configuration of a third modified example of the semiconductor device according to the embodiment. An example of the configuration of the semiconductor device according to the third modified example will be described with reference to this figure. The magnetic sensor circuit of the semiconductor device according to the third modified example differs in that it further includes a switch group 80 having a plurality of switchable switches SP1 to SP4, SN1 to SN4, and SS1 to SS4 between the current source 20 and the Hall element 10 and the differential amplifier 70A.

[0086] In the third modification, the open / closed states of multiple switches SP1-SP4, SN1-SN4, and SS1-SS4 can be switched sequentially and in a time-division manner, allowing for the extraction of a regular signal and offset pattern for signal processing. That is, in the third modification, the spinning current method can be applied, and the offset voltage of the Hall element 10 can be canceled. On the other hand, if the spinning current method is not applied, for example, as shown in Figure 9, by keeping switches SP1, SN1, SS2, and SS3 closed and the other switches SP2-SP4, SN2-SN4, SS1, and SS4 open, the semiconductor device 100C can be used substantially as the semiconductor device 100A.

[0087] In the third modified example, the spinning current method may be used for the semiconductor device 100C described in the second modified example.

[0088] Although preferred embodiments have been described above as examples of how to carry out the present invention, the present invention is not limited in any way to these embodiments, and various modifications and substitutions can be made without departing from the spirit of the invention. Furthermore, various other forms may be applied, such as by combining the configurations described in the above embodiments and examples. [Explanation of Symbols]

[0089] 100A, 100B, 100C… Semiconductor equipment 1A, 1B, 1C... Magnetic sensor circuits 2… Semiconductor substrates 3…Power terminal (first power terminal) 4…Power terminal (second power terminal) 10…Hall element Terminals 11, 12, 13, 14… (Terminals 1 through 4) 20, 21... Current sources (first current source, second current source) 30N, 31N, 32N, 30P, 31P, 32P... Transistors (first to third transistors) 40, 41, 40C, 41C... Resistors (first resistor, second resistor) 50, 50C... Reference voltage source 60... Operational amplifier 61…(Output terminal of operational amplifier) 70A, 70C... Differential amplifiers 71N, 72N, 71P, 72P... Input transistors

Claims

1. A semiconductor device including a semiconductor substrate, A first power supply terminal to which a first power supply voltage is supplied, A second power terminal to which a second power voltage is supplied, A Hall element having first to fourth terminals and formed on the semiconductor substrate, A first current source including a first terminal connected to the first power supply terminal and a second terminal connected to the first terminal of the Hall element, A second current source including a first terminal connected to the first power terminal and a second terminal, A first transistor including a drain connected to the second terminal of the second current source, a gate connected to the second terminal of the Hall element, and a source, A second transistor having a drain connected to the second terminal of the second current source and the drain of the first transistor, a gate connected to the fourth terminal of the Hall element, and a source connected to the source of the first transistor, Reference voltage source and An operational amplifier having an inverting input terminal to which the reference voltage source is connected, a non-inverting input terminal to which a voltage based on the voltage at the connection point between the source of the first transistor and the source of the second transistor is input, and an output terminal, A third transistor comprising a drain connected to the third terminal of the Hall element, a gate connected to the output terminal of the operational amplifier, and a source connected to the second power supply terminal, A semiconductor device equipped with a semiconductor device.

2. A first input transistor including a gate connected to the connection point between the gate of the first transistor and the second terminal of the Hall element, The differential amplifier further comprises a second input transistor including a gate connected to the connection point between the gate of the second transistor and the fourth terminal of the Hall element. The semiconductor device according to claim 1.

3. The first transistor, the second transistor, the first input transistor, and the second input transistor have the same threshold voltage. The semiconductor device according to claim 2.

4. The first transistor, the second transistor, the first input transistor, and the second input transistor are transistors designed so that the current density of the current flowing between the drain and source is equal. The semiconductor device according to claim 2 or claim 3.

5. A first resistor having a first terminal connected to the connection point between the source of the first transistor and the source of the second transistor, and a second terminal, The second resistor further comprises a first terminal connected to the second terminal of the first resistor and the non-inverting input terminal of the operational amplifier, and a second terminal connected to the second power supply terminal, The voltage based on the voltage at the connection point between the source of the first transistor and the source of the second transistor is the voltage obtained by dividing the voltage at the connection point between the source of the first transistor and the source of the second transistor by the first resistor and the second resistor. A semiconductor device according to any one of claims 1 to 4.

6. At least one of the first resistor and the second resistor is a variable resistor whose resistance value can be adjusted. The semiconductor device according to claim 5.

7. The Hall element is a horizontal Hall element that detects a magnetic field perpendicular to the surface of the semiconductor substrate, or a vertical Hall element that detects a magnetic field parallel to the surface of the semiconductor substrate. A semiconductor device according to any one of claims 1 to 6.

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