Method for manufacturing a display device and motherboard

Abstract

To provide a method of manufacturing a display device and a motherboard, which allow for suppressing reliability deterioration.SOLUTION: A method of manufacturing a display device according to an embodiment comprises forming a partition wall with a lower portion placed on a first surface side of a substrate and an upper portion projecting from a side face of the lower portion, and measuring the distance between the side face of the lower portion and an end of the upper portion from a side of a second surface of the substrate opposite the first surface.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a display device and a mother substrate.

Background Art

[0002] [[ID=1)]] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use.

[0003] By the way, the above-described display device is manufactured by preparing a mother substrate on which a plurality of display panels are formed on a mother substrate formed by integrating a plurality of base materials, and using each of the display panels cut from the mother substrate.

[0004] In the process of manufacturing such a display device, a technique for suppressing a decrease in the reliability of the display device is required.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0006] The object of the present invention is to provide a method for manufacturing a display device and a motherboard that can suppress a decrease in reliability. [Means for solving the problem]

[0007] The method for manufacturing the display device according to the embodiment involves forming a partition wall having a lower part positioned on the first surface side of the substrate and an upper part protruding from the side surface of the lower part. What to do and The distance between the lower side and the upper end is measured from the second surface side facing the first surface of the substrate. to possess . The substrate has a plurality of panel areas on which display panels are formed and a peripheral area that separates the plurality of panel areas. The partition wall is formed in both the plurality of panel areas and the peripheral area. The measurement is performed by photographing the partition wall formed in the peripheral area from the second side with a length measuring camera. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to an embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating a display element formed using a partition wall. [Figure 6] Figure 6 is a schematic cross-sectional view illustrating a display element formed using a partition wall. [Figure 7] Figure 7 is a schematic cross-sectional view illustrating a display element formed using a partition wall. [Figure 8] Figure 8 is a diagram illustrating the measurement of the protrusion amount of the partition wall. [Figure 9] Figure 9 is a diagram illustrating the measurement of the protrusion amount of the partition wall. [Figure 10] Figure 10 is a schematic diagram of the motherboard. [Figure 11] Figure 11 is a diagram illustrating the general outline of a method for manufacturing a display device. [Figure 12] FIG. 12 is a diagram showing an example of a pattern of partition walls formed in a peripheral region. [Figure 13] FIG. 13 is a schematic cross-sectional view of a peripheral region where partition walls are formed directly above a mother substrate. [Figure 14] FIG. 14 is a schematic cross-sectional view of a peripheral region where a first insulating layer and partition walls are sequentially formed on a mother substrate. [Figure 15] FIG. 15 is a schematic cross-sectional view of a peripheral region where a first insulating layer, ribs, and partition walls are sequentially formed on a mother substrate. [Figure 16] FIG. 16 is a schematic cross-sectional view of a peripheral region where a first insulating layer, a second insulating layer, and partition walls are sequentially formed on a mother substrate.

Embodiments for Carrying Out the Invention

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect for clearer explanation, but it is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each figure, components that exhibit the same or similar functions as those described above for the already presented figures may be assigned the same reference numerals, and detailed descriptions that are redundant may be omitted as appropriate.

[0010] Note that in the drawings, for ease of understanding as needed, the X-axis, Y-axis, and Z-axis perpendicular to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is called a plan view.

[0011] The display device in this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] Figure 1 shows an example of the configuration of a display device DSP in this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the base material 10 in plan view is rectangular. However, the shape of the base material 10 in plan view is not limited to a rectangle; it may be a square, circle, ellipse, or other shape.

[0014] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, along with sub-pixels SP1, SP2, and SP3. Furthermore, pixel PX may include sub-pixels SP of other colors in place of any of sub-pixels SP1, SP2, and SP3.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element 20.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown in Figure 1. The pixel circuit 1 may, for example, include more thin-film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element. For example, sub-pixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, sub-pixel SP2 is equipped with a display element 20 that emits light in the green wavelength range, and sub-pixel SP3 is equipped with a display element 20 that emits light in the blue wavelength range.

[0019] Figure 1 shows a display panel mainly used in the manufacture of a display device DSP. This display device DSP has a structure in which a circuit board equipped with a driver (driver IC chip) and the like that drives the display panel is connected to the display panel.

[0020] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example shown in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0021] When the subpixels SP1, SP2, and SP3 are arranged as shown in Figure 2, the display area DA forms columns in which subpixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0022] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example shown in Figure 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0023] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example shown in Figure 2, aperture AP2 is larger than aperture AP1, and aperture AP3 is larger than aperture AP2. Partition walls 6 are positioned at the boundary between adjacent sub-pixels SP and overlap with ribs 5 in a plan view.

[0024] The partition wall 6 has a plurality of first partition walls 6x extending in a first direction X and a plurality of second partition walls 6y extending in a second direction Y. The plurality of first partition walls 6x are arranged between adjacent openings AP1 and AP2 in the second direction Y, and between two adjacent openings AP3 in the second direction Y. The second partition walls 6y are arranged between adjacent openings AP1 and AP3 in the first direction X, and between adjacent openings AP2 and AP3 in the second direction.

[0025] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole is a grid that surrounds the openings AP1, AP2, and AP3. The partition wall 6 can also be said to have openings in the sub-pixels SP1, SP2, and SP3, similar to the rib 5.

[0026] In other words, in this embodiment, the rib 5 and the partition wall 6 are arranged to partition the sub-pixels SP1, SP2, and SP3.

[0027] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3. In the example shown in Figure 2, the outer shapes of upper electrode UE1 and organic layer OR1 are identical, the outer shapes of upper electrode UE2 and organic layer OR2 are identical, and the outer shapes of upper electrode UE3 and organic layer OR are identical.

[0028] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3.

[0029] The lower electrode LE1 is connected to the pixel circuit 1 that drives the sub-pixel SP1 (display element 20) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 that drives the sub-pixel SP2 (display element 20) through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 that drives the sub-pixel SP3 (display element 20) through the contact hole CH3.

[0030] In the example shown in Figure 2, contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent openings AP1 and AP2 in the second direction Y. Contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent openings AP3 in the second direction Y. In another example, at least a portion of contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0031] In the example shown in Figure 2, the lower electrodes LE1 and LE2 each have protrusions PR1 and PR2. Protrusion PR1 projects from the main body of the lower electrode LE1 (the part overlapping with the opening AP1) toward the contact hole CH1. Protrusion PR2 projects from the main body of the lower electrode LE2 (the part overlapping with the opening AP2) toward the contact hole CH2. Contact holes CH1 and CH2 overlap with protrusions PR1 and PR2, respectively.

[0032] Figure 3 is a schematic cross-sectional view of a display device DSP along the line III-III in Figure 2. In the display device DSP, an insulating layer 11 called an undercoat layer is placed on the first surface 10A (the surface on which the display elements 20 etc. are arranged) of the light-transmitting substrate 10, such as glass, as described above.

[0033] The insulating layer 11 has a three-layer laminated structure, for example, consisting of a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). However, the insulating layer 11 is not limited to a three-layer stacked structure; it may have a laminated structure of three or more layers, or it may have a single-layer structure or a two-layer laminated structure.

[0034] A circuit layer 12 is placed on top of the insulating layer 11. The circuit layer 12 has various circuits and wiring that drive the sub-pixels SP (SP1, SP2, and SP3), such as the pixel circuit 1 shown in Figure 1, scan line GL, signal line SL, and power line PL. The circuit layer 12 is covered by an insulating layer 13.

[0035] The insulating layer 13 functions as a planarizing film that flattens the irregularities caused by the circuit layer 12. Although not shown in Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the insulating layer 13.

[0036] The lower electrodes LE (LE1, LE2, and LE3) are positioned on the insulating layer 13. The ribs 5 are positioned on the insulating layer 13 and the lower electrodes LE. The ends (partially) of the lower electrodes LE are covered by the ribs 5.

[0037] The bulkhead 6 has a lower section 61 positioned on the rib 5 and an upper section 62 that covers the upper surface of the lower section 61. The upper section 62 is wider than the lower section 61. As a result, the bulkhead 6 has a shape in which both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the bulkhead 6 can also be described as overhanging.

[0038] The organic layers OR (OR1, OR2, and OR3) and upper electrodes UE (UE1, UE2, and UE3), together with the lower electrodes LE (LE1, LE2, and LE3) described above, constitute the display element 20. As shown in Figure 3, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b that are spaced apart from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b that are spaced apart from each other. The first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a part of the rib 5. The second organic layer OR1b is located above the upper part 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a is in contact with the side surface of the lower part 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0039] Furthermore, as shown in Figure 3, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b that are spaced apart from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b that are spaced apart from each other. The first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a portion of the rib 5. The second organic layer OR2b is located above the upper part 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. In addition, the first upper electrode UE2a contacts the side surface of the lower part 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0040] Furthermore, as shown in Figure 3, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b that are spaced apart from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b that are spaced apart from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a portion of the rib 5. The second organic layer OR3b is located above the upper part 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. In addition, the first upper electrode UE3a contacts the side surface of the lower part 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0041] In the example shown in Figure 3, the sub-pixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0042] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b that are spaced apart from each other. The first cap layer CP1a is located at the opening AP1 and is positioned above the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is positioned above the second upper electrode UE1b.

[0043] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b that are spaced apart from each other. The first cap layer CP2a is located at the opening AP2 and is positioned above the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is positioned above the second upper electrode UE2b.

[0044] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b that are spaced apart from each other. The first cap layer CP3a is located at the opening AP3 and is positioned above the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is positioned above the second upper electrode UE3b.

[0045] Sub-pixels SP1, SP2, and SP3 are each provided with sealing layers SE1, SE2, and SE3, respectively. Sealing layer SE1 continuously covers each component of sub-pixel SP1, including the first cap layer CP1a, partition wall 6, and second cap layer CP1b. Sealing layer SE2 continuously covers each component of sub-pixel SP2, including the first cap layer CP2a, partition wall 6, and second cap layer CP2b. Sealing layer SE3 continuously covers each component of sub-pixel SP3, including the first cap layer CP3a, partition wall 6, and second cap layer CP3b.

[0046] In the example shown in Figure 3, the second organic layer OR1b, second upper electrode UE1b, second cap layer CP1b, and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the second organic layer OR3b, second upper electrode UE3b, second cap layer CP3b, and sealing layer SE3 on the same partition wall 6. Similarly, the second organic layer OR2b, second upper electrode UE2b, second cap layer CP2b, and sealing layer SE2 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, second upper electrode UE3b, second cap layer CP3b, and sealing layer SE3 on the same partition wall 6.

[0047] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 14. The resin layer 14 is covered by a sealing layer 15. Furthermore, the sealing layer 15 is covered by a resin layer 16.

[0048] The insulating layer 13 and the resin layers 14 and 16 are made of organic material. The ribs 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are made of inorganic material such as silicon nitride (SiNx).

[0049] The lower part 61 of the partition wall 6 is conductive. The upper part 62 of the partition wall 6 may also be conductive. The lower electrode LE may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or it may have a laminated structure of a metallic material such as silver (Ag) and a conductive oxide. The upper electrode UE is formed of a metallic material such as an alloy of magnesium and silver (MgAg). The upper electrode UE may also be formed of a conductive oxide such as ITO.

[0050] When the potential of the lower electrode LE is relatively higher than the potential of the upper electrode UE, the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode. Conversely, when the potential of the upper electrode UE is relatively higher than the potential of the lower electrode LE, the upper electrode UE corresponds to the anode and the lower electrode LE corresponds to the cathode.

[0051] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between these functional layers. As an example, the organic layer OR has a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0052] The cap layer CP (CP1, CP2, and CP3) is formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. Furthermore, these multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrode UE and also different from the materials of the sealing layer SE. Note that the cap layer CP may be omitted.

[0053] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) that are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 of the sub-pixels SP (SP1, SP2, and SP3).

[0054] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0055] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0056] Figure 4 is a schematic enlarged cross-sectional view of the partition wall 6. In Figure 4, elements other than the rib 5, partition wall 6, insulating layer 13, and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE correspond to any of the lower electrodes LE1, LE2, and LE3 described above. Furthermore, the first partition wall 6x and the second partition wall 6y described above have the same structure as partition wall 6 shown in Figure 4.

[0057] In the example shown in Figure 4, the lower part 61 of the partition wall 6 includes a barrier layer 600 placed on the rib 5 and a metal layer 610 placed on the barrier layer 600. The barrier layer 600 is made of a different material from the metal layer 610, and is made of a metallic material such as molybdenum. The metal layer 610 is made thicker than the barrier layer 600. The metal layer 610 may be a single layer or a laminated structure of different metallic materials. As an example, the metal layer 610 may be made of aluminum (Al).

[0058] The upper part 62 is thinner than the lower part 61. In the example shown in Figure 4, the upper part 62 includes a first layer 621 placed on the metal layer 610 and a second layer 622 placed on the first layer 621. For example, the first layer 621 is made of titanium (Ti), and the second layer 622 is made of ITO.

[0059] In the example shown in Figure 4, the width of the lower part 61 decreases as it approaches the upper part 62. That is, the sides 61a and 61b of the lower part 61 are inclined with respect to the third direction Z. The upper part 62 has an end 62a that protrudes from the side 61a and an end 62b that protrudes from the side 61b.

[0060] The amount of protrusion D of the ends 62a and 62b from the sides 61a and 61b (hereinafter referred to as the amount of protrusion D of the partition wall 6) is, for example, 2.0 μm or less. In this embodiment, the amount of protrusion D of the partition wall 6 corresponds to the distance between the lower ends (barrier layer 600) of the sides 61a and 61b and the ends 62a and 62b in the width direction (first direction X or second direction Y) perpendicular to the third direction Z of the partition wall 6.

[0061] The structure of the partition wall 6 and the materials of each part of the partition wall 6 may be selected as appropriate, taking into consideration, for example, the method of forming the partition wall 6.

[0062] In this embodiment, the partition wall 6 is formed to partition the sub-pixels SP in a plan view. The organic layer OR described above is formed, for example, by an anisotropic or directional vacuum deposition method. However, when the organic material for forming the organic layer OR is deposited over the entire substrate 10 with the partition wall 6 in place, the partition wall 6 has the shape shown in Figures 3 and 4, so almost no organic layer OR is formed on the sides of the partition wall 6. This makes it possible to form an organic layer OR (display element 20) that is divided into sub-pixels SP by the partition wall 6.

[0063] Figures 5 to 7 are schematic cross-sectional views illustrating the display element 20 formed using the partition wall 6. The sub-pixels SPα, SPβ, and SPγ shown in Figures 5 to 7 correspond to any of the sub-pixels SP1, SP2, and SP3.

[0064] As described above, with the partition wall 6 in place, the organic layer OR, upper electrode UE, cap layer CP, and sealing layer SE are sequentially formed on the entire substrate 10 by vapor deposition, as shown in Figure 5. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. The overhanging partition wall 6 divides the organic layer OR into a first organic layer ORa covering the lower electrode LE and a second organic layer ORb on the partition wall 6, the upper electrode UE into a first upper electrode UEa covering the first organic layer ORa and a second upper electrode UEb covering the second organic layer ORb, and the cap layer CP into a first cap layer CPa covering the first upper electrode UEa and a second cap layer CPb covering the second upper electrode UEb. The first upper electrode UEa is in contact with the lower part 61 of the partition wall 6. The sealing layer SE continuously covers the first cap layer CPa, the second cap layer CPb, and the partition wall 6.

[0065] Next, as shown in Figure 6, a resist R is formed on the sealing layer SE. The resist R covers the subpixel SPα. That is, the resist R is located directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located on the subpixel SPα. The resist R is also located directly above the portion of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the subpixel SPα and the subpixel SPβ that is closer to the subpixel SPα. That is, at least a part of the partition wall 6 is exposed from the resist R.

[0066] Furthermore, etching using the resist R as a mask removes the portions of the organic layer OR, upper electrode UE, cap layer CP, and sealing layer SE that are exposed from the resist R, as shown in Figure 7. As a result, a display element 20 including the lower electrode LE, first organic layer ORa, first upper electrode UEa, and first cap layer CPa is formed in the sub-pixel SPα. On the other hand, the lower electrode LE is exposed in the sub-pixels SPβ and SPγ. The etching described above includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0067] As described above, once the display element 20 of the sub-pixel SPα is formed, the resist R is removed, and the display elements 20 of the sub-pixels SPβ and SPγ are formed sequentially, similar to the sub-pixel SPα.

[0068] As illustrated above, the sub-pixels SPα, SPβ, and SPγ are used to form the display elements 20 of the sub-pixels SP1, SP2, and SP3. By further forming the resin layer 14, the sealing layer 15, and the resin layer 16, the structure of the display device DSP shown in Figure 3 is realized.

[0069] As described above, the partition wall 6 has a lower part 61 and an upper part 62 that protrudes from the side of the lower part 61. However, if the amount of protrusion D (canopy width) of the partition wall 6 is not appropriate, the reliability of the display device DSP may decrease.

[0070] Specifically, in the DSP display device, the organic layer OR is divided for each sub-pixel SP by the partition wall 6. If the protrusion amount D is not sufficiently larger than the design value, it may not be possible to properly divide the organic layer OR. Also, if the side surface of the lower part 61 of the partition wall 6 is covered by the organic layer OR, the electrical connection between the lower part 61 and the upper electrode UE will be hindered. On the other hand, in the DSP display device, the upper electrode UE is in contact with the side surface of the lower part 61 of the partition wall 6. However, if the protrusion amount D of the partition wall 6 exceeds the design value, it is possible that the upper electrode UE will not be in contact with the side surface of the lower part 61.

[0071] In other words, if the protrusion amount D of the partition wall 6 is not appropriate, it is not possible to manufacture a highly reliable display device DSP. Therefore, it is useful to measure the protrusion amount D (i.e., the distance between the side surface of the lower part 61 and the end of the upper part 62 of the partition wall 6) during the manufacturing process of the display device DSP. For measuring the protrusion amount D of the partition wall 6, for example, a length measuring camera configured to measure the length of an object by capturing an image of the object can be used.

[0072] In this case, as shown in Figure 8, we assume that the amount of protrusion D of the partition wall 6 is measured by photographing the partition wall 6 from the third direction Z (i.e., the display surface side of the display device DSP) using the length measuring camera 100 when the partition wall 6 is formed. In this case, since the upper part 62 of the partition wall 6 has a larger width than the lower part 61 (i.e., the shape of the partition wall 6 is overhanging), if, for example, the upper part 62 includes a layer made of a light-shielding metal material that does not transmit light (e.g., titanium), the length measuring camera 100 cannot photograph the side of the lower part 61 (i.e., the end of the lower part 61 in the first direction X or the second direction Y). That is, in the example shown in Figure 8, it is possible to measure the length (width) of the upper part 62 in the first direction X or the second direction Y, but it is not possible to measure the amount of protrusion D of the partition wall 6.

[0073] Therefore, in this embodiment, as shown in Figure 9, the protrusion amount D of the partition wall 6 is measured by photographing the partition wall 6 from the opposite direction of the third direction Z (i.e., the back side opposite to the display surface of the display device DSP) using the length measuring camera 100. According to this, the length measuring camera 100 can photograph the ends of the lower 61 and upper 62 in the first direction X or the second direction Y, and thus it is considered that the protrusion amount D of the partition wall 6 can be measured.

[0074] However, as described above, in the display device DSP, a circuit layer 12 (various circuits and wiring) and a relatively thick insulating layer 13 are arranged on the substrate 10 and insulating layer 11. Therefore, even if the bulkhead 6 is photographed from the opposite direction of the third direction Z using the length measuring camera 100, it may not be possible to properly measure the protrusion amount D of the bulkhead 6 due to the influence of the circuit layer 12, etc.

[0075] Incidentally, in general, in the manufacturing process of a display device DSP, a mother board is manufactured by forming multiple display panels on a mother board which is formed by forming multiple substrates 10 together, and a display device DSP is manufactured using each of the display panels cut from the mother board.

[0076] Figure 10 schematically shows a motherboard (mother substrate). As shown in Figure 10, the motherboard 200 has multiple panel areas 201 and peripheral areas 202. The size of the motherboard 200 is, for example, about 1500 mm × 950 mm, but is not limited to this.

[0077] Each of the multiple panel regions 201 is a region where a display panel is formed, and they are arranged in a matrix in the first direction X and the second direction Y. The peripheral region 202 is the region that surrounds the multiple panel regions 201 and demarcates the multiple panel regions 201.

[0078] Here, since each of the display panels formed in the multiple panel regions 201 has a circuit layer 12 as explained in Figure 3, etc., it is not appropriate to photograph the partition wall 6 using the length measuring camera 100 in the panel region 201 (i.e., to measure the amount of protrusion D of the partition wall 6).

[0079] Therefore, in this embodiment, as an inspection of the motherboard 200 described above, the amount of protrusion D of the partition wall 6 is measured using the surrounding area 202 (for example, the area marked with an "x" in Figure 10). The areas marked with an "X" are selected from the surrounding area 202 where no light-shielding materials such as circuits, wiring, or alignment marks are formed. Then, a dummy partition wall 6, similar to the partition wall 6 formed in the panel area 201, is formed in these "X" marked areas, and the protrusion amount D is measured by photographing this dummy partition wall 6 with the length measuring camera 100. In this way, the protrusion amount D of the partition wall 6 can be measured without being affected by light-shielding materials.

[0080] The following describes the manufacturing method (manufacturing process) of the DSP display device according to this embodiment, with reference to Figure 11.

[0081] First, a mother substrate (hereinafter referred to as mother substrate 10 for convenience) is prepared by forming multiple substrates 10 together, and an insulating layer 11 is formed on the mother substrate 10 in the panel area 201 and the peripheral area 202. Next, a circuit layer 12 is formed on the insulating layer 11 in the panel area 201. In the peripheral area 202, no display panel is formed (i.e., no pixels exist), so a circuit layer 12 having circuits and wiring for driving pixels is not formed in the peripheral area 202.

[0082] Furthermore, in the panel region 201, an insulating layer 13, ribs 5, and partition walls 6 (lower 61 and upper 62) are formed sequentially on top of the circuit layer 12. Similarly, in the peripheral region 202, an insulating layer 13, ribs 5, and partition walls 6 (lower 61 and upper 62) are formed sequentially on top of the insulating layer 11.

[0083] Furthermore, the insulating layer 11, insulating layer 13, rib 5, and partition wall 6 described above are formed in the panel region 201 and the surrounding region 202 using the same process. Although omitted in Figure 11, the lower electrode LE formed in the panel region 201 does not need to be formed in the surrounding region 202.

[0084] As described above, once the partition wall 6 is formed, the protrusion amount D of the partition wall 6 is measured in the surrounding area 202 by photographing the partition wall 6 from the second surface 10B side (the side on which the display elements 20 etc. are not placed) that is opposite the first surface 10A of the mother substrate 10 using the length measuring camera 100. If the protrusion amount D of the partition wall 6 measured using the length measuring camera 100 is appropriate, the display elements 20 are formed as described in Figures 5 to 7 above. Subsequently, the display panels formed in each of the panel areas 201 are cut from the mother substrate 200, and a display device DSP is manufactured using the cut display panels.

[0085] Furthermore, whether the protrusion amount D of the partition wall 6 measured using the length-measuring camera 100 is appropriate can be determined by, for example, the person in charge of manufacturing the display device DSP. In addition, to assist the person in determining whether the protrusion amount D of the partition wall 6 is appropriate, a length-measuring camera 100 or electronic equipment connected to the length-measuring camera 100 may be used, for example, to output an alert when the measured protrusion amount D of the partition wall 6 does not fall within a predetermined range (i.e., the protrusion amount D is inappropriate).

[0086] Furthermore, the amount of protrusion D of the bulkhead 6 measured using the length measuring camera 100 may be the distance (length) between the first direction X and the second direction Y, or it may be the distance (length) of either the first direction X or the second direction Y.

[0087] Furthermore, although a detailed explanation will be omitted, the partition wall 6 in this embodiment is formed by, for example, performing anisotropic dry etching on the lower part 61 and the upper part 62, followed by isotropic wet etching. In this case, in this embodiment, the amount of protrusion D of the partition wall 6 is measured in order to suppress a decrease in the reliability of the display device DSP (display panel). However, if partition walls 6 with different amounts of protrusion D are formed in the panel area 201 and the surrounding area 202, the significance of measuring the amount of protrusion D in the surrounding area 202 is reduced.

[0088] Therefore, in this embodiment, in order to make the variation in the amount of etching when forming partition walls 6 in the panel region 201 and the peripheral region 202 the same (that is, to make the amount of protrusion of the upper part 61 of the partition walls in multiple panel regions 201 the same as the amount of protrusion of the upper part 61 of the partition walls in the peripheral region 202), partition walls 6 with the same pattern as partition walls 6 in panel region 201 are formed in at least the areas marked with an "x" in the peripheral region 202. Specifically, in panel region 201, partition walls 6 are formed with a pattern that demarcates subpixels SP, and similarly in peripheral region 202, partition walls 6 are formed with the same pattern as the pattern that demarcates subpixels SP, for example, as shown in Figure 12.

[0089] In order to form a partition wall 6 having a similar shape in the panel region 201 and the peripheral region 202, it is preferable that the peripheral region 202 (the region where the protrusion amount D of the partition wall 6 is measured) has a width that partitions at least a number of pixels PX (sub-pixels SP). In the example shown in Figure 12, it is assumed that the partition wall 6 is formed in a pattern that partitions 6 × 6 = 36 pixels PX (sub-pixels SP1, SP2, and SP3) in the area marked with an "x" in the peripheral region 202. However, the partition wall 6 may also be formed in a pattern that partitions a number of pixels PX, such as 10 × 10 = 100 pixels, in the area marked with an "x". The ribs 5 in the peripheral region 202 may be formed in the same pattern as in the panel region 201, or in a different pattern from that of the panel region 201.

[0090] Furthermore, although this embodiment describes measuring the amount of protrusion D of the partition wall 6 formed in the peripheral region 202, it is preferable that the measurement of the amount of protrusion D of the partition wall 6 be performed in all of the regions marked with an "x" in Figure 10 while moving the length measuring camera 100. This is thought to improve the reliability of all display panels (and the display devices DSPs manufactured using them) formed in the multiple panel regions 201 of the motherboard 200.

[0091] However, in order to reduce the burden of measuring the protrusion amount D of the partition wall 6, the protrusion amount D of the partition wall 6 may be measured in a part of the area marked with an "x" in Figure 10. In this case, the protrusion amount D of the partition wall 6 may be measured in areas near the four corners of the motherboard 200 and in an area near the center of the motherboard 200.

[0092] As described above, in this embodiment, the amount of protrusion D of the partition wall 6 (the distance between the side surface of the lower part 61 and the end of the upper part 62 of the partition wall 6) located on the first surface 10A side of the base material 10 is measured from the second surface 10B side of the base material 10. This configuration allows the DSP display device to be manufactured with an appropriate amount of protrusion D, thereby suppressing a decrease in the reliability of the DSP display device.

[0093] In this embodiment, a mother substrate 10 is provided having a plurality of panel regions 201 and a peripheral region 202 that divides the plurality of panel regions 201. In the plurality of panel regions 201, an insulating layer 11 (first insulating layer) is formed on the first surface 10A of the mother substrate 10, a circuit layer 12 having a pixel circuit for driving sub-pixels SP (pixels) is formed on the insulating layer 11, an insulating layer 13 (second insulating layer) is formed on the circuit layer 12, a lower electrode LE is formed at a position overlapping with the sub-pixels SP on the insulating layer 13, a rib 5 is formed that covers a part of the lower electrode LE and divides the sub-pixels SP, and a partition wall 6 is formed on the rib 5. On the other hand, in the peripheral region 202, an insulating layer 11 is formed on the first surface 10A of the mother substrate 10, an insulating layer 13 is formed on the insulating layer 11, a rib 5 is formed on the insulating layer 13, and a partition wall 6 is formed on the rib 5. In this case, the amount of protrusion D of the partition wall 6 formed in the peripheral region 202 is measured. With this configuration, even if it is difficult to accurately measure the protrusion amount D of the partition wall 6 in the panel area 201 due to the influence of the circuit layer 12, the protrusion amount D can be measured using the surrounding area 202 where the circuit layer 12 is not formed.

[0094] Furthermore, in this embodiment, the partition walls 6 in the multiple panel regions 201 are formed with a pattern that demarcates the sub-pixels SP. In contrast, the partition walls 6 in the peripheral region 202 are formed with the same pattern as the partition walls 6 formed in the multiple panel regions 201 (i.e., they are formed as dummy patterns that mimic the sub-pixels SP). This reduces the variation between the amount of etching when forming the partition walls 6 in the multiple panel regions 201 and the amount of etching when forming the partition walls 6 in the peripheral region 202. Therefore, by measuring the amount of protrusion D of the partition walls 6 formed in the peripheral region 202, it is possible to determine whether the partition walls 6 are properly formed in the panel region 201.

[0095] By the way, in this embodiment, for example, as explained in Figure 11, the amount of protrusion D of the partition wall 6 formed in the peripheral region 202 is measured. However, due to the influence of the laminated film in the lower layer of the partition wall 6 (insulating layer 11, insulating layer 13, and rib 5 between the mother substrate 10 and the partition wall 6), it may be difficult to photograph the partition wall 6 (lower part 61 and upper part 62) with the measuring camera 100. In such cases, it may not be possible to accurately measure the amount of protrusion D of the partition wall 6 (i.e., the measurement accuracy of the amount of protrusion D of the partition wall 6 may decrease).

[0096] Therefore, in this embodiment, at least one of the insulating layer 11, insulating layer 13, and rib, which are arranged between the mother substrate 10 and the partition wall 6 in the peripheral region 202, may be removed (omitted). Specifically, in the peripheral region 202, the partition wall 6 may be formed directly above the mother substrate 10, as shown in Figure 13.

[0097] Furthermore, for layers that are patterned in the panel region 201 (for example, the insulating layer 13 on which the contact holes CH are formed and the ribs 5 that demarcate the sub-pixels SP), it is considered relatively easy to remove these layers from the surrounding region 202 by etching. On the other hand, for layers that are not etched in the panel region 201 (for example, the insulating layer 11), in order to remove these layers from the surrounding region 202, it is necessary to etch only that surrounding region 202 separately. Therefore, from the viewpoint of suppressing manufacturing costs, etching of the insulating layer 11 may not be performed, and the surrounding region 202 may have a structure in which the insulating layer 11 (first insulating layer) and partition wall 6 are formed sequentially on the mother substrate 10, as shown in Figure 14 (i.e., a structure in which the insulating layer 13 and ribs 5 are removed).

[0098] Furthermore, since the insulating layer 13 may be formed from an organic material such as polyimide that is colored yellow or the like, it may reduce the accuracy of measuring the protrusion amount D of the partition wall 6 using the length measuring camera 100. From this perspective, it is desirable that the insulating layer 13 be removed between the mother substrate 10 and the partition wall 6 in the peripheral region 202. For example, as shown in Figure 15, the peripheral region 202 may have a structure in which an insulating layer 11 (first insulating layer), ribs 5 and partition wall 6 are formed in order on the mother substrate (substrate 10) (i.e., a structure in which the insulating layer 13 is removed).

[0099] Furthermore, since rib 5 is formed of an inorganic material such as silicon nitride, which has a relatively high refractive index, in order to suppress undesirable refraction caused by the difference in refractive index between rib 5 and other materials in contact with rib 5, the surrounding region 202 can also be made into a structure in which an insulating layer 11 (first insulating layer), an insulating layer 13 (second insulating layer), and a partition wall 6 are formed in order on the mother substrate (substrate 10), as shown in Figure 16 (i.e., a structure in which rib 5 is removed).

[0100] In other words, as described above, from the viewpoint of measurement accuracy of the protrusion amount D of the partition wall 6, it is preferable to remove all insulating layers 11, 13 and 5 in the peripheral region 202. However, if it is impossible to remove all of these layers, at least one of the insulating layers 11, 13 and 5 may be placed between the mother substrate 10 and the partition wall 6. Specifically, in this embodiment, the peripheral region 202 only needs to be configured so that the protrusion amount D of the partition wall 6 can be measured using the length measuring camera 100, and the layer structure between the mother substrate 10 and the partition wall 6 in the peripheral region 202 can be changed as appropriate. Accordingly, although not included in the examples shown in Figures 11 to 16, the peripheral region 202 may have a structure in which only the insulating layer 11 of the insulating layers 11, 13 and 5 is removed.

[0101] Furthermore, in this embodiment, it was explained that the upper part 62 of the partition wall 6 is formed of a light-shielding material that does not transmit light (for example, a metal material), and the amount of protrusion D of the partition wall 6 is measured from the second surface 10B side of the mother substrate 10. However, if, for example, the upper part 62 is formed of a transparent material that transmits light, the amount of protrusion D of the partition wall 6 may be measured from the first surface 10A side of the mother substrate 10 (i.e., the display surface of the display device DSP).

[0102] All methods for manufacturing a display device and a motherboard that can be implemented by those skilled in the art by appropriately modifying the design based on the methods for manufacturing a display device and a motherboard described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0103] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0104] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0105] DSP...Display device, DA...Display area, NDA...Non-display area, PX...Pixel, SP, SP1, SP2, SP3...Sub-pixel, LE, LE1, LE2, LE3...Lower electrode, UE, UE1, UE2, UE3...Upper electrode, OR, OR1, OR2, OR3...Organic layer, SE, SE1, SE2, SE3...Sealing layer, 1...Pixel circuit, 2...Pixel switch, 3...Drive transistor, 4...Capacitor, 5...Rib, 6...Partition, 10...Substrate (Mother substrate), 11...Insulating layer, 12...Circuit layer, 13...Insulating layer, 14...Resin layer, 15...Sealing layer, 16...Resin layer, 20...Display element, 61...Lower part, 62...Upper part.

Claims

1. A partition wall is formed having a lower part positioned on the first surface side of the base material and an upper part protruding from the side surface of the lower part. The distance between the lower side and the upper end of the substrate is measured from the second surface facing the first surface of the substrate. It is equipped with, The substrate has a plurality of panel regions on which a display panel is formed and a peripheral region that separates the plurality of panel regions. The partition wall is formed in both the plurality of panel areas and the surrounding area, The measurement is performed by photographing the partition wall formed in the surrounding area from the second side using a length measuring camera. A method for manufacturing a display device.

2. Before forming the partition wall, a first insulating layer is formed on the first surface of the substrate. In the plurality of panel regions, a circuit layer having a pixel circuit for driving pixels is formed on the first insulating layer, a second insulating layer is formed on the circuit layer, a lower electrode constituting the pixel is formed on the second insulating layer, a rib is formed that covers a part of the lower electrode and demarcates the pixel. The partition wall is formed on the ribs in the plurality of panel regions and on the first surface of the substrate in the peripheral region. A method for manufacturing a display device according to claim 1.

3. In the plurality of panel regions, the partition wall is formed in a pattern that divides the pixels. In the aforementioned peripheral region, the partition wall is formed in the same pattern as the partition walls formed in the plurality of panel regions. A method for manufacturing a display device according to claim 2.

4. The method for manufacturing a display device according to claim 2, wherein at least one of the first insulating layer, the second insulating layer, and the rib is formed between the substrate and the partition wall in the peripheral region.

5. After performing the above measurement, an organic layer is formed on the lower electrode. An upper electrode is formed on the aforementioned organic layer, A cap layer is formed on the upper electrode, A sealing layer is formed on the cap layer, A resist is formed on the aforementioned sealing layer. Using the resist as a mask, the sealing layer, the cap layer, the upper electrode, and the organic layer are removed. A method for manufacturing a display device according to claim 2.

6. The method for manufacturing a display device according to claim 1, wherein the partition wall is formed by performing isotropic wet etching after performing anisotropic dry etching.

7. A method for manufacturing a display device according to any one of claims 1 to 6, wherein the upper part of the partition wall is formed of a light-shielding material.

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