Memory and method for manufacturing the same

Abstract

To provide a manufacturing method for a memory, and the memory, in which control capability for a semiconductor channel of a gate is improved and the contact resistance between source-drain and the semiconductor chanel is reduced.SOLUTION: A manufacturing method for a memory provides a semiconductor substrate. In a semiconductor substrate 10, at least one memory cell is manufactured. The memory cell includes at least one transistor 11. In each transistor, a semiconductor channel 112 surrounds an outer peripheral side of at least a gate 110. A gate dielectric 111 is formed between the semiconductor channel and the gate. An upper electrode 113 and a lower electrode 114 both are located on the outside of the semiconductor channel, and are in contact with the semiconductor channel. The lower electrode is provided while being insulated below the upper electrode. By oxidizing a region to be oxidized in an effective semiconductor channel in at least one transistor in the memory cell, the region to be oxidized is formed in an oxide channel 1120.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and specifically to a memory and a manufacturing method thereof.

Background Art

[0002] With the miniaturization of technology nodes, capacitorless memory has become the focus of research. Currently, the structure of capacitorless memory tends to be a three-dimensional type structure. When defect improvement is performed on the channel of the three-dimensional type capacitorless memory by oxidation treatment, the entire channel is likely to be oxidized, resulting in an increase in the resistance of the entire channel, which is disadvantageous for improving electrical performance.

Summary of the Invention

[0003] Embodiments of the present disclosure provide a memory and a manufacturing method thereof that can improve the gate control ability for a semiconductor channel and reduce the contact resistance between the source / drain and the semiconductor channel.

[0004] The first aspect of the present disclosure provides a manufacturing method of a memory, and the manufacturing method of the memory includes: providing a semiconductor substrate; manufacturing at least one memory cell on the semiconductor substrate, where the memory cell includes at least one transistor, each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounds at least the outer peripheral side of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and contact the semiconductor channel, the lower electrode is provided below the upper electrode and insulated, and one of the upper electrode and the lower electrode is a source and the other is a drain; The step involves oxidizing a region of the active semiconductor channel in at least one of the transistors of the memory cell, thereby forming the region of oxidation in the oxidation channel, wherein the region of oxidation is at least a portion of the active semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxidation channel. valid The semiconductor channel includes a step which is a portion of the semiconductor channel located between the upper electrode and the lower electrode.

[0005] A second aspect of this disclosure provides a memory comprising a semiconductor substrate and at least one memory cell. The at least one memory cell is formed on the semiconductor substrate, the memory cell includes at least one transistor, each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounds at least the outer periphery of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is provided insulated below the upper electrode, one of the upper electrode and the lower electrode is a source and the other is a drain. In the memory cell, a portion of the effective semiconductor channel in at least one transistor is formed into an oxidized channel by an oxidation process, valid The semiconductor channel is the portion located between the upper electrode and the lower electrode of the semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxidation channel.

[0006] The technical proposal relating to the embodiments of this disclosure has at least the following advantages.

[0007] By oxidizing only the effective semiconductor channel located between the source and drain of the semiconductor channel, the gate's controllability over the semiconductor channel is improved, increasing the on-current. Furthermore, since the region of the semiconductor channel in contact with the source and drain is not oxidized, the contact resistance between the source / drain and the semiconductor channel can be reduced. [Brief explanation of the drawing]

[0008] The drawings herein are incorporated into the specification and constitute part of this specification, illustrating embodiments conforming to the disclosure and are used together with the specification to illustrate the principles of the disclosure. Clearly, the drawings in the following description are only a few embodiments of the disclosure, and those skilled in the art can, without creative work, derive other drawings from these. [Figure 1] A schematic diagram of the structure formed in accordance with step S100 in the memory manufacturing method according to the embodiment of this disclosure is shown. [Figure 2] A schematic diagram of the structure formed in accordance with step S102 in the memory manufacturing method according to the embodiment of this disclosure is shown. [Figure 3] A schematic diagram of the structure formed in accordance with step S104 in the memory manufacturing method according to the embodiment of this disclosure is shown. [Figure 4] This diagram shows a schematic representation of the structure after the corresponding gas passages have been formed in the memory manufacturing method according to the embodiment of this disclosure. [Figure 5] This diagram shows a schematic representation of the structure after an oxidation channel has been formed by introducing an oxidizing gas into the gas passage in the memory manufacturing method according to the embodiment of this disclosure. [Figure 6] This diagram shows a schematic representation of the structure after a filler has been formed by employing a partial filling method for the gas passage in the memory manufacturing method according to the embodiment of this disclosure. [Figure 7] A schematic diagram of the structure of a memory cell, including a read transistor and a write transistor, in the memory according to the embodiment of this disclosure is shown. [Figure 8]The schematic diagram shows the structure after forming an oxidation channel by oxidizing only the region of the read transistor to be oxidized in the memory manufacturing method according to the embodiment of this disclosure. [Figure 9] The schematic diagram shows the structure after forming an oxidation channel by oxidizing only the region of the writing transistor to be oxidized in the memory manufacturing method according to the embodiment of this disclosure. [Figure 10] The schematic diagram shows the structure after forming oxidation channels by oxidizing the region of the read transistor and the region of the write transistor, respectively, in the memory manufacturing method according to the embodiment of this disclosure. [Figure 11] This diagram shows a schematic representation of the structure after the corresponding gas passage has been formed in the memory manufacturing method according to Embodiment 1 of this disclosure. [Figure 12] The diagram shows a schematic representation of the structure after simultaneously forming a first oxidation channel and a second oxidation channel by introducing an oxidizing gas into a gas passage, in a memory manufacturing method according to Embodiment 1 of the present invention. [Figure 13] The diagram shows a schematic representation of the structure after the filling body has been formed by employing a complete filling method for the gas flow path in the memory manufacturing method according to Embodiment 1 of the present invention. [Figure 14] The diagram shows a schematic representation of the structure after the filling body has been formed by employing a partial filling method in the gas passage in the memory manufacturing method according to Embodiment 1 of the present invention. [Figure 15] A schematic diagram of the structure formed in step S200 of the memory manufacturing method in an embodiment of the present invention is shown. [Figure 16] A schematic diagram showing a structure formed in accordance with step S200 in the memory manufacturing method according to an embodiment of the present invention, viewed from a different perspective. [Figure 17] A schematic diagram showing a structure formed in accordance with step S200 in the memory manufacturing method according to an embodiment of the present invention, viewed from a different perspective. [Figure 18] A schematic diagram of the structure formed in accordance with step S202 of the memory manufacturing method in an embodiment of the present invention is shown. [Figure 19] The schematic diagram of the structure formed corresponding to the read transistor in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 20] The schematic diagram of the structure formed corresponding to step S2041 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 21] The schematic diagram of another structure formed corresponding to step S2041 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 22] The schematic diagram of yet another structure formed corresponding to step S2041 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 23] The schematic diagram of the structure formed corresponding to step S206 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 24] The schematic diagram of another structure formed corresponding to step S206 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 25] The schematic diagram of the structure formed corresponding to step S208 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 26] The schematic diagrams of the structure formed corresponding to step S208 in the method for manufacturing a memory according to an embodiment of the present disclosure, viewed from different perspectives, are shown. [Figure 27] The schematic diagrams of the structure formed corresponding to step S208 in the method for manufacturing a memory according to an embodiment of the present disclosure, viewed from different perspectives, are shown. [Figure 28] The schematic diagram of the structure formed corresponding to step S210 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 29] The schematic diagram of the structure formed corresponding to the write transistor in the method for manufacturing a memory according to an embodiment of the present disclosure is shown. [Figure 30] The schematic diagram of the structure formed corresponding to step S2121 in the method for manufacturing a memory according to an embodiment of the present invention is shown. [Figure 31]A schematic diagram of another structure formed in accordance with step S2121 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 32] This shows a schematic diagram of the structure formed in accordance with step S2131 in the memory manufacturing method according to an embodiment of the present invention. [Figure 33] A schematic diagram showing the structure formed in step S2132 of the memory manufacturing method according to an embodiment of the present invention, viewed from a different perspective. [Figure 34] A schematic diagram showing the structure formed in step S2132 of the memory manufacturing method according to an embodiment of the present invention, viewed from a different perspective. [Figure 35] This shows a schematic diagram of the structure formed in step S2133 of the memory manufacturing method according to an embodiment of the present invention. [Figure 36] A schematic diagram of the structure formed in step S214 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 37] A schematic diagram of another structure formed in accordance with step S214 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 38] A schematic diagram shows the horizontal arrangement of the memory cells and the second portion of the gas passage of the memory according to an embodiment of the present disclosure. [Figure 39] A schematic diagram of the structure formed in step S216 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 40] This diagram shows a schematic representation of the structure after the corresponding second gas passage has been formed in the memory manufacturing method according to Embodiment 2 of the present invention. [Figure 41] This diagram shows a schematic representation of the structure after the first gas passage has been formed in the memory manufacturing method according to Embodiment 2 of the present invention. [Figure 42] This diagram shows a schematic representation of the structure after the formation of the corresponding second oxidation channel in the memory manufacturing method according to Embodiment 2 of the present invention. [Figure 43] This diagram shows a schematic representation of the structure after the second filling body has been formed in the memory manufacturing method according to Embodiment 2 of the present invention. [Figure 44] This diagram shows a schematic representation of the structure after the corresponding first oxidation channel has been formed in the memory manufacturing method according to Embodiment 2 of the present invention. [Figure 45] This diagram shows a schematic representation of the structure after the first filling body has been formed in the memory manufacturing method according to Embodiment 2 of the present invention. [Figure 46] A schematic diagram of the structure formed in step S308 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 47] The diagram shows a schematic representation of the structure after forming the second filler body by employing a partial filling method for the second gas passage in the memory manufacturing method according to Embodiment 2 of the present invention. [Figure 48] A schematic diagram of the structure formed in step S406 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 49] A schematic diagram of another structure formed in accordance with step S406 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 50] A schematic diagram of the structure formed in step S408 in the memory manufacturing method according to an embodiment of the present invention is shown. [Figure 51] The diagram shows a schematic representation of the structure after the first filler has been formed by employing a partial filling method in the first gas passage in the memory manufacturing method according to Embodiment 2 of the present disclosure. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described in detail below with reference to the drawings. However, exemplary embodiments can be carried out in various forms and should not be limited to the examples described herein. On the contrary, by providing these embodiments, the present application becomes more comprehensive and complete, and the concepts of the exemplary embodiments are fully communicated to those skilled in the art.

[0010] Furthermore, the described features, structures, or properties can be combined in one or more embodiments in any suitable manner. Many specific details are provided in the following description to fully understand the embodiments of the present application. However, those skilled in the art will recognize that the technical solutions of the present application can be implemented without having one or more of the specific details, or that other methods, components, apparatus, steps, etc., can be used. In other cases, known methods, apparatus, implementations, or operations are not described or shown in detail to avoid obscuring each aspect of the present application.

[0011] The present application will be described in more detail below with reference to the drawings and specific embodiments. The technical features of each embodiment of the present application described below can be combined with each other, provided they do not contradict each other. The embodiments described below with reference to the drawings are illustrative and intended to illustrate the present application, and should not be understood as limiting the present application.

[0012] This disclosure provides a method for manufacturing a memory, the method for manufacturing the memory comprising steps S100, S102, and S104.

[0013] In step S100, a semiconductor substrate 10 is provided. As shown in Figure 1, for example, the semiconductor substrate 10 may be a silicon (Si) substrate, but is not limited to this; it may also be a germanium (Ge) substrate, etc., and will be determined according to the specific circumstances.

[0014] In step S102, at least one memory cell is manufactured on the semiconductor substrate 10, and the memory cell may include at least one transistor 11, as shown in Figure 2, the transistor 11 may have a three-dimensional structure, and specifically, each transistor 11 may include a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113 and a lower electrode 114, wherein the semiconductor channel 112 surrounds at least the outer periphery of the gate 110, and the gate dielectric 111 is formed between the semiconductor channel 112 and the gate 110 to avoid direct contact between the semiconductor channel 112 and the gate 110, and both the upper electrode 113 and the lower electrode 114 are located outside the semiconductor channel 112 and contact the semiconductor channel 112.

[0015] Here, the lower electrode 114 is provided insulated below the upper electrode 113, that is, the lower electrode 114 is closer to the semiconductor substrate 10 than the upper electrode 113, and one of the upper electrode 113 and the lower electrode 114 is the source and the other is the drain, and the portion located between the upper electrode 113 and the lower electrode 114 in the semiconductor channel 112 valid It can be defined as a semiconductor channel.

[0016] For example, multiple memory cells are provided and a memory array structure is formed by arranging them on a horizontal plane. Here, the memory array structure may consist of one layer or multiple layers stacked in the vertical direction. In this embodiment, the horizontal plane refers to a plane parallel or substantially parallel to the semiconductor substrate 10, and the vertical direction refers to a direction perpendicular or substantially perpendicular to the semiconductor substrate 10.

[0017] In step S104, at least one transistor 11 of the memory cells valid By oxidizing the region of the semiconductor channel to be oxidized, the region to be oxidized is formed in the oxidized channel 1120, as shown in Figure 3. Here, the region to be oxidized is valid This is at least a portion of the semiconductor channel, and neither the upper electrode 113 nor the lower electrode 114 is in contact with the oxide channel 1120.

[0018] In this embodiment, located between the source and drain in the semiconductor channel 112 valid By performing oxidation treatment only on the semiconductor channel, an oxidized channel 1120 with an oxygen vacancy is formed in the region located between the source and drain of the semiconductor channel 112, improving the control capability of the gate 110 over the semiconductor channel 112 and increasing the on-current. Furthermore, since oxidation treatment is not performed on the region of the semiconductor channel 112 that is in contact with the source and drain, the contact resistance between the source and drain and the semiconductor channel 112 can also be reduced.

[0019] Step S104 in this embodiment may belong to one of the substeps in step S102, but is not limited thereto. Step S104 may also be a step performed after the manufacturing of the entire memory cell is completed in step S102. This can be explained in detail thereafter according to the actual manufacturing situation, and will be omitted here.

[0020] Here, before performing oxidation treatment on the region to be oxidized in the semiconductor channel 112, the manufacturing method of this embodiment further includes the step of manufacturing a gas passage 12, as shown in Figure 4. The gas passage 12 includes a first portion 120 circumferentially located on the outer periphery of the region to be oxidized and a second portion 121 communicating with the first portion 120 and extending vertically upward. After the gas passage 12 is formed, an oxidizing gas introduced from above the second portion 121 acts on the region to be oxidized. That is, when performing oxidation treatment on the region to be oxidized in the semiconductor channel 112, as shown in Figure 5, an oxidizing gas can be introduced from the opening above the second portion 121. This oxidizing gas flows sequentially through the second portion 121 and the first portion 120 and acts on the region to be oxidized, thereby oxidizing the region to be oxidized into an oxidation channel 1120. Here, the thick dotted line with an arrow in the gas passage 12 in Figure 5 indicates the flow path of the oxidizing gas.

[0021] In this embodiment, the semiconductor channel 112 validBy forming an oxide channel 1120 in the semiconductor channel, the electrical performance of the transistor 11 can be improved, and a threshold voltage can be designed according to requirements to control the semiconductor channel 112. For example, the oxidizing gas in this embodiment may include at least oxygen gas.

[0022] Here, since the first portion 120 of the gas passage 12 is circumferentially located on the outer periphery of the region to be oxidized, the oxidation channel 1120 formed in this embodiment may be arranged in a ring shape, and more specifically, it may be arranged so as to surround the gate 110 of the transistor 11.

[0023] In an optional embodiment, after forming the gas passage 12 and before introducing the target gas from above the second portion 121, the manufacturing method of this embodiment may further include the step of introducing a repair agent from above the second portion 121 and allowing it to act on the region to be oxidized, thereby performing a repair treatment on the surface of the region to be oxidized.

[0024] For example, if the semiconductor channel 112 is manufactured using a metal oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide), the repair agent may contain, but is not limited to, hydrogen gas, and other types of repair agents may be used, depending on the actual situation.

[0025] Here, after forming the oxidation channel 1120, the manufacturing method of this embodiment may further include a step of filling the gas passage 12 with an insulating material to avoid subsequent processing processes affecting the oxidation channel 1120.

[0026] In some embodiments, the step of filling the gas passage 12 with insulating material may include the step of forming a filler 13 within the gas passage 12 by completely filling the gas passage 12 with insulating material, as shown in Figure 3. In order to completely fill the gas passage 12, the first portion 120 and the second portion 121 of the gas passage 12 are each filled with insulating material, and by designing in this way, structural stability can be ensured. Here, the upper surface of the filler 13 is flush with the upper surface of the gas passage 12, which ensures the flatness of the upper surface of the structure and is advantageous for forming other structural layers above it.

[0027] In this disclosure, the term "top surface" refers to the surface of the object that is not separated from the semiconductor substrate 10, and will not be explained again later.

[0028] In some other embodiments, the step of filling the gas passage 12 with insulating material may include the step of partially or completely filling the second portion 121 of the gas passage 12 with insulating material to form a filler 13 within the second portion 121, as shown in Figure 6, where the upper surface of the filler 13 is flush with the upper surface of the gas passage 12, which ensures the flatness of the upper surface of the structure and is advantageous for forming other structural layers above it.

[0029] As shown in Figure 6, the areas in the gas passage 12 other than those filled by the packing material 13 are voids. For example, if the packing material 13 fills only a portion of the second portion 121, the portions of the first portion 120 and the second portion 121 of the gas passage 12 that are not filled by the packing material 13 are both void regions. If the packing material 13 completely fills the second portion 121, the first portion 120 of the gas passage 12 is a void region. In other words, by partially and completely filling the second portion 121 of the gas passage 12 with insulating material, it is possible to avoid subsequent processing processes affecting the oxidation channels and to form the first portion 120 of the gas passage 12 as a void region. That is, there is a void between the upper electrode 113 and the lower electrode 114 of the transistor 11. As shown in Figure 6, in this way, the parasitic capacitance between the upper electrode 113 and the lower electrode 114 of the transistor 11 can be reduced.

[0030] Furthermore, when the second portion 121 of the gas passage 12 is partially filled with insulating material, the area to be filled should be the upper portion of the second portion 121. As shown in Figure 6, this ensures that the upper surface of the filler 13 is flush with the upper surface of the gas passage 12. Specifically, the filler 13 is formed by quickly sealing it using insulating material, and the filler 13 is formed in the upper portion of the second portion 121, while the lower portion of the second portion 121 and the first portion 120 are both void regions.

[0031] The manufacturing method of the memory will be described in detail below with reference to the drawings and the specific structure of the memory cell. In the embodiments of this disclosure, the memory cell may have a 2T0C structure, that is, the memory cell has a structure that includes two transistors 11 and does not have storage capacity, where one of the two transistors 11 of each memory cell is a read transistor 11R and the other is a write transistor 11W.

[0032] To facilitate subsequent explanations, in the embodiments of this disclosure, the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113, and lower electrode 114 of the write transistor 11W are defined as the first gate 110W, the first gate dielectric 111W, the first semiconductor channel 112W, the first upper electrode 113W, and the first lower electrode 114W, respectively, and the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113, and lower electrode 114 of the read transistor 11R are defined as the second gate 110R, the second gate dielectric 111R, the second semiconductor channel 112R, the second upper electrode 113R, and the second lower electrode 114R, respectively.

[0033] As shown in Figure 7, in the memory cell, the write transistor 11W is located above the read transistor 11R, and the first lower electrode 114W of the write transistor 11W is electrically connected to the second gate 110R of the read transistor 11R.

[0034] Here, in at least one transistor 11 of the memory cells mentioned in step S104 above, valid The step of forming an oxidized channel by oxidizing the region to be oxidized in the semiconductor channel specifically involves at least one of the write transistor 11W and the read transistor 11R valid The process may include a step of oxidizing the region of the semiconductor channel to be oxidized, that is, at least one of the write transistor 11W and the read transistor 11R valid The semiconductor channel includes the oxide channel 1120.

[0035] In some embodiments, the method for manufacturing the memory of the present disclosure involves one of the write transistor 11W and the read transistor 11R validThe process may include a step of oxidizing the region of the semiconductor channel to be oxidized to form an oxidized channel 1120, where the gas passage 12 is manufactured after the manufacturing of the transistor 11 corresponding to the region to be oxidized is completed. In this way, structures such as the gate dielectric 111 and gate 110 inside the semiconductor channel 112 protect it, reducing damage to the semiconductor channel 112 during the manufacturing process of the gas passage 12.

[0036] For example, as shown in Figure 8, in this embodiment, the step of oxidizing the region of transistor 11 in the memory cell is performed by oxidizing only the region of read transistor 11R in the memory cell, thereby reducing the read transistor 11R valid The semiconductor channel may include an oxide channel 1120, where the gas passage 12 is manufactured after the completion of the manufacturing of the read transistor 11R and is filled with gas before the start of the manufacturing of the write transistor 11W.

[0037] Alternatively, as shown in Figure 9, in this embodiment, the step of oxidizing the region of transistor 11 in the memory cell is performed by oxidizing only the region of the write transistor 11W in the memory cell, thereby reducing the write transistor 11W valid The semiconductor channel may include a step in which an oxide channel 1120 is included, where the gas passage 12 is manufactured after the completion of the manufacturing of the write transistor 11W.

[0038] In some other embodiments, the manufacturing method of the present disclosure involves the writing transistor 11W and the reading transistor 11R. valid The process may include the step of oxidizing both the regions of the semiconductor channel to be oxidized so that the regions of the write transistor 11W and the read transistor 11R are both formed in the oxidized channel 1120.

[0039] Here, to facilitate the subsequent explanation, the first semiconductor channel 112W in the writing transistor 11W validThe semiconductor channel is the first valid It can also be defined as a semiconductor channel, and the first in the writing transistor 11W valid The region of the semiconductor channel to be oxidized may be defined as the first region to be oxidized, and the second semiconductor channel 112R in the readout transistor 11R valid The semiconductor channel is the second valid It can also be defined as a semiconductor channel, and the second in the readout transistor 11R valid The region of the semiconductor channel that is oxidized may be defined as the region that is secondly oxidized.

[0040] Specifically, as shown in Figure 10, in the above-mentioned write transistor 11W and read transistor 11R valid The step of oxidizing both the regions to be oxidized in the semiconductor channel, thereby forming the regions to be oxidized in both the write transistor 11W and the read transistor 11R in the oxidized channel 1120, is the first step in the write transistor 11W. valid The first step is to oxidize the region of the semiconductor channel to form the first oxidation channel 1120W, and the second step is to oxidize the region of the semiconductor channel to form the first oxidation channel 1120W in the readout transistor 11R. valid The method may include the step of oxidizing the region of the semiconductor channel to form a second oxidation channel 1120R, thereby oxidizing both the region of the write transistor 11W and the read transistor 11R, which forms an oxidation channel 1120 in the write transistor 11W and the read transistor 11R, respectively, improving the electrical performance of the read transistor 11R and the write transistor 11W, and improving the memory cell's storage performance.

[0041] In this embodiment, the write transistor 11W and the read transistor 11R valid Embodiments of oxidizing all regions of a semiconductor channel may include the following multiple types.

[0042] [Embodiment 1] In this embodiment of the disclosure, the first oxide channel 1120W of the write transistor 11W and the second oxide channel 1120R of the read transistor 11R may be formed simultaneously. In other words, the first oxide channel 1120W and the second oxide channel 1120R are formed in the same manufacturing step, thereby improving manufacturing efficiency and reducing manufacturing costs.

[0043] In this embodiment, if the first oxidation channel 1120W and the second oxidation channel 1120R need to be formed simultaneously, the gas passage 12 is manufactured after the completion of the manufacturing of the writing transistor 11W. In this embodiment, as shown in Figure 11, the first portion 120 of the manufactured gas passage 12 may include an upper first portion 120W and a lower first portion 120R, where the upper first portion 120W refers to the upper portion of the first portion 120 that is away from the semiconductor substrate 10 and surrounds the outer periphery of the first oxidation target region, and the lower first portion 120R refers to the lower portion of the first portion 120 that is closer to the semiconductor substrate 10 and surrounds the outer periphery of the second oxidation target region.

[0044] As shown in Figure 11, in this embodiment, the upper first portion 120W and the lower first portion 120R of the gas passage 12 are spaced apart in the vertical direction Z and connected by the second portion 121. Specifically, the second portion 121 extends vertically upward to the upper surface of the memory cell, connecting the upper first portion 120W and the lower first portion 120R. This enables the oxidizing gas introduced from above the second portion 121 to act simultaneously on the first oxidation target region and the second oxidation target region, thereby performing the oxidation process. As shown in Figure 12, the oxidizing gas enters the second part 121 through its intake port. A portion of the oxidizing gas is diverted into the upper first part 120W, acting on the first region to be oxidized and performing oxidation treatment. Another portion of the oxidizing gas is diverted into the lower first part 120R, acting on the second region to be oxidized and performing oxidation treatment. In this way, the first oxidation channel 1120W and the second oxidation channel 1120R are formed simultaneously. The thick dashed lines with arrows in Figure 12 indicate the flow paths of the oxidizing gas.

[0045] Exemplary, after the first oxidation channel 1120W and the second oxidation channel 1120R are formed simultaneously, as shown in Figure 13, the gas passage 12 can be completely filled with insulating material to form a filler 13 within the gas passage 12. That is, the upper first portion 120W, the lower first portion 120R, and the second portion 121 of the gas passage 12 are all filled with a filler 13 manufactured using insulating material, ensuring the structural stability of the memory cell. Here, the upper surface of the filler 13 can be flush with the upper surface of the memory cell, thereby ensuring the flatness of the upper surface of the memory array structure, which is advantageous for the manufacturing of subsequent structural layers.

[0046] Furthermore, after the first oxidation channel 1120W and the second oxidation channel 1120R are formed simultaneously, the gas passage 12 is not limited to being filled using the complete filling method described above, but may also be filled using an incomplete filling method. For example, the second portion 121 is divided into an upper main region and a lower communication region along the vertical direction Z, the upper main region extends from the top surface of the memory cell to the upper first portion 120W and communicates with the upper first portion 120W, and the lower communication region The region connects the upper first portion 120W and the lower first portion 120R. Here, in order to form a filler 13 in the upper main region of the second portion 121, a method of quickly sealing is employed to fill the upper main region with insulating material. As shown in Figure 14, the upper surface of this filler 13 is flush with the upper surface of the memory cell. The filler 13 may completely fill the upper main region of the second portion 121, or it may fill the upper half of the upper main region.

[0047] Here, after filling the gas passage 12 using the incomplete filling method described above, as shown in Figure 14, the upper first portion 120W and the lower first portion 120R are both void regions not filled with the packing material 13. That is, there are voids between the first upper electrode 113W and the first lower electrode 114W, and between the second upper electrode 113R and the second lower electrode 114R. In this way, the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W, and between the second upper electrode 113R and the second lower electrode 114R can be reduced.

[0048] In one specific embodiment of the embodiments of the present disclosure, the method for manufacturing the gas passage 12, which includes an upper first portion 120W, a lower first portion 120R, and a second portion 121, may include at least steps S200, S202, S204, S206, S208, S210, S212, S214, and S216.

[0049] In step S200, a lower multilayer film is formed on the semiconductor substrate 10. As shown in Figure 15, the lower multilayer film includes a second lower electrode 114R, a lower sacrificial insulating film layer 141R, a second upper electrode 113R, and a lower partition insulating film layer 142R, which are sequentially stacked at least along the vertical Z direction. Here, the material of the lower partition insulating film layer 142R may be different from the material of the lower sacrificial insulating film layer 141R and the subsequent upper sacrificial insulating film layer, in order to avoid the risk of the lower partition insulating film layer 142R also being removed in the subsequent removal step of the upper sacrificial insulating film layer and the lower sacrificial insulating film layer 141R.

[0050] In some embodiments, as shown in Figure 15, the lower laminated film layer may further include a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, the first lower interlayer dielectric layer 143R being formed between the second upper electrode 113R and the lower sacrificial insulating film layer 141R, and the second lower interlayer dielectric layer 144R being formed between the second lower electrode 114R and the lower sacrificial insulating film layer 141R.

[0051] Here, the materials of the first interlayer dielectric layer 143R and the second interlayer dielectric layer 144R are different from the material of the lower sacrificial insulating film layer 141R, so as to avoid the risk that the first interlayer dielectric layer 143R and the second interlayer dielectric layer 144R will also be removed in the subsequent step of removing the lower sacrificial insulating film layer 141R, thereby protecting the second upper electrode 113R and the second lower electrode 114R.

[0052] For example, the insulating materials of the first interlayer dielectric layer 143R, the second interlayer dielectric layer 144R, and the lower partition insulating film layer 142R may be the same, for example, all of which may be silicon oxide. The insulating material of the lower sacrificial insulating film layer 141R may be silicon nitride, silicon oxynitride, or silicon carbonitride, but is not limited to these and can be determined according to the actual situation.

[0053] In some embodiments of this disclosure, step S200 may specifically include steps S2001, S2002, S2003, and S2004.

[0054] In step S2001, the semiconductor substrate 10 has a plurality of second down signal lines 145R arranged side by side with spacing in the first horizontal direction X and extending in the second horizontal direction Y, and a second lower partition insulating portion 146R located between adjacent second down signal lines 145R. Referring to Figures 16 and 17, in this embodiment, the second lower partition insulating portion 146R insulates adjacent second down signal lines 145R from each other. Here, the second down signal lines 145R may be formed on the semiconductor substrate 10 before the second lower partition insulating portion 146R, but is not limited to this, and the second lower partition insulating portion 146R may be formed first, and then the plurality of second down signal lines 145R may be formed.

[0055] In this disclosure, the first horizontal direction X and the second horizontal direction Y, as referred to at any point, are defined as directions parallel or substantially parallel to the semiconductor substrate 10. Here, the first horizontal direction X intersects with the second horizontal direction Y, and furthermore, the first horizontal direction X and the second horizontal direction Y are perpendicular or substantially perpendicular, thereby reducing the difficulty of design and saving space.

[0056] In step S2002, as shown in Figures 16 and 17, a second interlayer dielectric layer 144R, a lower sacrificial insulating film layer 141R, and a first interlayer dielectric layer 143R are formed sequentially along the vertical direction Z on the upper surface (i.e., the surface away from the semiconductor substrate 10) of the second down signal line 145R and the second lower partition insulating portion 146R.

[0057] In step S2003, as shown in Figures 16 and 17, the first interlayer dielectric layer 143R has a plurality of second up signal lines 147R arranged side by side with spacing in the second horizontal direction Y and extending in the first horizontal direction X, and a second upper partition insulating portion 148R located between adjacent second up signal lines 147R. In this embodiment, the second upper partition insulating portion 148R insulates adjacent second up signal lines 147R from each other. Here, the second up signal lines 147R are formed in the first interlayer dielectric layer 143R before the second upper partition insulating portion 148R, but are not limited to this; the second upper partition insulating portion 148R may be formed first, and then the plurality of second up signal lines 147R may be formed.

[0058] In this embodiment of the disclosure, one of the second up signal line 147R and the second down signal line 145R is a read bit line, and the other is a read word line. As shown in Figures 16 and 17, the orthogonal projection of the second up signal line 147R onto the semiconductor substrate 10 overlaps with the orthogonal projection of the second down signal line 145R onto the semiconductor substrate 10. Here, the portion corresponding to the overlapping region in the second up signal line 147R is defined as the second upper electrode 113R, and the portion corresponding to the overlapping region in the second down signal line 145R is defined as the second lower electrode 114R.

[0059] For example, the second up signal line 147R and the second down signal line 145R may include one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), A1 (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and polysilicon, but are not limited to these. Other conductive materials may be used as long as the performance of the second up signal line 147R and the second down signal line 145R can be ensured.

[0060] In step S2004, as shown in Figures 16 and 17, a lower partition insulating film layer 142R is formed that completely covers the second up signal line 147R and the second upper partition insulating portion 148R.

[0061] The lower partition insulating film layer 142R may be integrally molded with the second upper partition insulating part 148R, but is not limited to this, and may be manufactured separately depending on the specific circumstances.

[0062] In some other embodiments, the lower laminated film layer may not include the first interlayer dielectric layer 143R and the second interlayer dielectric layer 144R shown in Figures 15 to 17, depending on the specific circumstances.

[0063] In step S202, a lower through-hole 149R is formed that penetrates at least the lower partition insulating film layer 142R, the second upper electrode 113R, and the lower sacrificial insulating film layer 141R. As shown in Figure 18, the second lower electrode 114R is exposed through the lower through-hole 149R. The second upper electrode 113R belongs to the portion of the second up signal line 147R that overlaps with the second down signal line 145R, and the second lower electrode 114R belongs to the portion of the second down signal line 145R that overlaps with the second up signal line 147R. Therefore, it can be understood that the lower through-hole 149R in this embodiment is formed in the region where the second up signal line 147R and the second down signal line 145R overlap.

[0064] Here, if the lower laminated film layer further includes a first interlayer dielectric layer 143R and a second interlayer dielectric layer 144R, the lower through-hole 149R may further penetrate the first interlayer dielectric layer 143R and the second interlayer dielectric layer 144R, as shown in Figure 18.

[0065] For example, the lower surface of the lower through-hole 149R can extend into the second lower electrode 114R, as shown in Figure 18, thereby increasing the area of ​​the second lower electrode 114R that is exposed, increasing the contact area with the subsequent semiconductor channel 112, ensuring that the second lower electrode 114R is exposed, reducing etching accuracy, and lowering etching costs. However, the lower surface of the lower through-hole 149R is not limited to extending into the second lower electrode 114R; it may extend to the upper surface of the second lower electrode 114R, or the lower through-hole 149R may penetrate the second lower electrode 114R, etc. (i.e., the lower surface of the lower through-hole 149R is flush with the lower surface of the second lower electrode 114R, or lower than the lower surface of the second lower electrode 114R).

[0066] In step S204, a second semiconductor channel 112R, a second gate dielectric 111R, and a second gate 110R are formed in the lower through-hole 149R, thereby forming a readout transistor 11R. As shown in Figure 19, the region of the second semiconductor channel 112R that is to be oxidized corresponds to the lower sacrificial insulating film layer 141R, that is, the region of the second semiconductor channel 112R that is to be oxidized is located in a position surrounded by the lower sacrificial insulating film layer 141R.

[0067] Furthermore, if the lower laminated film layer includes a first interlayer dielectric layer 143R and a second interlayer dielectric layer 144R, after step S204, both the first interlayer dielectric layer 143R and the second interlayer dielectric layer 144R are second valid It is provided so as to surround the semiconductor channel, and specifically, the first lower interlayer dielectric layer 143R is the second valid The second lower interlayer dielectric layer 144R may surround the region located above the region to be secondly oxidized in the semiconductor channel, and the second lower interlayer dielectric layer 144R is the second valid It may also surround the region located below the region targeted for secondary oxidation in the semiconductor channel.

[0068] In some embodiments of this disclosure, step S204 may include at least steps S2041 and S2042.

[0069] In step S2041, after forming the lower through-hole 149R, the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R are sequentially deposited on the lower multilayer film. As shown in Figure 20, the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R all completely cover the lower multilayer film. In other words, the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R are The lower partition insulating film layer 142R can be deposited on the upper surface and within the lower through-hole 149R. Here, as shown in Figure 20, the portions of the lower semiconductor thin film layer 151R and the lower gate dielectric thin film layer 152R located within the lower through-hole 149R may be U-shaped, and the portion of the lower gate thin film layer 153R located within the lower through-hole 149R may also be U-shaped, or, as shown in Figure 21, the lower gate thin film layer 153R fills the lower through-hole 149R.

[0070] For example, the material of the lower semiconductor thin film layer 151R may be a semiconductor material such as IGZO, but is not limited to that, and may be other semiconductor materials; the material of the lower gate dielectric thin film layer 152R may be a high dielectric insulating material such as silicon oxide, but is not limited to that, and may be a low dielectric material; and the material of the lower gate thin film layer 153R may be a conductive material having good gate control ability such as ZnO (zinc oxide), ITO (indium tin oxide), or IZO (indium zinc oxide), but is not limited to that, and may be other conductive materials.

[0071] Furthermore, if the portion of the lower gate thin film layer 153R located within the lower through-hole 149R is U-shaped as shown in Figure 20, step S2041 may further include the step of depositing a lower conductive filling thin film layer 154R that completely covers the lower gate thin film layer 153R after depositing the lower gate thin film layer 153R. As shown in Figure 22, the portion of the lower conductive filling thin film layer 154R located within the lower through-hole 149R fills the lower through-hole 149R. In this embodiment, the lower conductive filling thin film layer 154R can be made of a conductive material that has good conductivity and a lower cost than the lower gate thin film layer 153R.

[0072] In step S2042, as shown in Figure 19, portions of the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R that exceed the target distance value from the hole boundary of the lower through-hole 149R are etched and removed, thereby forming a second semiconductor channel 112R, a second gate dielectric 111R, and a second gate 110R in the lower through-hole 149R, and thus forming a readout transistor 11R.

[0073] Here, the acquired target distance value mentioned in step S2042 may be 0, meaning that the portions of the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R that extend beyond the boundary of the lower through-hole 149R are all etched and removed. However, it is not limited to this, and the acquired target distance value mentioned in step S2042 may be greater than 0, but it must be smaller than half the distance between adjacent lower through-holes 149R. In addition to the portions of the second semiconductor channel 112R, the second gate dielectric 111R, and the second gate 110R manufactured in this way that are located within the lower through-hole 149R, there are further portions that extend away from the hole axis and are mounted on the upper surface of the lower partition insulating film layer 142R. When forming multiple readout transistors 11R arranged in an array in this way, as shown in Figure 19, the difficulty of etching can be reduced and the quality of the product can be guaranteed.

[0074] Furthermore, in step S2041, if a lower conductive filling thin film layer 154R that completely covers the lower gate thin film layer 153R is included, it should be understood that in step S2042, in the process of etching and removing portions of the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R that exceed the target distance value from the hole boundary, the process further includes etching and removing portions of the lower conductive filling thin film layer 154R that exceed the target distance value from the hole boundary. Here, the remaining unetched portion of the lower conductive filling thin film layer 154R is defined as the lower conductive filling portion 115R, and the lower conductive filling portion 115R may be included in the read transistor 11R, a part of the lower conductive filling portion 115R filling the lower through-hole 149R and contacting the second gate 110R, and the other part mounted on the upper surface of the second gate 110R, and the upper surface of the second gate 110 as referred to in this disclosure refers to the surface of the second gate 110 that is furthest from the semiconductor substrate 10.

[0075] In step S206, an intermediate partition insulating film layer 16 is formed on the lower laminated film layer, and as shown in Figure 23, the intermediate partition insulating film layer 16 covers at least the area on the upper surface of the lower partition insulating film layer 142R that is not covered by the read transistor 11R, and the orthogonal projection of at least a portion of the second gate 110R onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the intermediate partition insulating film layer 16 onto the semiconductor substrate 10, that is, at least a portion of the second gate 110R is not shielded by the intermediate partition insulating film layer 16 so as to be connected to the first lower electrode 114W of the write transistor 11W that is formed later.

[0076] Here, as shown in Figure 23, the portion of the second gate 110R located within the lower through-hole 149R is U-shaped, and when the lower through-hole 149R is filled with the lower conductive filling portion 115R, the upper surface of the intermediate partition insulating film layer 16 may be higher than the upper surface of the lower conductive filling portion 115R, and the intermediate partition insulating film layer 16 has a plurality of intermediate vias 160 that correspond one-to-one with the lower conductive filling portion 115R, and the intermediate vias 160 expose at least a portion of the upper surface of the lower conductive filling portion 115R. As shown in Figure 24, when the second gate 110R fills the lower through-hole 149R, the upper surface of the intermediate partition insulating film layer 16 may be higher than the upper surface of the second gate 110R, and the intermediate partition insulating film layer 16 has a plurality of intermediate vias 160 that correspond one-to-one with the second gate 110R of the read transistor 11R, and the intermediate vias 160 expose at least a portion of the upper surface of the second gate 110R.

[0077] In step S208, an upper laminated film layer is formed, as shown in Figure 25, and the upper laminated film layer includes a first lower electrode 114W, an upper sacrificial insulating film layer 171W, a first upper electrode 113W, and an upper partition insulating film layer 172W that are sequentially stacked at least along the vertical direction Z, the first lower electrode 114W is connected to the second gate 110R, and the upper surface of the first lower electrode 114W is flush with the upper surface of the intermediate partition insulating film layer 16.

[0078] For example, by using a different material for the upper partition insulating film layer 172W than for the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, the risk of the upper partition insulating film layer 172W being removed during the subsequent removal step of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R is avoided.

[0079] In some embodiments, as shown in Figure 25, the upper laminated film layer may further include a first interlayer dielectric layer 173W and a second interlayer dielectric layer 174W, the first interlayer dielectric layer 173W being formed between the first upper electrode 113W and the upper sacrificial insulating film layer 171W, and the second interlayer dielectric layer 174W being formed between the intermediate partition insulating film layer 16 and the upper sacrificial insulating film layer 171W.

[0080] For example, by using materials different from those of the upper sacrificial insulating film layer 171W and lower sacrificial insulating film layer 141R, the risk of the first and second interlayer dielectric layers 173W and 174W being removed during the subsequent removal step of the upper sacrificial insulating film layer 171W and lower sacrificial insulating film layer 141R can be avoided, and the first upper electrode 113W and first lower electrode 114W can be protected using the first and second interlayer dielectric layers 173W and 174W.

[0081] For example, the insulating materials of the first upper interlayer dielectric layer 173W, the second upper interlayer dielectric layer 174W, the upper partition insulating film layer 172W, the intermediate partition insulating film layer 16, and the lower partition insulating film layer 142R may be the same, for example, all of which may be silicon oxide. The insulating materials of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R may also be the same, for example, all of which may be silicon nitride, silicon oxynitride, or silicon carbonitride. It should be understood that the insulating materials of each interlayer dielectric layer, partition insulating film layer, and sacrificial insulating film layer are not limited to those exemplified above, and other insulating materials may be used in some cases.

[0082] In some embodiments of this disclosure, step S208 may specifically include steps S2081, S2082, and S2083.

[0083] In step S2081, as shown in Figures 26 and 27, a plurality of first lower electrodes 114W are formed, arranged in an array along the first horizontal direction X and the second horizontal direction Y, with each first lower electrode 114W corresponding one-to-one within the intermediate via 160, that is, each first lower electrode 114W is connected to one second gate 110R.

[0084] When the second gate 110R fills the lower through-hole 149R, the lower surface of the first lower electrode 114W comes into direct contact with the upper surface of the second gate 110R, thereby achieving a direct connection between the first lower electrode 114W and the second gate 110R. Here, the first lower electrode 114W and the second gate 110R may be integrally molded, but are not limited to this, and may be manufactured separately. That is, the manufacturing of the second gate 110R may be completed first, followed by the manufacturing of the first lower electrode 114W. Furthermore, the first lower electrode 114W and the second gate 110R may be manufactured from the same conductive material, but are not limited to this, and may be manufactured from different conductive materials, and should be understood to be determined according to the specific circumstances.

[0085] If the portion of the second gate 110R located within the lower through-hole 149R is U-shaped and the lower through-hole 149R is filled with the lower conductive filling portion 115R, the lower surface of the first lower electrode 114W directly contacts the upper surface of the lower conductive filling portion 115R, thereby achieving indirect connection with the second electrode via the lower conductive filling portion 115R. Here, the first lower electrode 114W may be integrally molded with the lower conductive filling portion 115R, but is not limited to this, and the lower conductive filling portion 115R and the first lower electrode 114W may be manufactured separately. That is, the manufacturing of the lower conductive filling portion 115R may be completed first, and then the first lower electrode 114W may be manufactured. Furthermore, the first lower electrode 114W and the lower conductive filling portion 115R may be manufactured from the same conductive material, but is not limited to this, and may be manufactured from different conductive materials, and can be determined according to the specific circumstances.

[0086] For example, when the first lower electrode 114W and the second gate 110R are integrally molded, or when the first lower electrode 114W and the lower conductive fill portion 115R are integrally molded, the intermediate partition insulating film layer 16 may be selected as an integrally molded layer-whole structure. For example, after the first lower electrode 114W is integrally molded with the second gate 110R or the lower conductive fill portion 115R, step S206 may specifically include first forming an intermediate partition insulating thin film that completely covers the lower partition insulating film layer 142R, the second gate 110R (or the lower conductive fill portion 115R), and the first lower electrode 114W, and then forming the intermediate partition insulating film layer 16 by removing the entire portion of the intermediate partition insulating thin film that is higher than the upper surface of the first lower electrode 114W, wherein the upper surface of this intermediate partition insulating film layer 16 is flush with the upper surface of the first lower electrode 114W.

[0087] Furthermore, if the first lower electrode 114W is manufactured separately from the second gate 110R or separately from the lower conductive filling portion 115R, the intermediate partition insulating film layer 16 may be an integrally molded layer structure. For example, after the second gate 110R or the lower conductive filling portion 115R is formed, and before the first lower electrode 114W is formed, step S206 completely covers the lower partition insulating film layer 142R and the second gate 110R (or lower conductive filling portion 115R). The process may include the step of first forming an intermediate partition insulating thin film, and then removing the portion of the intermediate partition insulating thin film that is higher than the upper surface of the second gate 110R (or lower conductive filling portion 115R) to form an intermediate partition insulating film layer 16 including an intermediate via 160, and then performing step S2081, but is not limited thereto, and if the first lower electrode 114W is manufactured separately from the second gate 110R or separately from the lower conductive filling portion 115R, the intermediate The partition insulating film layer 16 may be manufactured in two layers. For example, after forming the second gate 110R or the lower conductive filling portion 115R, a first intermediate insulating thin film is first formed to completely cover the lower partition insulating film layer 142R and the second gate 110R (or the lower conductive filling portion 115R). Then, the entire portion of the first intermediate insulating thin film that is higher than the upper surface of the second gate 110R (or the lower conductive filling portion 115R) is removed to form a first intermediate insulating film layer. This first intermediate insulating film layer covers the area on the upper surface of the lower partition insulating film layer 142R that is not covered by the read transistor 11R. Then, a second intermediate insulating thin film is formed to completely cover the second intermediate insulating film layer and the second gate 110R (or the lower conductive filling portion 115R). Furthermore, a second intermediate insulating film layer including intermediate vias is formed by performing a hole-making process on the second intermediate insulating thin film. This second intermediate insulating film layer and the first intermediate insulating film layer constitute the intermediate partition insulating film layer 16.

[0088] The manufacturing step for the second intermediate insulating film layer may be performed after the manufacturing step for the first lower electrode 114W, or before the manufacturing step for the first lower electrode 114W, or it may be determined in some cases, and the explanation is omitted here.

[0089] In step S2082, as shown in Figures 26 and 27, a second upper interlayer dielectric layer 174W, an upper sacrificial insulating film layer 171W, and a first upper interlayer dielectric layer 173W are sequentially stacked on the upper surfaces of the intermediate partition insulating film layer 16 and the first lower electrode 114W.

[0090] In step S2083, the first interlayer dielectric layer 173W has a plurality of write bit lines 175W arranged side by side with spacing in the second horizontal direction Y and extending in the first horizontal direction X, and a first lower partition insulating portion 176W located between adjacent write bit lines 175W. As shown in Figures 26 and 27, in this embodiment, the first lower partition insulating portion 176W can insulate adjacent write bit lines 175W from each other. Here, the write bit lines 175W are formed on the first interlayer dielectric layer 173W before the first lower partition insulating portion 176W, but are not limited to this, and the first lower partition insulating portion 176W may be formed first, and then the plurality of write bit lines 175W may be formed.

[0091] In the embodiments of this disclosure, the writing bit line 175W may include a first upper electrode 113, and the orthogonal projection of the first upper electrode 113 onto the semiconductor substrate 10 has an overlapping region with the orthogonal projection of the first lower electrode 114W onto the semiconductor substrate 10.

[0092] In step S2084, as shown in Figures 26 and 27, an upper partition insulating film layer 172W is formed that completely covers the writing bit line 175W and the first lower partition insulating portion 176W.

[0093] In some other embodiments, the upper laminated film layer may not include the first interlayer dielectric layer 173W and the second interlayer dielectric layer 174W, depending on the specific circumstances.

[0094] In step S210, an upper through-hole 177W is formed that penetrates at least the upper partition insulating film layer 172W, the first upper electrode 113W, and the upper sacrificial insulating film layer 171W, as shown in Figure 28, where the first lower electrode 114W is exposed through the upper through-hole 177W, that is, the upper through-hole 177W may be formed in a region where the first upper electrode 113W and the first lower electrode 114W correspond to and overlap.

[0095] For example, the orthogonal projections of the upper through-hole 177W and the lower through-hole 149R onto the semiconductor substrate 10 can overlap so that the write transistor 11W and the read transistor 11R of the memory cell overlap as much as possible in the vertical direction Z, thereby ensuring the performance of the memory cell and reducing the horizontal area occupied by the memory cell. This allows more memory cells to be placed within a unit area, thereby improving the memory's storage density.

[0096] In some embodiments, as shown in Figure 28, if the upper laminated film layer further includes a first interlayer dielectric layer 173W and a second interlayer dielectric layer 174W, the upper through-hole 177W may further penetrate the first interlayer dielectric layer 173W and the second interlayer dielectric layer 174W.

[0097] For example, as shown in Figure 28, the orthogonal projection of the upper through-hole 177W onto the semiconductor substrate 10 can completely cover the orthogonal projection of the first lower electrode 114W onto the semiconductor substrate 10. In this case, the lower surface of the upper through-hole 177W extends just to the upper surface of the first lower electrode 114W, thereby avoiding the subsequent etching being prone to etching defects due to the difference in materials between the first lower electrode 114W and the intermediate partition insulating film layer 16.

[0098] Furthermore, the orthogonal projection of the upper through-hole 177W onto the semiconductor substrate 10 may be located within the orthogonal projection of the first lower electrode 114W onto the semiconductor substrate 10. In this case, the lower surface of the upper through-hole 177W may extend into the interior of the first lower electrode 114W. In this way, the area exposed of the first lower electrode 114W can be increased, thereby increasing the contact area with the subsequent semiconductor channel 112. This ensures that the first lower electrode 114W is exposed while reducing etching accuracy and thus reducing etching costs. However, it should be understood that the lower surface of the upper through-hole 177W is not limited to extending into the first lower electrode 114W, but may extend just above the first lower electrode 114W.

[0099] In step S212, as shown in Figure 29, a first semiconductor channel 112W, a first gate dielectric 111W, and a first gate 110W are sequentially formed in the upper through-hole 177W to form a writing transistor 11W. Here, the first oxidation target region of the first semiconductor channel 112W corresponds to the upper sacrificial insulating film layer 171W, that is, the first oxidation target region of the first semiconductor channel 112W is located in a position surrounded by the upper sacrificial insulating film layer 171W.

[0100] Furthermore, if the upper laminated film layer includes a first interlayer dielectric layer 173W and a second interlayer dielectric layer 174W, after performing step S212, as shown in Figure 29, the first interlayer dielectric layer 173W and the second interlayer dielectric layer 174W are both first valid It may be provided so as to surround the semiconductor channel, and specifically, the first upper interlayer dielectric layer 173W is the first valid The second upper interlayer dielectric layer 174W may surround the region located above the first oxidation target region in the semiconductor channel, and the first valid It may also surround the region located below the region targeted for first oxidation in the semiconductor channel.

[0101] In some embodiments of this disclosure, step S212 may include at least steps S2121 and S2122.

[0102] In step S2121, after forming the upper through-hole 177W, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W are sequentially deposited on the upper laminated film layer. As shown in Figure 30, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W all completely cover the upper laminated film layer. In other words, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W may be deposited on the upper surface of the upper partition insulating film layer 172W and inside the upper through-hole 177W.

[0103] Here, as shown in Figure 31, the portions of the upper semiconductor thin film layer 181W and the upper gate dielectric thin film layer 182W located within the upper through-hole 177W may be U-shaped, the portion of the upper gate thin film layer 183W located within the upper through-hole 177W may also be U-shaped, or, as shown in Figure 30, the upper gate thin film layer 183W may fill the upper through-hole 177W.

[0104] For example, the material of the upper semiconductor thin film layer 181W may be a semiconductor material such as IGZO, but is not limited to this, and may be other semiconductor materials; the material of the upper gate dielectric thin film layer 182W may be a high dielectric insulating material such as silicon oxide, but is not limited to this, and may be a low dielectric material; and the material of the upper gate thin film layer 183W may be a conductive material having good gate control capability such as ZnO (zinc oxide), ITO (indium tin oxide), or IZO (indium zinc oxide), but is not limited to this, and may be other conductive materials.

[0105] In step S2122, the portions of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W that exceed the target distance value from the hole boundary of the upper through-hole 177W are etched and removed, thereby forming a first semiconductor channel 112W, a first gate dielectric 111W, and a first gate 110W in the upper through-hole 177W, and thus forming the write transistor 11W.

[0106] In the embodiments of this disclosure, the acquired target distance value mentioned in step S2122 may be 0, meaning that the portions of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W that extend beyond the boundary of the upper through-hole 177W are all etched and removed. However, the acquired target distance value mentioned in step S2122 may be greater than 0, but it must be less than half the distance between adjacent upper through-holes 177W. In addition to the portions of the first semiconductor channel 112W, the first gate dielectric 111W, and the first gate 110W manufactured in this manner that are located within the upper through-hole 177W, there are further portions that extend away from the hole axis and are mounted on the upper surface of the upper partition insulating film layer 172W. When forming a plurality of writing transistors 11W arranged in an array in this manner, as shown in Figure 29, the difficulty of etching can be reduced and the quality of the product can be guaranteed.

[0107] Here, if the portion located within the upper through-hole 177W of the first gate 110W is U-shaped, the writing transistor 11W of this embodiment may further include an upper conductive filling portion 115W that fills at least the upper through-hole 177W, as shown in Figure 29. In this embodiment, the upper conductive filling portion 115W may be made of a conductive material that has good conductivity and a lower cost than the first gate 110W.

[0108] For example, the upper conductive filling portion 115W in this embodiment may be columnar, and the upper surface of the columnar upper conductive filling portion 115W may be flush with the upper surface of the first gate 110W, but is not limited to this. The upper conductive filling portion 115W may also be T-shaped, and as shown in Figure 29, the T-shaped upper conductive filling portion 115W may fill the upper through-hole 177W and cover the upper surface of the first gate 110W, and this upper surface of the first gate 110W may be the surface furthest from the semiconductor substrate 10 in the first gate 110W.

[0109] In some embodiments, the manufacturing method for the upper conductive filling portion 115W may include the following steps: In step S2121, after depositing the upper gate thin film layer 183W, an upper conductive filling thin film layer 184W that completely covers the upper gate thin film layer 183W is further deposited as shown in Figure 31; then, step S2112 is performed to etch away portions of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W that exceed the target distance value from the hole boundary, and to etch away portions of the upper conductive filling thin film layer 184W that exceed the target distance value from the hole boundary, thereby forming a T-shaped upper conductive filling portion. If a columnar upper conductive filling portion is to be formed, after performing step S2112, the portion of the T-shaped upper conductive filling portion that exceeds the upper surface of the first gate 110W may be removed to form a columnar upper conductive filling portion.

[0110] Furthermore, the columnar upper conductive filling portion is not limited to those manufactured by the above method. For example, after performing step S2122 to form the first gate 110W, the first gate dielectric 111W, and the first semiconductor channel 112W of the writing transistor 11W, the upper conductive filling thin film layer 184W may be deposited first. This upper conductive filling thin film layer 184W not only completely covers the structural layer located below it but also fills the upper through-hole 177W. Subsequently, a patterning process is performed on the upper conductive filling thin film layer 184W to form a columnar upper conductive filling portion filled in each upper through-hole 177W.

[0111] In some embodiments of this disclosure, after forming the write transistor 11W, step S212 may further include steps S2131, S2132, and S2133.

[0112] In step S2131, a filled partition insulating portion 178W is formed on the upper surface of the upper partition insulating film layer 172W. As shown in Figure 32, the filled partition insulating portion 178W can cover the upper surface of the upper partition insulating film layer 172W that is not covered by the writing transistor 11W. Furthermore, when the first gate 110W itself fills the upper through-hole 177W, or when the manufactured columnar upper conductive filling portion fills the upper through-hole 177W, the upper surface of the filled partition insulating portion 178W formed therein can be flush with the upper surfaces of the first gate 110W and the columnar upper conductive filling portion. When the manufactured T-shaped upper conductive filling portion fills the upper through-hole 177W, the upper surface of the filled partition insulating portion 178W formed therein can be flush with the T-shaped upper conductive filling portion, thereby ensuring that the subsequent writing word lines are formed flush.

[0113] In step S2132, as shown in Figures 33 and 34, a plurality of writing word lines 179W are arranged side by side with spacing in the first horizontal direction X and extend in the second horizontal direction Y, and a first upper partition insulating section 180W is located between adjacent writing word lines 179W.

[0114] Here, the writing word line 179W may be connected to the first gate 110W of a plurality of writing transistors 11W arranged in a row with spacing in the second horizontal direction Y. Here, when the first gate 110W itself fills the upper through-hole 177W, the writing word line 179W directly contacts the first gate 110W, realizing a direct connection between the two. When the upper through-hole 177W is filled by the T-shaped upper conductive filling portion, the writing word line 179W directly contacts the upper surface of the T-shaped upper conductive filling portion, realizing an indirect connection with the first gate 110W via the T-shaped upper conductive filling portion. When the upper through-hole 177W is filled by the columnar upper conductive filling portion, the writing word line 179W may simultaneously directly contact the first gate 110W and the upper surface of the columnar upper conductive filling portion, realizing a connection between the three.

[0115] In step S2133, as shown in Figure 35, a cap insulating layer 19 is formed that covers the entire surface. The cap insulating layer 19 covers the writing word line 179W and the filling partition insulating portion 178W, and the upper surface of the cap insulating layer 19 is a plane that is parallel or substantially parallel to the semiconductor substrate 10.

[0116] In this embodiment, adjacent writing word lines 179W are insulated from each other by a first upper partition insulating section 180W. Specifically, the writing word lines 179W may be formed before the first upper partition insulating section 180W, but are not limited to this. The first upper partition insulating section 180W may be formed first, and then multiple writing word lines 179W may be formed.

[0117] In some embodiments, when the writing word line 179W is formed first, and then the first upper partition insulating part 180W is formed, the first upper partition insulating part 180W may be integrally molded with the cap insulating layer 19, but is not limited to this, and the first upper partition insulating part 180W may be manufactured separately from the cap insulating layer 19, that is, the first upper partition insulating part 180W may be formed first, and then the cap insulating layer 19 may be manufactured.

[0118] In other embodiments, when the first upper partition insulation portion 180W is formed first, and then the writing word line 179W is formed, the first upper partition insulation portion 180W may be integrally molded with the filling partition insulation portion 178W, but is not limited to this, and the first upper partition insulation portion 180W may be manufactured separately from the filling partition insulation portion 178W, that is, the filling partition insulation portion 178W may be formed first, and then the first upper partition insulation portion 180W may be manufactured.

[0119] Furthermore, the writing word line 179W in this disclosure is not limited to being formed after the first gate 110W or the upper conductive filling portion 115W, and may be integrally molded with the first gate 110W or the upper conductive filling portion 115W, or it may be determined according to the specific circumstances, and such details are omitted here. Furthermore, in this disclosure, the writing bit line 175W is not limited to extending in the first horizontal direction X and the writing word line 179W extends in the second horizontal direction Y, and if the extending directions of the writing word line 179W and the writing bit line 175W intersect, the writing bit line 175W may extend in the second horizontal direction Y and the writing word line 179W may extend in the first horizontal direction X.

[0120] In step S214, after forming the writing transistor 11W, the second portion 121 of the gas passage 12 is formed, and the orthogonal projection of the second portion 121 onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the lower through-hole 149R and the upper through-hole 177W onto the semiconductor substrate 10, as shown in Figures 36 and 37, the second portion 121 penetrates at least the upper partition insulating film layer 172W, the upper sacrificial insulating film layer 171W, the intermediate partition insulating film layer 16 and the lower partition insulating film layer 142R, exposing the lower sacrificial insulating film layer 141R, and here the gas passage The second portion 121 of the gas passage 12 may extend along the vertical Z direction into the interior of the lower sacrificial insulating film layer 141R, thereby reducing the difficulty of the process and increasing the area of ​​the lower sacrificial insulating film layer 141R that is exposed, thereby accelerating the rate at which the subsequent lower sacrificial insulating film layer 141R is etched and removed. However, the second portion 121 of the gas passage 12 may extend just to the top surface of the lower sacrificial insulating film layer 141R, or it may penetrate the lower sacrificial insulating film layer 141R.

[0121] In some embodiments, as shown in Figure 36, the second portion 121 of the gas passage 12 may be manufactured after the cap insulating layer 19 is formed. In this case, the "upper surface of the memory cell" in the aforementioned statement "the second portion 121 extends vertically upward to the upper surface of the memory cell" refers to the upper surface of the cap insulating layer 19. That is, after forming the cap insulating layer 19, hole etching is performed vertically downward from the upper surface of the cap insulating layer 19 until etching is made to the lower sacrificial insulating film layer 141R. By manufacturing the second portion 121 of the gas passage 12 after the completion of the formation of the cap insulating layer 19, the write transistor 11W and the write word line 179W can be protected using the cap insulating layer 19, thereby avoiding damage to the write transistor 11W and the write word line 179W during subsequent hole etching.

[0122] In some other embodiments, the second portion 121 of the gas passage 12 may be manufactured after the writing transistor 11W (or upper conductive filling portion 115W) is formed and before the writing word line 179W is formed, in which case protection of the writing transistor 11W is achieved, and as shown in Figure 37, after the writing transistor 11W (or upper conductive filling portion 115W) is formed, a first upper partition insulating thin film layer 180 covering the entire surface may be formed, in which case the "upper surface of the memory cell" in the above-mentioned "the second portion 121 extends vertically upward to the upper surface of the memory cell" is the first upper part Pointing to the upper surface of the cutting insulating thin film layer 180, then hole etching is performed vertically downward from the upper surface of the first upper partition insulating thin film layer 180 until etching is performed to the lower sacrificial insulating film layer 141R. After that, the subsequent steps are performed, where the formation of the first oxidation channel 1120W and the second oxidation channel 1120R is completed and the second portion 121 of the gas passage 12 is partially or completely filled with insulating material. Then, the first upper partition insulating thin film layer 180 is etched to form the first upper partition insulating portion 180W, and subsequently, the writing word line 179W and the cap insulating layer 19 are formed.

[0123] In some embodiments, as shown in Figures 36 and 37, if the lower laminated film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, and the upper laminated film layer includes a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, the second portion 121 of the gas passage 12 may further penetrate the first upper interlayer dielectric layer 173W, the second upper interlayer dielectric layer 174W, and the first lower interlayer dielectric layer 143R.

[0124] In some embodiments, as shown in Figure 38, the orthogonal projection of the second portion 121 of the gas passage 12 onto the semiconductor substrate 10 does not overlap with the orthogonal projections of the write word line 179W, write bit line 175W, second down signal line 145R, and second up signal line 147R onto the semiconductor substrate 10, thereby ensuring the performance of the write word line 179W, write bit line 175W, second down signal line 145R, and second up signal line 147R. Here, as shown in Figure 36, the orthogonal projection of the second portion 121 of the gas passage 12 onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the writing word line 179W, writing bit line 175W, second down signal line 145R, and second up signal line 147R onto the semiconductor substrate 10. Therefore, the second portion 121 of the gas passage 12 may penetrate not only the above-mentioned film layer, but also the first upper partition insulating portion 180W, the first lower partition insulating portion 176W, and the second upper partition insulating portion 148R.

[0125] In some embodiments, as shown in Figure 38, there may be multiple second portions 121 of the gas passage 12, and the outer periphery of each memory cell C may be surrounded by multiple second portions 121, which not only increases the etching rate of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R but also ensures etching uniformity.

[0126] In step S216, as shown in Figure 39, an etching agent is introduced into the second portion 121 to remove the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, thereby forming an upper first portion 120W that surrounds the first region to be oxidized and a lower first portion 120R that surrounds the second region to be oxidized.

[0127] In this process, during the removal of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R using an etching agent, the first lower interlayer dielectric layer 143R, the second lower interlayer dielectric layer 144R, the first upper interlayer dielectric layer 173W, and the second upper interlayer dielectric layer 174W are retained, meaning they are either not etched by the etching agent or are etched very little.

[0128] For example, the etching agent in this embodiment may be a liquid, but is not limited to a liquid, and may also be a gas. Here, if the insulating material of the interlayer dielectric layer, partition insulating layer, and partition insulating portion mentioned above is silicon oxide, and the insulating material of the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R is silicon nitride, silicon oxynitride, or silicon carbonitride, this embodiment may completely etch the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R using chlorine gas or liquid phosphoric acid, but is not limited to a liquid. In this embodiment, the etching agent may etch the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R while ensuring that the effect on the interlayer dielectric layer, partition insulating layer, and partition insulating portion mentioned above is small or nonexistent, and if the interlayer dielectric layer, partition insulating layer, and partition insulating portion mentioned above are retained, the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R may be etched using other etching agents.

[0129] [Embodiment 2] In the embodiments of this disclosure, the first oxide channel 1120W of the write transistor 11W and the second oxide channel 1120R of the read transistor 11R may be manufactured separately. Specifically, the second oxide channel 1120R of the read transistor 11R may be formed first, followed by the first oxide channel 1120W of the write transistor 11W. In this way, the quality of the first oxide channel 1120W and the second oxide channel 1120R can be ensured.

[0130] Here, if the first oxide channel 1120W of the write transistor 11W and the second oxide channel 1120R of the read transistor 11R are formed by manufacturing them separately, the gas passage 12 described above must include two passages that are manufactured one after the other. That is, the gas passage 12 can include the first gas passage 12W shown in Figure 41 and the second gas passage 12R shown in Figure 40, the first gas passage 12W and the second gas passage 12R are manufactured separately, and the second gas passage 12R is manufactured before the first gas passage 12W.

[0131] Here, as shown in Figure 40, the second gas passage 12R includes a first portion 120 surrounding the region to be oxidized second, and a second portion 121 that communicates with the first portion 120 of the second gas passage 12 and extends vertically upward to the top surface of the read transistor 11R. As shown in Figure 41, the first gas passage 12W includes a first portion 120 surrounding the region to be oxidized first, and a second portion 121 that communicates with the first portion 120 of the first gas passage 12W and extends vertically upward to the top surface of the memory cell.

[0132] Based on this, the manufacturing method of this embodiment includes the following steps, as shown in Figure 42, first the second of the read transistor 11R valid By oxidizing the region of the semiconductor channel to be secondly oxidized, a second oxidation channel 1120R is formed. After forming the second oxidation channel 1120R, the second gas passage 12R is filled with insulating material to form a second filler 13R. As shown in Figure 43, the upper surface of the second filler 13R is flush with the upper surface of the second gas passage 12R, thereby ensuring the flatness of the upper surface of the structural layer, which is advantageous for the subsequent manufacturing of the structural layer. As shown in Figure 44, the first valid By oxidizing the first region of the semiconductor channel to be oxidized, a first oxidation channel 1120W is formed. As shown in Figure 45, after forming the first oxidation channel 1120W, the first gas passage 12W is filled with an insulating material to form a first filler 13. The upper surface of the first filler 13 is flush with the upper surface of the first gas passage 12W, thereby ensuring the flatness of the upper surface of the memory array structure, which is advantageous for the manufacturing of subsequent structural layers.

[0133] In specific embodiments of this disclosure, the method for manufacturing the first gas passage 12W may include steps S300, S302, S304, S306, S308, and S310.

[0134] Here, step S300 can refer to the explanation of step S200 above, step S302 can refer to the explanation of step S202 above, and step S304 can refer to the explanation of step S204 above. Detailed explanations of the contents of steps S300, S302, and S304 are omitted here.

[0135] In step S306, an intermediate partition insulating film layer 16 is formed on the lower laminated film layer. The intermediate partition insulating film layer 16 covers at least the area on the upper surface of the lower partition insulating film layer 142R that is not covered by the read transistor 11R. Here, the intermediate partition insulating film layer 16 formed in step S306 protects the read transistor 11R by completely covering it. Furthermore, if a lower conductive filling portion 115R is formed on the read transistor 11, the intermediate partition insulating film layer formed in step S306 provides insulation. The edge film layer 16 may completely cover the read transistor 11 and the lower conductive fill portion 115R, thereby protecting both the read transistor 11 and the lower conductive fill portion 115R simultaneously, but is not limited to this. At least a portion of the second gate 110R or the lower conductive fill portion 115R does not need to be shielded by the intermediate partition insulating film layer 16, thereby facilitating direct connection, indirect connection, or integral molding of the subsequent first lower electrode 114W and the second gate 110R, and is specifically determined according to the actual circumstances.

[0136] In step S308, the second portion 121 of the second gas passage 12R is formed, and as shown in Figure 46, the orthogonal projections of the second portion 121 of the second gas passage 12R and the lower through-hole 149R onto the semiconductor substrate 10 do not overlap, and the second portion 121 of the second gas passage 12R penetrates at least the intermediate partition insulating film layer 16 and the lower partition insulating film layer 142R, exposing the lower sacrificial insulating film layer 141R.

[0137] Here, the orthogonal projection of the second portion 121 of the second gas passage 12R onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the read word line and read bit line onto the semiconductor substrate 10, thereby ensuring the performance of the read word line and read bit line. Since the orthogonal projection of the second portion 121 of the second gas passage 12R onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the read word line and read bit line onto the semiconductor substrate 10, the second portion 121 of the second gas passage 12R may, in addition to penetrating the film layer described above, also further penetrate the second upper partition insulating portion 148R. Furthermore, if the lower laminated film layer includes a first interlayer dielectric layer 143R and a second interlayer dielectric layer 144R, the second portion 121 of the second gas passage 12R may further penetrate the first interlayer dielectric layer 143R.

[0138] As shown in Figure 41, the second portion 121 of the second gas passage 12R extends vertically upward to the upper surface of the readout transistor 11R. Here, "upper surface of the readout transistor 11R" may be understood as the upper surface of the structural layer on which the readout transistor 11R is located. Here, the structural layer on which the readout transistor 11R is located includes a lower multilayer film layer and an intermediate partition insulating film layer 16 located above the lower multilayer film layer. Therefore, "upper surface of the readout transistor 11R" may be understood as the upper surface of the intermediate partition insulating film layer 16. In other words, the second portion 121 of the second gas passage 12R may extend vertically downward from the upper surface of the intermediate partition insulating film layer 16 to the lower sacrificial insulating film layer 141R.

[0139] In some embodiments, the second portion 121 of the second gas passage 12R can extend along the vertical Z direction into the interior of the lower sacrificial insulating film layer 141R, thereby reducing the difficulty of the process and increasing the area of ​​the lower sacrificial insulating film layer 141R that is exposed, thereby accelerating the rate at which the subsequent lower sacrificial insulating film layer 141R is etched and removed. However, as shown in Figure 46, the second portion 121 of the second gas passage 12R may extend just to the top surface of the lower sacrificial insulating film layer 141R, or it may penetrate the lower sacrificial insulating film layer 141R.

[0140] In some embodiments, there may be multiple second portions 121 of the second gas passage 12R, and the outer periphery of each readout transistor 11R may be surrounded by multiple second portions 121 of the second gas passage 12R. In this way, not only can the etching rate of the lower sacrificial insulating film layer 141R be increased, but etching uniformity can also be ensured.

[0141] In step S310, as shown in Figure 42, the lower sacrificial insulating film layer 141R is removed by introducing an etching agent into the second portion 121 of the second gas passage 12R, thereby forming the first portion 120 of the second gas passage 12R, which is provided to surround the region to be oxidized. Regarding the limitations of the etching agent, please refer to the previously mentioned description and will not be explained here.

[0142] Here, after step S310 is performed, an oxidizing gas is introduced through the second portion 121 of the second gas passage 12R, and the oxidizing gas acts on the region to be oxidized second through the first portion 120 of the second gas passage 12R, thereby oxidizing the region to be oxidized second and forming a second oxidation channel 1120R. After the formation of the second oxidation channel 1120R, the second gas passage 12R is further filled with insulating material to form a second filler 13R. As shown in Figure 43, the upper surface of this second filler 13R is flush with the upper surface of the intermediate partition insulating film layer 16, thereby facilitating the subsequent formation of the writing transistor 11W and the structural layer in which it is located. In some embodiments, when the second gas passage 12R is filled with insulating material, a complete filling method can be adopted, that is, as shown in Figure 43, the formed second filler 13R completely fills the first portion 120 and the second portion 121 of the second gas passage 12R, thereby ensuring structural stability. However, the invention is not limited to this, and in other embodiments, as shown in Figure 47, a portion of the second gas passage 12R may be filled with insulating material. That is, the formed second filler 13R may partially or completely fill the second portion 121 of the second gas passage 12R. For example, the second filler 13R is formed within the second portion 121 of the second gas passage 12R by filling the second portion 121 of the second gas passage 12R with insulating material in a rapid sealing manner.

[0143] Furthermore, when the second packing material 13R partially or completely fills the second portion 121 of the second gas passage 12R, the region of the second gas passage 12R other than the region filled by the second packing material 13R is a void region. Specifically, as shown in Figure 47, at least the first portion 120 of the second gas passage 12R may be a void region not filled by the second packing material 13R. This reduces the parasitic capacitance between the second upper electrode 113R and the second lower electrode 114R of the readout transistor 11R.

[0144] In specific embodiments of this disclosure, the method for manufacturing the first gas passage 12W may include steps S400, S402, S404, S406, and S408.

[0145] Here, regarding step S400, you can refer to the explanation of step S208 above; regarding step S402, you can refer to the explanation of step S210 above; regarding step S404, you can refer to the explanation of step S212 above; therefore, the contents of steps S400, S402, and S404 will not be explained in detail here.

[0146] In step S406, after forming the writing transistor 11W, the second portion 121 of the first gas passage 12W is formed, and as shown in Figure 48, the orthogonal projections of the second portion 121 of the first gas passage 12W and the upper through-hole 177W onto the semiconductor substrate 10 do not overlap, and the second portion 121 of the first gas passage 12W penetrates at least the upper partition insulating film layer 172W, exposing the upper sacrificial insulating film layer 171W.

[0147] Here, the second portion 121 of the first gas passage 12W can extend along the vertical direction Z into the interior of the upper sacrificial insulating film layer 171W, thereby reducing the difficulty of the process and increasing the area of ​​the upper sacrificial insulating film layer 171W that is exposed, thereby accelerating the rate at which the subsequent upper sacrificial insulating film layer 171W is etched and removed. However, it is not limited to this, and as shown in Figure 48, the second portion 121 of the first gas passage 12W may extend just to the top surface of the upper sacrificial insulating film, or it may penetrate the upper sacrificial insulating film.

[0148] Furthermore, multiple second portions 121 of the first gas passage 12W may be provided, and the outer periphery of each writing transistor 11W may be surrounded by multiple second portions 121 of the first gas passage 12W. This not only increases the etching speed of the upper sacrificial insulating film layer 171W but also ensures etching uniformity.

[0149] In some embodiments, the method for manufacturing the first gas passage 12W may further include steps S4051, S4052, and S4053, where step S4051 may refer to the description of step S2131, step S4052 may refer to the description of step S2132, and step S4053 may refer to the description of step S2133. The contents of steps S4051, S4052, and S4053 will not be described in detail here.

[0150] Here, the orthogonal projection of the second portion 121 of the first gas passage 12W onto the semiconductor substrate 10 does not have to overlap with the orthogonal projection of the writing word line 179W and the writing bit line 175W onto the semiconductor substrate 10, thereby guaranteeing the performance of the writing word line 179W and the writing bit line 175W, and the orthogonal projection of the second portion 121 of the first gas passage 12W onto the semiconductor substrate 10 does not have to overlap with the orthogonal projection of the writing word line 179W and the writing bit line 175W. Since it does not overlap with the orthogonal projection onto the conductive substrate 10, the second portion 121 of the first gas passage 12W may penetrate not only the above-mentioned film layer but also the first upper partition insulating portion 180W and the first lower partition insulating portion 176W. Furthermore, if the upper laminated film layer includes a first interlayer dielectric layer 173W and a second interlayer dielectric layer 174W, the second portion 121 of the first gas passage 12W may further penetrate the first interlayer dielectric layer 173W. Furthermore, the second portion 121 of the first gas passage 12W extends vertically upward to the top surface of the memory cell, where "top surface of the memory cell" may be understood as the top surface of the cap insulating layer 19. That is, after the cap insulating layer 19 is formed, as shown in Figure 49, hole etching is performed vertically downward from the top surface of the cap insulating layer 19 until etching is performed to the upper sacrificial insulating film layer 171W. By manufacturing the second portion 121 of the first gas passage 12W after the cap insulating layer 19 is formed, the writing transistor 11W and the writing word line 179W can be protected using the cap insulating layer 19, thereby avoiding damage to the writing transistor 11W and the writing word line 179W when hole etching is performed later. However, the second portion 121 of the first gas passage 12W may be manufactured after the writing transistor 11W (or upper conductive filling portion 115W) is formed and before the writing word line 179W is formed, in which case protection of the writing transistor 11W is achieved, and after the writing transistor 11W (or upper conductive filling portion 115W) is formed, a first upper partition insulating thin film layer 180 covering the entire surface may be formed, in which case the above-mentioned "upper surface of memory cell" refers to the first upper partition insulating thin film layer 180 Referring to the upper surface, as shown in Figure 48, hole etching is performed vertically downward from the upper surface of the first upper partition insulating thin film layer 180 until etching is performed to the upper sacrificial insulating film layer 171W. Then, the subsequent steps are performed, at which point the formation of the first oxidation channel 1120W is completed and the first gas passage 12W is filled with insulating material. After that, the first upper partition insulating thin film layer 180 is etched to form the first upper partition insulating section 180W, and then the writing word line 179W and the cap insulating layer 19 are formed.

[0151] In step S408, the upper sacrificial insulating film layer 171W is removed by introducing an etching agent into the second portion 121 of the first gas passage 12W, thereby forming the first portion 120 of the first gas passage 12W that surrounds the region to be oxidized, as shown in Figure 50. Here, the limitations of the etching agent can be found in the previously mentioned description and are omitted here.

[0152] Here, after step S408 is performed, an oxidizing gas is introduced through the second portion 121 of the first gas passage 12W, and the oxidizing gas acts on the region to be oxidized through the first portion 120 of the first gas passage 12W, thereby oxidizing the region to be oxidized and forming the first oxidation channel 1120W. After the formation of the first oxidation channel 1120W, the first gas passage 12W is further filled with insulating material to form the first filler 13W, and as shown in Figure 51, the upper surface of this first filler 13W may be flush with the upper surface of the memory cell to facilitate the formation of subsequent structural layers. In some embodiments, when the first gas passage 12W is filled with insulating material, a complete filling method can be adopted, as shown in Figure 45, that is, the formed first filler 13W can completely fill the first portion 120 and the second portion 121 of the first gas passage 12W, ensuring structural stability. However, the invention is not limited to this, and in other embodiments, a portion of the first gas passage 12W may be filled with insulating material. That is, as shown in Figure 51, the formed first filler 13W may partially or completely fill the second portion 121 of the first gas passage 12W. For example, the first filler 13W may be formed within the second portion 121 of the first gas passage 12W by filling the second portion 121 of the first gas passage 12W with insulating material using a rapid sealing method.

[0153] Furthermore, when the first filler 13W partially or completely fills the second portion 121 of the first gas passage 12W, the region of the first gas passage 12W other than the region filled by the first filler 13W is a void region. Specifically, as shown in Figure 51, at least the first portion 120 of the first gas passage 12W is a void region not filled by the first filler 13W. This reduces the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W of the writing transistor 11W.

[0154] Embodiments of the present disclosure provide a memory comprising a semiconductor substrate 10 and at least one memory cell. The memory cell is formed on the semiconductor substrate 10 and includes at least one transistor 11, each transistor 11 comprising a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113 and a lower electrode 114, wherein the semiconductor channel 112 surrounds at least the outer periphery of the gate 110, the gate dielectric 111 is formed between the semiconductor channel 112 and the gate 110, the upper electrode 113 and the lower electrode 114 are both located outside the semiconductor channel 112 and in contact with the semiconductor channel 112, the lower electrode 114 is provided insulated below the upper electrode 113, one of the upper electrode 113 and the lower electrode 114 is a source and the other is a drain.

[0155] Here, in the memory cell, as shown in Figure 8, Figure 9, or Figure 10, at least one transistor 11 valid A portion of the semiconductor channel is oxidized to form an oxidized channel by oxidation treatment. valid The semiconductor channel is the portion located between the upper electrode 113 and the lower electrode 114 in the semiconductor channel 112, and neither the upper electrode 113 nor the lower electrode 114 is in contact with the oxide channel.

[0156] The memory of the embodiment of this disclosure may be manufactured by the manufacturing method described in any of the embodiments described above, and is not limited to this, although it will not be described again here. The memory of this embodiment may also be formed by other manufacturing methods.

[0157] In the embodiments of this disclosure, as shown in Figures 8, 9, or 10, there are multiple memory cells, which are formed by arranging a memory array structure in a horizontal plane, and each memory cell includes two transistors 11, the two transistors 11 being a read transistor 11R and a write transistor 11W, respectively. The write transistor 11W includes a first gate 110W, a first gate dielectric 111W, a first semiconductor channel 112W, a first upper electrode 113W, and a first lower electrode 114W, the read transistor 11R includes a second gate 110R, a second gate dielectric 111R, a second semiconductor channel 112R, a second upper electrode 113R, and a second lower electrode 114R, the write transistor 11W is located above the read transistor 11R, and the first lower electrode 114W and the second gate 110R are electrically connected, and here, at least one of the write transistor 11W and the read transistor 11R valid A portion of the semiconductor channel 112 is formed into an oxide channel 1120 by oxidation treatment.

[0158] In a memory array structure, as shown in Figure 38, multiple memory cells are arranged in an array along a first horizontal direction X and a second horizontal direction Y, and the first horizontal direction X and the second horizontal direction Y intersect. For example, the first horizontal direction X and the second horizontal direction Y are perpendicular or nearly perpendicular.

[0159] As shown in Figures 26, 27, 33, 34, and 38, the memory further includes a second down signal line 145R, a second up signal line 147R, a write word line 179W, and a write bit line 175W, wherein the second down signal line 145R extends in the second horizontal direction Y, and multiple second down signal lines 145R are provided and arranged in a row with spacing in the first horizontal direction X, and each second down signal line 145R is arranged in a row in the second horizontal direction Y. The second up signal line 147R is connected to the second lower electrode 114 of each readout transistor 11R, extends in the first horizontal direction X, and multiple second up signal lines 147R are provided and arranged in a row with spacing in the second horizontal direction Y, the second up signal line 147R is located on the side of the second down signal line 145R away from the semiconductor substrate 10, and each second up signal line 147R is connected to each readout transistor 11 in a row arranged in the first horizontal direction X. Connected to the second upper electrode 113 of R, one of the second up signal line 147R and the second down signal line 145R is a read word line, the other is a read bit line, the write bit line 175W is formed on the side of the second up signal line 147R away from the semiconductor substrate 10, and the write word line 179W is formed on the side of the write bit line 175W away from the semiconductor substrate 10, where one of the write word line 179W and the write bit line 175W One of the bit lines extends in the first horizontal direction X and is provided in multiples at intervals in the second horizontal direction Y, and the other extends in the second horizontal direction Y and is provided in multiples at intervals in the first horizontal direction X. Each bit line 175W is connected to the first upper electrode 113 of each writing transistor 11W arranged in a row in the direction of its extension, and each word line 179W is connected to the first gate 110W of each writing transistor 11W arranged in a row in the direction of its extension.

[0160] In some embodiments, as shown in Figures 14 and 51, the first writing transistor 11W valid A portion of the semiconductor channel 112 is formed into a first oxide channel 1120W by oxidation treatment, and a first void region is formed between the first upper electrode 113 and the first lower electrode 114, with the first void region surrounding the first oxide channel 1120W.

[0161] Furthermore, as shown in Figures 14 and 51, a first interlayer dielectric layer 173W is formed between the first upper electrode 113 and the first void region, and a second interlayer dielectric layer 174W is formed between the first lower electrode 114 and the first void region. Both the first interlayer dielectric layer 173W and the second interlayer dielectric layer 174W are first valid It is provided so as to surround the semiconductor channel 112 and does not come into contact with the first oxide channel 1120W.

[0162] In some other embodiments, as shown in Figures 9, 10, 13, or 45, the first write transistor 11W valid A portion of the semiconductor channel 112 is formed into a first oxide channel 1120W by oxidation treatment, and a first insulating layer is formed between the first upper electrode 113 and the first lower electrode 114. The first insulating layer is provided so as to surround the first oxide channel 1120W and is in contact with the lower surface of the first upper electrode 113 and the upper surface of the first lower electrode 114 without any gaps.

[0163] For example, the first insulating layer may be a composite film layer including a first interlayer dielectric layer 173W, a second interlayer dielectric layer 174W, and a first filler 13W.

[0164] In some embodiments, as shown in Figure 14 or Figures 47 to 51, the second reading transistor 11R valid A portion of the semiconductor channel 112 is formed into a second oxide channel 1120R by oxidation treatment, and a second void region is formed between the second upper electrode 113 and the second lower electrode 114, with the second void region surrounding the second oxide channel 1120R.

[0165] Furthermore, a first interlayer dielectric layer 143R is formed between the second upper electrode 113 and the second void region, and a second interlayer dielectric layer 144R is formed between the second lower electrode 114 and the second void region. Both the first interlayer dielectric layer 143R and the second interlayer dielectric layer 144R are second valid It is provided so as to surround the semiconductor channel 112 and does not come into contact with the second oxide channel 1120R.

[0166] In other embodiments, as shown in Figures 8, 10, 13, or 44, the second reading transistor 11R valid A portion of the semiconductor channel 112 is formed into a second oxide channel 1120R by oxidation treatment, and a second insulating layer is formed between the second upper electrode 113 and the second lower electrode 114. The second insulating layer is provided so as to surround the second oxide channel 1120R and is in close contact with the lower surface of the second upper electrode 113 and the upper surface of the second lower electrode 114 without any gaps.

[0167] For example, the second insulating layer may be a composite film layer including the first interlayer dielectric layer 143R, the second interlayer dielectric layer 144R, and the second filler 13R.

[0168] Furthermore, terms such as "first," "second," etc., are solely for the purpose of describing the objective and should not be understood as indicating or implying relative importance, nor as implicitly indicating the number of technical features being referred to. Accordingly, features limited to "first" and "second" may explicitly or implicitly include one or more such features. In the description of this application, "multiple" means two or more unless otherwise specifically limited.

[0169] In this specification, any description referring to terms such as “several examples” or “exemplary” means that the specific features, structures, materials, or characteristics described with reference to such examples are included in at least one example of this application. In this specification, the general expressions of the above terms do not necessarily refer to the same example or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in an appropriate manner in any one or more examples. Also, a person skilled in the art may combine different examples and features described herein, provided they do not conflict with each other.

[0170] Although embodiments of the present application have been described above, these embodiments are illustrative and should not be understood as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and alterations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made based on the claims and specification of the present application should fall within the scope of the present application. [Explanation of Symbols]

[0171] 10. Semiconductor substrates, 11. Transistor, 110. Gate, 111. Gate dielectric, 112. Semiconductor channel, 1120. Oxide channel, 113. Upper electrode, 114. Lower electrode, 11W, writing transistor; 110W, first gate; 111W, first gate dielectric; 112W, first semiconductor channel; 1120W, first oxide channel; 113W, first upper electrode; 114W, first lower electrode; 115W, upper conductive filler section. 11R, Readout transistor, 110R, Second gate, 111R, Second gate dielectric, 112R, Second semiconductor channel, 1120R, Second oxide channel, 113R, Second upper electrode, 114R, Second lower electrode, 115R, Lower conductive filler section, 12, gas passage, 12W, first gas passage, 12R, second gas passage, 120, first section, 120W, upper first section, 120R, lower first section, 121, second section, 13, Filler, 13W, First Filler, 13R, Second Filler, 141R, lower sacrificial insulating film layer, 142R, lower partition insulating film layer, 143R, first interlayer dielectric layer, 144R, second interlayer dielectric layer, 145R, second down signal line, 146R, second lower partition insulation section, 147R, second up signal line, 148R, second upper partition insulation section, 149R, lower through-hole, 151R, lower semiconductor thin film layer, 152R, lower gate dielectric thin film layer, 153R, lower gate thin film layer, 154R, lower conductive filler thin film layer, 16, intermediate partition insulating film layer, 160, intermediate via, 171W, upper sacrificial insulating film layer, 172W, upper partition insulating film layer, 173W, first upper interlayer dielectric layer, 174W, second upper interlayer dielectric layer, 175W, bit line for writing, 176W, first lower partition insulating part, 177W, upper through-hole, 178W, filling partition insulating part, 179W, word line for writing, 180, First upper partition insulating thin film layer, 180W, First upper partition insulating part, 181W, upper semiconductor thin film layer, 182W, upper gate dielectric thin film layer, 183W, upper gate thin film layer, 184W, upper conductive filler thin film layer, 19. Cap insulating layer, C: Memory cell, X: First horizontal direction, Y: Second horizontal direction, Z: Vertical direction

Claims

1. The steps include providing a semiconductor substrate and The semiconductor substrate comprises the step of manufacturing at least one memory cell, wherein the memory cell includes at least one transistor, each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounds at least the outer periphery of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is provided insulated below the upper electrode, one of the upper electrode and the lower electrode is a source and the other is a drain. The step includes oxidizing a region to be oxidized in the active semiconductor channel of at least one transistor of the memory cell, thereby forming the region to be oxidized in the oxidation channel, wherein the region to be oxidized is at least a portion of the active semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxidation channel, and the active semiconductor channel is the portion located between the upper electrode and the lower electrode in the semiconductor channel. A method for manufacturing memory characterized by the following:

2. The process further includes the step of oxidizing the region to be oxidized, and then heat-treating the oxidized region, or The process further includes oxidizing the region to be oxidized and simultaneously heat-treating the region to be oxidized. A method for manufacturing a memory according to claim 1, characterized in that it is described above.

3. Before oxidizing the region to be oxidized, the method for manufacturing the memory further includes the step of manufacturing a gas passage, the gas passage comprising a first portion circumferentially provided on the outer periphery of the region to be oxidized and a second portion communicating with the first portion and extending vertically upward, thereby enabling an oxidizing gas introduced from above the second portion to act upon the region to be oxidized. A method for manufacturing a memory according to claim 1 or 2, characterized in that it is as described above.

4. After forming the oxidation channel, the method for manufacturing the memory further includes the step of filling the gas passage with an insulating material. The method for manufacturing a memory according to claim 3, characterized in that it is as described above.

5. The step of filling the gas passage with insulating material includes the step of forming a filler body within the gas passage by completely filling the gas passage with insulating material, wherein the upper surface of the filler body is flush with the upper surface of the gas passage. The method for manufacturing a memory according to claim 4.

6. The step of filling the gas passage with an insulating material includes the step of forming a filler within the second portion of the gas passage by partially or completely filling the second portion of the gas passage with an insulating material, wherein the upper surface of the filler is flush with the upper surface of the gas passage, and the region of the gas passage other than the region filled by the filler is a void region. The method for manufacturing a memory according to claim 4.

7. The number of memory cells is multiple, and they are formed by arranging a memory array structure on a horizontal plane. Each memory cell includes two transistors, and these two transistors are a read transistor and a write transistor, respectively. The writing transistor includes a first gate, a first gate dielectric, a first semiconductor channel, a first upper electrode, and a first lower electrode. The readout transistor includes a second gate, a second gate dielectric, a second semiconductor channel, a second upper electrode, and a second lower electrode. The write transistor is located above the read transistor, and the first lower electrode and the second gate are electrically connected. The method for manufacturing the memory includes the step of oxidizing a region to be oxidized in at least one of the writing transistor and the reading transistor's active semiconductor channel, The method for manufacturing a memory according to claim 4.

8. The method for manufacturing the memory includes the step of oxidizing a region of the effective semiconductor channel of one of the write transistor and the read transistor to form an oxidized channel, The gas passage is manufactured after the manufacturing of the transistor corresponding to the region to be oxidized is completed. The method for manufacturing a memory according to feature 7.

9. A step of oxidizing a first region to be oxidized, comprising the step of oxidizing a first region to be oxidized in a first effective semiconductor channel in the writing transistor so as to form the first region to be oxidized in a first oxidation channel, A step of oxidizing a region to be secondly oxidized, comprising the step of oxidizing a region to be secondly oxidized in a second effective semiconductor channel in the readout transistor so as to form the region to be secondly oxidized in a second oxidation channel, The method for manufacturing a memory according to feature 7.

10. The first oxidation channel and the second oxidation channel are formed simultaneously, and the gas passage is manufactured after the manufacturing of the writing transistor is completed. The first portion of the gas passage includes an upper first portion surrounding the outer periphery of the first region to be oxidized and a lower first portion surrounding the outer periphery of the second region to be oxidized, with the upper first portion and the lower first portion spaced apart vertically, and the second portion extending vertically upward to the upper surface of the memory cell, connecting the upper first portion and the lower first portion, thereby enabling oxidation treatment by introducing an oxidizing gas from above the second portion to act simultaneously on the first region to be oxidized and the second region to be oxidized. The method for manufacturing a memory according to feature 9.

11. The method for manufacturing the aforementioned gas passage is: The semiconductor substrate is formed in the step of forming a lower multilayer film layer, wherein the lower multilayer film layer includes at least the second lower electrode, the lower sacrificial insulating film layer, the second upper electrode, and the lower partition insulating film layer, which are stacked in order along the vertical direction. A step in which a lower through-hole is formed that penetrates at least the lower partition insulating film layer, the second upper electrode, and the lower sacrificial insulating film layer, wherein the second lower electrode is exposed through the lower through-hole, The step of forming the readout transistor by forming the second semiconductor channel, the second gate dielectric, and the second gate in the lower through-hole, wherein the region of the second semiconductor channel to be oxidized is located in a position surrounded by the lower sacrificial insulating film layer, The lower laminated film layer is formed in the intermediate partition insulating film layer, wherein the intermediate partition insulating film layer covers at least the area on the upper surface of the lower partition insulating film layer that is not covered by the readout transistor, and the orthogonal projections of at least a portion of the second gate and the intermediate partition insulating film layer onto the semiconductor substrate do not overlap. A step of forming an upper laminated film layer, wherein the upper laminated film layer includes at least the first lower electrode, an upper sacrificial insulating film layer, a first upper electrode, and an upper partition insulating film layer stacked in order along the vertical direction, the first lower electrode being connected to the second gate, and the upper surface of the first lower electrode being flush with the upper surface of the intermediate partition insulating film layer, A step in which at least the upper partition insulating film layer, the first upper electrode, and the upper sacrificial insulating film layer are penetrated by an upper through-hole, wherein the first lower electrode is exposed through the upper through-hole, The writing transistor is formed by sequentially forming the first semiconductor channel, the first gate dielectric, and the first gate in the upper through-hole, wherein the region of the first semiconductor channel to be oxidized is located in a position surrounded by the upper sacrificial insulating film layer. A step of forming the second portion of the gas passage after forming the writing transistor, wherein the orthogonal projection of the second portion onto the semiconductor substrate does not overlap with the orthogonal projection of the lower through-hole and the upper through-hole onto the semiconductor substrate, and the second portion penetrates at least the upper partition insulating film layer, the upper sacrificial insulating film layer, the intermediate partition insulating film layer and the lower partition insulating film layer, and exposes the lower sacrificial insulating film layer. The process includes the step of introducing an etching agent into the second portion to remove the upper sacrificial insulating film layer and the lower sacrificial insulating film layer, thereby forming an upper first portion that surrounds the first region to be oxidized and a lower first portion that surrounds the second region to be oxidized. A method for manufacturing a memory according to claim 10.

12. The gas passage includes a first gas passage and a second gas passage, the first gas passage includes a first portion circumferentially provided on the first region to be oxidized and a second portion communicating with the first portion of the first gas passage and extending vertically upward to the upper surface of the memory cell, the second gas passage includes a first portion circumferentially provided on the second region to be oxidized and a second portion communicating with the first portion of the second gas passage and extending vertically upward to the upper surface of the read transistor, and the method for manufacturing the memory is, First, the region of the second active semiconductor channel of the readout transistor to be oxidized is oxidized to form a second oxidation channel, and after the formation of the second oxidation channel, the second gas passage is filled with an insulating material to form a second filler, wherein the upper surface of the second filler is flush with the upper surface of the second gas passage. Next, the process includes the step of oxidizing a first region of the first effective semiconductor channel of the writing transistor to form a first oxidation channel, and after forming the first oxidation channel, filling the first gas passage with an insulating material to form a first filler, wherein the upper surface of the first filler is flush with the upper surface of the first gas passage. The method for manufacturing a memory according to feature 9.

13. The second packing body completely fills the first and second portions of the second gas passage, Alternatively, the second packing material partially or completely fills the second portion of the second gas passage, and the region of the second gas passage other than the region filled by the second packing material is a void region. A method for manufacturing a memory according to claim 12, characterized in that it is a memory manufacturing method.

14. The first packing body completely fills the first and second portions of the first gas passage, Alternatively, the first filler partially or completely fills the second portion of the first gas passage, and the region of the first gas passage other than the region filled by the first filler is a void region. A method for manufacturing a memory according to claim 12, characterized in that it is a memory manufacturing method.

15. The method for manufacturing the first gas passage is as follows: The semiconductor substrate is formed in the step of forming a lower multilayer film layer, wherein the lower multilayer film layer includes at least the second lower electrode, the lower sacrificial insulating film layer, the second upper electrode, and the lower partition insulating film layer, which are sequentially stacked. A step in which a lower through-hole is formed that penetrates at least the lower partition insulating film layer, the second upper electrode, and the lower sacrificial insulating film layer, wherein the second lower electrode is exposed through the lower through-hole, The step of forming the readout transistor by forming the second semiconductor channel, the second gate dielectric, and the second gate in the lower through-hole, wherein the region of the second semiconductor channel to be oxidized is located in a position surrounded by the lower sacrificial insulating film layer, The lower laminated film layer is formed by an intermediate partition insulating film layer, wherein the intermediate partition insulating film layer covers at least the area on the upper surface of the lower partition insulating film layer that is not covered by the readout transistor, forming a second portion of the second gas passage, the orthogonal projections of the second portion of the second gas passage and the lower through-hole onto the semiconductor substrate do not overlap, and the second portion of the second gas passage penetrates at least the intermediate partition insulating film layer and the lower partition insulating film layer to expose the lower sacrificial insulating film layer. The process includes the step of introducing an etching agent into the second portion of the second gas passage to remove the lower sacrificial insulating film layer and to form the first portion of the second gas passage that surrounds the second region to be oxidized. A method for manufacturing a memory according to claim 12, characterized in that it is a memory manufacturing method.

16. The method for manufacturing the first gas passage is as follows: A step of forming an upper laminated film layer, wherein the upper laminated film layer includes at least the first lower electrode, the upper sacrificial insulating film layer, the first upper electrode, and the upper partition insulating film layer, the first lower electrode being connected to the second gate, and the upper surface of the first lower electrode being flush with the upper surface of the intermediate partition insulating film layer, A step in which at least the upper partition insulating film layer, the first upper electrode, and the upper sacrificial insulating film layer are penetrated by an upper through-hole, wherein the first lower electrode is exposed through the upper through-hole, The writing transistor is formed by sequentially forming the first semiconductor channel, the first gate dielectric, and the first gate in the upper through-hole, wherein the region of the first semiconductor channel to be oxidized is located in a position surrounded by the upper sacrificial insulating film layer. After forming the writing transistor, the second portion of the first gas passage is formed such that the orthogonal projections of the second portion of the first gas passage and the upper through-hole onto the semiconductor substrate do not overlap, and the second portion of the first gas passage penetrates at least the upper partition insulating film layer and is exposed to the upper sacrificial insulating film layer. The process includes the step of introducing an etching agent into the second portion of the first gas passage to remove the upper sacrificial insulating film layer and to form a first portion of the first gas passage that surrounds the first region to be oxidized. A method for manufacturing a memory according to claim 15, characterized in that it is a memory manufacturing method.

17. The lower laminated film layer further includes a first interlayer dielectric layer and a second interlayer dielectric layer made of a material different from that of the lower sacrificial insulating film layer, wherein the first interlayer dielectric layer is formed between the second upper electrode and the lower sacrificial insulating film layer and is provided to surround the second effective semiconductor channel, and the second interlayer dielectric layer is formed between the second lower electrode and the lower sacrificial insulating film layer and is provided to surround the second effective semiconductor channel. The upper laminated film layer further includes a first interlayer dielectric layer and a second interlayer dielectric layer made of a material different from that of the upper sacrificial insulating film layer, wherein the first interlayer dielectric layer is formed between the first upper electrode and the upper sacrificial insulating film layer and is provided to surround the first effective semiconductor channel, and the second interlayer dielectric layer is formed between the first lower electrode and the upper sacrificial insulating film layer and is provided to surround the first effective semiconductor channel. In the process of removing the upper sacrificial insulating film layer and the lower sacrificial insulating film layer with the etching agent, the first interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer, and the second interlayer dielectric layer are retained. The method for manufacturing a memory according to claim 11.

18. The lower laminated film layer further includes a first interlayer dielectric layer and a second interlayer dielectric layer made of a material different from that of the lower sacrificial insulating film layer, wherein the first interlayer dielectric layer is formed between the second upper electrode and the lower sacrificial insulating film layer and is provided to surround the second effective semiconductor channel, and the second interlayer dielectric layer is formed between the second lower electrode and the lower sacrificial insulating film layer and is provided to surround the second effective semiconductor channel. The upper laminated film layer further includes a first interlayer dielectric layer and a second interlayer dielectric layer made of a material different from that of the upper sacrificial insulating film layer, wherein the first interlayer dielectric layer is formed between the first upper electrode and the upper sacrificial insulating film layer and is provided to surround the first effective semiconductor channel, and the second interlayer dielectric layer is formed between the first lower electrode and the upper sacrificial insulating film layer and is provided to surround the first effective semiconductor channel. In the process of removing the upper sacrificial insulating film layer and the lower sacrificial insulating film layer with the etching agent, the first interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer, and the second interlayer dielectric layer are retained. The method for manufacturing a memory according to claim 16.

19. A memory comprising a semiconductor substrate and at least one memory cell, The at least one memory cell is formed on the semiconductor substrate, the memory cell includes at least one transistor, each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounds at least the outer periphery of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is provided insulated below the upper electrode, one of the upper electrode and the lower electrode is a source and the other is a drain. In the memory cell, at least one transistor has an oxidation channel, the oxidation channel is formed within a portion of the active semiconductor channel, the active semiconductor channel is the portion located between the upper electrode and the lower electrode in the semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxidation channel. A memory characterized by the following features.

20. The number of memory cells is multiple, and they are formed by arranging a memory array structure on a horizontal plane. Each memory cell includes two transistors, and these two transistors are a read transistor and a write transistor, respectively. The writing transistor includes a first gate, a first gate dielectric, a first semiconductor channel, a first upper electrode, and a first lower electrode. The readout transistor includes a second gate, a second gate dielectric, a second semiconductor channel, a second upper electrode, and a second lower electrode. The write transistor is located above the read transistor, and the first lower electrode and the second gate are electrically connected. A portion of the effective semiconductor channel of at least one of the write transistor and the read transistor is formed in the oxide channel. The memory according to feature 19.

21. In the memory array structure, the plurality of memory cells are arranged in an array in a first horizontal direction and a second horizontal direction, and the first horizontal direction intersects with the second horizontal direction. The memory according to claim 20, characterized in that it is a memory.

22. A memory further comprising: a plurality of second down signal lines arranged side by side with spacing in a first horizontal direction and extending in a second horizontal direction; a plurality of second up signal lines arranged side by side with spacing in a second horizontal direction and extending in a first horizontal direction; a write word line; and a write bit line, Each of the aforementioned second down signal lines is connected to the second lower electrode of each of the aforementioned readout transistors arranged in a row in the second horizontal direction. The second up signal line is located on the side of the second down signal line away from the semiconductor substrate, and each of the second up signal lines is connected to the second upper electrode of each of the read transistors arranged in a row in the first horizontal direction, with one of the second up signal line and the other down signal line being a read word line and the other being a read bit line. The write bit line is formed on the side of the second up signal line away from the semiconductor substrate, the write word line is formed on the side of the write bit line away from the semiconductor substrate, one of the write word line and the write bit line extends in a first horizontal direction and is arranged in a row with spacing in a second horizontal direction, the other extends in a second horizontal direction and is arranged in a row with spacing in the first horizontal direction, each write bit line is connected to the first upper electrode of each of the write transistors arranged in a row in the direction of its extension, and each write word line is connected to the first gate of each of the write transistors arranged in a row in the direction of its extension. The memory according to feature 21.

23. A portion of the first effective semiconductor channel of the writing transistor is formed as a first oxide channel, and a first void region is formed between the first upper electrode and the first lower electrode, and the first void region is provided so as to surround the first oxide channel. A portion of the second active semiconductor channel of the readout transistor is formed as a second oxide channel, and a second void region is formed between the second upper electrode and the second lower electrode, with the second void region surrounding the second oxide channel. The memory according to claim 20, characterized in that it is a memory.

24. A first interlayer dielectric layer is formed between the first upper electrode and the first void region, and a second interlayer dielectric layer is formed between the first lower electrode and the first void region. Both the first interlayer dielectric layer and the second interlayer dielectric layer are provided so as to surround the first effective semiconductor channel and not in contact with the first oxide channel. A first interlayer dielectric layer is formed between the second upper electrode and the second void region, and a second interlayer dielectric layer is formed between the second lower electrode and the second void region. Both the first interlayer dielectric layer and the second interlayer dielectric layer are provided so as to surround the second effective semiconductor channel and do not come into contact with the second oxide channel. The memory according to feature 23.

25. A portion of the first active semiconductor channel of the writing transistor is formed as a first oxide channel, and a first insulating layer is formed between the first upper electrode and the first lower electrode, and the first insulating layer is provided so as to surround the first oxide channel and is in gapless contact with the lower surface of the first upper electrode and the upper surface of the first lower electrode. A portion of the second active semiconductor channel of the readout transistor is formed as a second oxide channel, and a second insulating layer is formed between the second upper electrode and the second lower electrode. The second insulating layer is provided so as to surround the second oxide channel and is in close contact with the lower surface of the second upper electrode and the upper surface of the second lower electrode without any gaps. The memory according to claim 20, characterized in that it is a memory.

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