Methods for simulating electric motors

Abstract

To provide a method for real-time simulation of an electric motor.SOLUTION: An electrical motor is modeled in a graphical model including two blocks. The graphical model includes at least two matrix operations. The matrix operations are implemented in two separate blocks of a matrix routing block and a matrix calculation block. The matrix routing block is configured to supply the matrix calculation block with an input signal and to store a calculated output signal. The matrix calculation block is configured to apply an operation on a currently received input signal in order to calculate an output signal. A first matrix operation and a second matrix operation include two separate matrix routing blocks and one common matrix calculation block. A matrix routing block of the first matrix operation and a matrix routing block of the second matrix operation alternately provide input signals to the matrix calculation block and receive output signals. A bitstream is generated from the graphical model and executed on a programmable logic module.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a computer-implemented method, a computer system, and a computer-readable storage medium for real-time simulation of electric circuits, particularly electric motors.

Background Art

[0002] Recent products such as control devices are developed in a wide variety of ways using computer-aided simulations of dynamic systems. For example, the regulator section can be simulated in order to test components such as control devices in a hardware-in-the-loop simulation before the completion of the entire product. For this purpose, a special real-time computer that guarantees a reaction within a preset maximum time is used. In many cases, the dynamic characteristics of the system are limited, so that, for example, a maximum waiting time in the millisecond range is reasonable and a real-time computer with a normal processor can be used.

[0003] However, for electrical circuits such as electric motors and inverters that drive and control electric motors, the maximum allowable latency for real-time simulation can be in the range of microseconds. In such cases, a real-time computer having a programmable logic module, particularly a field programmable gate array (FPGA), is preferably used. Here, it may be assumed that drive control or higher-level slow control is performed by a computing node having a processor that exchanges data with the programmable logic module. Since the FPGA is configured by reading bitstreams that directly affect the interconnections of individual logic elements, the circuit to be executed is pre-configured. From German Patent Application Publication No. 102019107817, a method for simulating dynamic systems is known that enables simulation with particularly short latency, using a fixedly pre-configured configuration, especially for small electronic circuits. Since the characteristics of electric motors, such as the number of stator poles, are variable, and various discretization methods (or solvers) are also used depending on the application, it is purposeful to create bitstreams model-based for specific motors rather than using a fixed configuration. However, according to conventional technology, this leads to a decrease in resource utilization efficiency and relatively long waiting times. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Against this backdrop, the objective of the present invention is to provide a method and apparatus for simulating electrical circuits, particularly electric motors, that further develops the prior art, and in particular, efficient utilization of FPGA resources is desired. [Means for solving the problem]

[0005] This problem is solved by a method for real-time simulation of an electrical circuit, particularly an electric motor, having the features of claim 1, and a computer system having the features of claim 12. Preferred embodiments of the present invention are subject to the dependent claims.

[0006] In other words, the present invention provides a method for real-time simulation of an electrical circuit, in particular an electric motor, wherein the electrical circuit is modeled in a graphic model comprising at least two blocks connected by signals, wherein the graphic model comprises at least two matrix operations that generate a multidimensional output signal from at least one multidimensional input signal. The method is performed on a computer system comprising an operating computer and a real-time computer connected to the operating computer, wherein the operating computer runs a graphic modeling environment and the real-time computer has at least one programmable logic module. The matrix operations are implemented in two separate blocks, a matrix routing block and a matrix operation block, wherein the matrix routing block is configured to supply at least one input signal to each of the matrix operation blocks and to store the calculated output signal, wherein the matrix operation block is configured to apply operations to the input signal currently being received in order to calculate the output signal. The first and second matrix operations each include two separate matrix routing blocks, but also one common matrix operation block, where the matrix routing blocks of the first and second matrices alternately supply input signals to the matrix operation block and receive output signals. A bitstream is generated from a portion of the graphic model that includes at least matrix operations and is executed on a programmable logic module.

[0007] One embodiment of the present invention provides a method for real-time simulation of an electrical circuit, in particular an electric motor, wherein the characteristics of the electrical circuit are modeled in a graphic model comprising at least two blocks connected by signals, wherein the graphic model comprises at least two matrix operations that generate a multidimensional output signal from one or more multidimensional input signals. The method is performed on a computer system comprising an operating computer and a real-time computer connected to the operating computer, wherein the operating computer runs a graphic modeling environment and the real-time computer has at least one programmable logic module. Matrix operations are implemented in two separate blocks: a matrix routing block and a matrix operation block, where the first and second matrix operations each include two separate matrix routing blocks, but also include one common matrix operation block, where the first and second matrix routing blocks are configured to supply one or more input signals to the matrix operation block and store the calculated output signals, where the matrix operation block is configured to receive various input signals in sequentially consecutive clocks and apply them to the operation, where the resulting output signals are not stored in the matrix operation block, where a bitstream is generated from at least a portion of the graphic model including matrix operations and executed on a programmable logic module.

[0008] Preferably, the method according to the present invention can maximize the sampling rate to enable better utilization of FPGA hardware resources and reduced or optimized latency for computation.

[0009] Furthermore, improved calculation accuracy is possible, and preferably, the data type of the input signal and / or the data type of the output signal and / or the data type of the matrix elements are floating-point types, particularly Double. The method according to the present invention is applicable regardless of the data type and is not limited to fixed-point types, which have problems with accuracy and scaling.

[0010] Purposefully, the matrix operation block is configured to apply row-by-row parallel operations to at least one element of an input signal. To achieve a good compromise between resource demand and latency, it may be assumed that the sequence of input signals is processed sequentially. Accordingly, it is also possible that the column-by-column parallel operations are performed using row-by-row sequential operations.

[0011] In one embodiment of the present invention, the number of elements to be processed in parallel can be adapted before the bitstream is generated, depending on parameters, particularly user-defined settings, or the characteristics of the programmable logic module. For example, if the parameters exceed a threshold, all input rows can be processed in parallel; if they fall below the threshold, the rows can be divided into multiple blocks, in which case only the elements of one block are processed in parallel. By adapting the number of values ​​to be processed in parallel, existing free space or existing logic elements on the programmable logic module can be used to the best of their ability.

[0012] Preferably, the matrix operation block is configured to process a square matrix, where the size of the square matrix is ​​selected such that it can include both the input signals for the first matrix operation and the input signals for the second matrix operation, and in particular, based on the maximum dimension of each input signal, where the calculation of the square matrix stops as soon as all elements of the output signals of the currently active matrix operation have been calculated. This allows for low latency with high parallelism without excessive consumption of free space on the programmable logic module.

[0013] Preferably, the matrix operation block does not primarily store the output signal resulting from the application of operations to the input signal. This avoids excessive consumption of memory resources within the programmable logic module.

[0014] Preferably, the matrix routing blocks of the first and second matrix operations receive and forward a trigger signal to determine the active matrix routing block, in which case the matrix operation block is always active. Upon receiving the trigger signal, the matrix routing block becomes active and transmits its input signal to the matrix operation block, which then performs the desired matrix operation. After receiving the result, the currently active matrix routing block purposefully forwards the trigger signal, thereby allowing the next matrix routing block to become active. In other words, particularly preferably, upon receiving the trigger signal, the matrix routing block directs at least one input signal to the connected matrix operation block, stores the resulting output signal, and then forwards the trigger signal.

[0015] Preferably, three or more matrix routing blocks can be connected to a matrix operation block, which is configured to perform matrix operations on all connected matrix routing blocks sequentially, so that all matrix operations belonging to the connected matrix routing blocks are performed once at each time step of the simulation. It may be assumed that a scheduler is used to control the processing of matrix operations based on an externally pre-configured order or higher-level control.

[0016] Preferably, the graphic model includes one or more matrix operation blocks, where at least two first matrix routing blocks are connected to the first matrix operation block, and at least two second matrix routing blocks are connected to the second matrix operation block. In particular, the first matrix operation blocks perform the calculations of the first matrix routing blocks sequentially at each time step, and the second matrix operation blocks perform the calculations of the second matrix routing blocks sequentially at each time step. Alternatively, the use of one scheduler each may be assumed. By using multiple instances of matrix operation blocks, more calculations can be performed in parallel (as long as the required resources are available on the programmable logic module). The size of the matrix operation blocks can be selected based on their respective input signals, where the first matrix operation block is a different size from the second matrix operation block if the input signals have different dimensions.

[0017] Preferably, the matrix operation block supports various matrix operations, such as the addition of two matrices, the multiplication of matrices, or the multiplication of a matrix and a vector, where the active matrix operation is selected based on a control signal. In one embodiment, it may be assumed that a predefined mathematical function is applied to each element of the input matrix. For example, calculations of the reciprocal 1 / x or trigonometric functions such as sin x, cos x, and tan x can be performed. Preferably, the type and number of supported arithmetic operations or functions are predefined in the model or selected depending on the parameters. In particular, the functionality of the provided matrix operation block can be selected depending on the available space or available logic elements of the programmable logic module used.

[0018] Preferably, the matrix routing block is configured to adapt the input signal, in particular to rename it or shift its elements to a desired area of ​​the matrix operation block, and to output a control signal to the matrix operation block for selection of the active matrix operation.

[0019] The present invention further relates to a computer system including an operating computer having a man-machine interface and a working computer, wherein the working computer includes a processor and a programmable logic module and is configured to execute the method according to the present invention.

[0020] Furthermore, the present invention relates to a computer-readable storage medium in which instructions are embedded that are configured to cause the computer system to execute the method according to the present invention when the instructions are executed by a computer system including a processor and a programmable logic module.

[0021] Hereinafter, the present invention will be described in more detail with reference to the drawings. Here, the same reference numerals are assigned to the same parts. The illustrated embodiments are greatly simplified, that is, the distances and dimensions are not to scale and do not have geometric relationships that can be derived from each other unless otherwise specified.

Brief Description of the Drawings

[0022] [Figure 1] A preferred embodiment of the operating computer. [Figure 2] A preferred embodiment of the real-time computer. [Figure 3] A schematic diagram of the components of a hybrid vehicle. [Figure 4] A schematic diagram of the simulation of a hybrid vehicle. [Figure 5] A schematic diagram of a graphic model involving a plurality of matrix operations. [Figure 6] An embodiment of matrix operation using a matrix routing block and a matrix operation block. [Figure 7] A schematic diagram of the operating rate of the matrix operation block that executes the matrix operation of FIG. 6.

Embodiments for Carrying Out the Invention

[0023] Figure 1 shows a preferred embodiment of an operating computer PC. This operating computer PC has a processor CPU, which may in particular be implemented as a multi-core processor, a working memory RAM, and a bus controller BC. Preferably, the operating computer PC is designed to be directly and manually operated by a user, in which case a monitor DIS is connected via a graphics card GPU, and a keyboard KEY and a mouse MOU are connected via a peripheral device interface HMI. In principle, the operating computer PC may also have a touch interface. The operating computer further includes a non-volatile data memory HDD, which may in particular be implemented as a hard disk and / or a solid state disk, as well as an interface NET, in particular a network interface.

[0024] Via the interface NET, further computers, in particular a real-time computer ES, can be connected. In principle, one or more arbitrary interfaces, in particular a wired interface, may be present in the operating computer PC and each may be used for connection to a further computer. Expediently, a network interface compliant with the Ethernet standard can be used, in which case at least the physical layer is executed in accordance with the standard and one or more upper protocol layers may be implemented proprietary or adapted to the real-time computer. The interface NET may in particular be executed wirelessly, as a WLAN interface or in accordance with a standard such as Bluetooth. Here, it may be a mobile communication connection such as LTE, in which case preferably the data exchanged is encrypted. Preferably, at least one interface of the operating computer is executed as a standard Ethernet interface, so that a further computer can be easily connected to the operating computer PC.

[0025] The operating computer PC may have a protected data container SEC, which facilitates the use of licensed applications on the operating computer, but it is also possible to use the operating computer as a license server for the real-time computer. The protected data container SEC may be implemented, for example, in the form of a dongle connected to a peripheral device interface. Alternatively, the protected data container SEC may be permanently incorporated into the operating computer as a component, or stored in non-volatile data memory HDD in the form of a file.

[0026] Figure 2 shows a preferred embodiment of a real-time computer ES. This real-time computer ES includes a compute node CN, which is connected to an operating computer PC via a network interface NET. In principle, this connection needs to exist only while the configuration of the real-time computer ES is being adapted, and preferably continuously. The compute node CN has at least one processor CPU, in particular a multi-core processor or multiple processors, working memory RAM, and non-volatile memory NVM, on which preferably an operating system and / or boot loader is stored. At least one logic board FPGA and a device interface DEV are connected to the compute node via a high-speed bus SBC or a corresponding controller. The logic board FPGA includes a programmable logic module that can be configured according to the present invention. It is conceivable that the real-time computer ES has multiple logic board FPGAs or multiple programmable logic modules on a logic board. Multiple modules, such as an error simulation circuit FIU that applies defined electrical errors to connected devices, or an interface card IOC that provides one or more analog or digital I / O channels, can be connected via the device interface DEV.

[0027] Figure 3 shows a schematic diagram of the components of a hybrid vehicle or an automobile that is at least temporarily driven by an electric motor.

[0028] The drive control of an electric motor is performed by an ECU (Electronic Control Unit), which includes a regulator and an output stage. The ECU is connected to the electric motor and supplies it with, for example, a three-phase voltage. Electric motors have a large number of coils and therefore require a corresponding number of phase voltages or phase currents. The electric motor is mechanically connected to a transmission, which can drive one or more wheels in particular. However, electric motors are also used in a range of other vehicle applications, which can also be simulated. A vehicle has a series of sensors, such as wheel speed sensors. At least one output signal or one or more sensor signals from the sensors are supplied to the vehicle control unit. An electric motor also has a series of sensors, such as a position sensor indicating the position of the rotor relative to the stator, and this position signal is also supplied to the control unit.

[0029] The control equipment includes an application controller that receives vehicle sensor signals and electric motor position signals, and determines target values ​​for each phase of the electric motor based on a control algorithm. The current controller drives and controls semiconductor switches in the output stage or inverter according to the target values, or according to a comparison with current signals from current sensors, such as shunt resistors, located in the output stage.

[0030] The three dashed lines illustrate the different levels at which electric motor simulations can be initiated. At the signal level where the regulator operates, only electrical signals or numerical values ​​exist. The inverter operates at a power level where significant voltage, current, or power can be generated. The electric motor converts this power into mechanical force. If the entire system, consisting of control equipment and the motor, needs to be tested at the mechanical level, a corresponding test bench is required. Testing of control algorithms at the signal level may, in some cases, be done in the form of software simulation.

[0031] Figure 4 shows a schematic diagram of a simulation of a hybrid vehicle or an automobile that is at least temporarily powered by an electric motor.

[0032] The illustrated simulation system has an electronic load capable of processing or manipulating voltages and currents generated at the power level. This allows for testing of control devices that exist as real components without the presence of the entire vehicle or the risk associated with driving tests. The vehicle or mechanical components are simulated on the processor CPU of the computing node CN or real-time computer ES based on the simulation model. Sensor signals required by the control devices are generated using sensor simulations performed by the processor and / or programmable logic module FPGA.

[0033] To ensure minimal latency, the electronic load is driven and controlled by a programmable logic module FPGA, the configuration of which is created, for example, based on a block library. Preferably, this block library includes matrix routing blocks and matrix operation blocks for carrying out the method according to the present invention.

[0034] Figure 5 shows a schematic diagram of a graphic model involving multiple matrix operations.

[0035] The illustrated model includes four matrix operation blocks B1, B2, B3, and B4, which are connected to each other via signals. Each matrix operation block has two input signals and outputs one output signal. Block B1 receives two matrix signals A and B and calculates their product A × B. Block B2 receives the output signal from B1 and an additional matrix signal C and calculates the sum (A × B) + C. Block B3 receives the output signal from B2 and an additional matrix signal D and calculates the product ((A × B) + C) × D. Block B4 receives the output signals from B1 and B3 and outputs the sum (((A × B) + C) × D) + (A × B) as its output signal.

[0036] Because processing over time causes a predetermined delay, and downstream operations must wait for the results of upstream operations, subsequent operations are purposefully activated by an external pulse. The matrix operation block has a trigger input Trig for this purpose. When an operation is performed, a trigger pulse to activate the operation is transferred to the next component via the trigger output New.

[0037] If matrix operation blocks are implemented like conventional monolithic blocks, this will result in poor hardware utilization efficiency. This is because matrix operations are only active for a short time ("work-time"), and after the calculation is performed, the system must wait for the next pulse ("idle-time"). However, the next trigger pulse is only received after a complete chain of matrix operation blocks has been completed. This leads to reduced utilization efficiency or a worsening of the work-idle ratio of the implemented matrix operations. Matrix operation blocks occupy a large area on the programmable logic module.

[0038] Figure 6 shows one embodiment of matrix operations using the matrix routing block and matrix operation block according to the present invention.

[0039] Instead of a monolithic matrix operation block, a matrix routing block GRU and a matrix operation block GCU are used. The matrix routing block GRU receives input signals A and B and outputs an output signal Out. Furthermore, the matrix routing block GRU has a trigger input Trig and a trigger output New. The matrix routing block GRU provides "Gateway / Routing" functionality, transferring each data to the combined matrix operation block GCU, which then performs the respective calculations. After the calculations are performed, the results are stored back into the matrix routing block GRU, which also transfers the trigger signal.

[0040] Multiple matrix routing blocks may be connected to a single matrix operation block (GCU). Since downstream calculations are performed by the same GCU, a much better utilization efficiency of logic elements can be achieved on the programmable logic module. Only the operation block (GCU) requires dedicated hardware resources for calculations, and furthermore, it can support calculations applicable to more complex matrices in addition to various basic arithmetic types. Purposefully, the matrix routing block (GRU) can select and, therefore, control the current arithmetic operations of the matrix operation blocks via configuration signals or a configuration language.

[0041] Figure 7 shows a schematic diagram of the utilization rate of the matrix operation block GCU that performs the matrix operations shown in Figure 4.

[0042] This section indicates which of the numbered matrix operations or blocks B1, B2, B3, and B4 is currently being executed by the matrix operation block GCU. The matrix operation blocks are fully utilized, and only brief delays may occur at the transitions between the various matrix operations indicated by dashed lines.

[0043] When more computing power is required, a wide range of matrix operation blocks (GCUs) can be used, or more GCU blocks can be used. These blocks are connected to parts of the matrix routing blocks (GRUs), thereby enabling parallel processing.

[0044] In one embodiment of the present invention, matrix routing blocks and matrix operation blocks may be implemented in a block library for a technical computing environment such as MATLAB / Simulink. Preferably, the matrix routing block has a user interface that allows the user to select a matrix operation block to which an input signal for computation is supplied. The user interface also allows the user to select the desired arithmetic operation, such as matrix multiplication, addition, or element-wise application of a predefined function to the elements of the input matrix. The matrix operation block may be designed as a general-purpose operation block that supports a predefined computation range, in which case the connected matrix routing block selects the desired computation from the predefined range via a signal or command. The matrix operation block may be envisioned to have a user interface that allows the user to select the degree of computation parallelization. In particular, it is possible to parallelize an entire row of a matrix or divide it into blocks to be processed in parallel, which can be set by the user, for example, via a slider. The block library can contain matrix operation blocks of various sizes so that the appropriate block can be easily selected. The correspondence between matrix routing blocks and matrix operation blocks can be made by computation number and / or block identifier or name. From the created model, bitstreams for programmable logic modules can be generated, for example, using Xilinx System Generator.

[0045] According to the calculation method described, the following advantages can be obtained: Based on the signal paths between matrix routing blocks, the order of matrix operations can be easily understood, maintaining the readability of the model. Routing from the matrix routing block GRU to various matrix operation blocks GCU is implemented transparently for the user. • Improved efficiency in utilizing dedicated computing hardware resources such as DSP-Slices.

[0046] By using fewer computational blocks, more dedicated computing hardware resources can be used per block, which enables further advantages. That is, Matrix operations can be structured in near-parallel order, thereby minimizing latency. Matrix operations can be performed with higher bit widths (for example, double precision instead of single precision), which enables more accurate simulations.

Claims

1. A method for real-time simulation of electrical circuits, particularly electric motors, The aforementioned electrical circuit is modeled in a graphic model that includes at least two blocks connected by signals, The graphic model includes at least two matrix operations that generate a multidimensional output signal from at least one multidimensional input signal, The method described above is performed on a computer system comprising an operating computer and a real-time computer connected to the operating computer. The operating computer runs a graphic modeling environment, and the real-time computer has at least one programmable logic module. The aforementioned matrix operations are implemented in two separate blocks: a matrix routing block and a matrix operation block. The matrix routing block is configured to supply at least one input signal to each of the matrix operation blocks and to store the calculated output signals. The matrix operation block is configured to apply operations to the currently received input signal in order to calculate the output signal. The first and second matrix operations each include two separate matrix routing blocks, but also one common matrix operation block. The matrix routing block for the first matrix operation and the matrix routing block for the second matrix operation alternately supply input signals to the matrix operation block and receive output signals. A bitstream is generated from at least a portion of the graphic model that includes the matrix operations, and is executed on a programmable logic module. method.

2. The matrix operation block is configured such that operations are applied in parallel to each row for each element of at least one input signal. The method according to claim 1.

3. The matrix operation block is configured to process a square matrix, the size of which is selected based on the maximum dimensions of the input signals for the first and second matrix operations, such that the square matrix can include both the input signals for the first matrix operation and the input signals for the second matrix operation, and the calculation of the square matrix is ​​stopped as soon as all elements of the output signals of the currently active matrix operation have been calculated. The method according to claim 1 or 2.

4. The matrix operation block does not temporarily store the output signal resulting from the application of the operation to the input signal. The method according to any one of claims 1 to 3.

5. The matrix routing block of the first matrix operation and the matrix routing block of the second matrix operation receive and transmit trigger signals to determine the active matrix routing block, in which case the matrix operation block is always active. The method according to any one of claims 1 to 4.

6. When a matrix routing block receives the trigger signal, it supplies the at least one input signal to the connected matrix operation block, stores the resulting output signal, and then forwards the trigger signal. The method according to claim 5.

7. Three or more matrix routing blocks can be connected to a matrix operation block, which is configured to perform matrix operations on all connected matrix routing blocks sequentially, so that at each time step of the simulation, all matrix operations belonging to the connected matrix routing blocks are performed once. The method according to any one of claims 1 to 6.

8. The graphic model includes two or more matrix operation blocks, wherein at least two first matrix routing blocks are connected to the first matrix operation block, and at least two second matrix routing blocks are connected to the second matrix operation block. The method according to any one of claims 1 to 7.

9. At least one element of the multidimensional input signal and / or at least one element of the multidimensional output signal have a floating-point number as their data type. The method according to any one of claims 1 to 8.

10. The matrix operation block supports various matrix operations, such as the addition of two matrices, the multiplication of matrices, or the multiplication of a matrix and a vector, and the active matrix operation is selected based on a control signal. The method according to claim 3.

11. The matrix routing block is configured to rename an input signal or shift its elements to a desired region of the matrix operation block, and to output a control signal to the matrix operation block for the selection of an active matrix operation. The method according to any one of claims 1 to 10.

12. A computer system including an operating computer having a human-machine interface and a real-time computer, The real-time computer includes a processor and a programmable logic module, and the computer system is configured to perform the method according to any one of claims 1 to 11. Computer system.

13. A computer-readable storage medium, When an instruction is executed by a computer system including a processor and a programmable logic module, the instruction is embedded in which the computer system is configured to cause the computer system to perform the method described in any one of claims 1 to 11. Computer-readable storage medium.

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