Processing apparatus, processing program, and processing method

Abstract

To provide a processing apparatus configured to perform processing based on an accurate memory address even when DMA transfer completion interrupt is lost.SOLUTION: A processing apparatus which sequentially processes data transferred to a memory by a DMA controller includes: management information that manages address information of each of multiple buffers allocated in advance on a memory, the buffers having the same size as a data transfer size that the DMA controller travels, and buffer processing information indicating a current buffer the processing apparatus has processed; travel address acquisition means which acquires a travel address of the DMA controller; and management means which specifies, on receipt of an interrupt indicating a DMA transfer completion at a timing when data is completely transferred from the DMA controller to each of the buffers, a buffer that stores unprocessed data which is to be processed by the processing apparatus, on the basis of the acquired travel address and the management information.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a processing device, a processing program, and a processing method, and can be applied to, for example, a method for monitoring data transfer by DMA (Direct Memory Access).

Background Art

[0002] DMA is one of the data transfer methods in a computer system, and is a method of directly transferring data between a peripheral device and a memory (RAM: Random Access Memory) under the control of a dedicated controller (DMA controller) without going through the CPU (Central Processing Unit).

[0003] When the DMA transfer is completed, the DMA controller notifies the CPU of a signal (DMA transfer completion interrupt) indicating that the DMA transfer has been completed. Then, the CPU calls the handler registered in the vector table on the occasion of the DMA transfer completion interrupt, and performs the target processing using the data transferred by the DMA controller (the data written to the memory) in the handler (see Non-Patent Document 1).

[0004] Generally, on the CPU side, memory address management is performed within a predetermined application. For example, each time an interrupt of DMA transfer completion occurs, the application counts up the memory address management, and derives the target memory address from the number of interrupts.

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

[0006] However, if a DMA transfer completion interrupt is lost due to delays in interrupt latency, the memory address management described above calculates the memory address from the number of DMA transfer completion interrupts. As a result, processing cannot be performed based on the correct memory address, leading to a problem where data integrity cannot be maintained.

[0007] Therefore, there is a need for a processing unit, processing program, and processing method that can perform processing based on the correct memory address even if the DMA transfer completion interrupt is lost. [Means for solving the problem]

[0008] The first aspect of the present invention is a processing device for sequentially processing data transferred to memory by a DMA controller, characterized in that: (1) a plurality of buffers of the same size as the data transfer size used by the DMA controller are allocated in advance on the memory, and management information that manages at least the address information of each of the buffers and buffer processing information indicating which of the buffers the processing device has currently processed; (2) a travel address acquisition means for acquiring the travel address that the DMA controller is currently accessing in the memory; and (3) a management means that, when an interrupt indicating the completion of a DMA transfer is received from the DMA controller at the timing when the transfer to each of the buffers is completed, identifies the buffer in which the processing device stores unprocessed data to be processed, based on the travel address acquired by the travel address acquisition means and the management information.

[0009] The second processing program of the present invention is characterized in that a computer mounted on a processing device that sequentially processes data transferred to memory by a DMA controller functions as a management means that (1) allocates a plurality of buffers of the same size as the data transfer size used by the DMA controller in a cyclic manner on the memory in advance, manages at least the address information of each of the buffers and buffer processing information indicating which of the buffers the processing device has currently processed; (2) acquires a travel address that the DMA controller is currently accessing on the memory; and (3) when the DMA controller receives an interrupt indicating the completion of a DMA transfer at the timing when the transfer to each of the buffers is completed, the computer functions as a management means that identifies the buffer in which the processing device stores unprocessed data to be processed, based on the travel address acquired by the travel address acquisition means and the management information.

[0010] The third aspect of the present invention relates to a processing method for use in a processing device that sequentially processes data transferred to memory by a DMA controller, wherein (1) the processing device has a plurality of buffers of the same size as the data transfer size used by the DMA controller in a cyclic manner allocated in the memory in advance, and comprises management information that manages at least the address information of each of the buffers and buffer processing information that indicates which of the buffers the processing device has currently processed, a travel address acquisition step, and a management step, (2) the travel address acquisition step acquires the travel address that the DMA controller is currently accessing in the memory, and (3) when the management step receives an interrupt indicating the completion of a DMA transfer at the timing when the transfer to each of the buffers has been completed by the DMA controller, it identifies the buffer in which the unprocessed data to be processed by the processing device is stored, based on the travel address acquired in the travel address acquisition step and the management information. [Effects of the Invention]

[0011] According to the present invention, even if the DMA transfer completion interrupt is lost, processing based on the correct memory address can be performed. [Brief explanation of the drawing]

[0012] [Figure 1] This is an overall configuration diagram showing the overall configuration of the information processing device according to the embodiment. [Figure 2] This is an explanatory diagram showing an example of a parameter RAM according to the embodiment. [Figure 3] This is an explanatory diagram showing an example of management data for the management API according to the embodiment. [Figure 4] This figure shows an example of RAM (a region for temporarily storing data via a DMA controller) according to the embodiment. [Figure 5] This is a flowchart illustrating the characteristic operation of the information processing device (control program) according to the embodiment. [Figure 6] This is an explanatory diagram showing a specific example of the characteristic operation (processing in Figure 5) of the information processing device (control program) according to the embodiment. [Modes for carrying out the invention]

[0013] (A) Main embodiment Hereinafter, an embodiment of the processing apparatus, processing program, and processing method according to the present invention will be described in detail with reference to the drawings.

[0014] (A-1) Configuration of the embodiment Figure 1 is an overall configuration diagram showing the overall configuration of an information processing device according to an embodiment. As shown in Figure 1, the information processing device 1 has a hardware configuration consisting of a CPU 10, a ROM (Read Only Memory) 20, a RAM 30, a peripheral device 40, and a DMA controller 50. The CPU 10, ROM 20, RAM 30, peripheral device 40, and DMA controller 50 are interconnected by a bus N.

[0015] The CPU 10 functions as an arithmetic processing unit and a control unit, and controls the overall operations within the information processing apparatus 1 according to various programs. For example, when the CPU 10 cooperates with the ROM 20 and the RAM 30 described later, the control program 11 described later is executed.

[0016] The ROM 20 stores programs (such as the control program 11 described later) used by the CPU 10.

[0017] The RAM 30 is used as a work area for the CPU 10 and also as a temporary storage area for data transmitted and received via the ROM 20, the peripheral device 40 described later, etc.

[0018] The peripheral device 40 is a peripheral device of the information processing apparatus 1 (regardless of whether it is built-in or external), and examples include a printer, a HDD (Hard Disk Drive), an audio device, a LAN (Local Area Network) controller, etc.

[0019] The DMA controller 50 performs data transmission and reception processing (DMA transfer) between the RAM 30, the ROM 20, and the peripheral device 40. For example, when the peripheral device 40 is a LAN controller, the DMA controller 50 controls the DMA transfer of the stored network data to the transfer destination address of a pre-specified memory area (buffer B in FIG. 4 described later) in the RAM 30. Further, when the DMA transfer is completed, the DMA controller 50 notifies the CPU 10 of the completion of the DMA transfer (DMA transfer completion interrupt) using an interrupt.

[0020] The DMA controller 50 has a parameter RAM 51 which is a setting register for controlling the DMA transfer.

[0021] Figure 2 is an explanatory diagram showing an example of a parameter RAM according to the embodiment. As shown in Figure 2(A), the parameter RAM 51 is set to a parameter RAM number that identifies each parameter RAM, a "source address" indicating the address from which the data is transferred, a "destination address" indicating the address to which the data is transferred, a "transfer size" indicating the data transfer size, and a "link" indicating the parameter RAM number to which the transfer continues after completion. Note that the parameter RAM 51 in Figure 2(A) is simply described to make it easier to explain the features of this embodiment, but various other items may be added in addition to those mentioned above.

[0022] Figure 2(B) is an explanatory diagram illustrating the process of continuously transferring data according to the parameter RAM 51 described above. Figure 2(B) shows three parameter RAMs 51 (51-1 to 51-3). Of these, parameter RAM 51-1 is the latest setting currently being transferred under the control of the DMA controller 50.

[0023] In this embodiment, it is assumed that the DMA controller 50 has a mechanism (function) that updates the source address and destination address of parameter RAM 51-1 in real time to the address that the DMA controller 50 is currently accessing on RAM 30. Similarly, it is assumed that the DMA controller 50 has a function that returns the destination address of parameter RAM 51-1 (the address to be updated in real time) in response to an acquisition request from the management API 13 of the control program 11, which will be described later.

[0024] When the DMA controller 50 has finished transferring the contents specified (set) in parameter RAM 51-1, it continues the transfer according to the contents specified in the next parameter RAM number specified in the link of parameter RAM 51-1 (the contents specified in parameter RAM 51-2). When continuing the transfer, the contents specified in parameter RAM 51-2 are copied to parameter RAM 51-1, and the transfer is performed according to parameter RAM 51-1 (similarly, once the transfer is complete, the contents of parameter RAM 51-3 are processed next).

[0025] In other words, on the CPU side (control program 11), by monitoring the destination address of parameter RAM 51-1, it is possible to confirm which address on RAM 30 the DMA controller 50 is currently accessing.

[0026] Next, we will explain the control program 11 that is executed on the CPU 10.

[0027] The control program 11 utilizes hardware resources such as the CPU 10 and RAM 30 to perform interrupt management, task management, memory management, etc. As shown in Figure 1, the control program 11 includes a handler 12, a management API 13, and a task 14.

[0028] Handler 12 is called by the CPU 10 when it detects an interrupt (such as a DMA transfer completion interrupt) requested by the DMA controller 50 or the like in the CPU 10, and executes processing corresponding to the detected interrupt. In this embodiment, handler 12 calls the management API 13, which will be described later, to identify the address on RAM 30 where the target processing will be performed. Once handler 12 obtains the address to be processed via the management API 13, it notifies task 14 of the processing that corresponds to it.

[0029] The management API 13 obtains the destination address of the parameter RAM 51-1 mentioned above, compares the obtained destination address (the latest address that the DMA controller 50 has transferred (written) to RAM 30) with the address value managed by the program (the unprocessed buffer counter C described later), and identifies the address that the program should process (the unprocessed buffer in RAM 30).

[0030] The management API 13 includes an unprocessed buffer counter C that indicates the memory area (buffer B) to be processed in RAM 30, and management data D that indicates the memory area to be transferred to RAM 30 by the DMA controller 50.

[0031] Figure 3 is an explanatory diagram showing an example of management data for the management API according to the embodiment. As shown in Figure 3, the management data D has items for "buffer" which indicates the memory area (each buffer B) to be transferred from the DMA controller 50 to the RAM 30, and "starting address" which indicates the starting address of each buffer B.

[0032] In this embodiment, a region for temporary data storage by peripheral devices 40, etc., via the DMA controller 50 is predetermined on the RAM 30. Figure 4 shows an example of the RAM (region for temporary data storage via the DMA controller) according to the embodiment. In Figure 4, five buffers B (B1 to B5) are pre-allocated in the RAM 30 as temporary data storage regions. In Figure 4, the size of one buffer B is 256 bytes, and an example of five buffers B is shown, but this is not limited to this, and the size and number of buffers B are set appropriately according to the system, for example.

[0033] Furthermore, in this embodiment, the size of buffer B is the same as the transfer size of parameter RAM 51. That is, if the size of buffer B is 256 bytes, the transfer size of each parameter RAM 51 will be 256 bytes, and the DMA controller 50 will use the five buffers B cyclically to transfer data according to the contents of each parameter RAM 51.

[0034] In Figure 3, each buffer B is managed by associating it with its starting address, but this is not the only way to manage each buffer B; various methods can be used.

[0035] Task 14 performs a variety of processes, but in this embodiment, it is a task that performs some processing on data that has been notified to the handler 12 and transferred from the DMA controller 50 to the RAM 30. Task 14 will process up to the address of RAM 30 (buffer B) notified by the handler 12.

[0036] (A-2) Operation of the embodiment Next, the operation of the information processing device 1 according to the embodiment having the above configuration will be described.

[0037] (A-2-1) Characteristics and operation of the information processing device 1 Figure 5 is a flowchart showing the characteristic operation of the information processing device (control program) according to the embodiment.

[0038] <s101> The CPU 10 (control program 11) receives a DMA transfer completion interrupt from the DMA controller 50 and calls the handler 12.

[0039] <s102> Handler 12 calls management API 13 to identify buffer B in RAM 30 that was transferred by DMA controller 50. Management API 13 obtains the address that DMA controller 50 is currently traversing on RAM 30. Specifically, management API 13 obtains the destination address of parameter RAM 51-1, whose traversing address is being updated in real time, from DMA controller 50. Management API 13 further obtains the value (buffer B) indicated by the unprocessed buffer counter C.

[0040] <s103> The management API 13 checks whether the acquired destination address falls within the range of the address of the next buffer B indicated by the acquired unprocessed buffer counter C (buffer B). For example, if the value indicated by the unprocessed buffer counter C is buffer B0, then the next buffer B is buffer B1 (0x1000_0100~0x1000_01FF).

[0041] <s104> If, in the process of step S103 described above, the management API 13 obtains a destination address that falls within the range of the address of the next buffer B indicated by the value of the unprocessed buffer counter C (in other words, if no interrupt loss has occurred), it returns the address of buffer B indicated by the unprocessed buffer counter C to the handler 12.

[0042] Handler 12 notifies task 14 of the address returned from management API 13 (requesting that it process one buffer).

[0043] <s105> In the process of step S103 described above, if the destination address obtained does not fall within the range of the next buffer B address indicated by the unprocessed buffer counter C (in other words, if an interrupt loss has occurred), the management API 13 refers to the management data D to identify the buffer B (one of B1 to B5) to which the address indicated by the destination address belongs. The buffer between the buffer indicated by the unprocessed buffer counter C and the buffer B immediately preceding the identified buffer B becomes the unprocessed buffer.

[0044] <s106> The management API 13 returns the address (starting address) of each buffer B to the handler 12, corresponding to the number of unprocessed buffer B items.

[0045] Handler 12 notifies Task 14 of each address returned from Management API 13 (requesting that it process the remaining unprocessed buffer).

[0046] <s107> The management API 13 increments the value of the unprocessed buffer counter C according to the number of buffers B that have been processed. For example, if the unprocessed buffer counter C indicates buffer B1 and one buffer B has been processed (following the route of step S104 above), buffer B1 will be renumbered as "buffer B2". On the other hand, if n buffer B items have been processed (following the route of step S106 above), buffer B1 will be renumbered as "buffer B(1+n)".

[0047] (A-2-2) Specific examples of feature processing Next, we will explain the process in the flowchart of Figure 5 again, using a specific example.

[0048] Figure 6 is an explanatory diagram showing a specific example of the characteristic operation (processing in Figure 5) of the information processing apparatus according to the embodiment.

[0049] For the purposes of the following explanation, it is assumed that the initial state of the unprocessed buffer counter C is "Buffer B0", and that the management data D is as shown in Figure 3.

[0050] First, when the CPU 10 receives the first DMA transfer completion interrupt, it calls the handler 12. The handler 12 calls the management API 13 to identify buffer B in RAM 30 that was transferred by the DMA controller 50. The management API 13 obtains the destination address of the DMA controller 50 (parameter RAM 51-1). Furthermore, the management API 13 obtains the value (buffer B) indicated by the unprocessed buffer counter C. If the destination address is within the range of buffer B1 (0x1000_0100~0x1000_01FF), the management API 13 determines that it is successful and notifies the task 14 to process one unprocessed buffer B0 (0x1000_0000~0x100_00FF).

[0051] Task 14 has processed one item in buffer B, so CPU 10 increments the unprocessed buffer counter C from buffer B0 to buffer B1.

[0052] Next, when CPU 10 receives the second DMA transfer completion interrupt, it similarly calls handler 12. Handler 12 similarly calls management API 13 to identify buffer B in RAM 30 that was transferred by DMA controller 50. Management API 13 obtains the destination address of DMA controller 50 (parameter RAM 51-1). Management API 13 further obtains the value (buffer B) indicated by the unprocessed buffer counter C. If the destination address is within the range of buffer B2 (0x1000_0200~0x1000_02FF), management API 13 determines that it is successful and notifies task 14 to process one unprocessed buffer B1 (0x1000_0100~0x100_01FF).

[0053] Since CPU10 has processed one item in buffer B, it increments the unprocessed buffer counter C from buffer B0 to buffer B1.

[0054] If the destination address is within the range of buffer B3 (0x1000_0300~0x100003FF), the management API 13 will determine that the DMA transfer completion interrupt for buffer B2 (0x1000_0200~0x1000_02FF) has been lost. In this case, the handler 12 will notify task 14 to process the two unprocessed buffers B1 (0x1000_0100~0x100_01FF) and buffer B2 (0x1000_0200~0x1000_02FF).

[0055] Task 14 has processed two items in buffer B, so CPU 10 increments the unprocessed buffer counter C from buffer B1 to buffer B3.

[0056] Although not shown in Figure 6, the CPU 10 executes the following processes sequentially.

[0057] When CPU 10 receives the nth (third or later) DMA transfer completion interrupt, it similarly obtains the destination address of the DMA controller 50 (parameter RAM 51-1). Management API 13 further obtains the value indicated by the unprocessed buffer counter C (buffer B). Similarly, when management API 13 determines that the DMA transfer completion interrupt is normal, handler 12 similarly notifies task 14 to process buffer B related to one unprocessed transfer.

[0058] Similarly, CPU10 has processed one item in buffer B, so it increments the unprocessed buffer counter C from buffer B0 to buffer B1.

[0059] If the management API 13 similarly determines that it has lost information regarding the DMA transfer completion interrupt, the handler 12 similarly notifies task 14 to process the unprocessed buffer B.

[0060] Task 14 has processed the remaining number of items in buffer B, so CPU 10 increments the unprocessed buffer counter C based on the number of items in buffer B that were processed.

[0061] (A-3) Effects of the Embodiment This embodiment provides the following effects.

[0062] The control program 11 (handler 12 and management API 13) executed by the CPU 10 investigates the address where the DMA controller 50 is running, ensuring that even if the DMA transfer completion interrupt is lost, task 14 can reliably process the target data.

[0063] For example, in designs where the interval between DMA transfer completion interrupts is as short as tens of microseconds (i.e., designs requiring real-time data processing), latency and overhead can cause interrupts to occur while processing is underway within handler 12, potentially resulting in data loss. This embodiment is particularly effective in such designs.

[0064] (B) Other embodiments Although various modified embodiments were mentioned in the embodiments described above, the following modified embodiments can also be applied.

[0065] In the above embodiment, an example was shown in which the unprocessed data in buffer B on RAM 30 is processed in response to a DMA transfer completion interrupt. However, a periodic interrupt (timer interrupt) may be used as an interrupt when the DMA transfer completion interrupt is lost, and the unprocessed data in buffer B on RAM 30 may be processed in the same way as in the above embodiment. [Explanation of Symbols]

[0066] 1... Information processing device, 10... CPU, 11... Control program, 12... Handler, 13... Management API, 14... Task, 20... ROM, 30... RAM, 40... Peripheral device, 50... DMA controller, 51 (51-1~51-3)... Parameter RAM, ... Parameter RAM, 51-2... Parameter RAM, ... Parameter RAM, B (B0~B3)... Buffer, ... Buffer, C... Unprocessed buffer counter, D... Management data, N... Bus. < / url:>

Claims

1. A processing unit that sequentially processes data transferred to memory by a DMA controller, Multiple buffers of the same size as the data transfer size used by the DMA controller are pre-allocated on the memory, and management information manages at least the address information of each buffer and buffer processing information indicating which buffer the processing unit has currently processed, The DMA controller includes a means for obtaining the driving address currently being accessed from the memory, When the DMA controller receives an interrupt indicating the completion of DMA transfer at the time when the transfer to each of the buffers is completed, the management means identifies the buffer in which the unprocessed data to be processed by the processing unit is stored, based on the travel address acquired by the travel address acquisition means and the management information. A processing apparatus characterized by having

2. The processing device according to claim 1, characterized in that the management means determines that no interrupt has been lost if the travel address indicates an address within the range of the next buffer to be processed by the processing device in the order of cyclic use of the buffers, and determines that the buffer immediately preceding the buffer indicated by the travel address is the buffer to be processed by the processing device.

3. The processing device according to claim 1 or 2, characterized in that the management means determines that an interrupt has been lost if the travel address indicates an address within the range of buffers that the processing device should process in the order of cyclic use of the buffers, from the buffer that the processing device should process next in the order of use of the buffers, up to the buffer immediately preceding the buffer indicated by the travel address, and determines that each of the buffers that the processing device should process is a buffer.

4. A computer mounted on a processing unit that sequentially processes data transferred to memory by a DMA controller, Multiple buffers of the same size as the data transfer size used by the DMA controller are pre-allocated on the memory, and management information manages at least the address information of each buffer and buffer processing information indicating which buffer the processing unit has currently processed, The DMA controller includes a means for obtaining the driving address currently being accessed from the memory, When the DMA controller receives an interrupt indicating the completion of DMA transfer at the time when the transfer to each of the buffers is completed, the management means identifies the buffer in which the unprocessed data to be processed by the processing unit is stored, based on the travel address acquired by the travel address acquisition means and the management information. A processing program characterized by its ability to function in this way.

5. A processing method used in a processing unit that sequentially processes data transferred to memory by a DMA controller, The processing device has, in advance, multiple buffers of the same size as the data transfer size used by the DMA controller in rotation, allocated on the memory, and includes management information that manages at least the address information of each buffer and buffer processing information that indicates which buffer the processing device has currently processed, a travel address acquisition step, and a management step. The aforementioned driving address acquisition step involves the DMA controller acquiring the driving address currently being accessed by the memory, When the management step receives an interrupt indicating the completion of DMA transfer when the transfer from the DMA controller to each of the buffers is completed, it identifies the buffer in which the unprocessed data to be processed by the processing unit is stored, based on the travel address obtained in the travel address acquisition step and the management information. A processing method characterized by the following.

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