Power circuit

Abstract

This invention provides a power supply circuit that can reduce the core loss within an inductor. [Solution] The power supply circuit comprises a transformer having a primary winding and a secondary winding, a full-bridge circuit having four switching elements, an inductor provided between the primary winding and the full-bridge circuit, and a rectifier circuit configured so that the current flowing through the inductor is unidirectional.

Description

Technical Field

[0001] The present disclosure relates to a power supply circuit.

Background Art

[0002] Power supplies are used in various fields. As related art, Patent Document 1 discloses a technique related to a DC-DC converter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the power supply related to Patent Document 1, a technique capable of reducing the loss of the core in the inductor is required.

[0005] One of the objectives of each aspect of the present disclosure is to provide a power supply circuit capable of solving the above problems.

Means for Solving the Problems

[0006] According to one aspect of the present disclosure, the power supply circuit includes a transformer having a primary winding and a secondary winding, a full-bridge circuit having four switching elements, an inductor provided between the primary winding and the full-bridge circuit, and a rectifier circuit configured such that the current flowing through the inductor is in one direction.

Effects of the Invention

[0007] According to each aspect of the present disclosure, the loss of the core in the inductor can be reduced.

Brief Description of the Drawings

[0008] [Figure 1] This figure shows an example of the configuration of a power supply circuit according to some embodiments of the present disclosure. [Figure 2] This figure shows an example of the configuration of a power supply circuit when the switching element according to some embodiments of the present disclosure is a MOS transistor. [Figure 3] This figure shows an example of a magnetic hysteresis curve according to some embodiments of the present disclosure. [Figure 4] This figure shows an example of a time chart for a power supply circuit according to some embodiments of the present disclosure. [Figure 5] This figure shows an example of the configuration of a power supply circuit according to some embodiments of the present disclosure. [Figure 6] This figure shows an example of the configuration of a power supply circuit according to some embodiments of the present disclosure. [Figure 7] This figure shows an example of the configuration of a power supply circuit according to some embodiments of the present disclosure. [Figure 8] This figure shows an example of the configuration of a power supply circuit according to some embodiments of the present disclosure. [Figure 9] This is a schematic block diagram showing the configuration of a computer according to at least one embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the drawings. <Embodiment> (Power supply circuit configuration) A power supply circuit 1 according to one embodiment of the present disclosure will be described with reference to the drawings. The power supply circuit 1 is an isolated DC (Direct Current)-DC power supply circuit that can reduce the loss of the core in the inductor.

[0010] Figure 1 shows an example of the configuration of a power supply circuit 1 according to several embodiments of the present disclosure. As shown in Figure 1, a power supply circuit 1 according to one embodiment of the present disclosure comprises a DC voltage source Vin, a capacitor Cin, switching elements Q1, Q2, Q3, Q4, diodes Dr1, Dr2, Dr3, Dr4, inductor Lr, transformer T1, diodes D1, D2, inductor Lo, capacitor Co, load LD, and a power supply control unit 10. The power supply control unit 10 controls the switching of each of the switching elements Q1, Q2, Q3, and Q4. For example, switching elements Q1 and Q2 constitute a leg, and alternate between the on state and the off state. Similarly, switching elements Q3 and Q4 constitute a leg, and alternate between the on state and the off state. Hereinafter, as specific examples of switching elements Q1, Q2, Q3, and Q4, MOS (Metal Oxide Semiconductor) transistors are given, and the power supply circuit 1 will be described assuming that the power supply control unit 10 controls the switching of these MOS transistors.

[0011] Figure 2 shows an example of the configuration of a power supply circuit 1 when the switching elements Q1, Q2, Q3, and Q4 according to some embodiments of the present disclosure are MOS transistors. As shown in Figure 2, the power supply circuit 1 includes a MOS transistor M1 as the switching element Q1. The power supply circuit 1 also includes a MOS transistor M2 as the switching element Q2. The power supply circuit 1 also includes a MOS transistor M3 as the switching element Q3. The power supply circuit 1 also includes a MOS transistor M4 as the switching element Q4. For example, each of the MOS transistors M1, M2, M3, and M4 is an N(Negative)MOS transistor.

[0012] In Figure 2, the symbol CQ1 represents the output capacitor of MOS transistor M1. The symbol CQ2 represents the output capacitor of MOS transistor M2. The symbol CQ3 represents the output capacitor of MOS transistor M3. The symbol CQ4 represents the output capacitor of MOS transistor M4.

[0013] Also, in FIG. 2, reference sign DQ1 represents the parasitic diode between the drain and source of MOS transistor M1. Also, reference sign DQ2 represents the parasitic diode between the drain and source of MOS transistor M2. Also, reference sign DQ3 represents the parasitic diode between the drain and source of MOS transistor M3. Also, reference sign DQ4 represents the parasitic diode between the drain and source of MOS transistor M4.

[0014] As shown in FIG. 2, transformer T1 includes a primary winding TL1 and a secondary winding TL2. The primary winding TL1 is the winding on the primary side (input side) of transformer T1. Also, the secondary winding TL2 is the winding on the secondary side (output side) of transformer T1.

[0015] The first terminal of DC voltage source Vin is connected to the first terminal of capacitor Cin, the drain of MOS transistor M1, and the drain of MOS transistor M3. The second terminal of DC voltage source Vin is connected to the second terminal of capacitor Cin, the source of MOS transistor M2, and the source of MOS transistor M4.

[0016] The source of MOS transistor M1 is connected to the drain of MOS transistor M2, the anode of diode Dr1, and the cathode of diode Dr2. The source of MOS transistor M3 is connected to the drain of MOS transistor M4 and the first terminal of primary winding TL1.

[0017] The cathode of diode Dr1 is connected to the cathode of diode Dr3 and the first terminal of inductor Lr. The anode of diode Dr2 is connected to the anode of diode Dr4 and the second terminal of inductor Lr. The anode of diode Dr3 is connected to the cathode of diode Dr4 and the second terminal of primary winding TL1.

[0018] The first terminal of the second winding TL2 is connected to the anode of the diode D1. The second terminal of the second winding TL2 is connected to the first terminal of the capacitor Co and the first terminal of the load LD. The third terminal of the second winding TL2 is connected to the anode of the diode D2.

[0019] The cathode of the diode D1 is connected to the cathode of the diode D2 and the first of the inductor Lo. The second terminal of the inductor Lo is connected to the second terminal of the capacitor Co, the second terminal of the load LD, and the first terminal of the power control unit 10.

[0020] The second terminal of the power control unit 10 is connected to the gate of the MOS transistor M1. The third terminal of the power control unit 10 is connected to the gate of the MOS transistor M2. The fourth terminal of the power control unit 10 is connected to the gate of the MOS transistor M3. The fifth terminal of the power control unit 10 is connected to the gate of the MOS transistor M4.

[0021] In the power supply circuit 1 according to an embodiment of the present disclosure, diodes Dr1, Dr2, Dr3, and Dr4 are used to make the current flowing through the inductor Lr flow in one direction. As a result, the magnetic flux of the core in the inductor Lr becomes the magnitude of the first quadrant portion of the magnetic hysteresis curve (B-H curve) described later, and the core loss can be significantly reduced.

[0022] Here, the magnetic hysteresis curve will be described. FIG. 3 is a diagram showing an example of a magnetic hysteresis curve according to some embodiments of the present disclosure. The magnetic hysteresis curve shown in FIG. 3 represents the change in magnetic flux of a magnetic material. The horizontal axis indicates the magnetic field strength H (A / m). The vertical axis indicates the magnetic flux density B (T). In the magnetic hysteresis curve, the region where 0≦H and 0≦B is the first quadrant. Also, the region where H≦0 and 0≦B is the second quadrant. Also, the region where H≦0 and B≦0 is the third quadrant. Also, the region where 0≦H and B≦0 is the fourth quadrant.

[0023] In a magnetic hysteresis curve, the magnetic flux strength H is proportional to the current flowing through the inductor Lr. Therefore, when the current on the primary side of transformer T1 flows in both the positive and negative directions, the current in the inductor Lr connected in series with transformer T1 also flows in both the positive and negative directions. As a result, the magnetic flux density B changes between the positive region (i.e., the first quadrant) and the negative region (i.e., the third quadrant).

[0024] As shown in Figure 3, in the magnetic hysteresis curve for a magnetic material, the trajectory of the magnetic flux density B when the magnetic field strength H increases is different from the trajectory of the magnetic flux density B when the magnetic field strength H decreases (demonstrating the phenomenon of hysteresis). The area within the BH loop in the magnetic hysteresis curve represents the energy loss. Therefore, when the current in the inductor Lr flows in only one direction, the positive direction (i.e., the first quadrant), compared to when the current in the inductor Lr flows in both the positive and negative directions (i.e., both the first and third quadrants), the area of ​​the BH loop becomes significantly smaller, and the energy loss in the core of the inductor Lr per period (i.e., switching period) is significantly reduced.

[0025] Furthermore, when the load LD is a light load, the losses (hereinafter referred to as "switching losses") incurred when the switching elements Q1, Q2, Q3, and Q4 operate can be reduced by increasing the inductance value of the inductor Lr. However, increasing the inductance value requires either increasing the number of turns of the inductor Lr or increasing the effective cross-sectional area of ​​the inductor Lr's core.

[0026] For example, when switching element Q2 transitions from the off state to the on state, a period is provided during which both switching elements Q2 and Q1 are in the off state (hereinafter referred to as the "dead time period") before switching element Q2 transitions to the ON state. In this case, during the dead time period (i.e., the period during which both switching elements Q1 and Q2 are in the off state), switching element Q2 uses the magnetic energy stored in inductor Lr (energy stored due to the flow of current in the order of switching element Q1, inductor Lr, first winding TL1, and switching element Q4 in the previous state) to extract the charge stored in the output capacitance of switching element Q2 (parasitic capacitance of switching element Q2). Then, if the Vds (drain-source voltage) of switching element Q2 drops to zero before switching element Q2 turns ON (an ON signal is applied to the gate of switching element Q2), switching element Q2 is turned ON. As a result, switching element Q2 becomes zero-voltage switching, which reduces switching losses. Under light load conditions, before switching element Q2 turns on (when both switching elements Q1 and Q4 are on, and current flows in the order of switching element Q1, inductor Lr, first winding TL1, and switching element Q4), the current flowing through inductor Lr is small (because the load current is small, the current flowing through the first winding TL1 is also small), and therefore the energy stored in inductor Lr is also small. As a result, the charge stored in the output capacitance of switching element Q2 cannot be extracted during the dead time period (the period when both switching elements Q1 and Q2 are off) (the Vds (drain-source voltage) of switching element Q2 decreases. However, the Vds (drain-source voltage) of switching element Q2 cannot be reduced to zero). Consequently, the Vds (drain-source voltage) of switching element Q2 remains at a voltage, and switching element Q2 transitions to the ON state in this state. Therefore, switching losses occur in switching element Q2. Therefore, in order to perform zero-voltage switching for the switching element Q2 under light load conditions, it is necessary to increase the energy stored in the inductor Lr.However, the current value before switching element Q2 turns on (i.e., when both switching elements Q1 and Q4 are on, and current flows in the order of switching element Q1, inductor Lr, first winding TL1, and switching element Q4) is determined by the load current and therefore cannot be increased. As a result, in order to perform zero-voltage switching for switching element Q2 under light load conditions, the inductance of inductor Lr needs to be increased.

[0027] Normally, when the inductor current flows in both the positive and negative directions (i.e., both the first and third quadrants), ferrite, which has low core losses in the inductor Lr, is used as the magnetic material for the core. However, in this case, the saturation magnetic flux density is small, so the number of turns of the inductor Lr needs to be increased. On the other hand, when a magnetic material with a large magnetic flux density B (for example, a metallic dust core (Sendust, Hyflux, etc.)) is used for the core of the inductor Lr, the number of turns of the inductor Lr can be reduced. However, when the inductor current flows in both the positive and negative directions, the core losses of the inductor Lr become large. Therefore, as in one embodiment of this disclosure, by making the current flowing through the inductor Lr unidirectional, the change in magnetic flux density B is limited to only the first quadrant in the magnetic hysteresis curve, thereby reducing the core losses of the inductor Lr and enabling miniaturization of the inductor Lr.

[0028] In the case of metal dust cores, the air gap is evenly distributed within the magnetic material. Therefore, the inductance of inductor Lr is largest when the current flowing through inductor Lr is zero. Also, the inductance of inductor Lr decreases as the current flowing through inductor Lr increases.

[0029] The above-described processing performed by the power supply circuit 1 according to one embodiment of this disclosure is merely an example and is not limited to the above-described processing. For example, the power supply circuit 1 may perform the processing described below.

[0030] (Processing performed by the power supply circuit) Next, the processes performed by the power supply circuit 1 will be described. Figure 4 is a diagram showing an example of a time chart of the power supply circuit 1 according to some embodiments of the present disclosure. Here, the processes performed by the power supply circuit 1 will be described with reference to the time chart shown in Figure 4. Note that each of the switching elements Q1, Q2, Q3, and Q4 is an NMOS transistor (i.e., MOS transistors M1, M2, M3, and M4). Furthermore, MOS transistors M1 and M2 are provided with a dead time in which they are both in an off state under the control of the power supply control unit 10, and alternate between the on state and the off state with a duty cycle of approximately 50%. Furthermore, MOS transistors M3 and M4 are provided with a dead time in which they are both in an off state under the control of the power supply control unit 10, and alternate between the on state and the off state with a duty cycle of approximately 50%.

[0031] First, let's explain the process performed by the power supply circuit 1 during period A of the time chart shown in Figure 4. The power supply control unit 10 applies a high-level voltage, as shown in Figure 4, to the gates of MOS transistors M1 and M4. The power supply control unit 10 also applies a low-level voltage, as shown in Figure 4, to the gates of MOS transistors M2 and M3. As a result, MOS transistors M1 and M4 are turned ON, while MOS transistors M2 and M3 are turned OFF. Consequently, while the DC voltage source Vin charges the capacitor Cin, current flows in the following order: MOS transistor M1, diode Dr1, inductor Lr, diode Dr4, first winding TL1, and MOS transistor M4. In this case, the voltage applied to inductor Lr is the DC voltage source Vin minus the forward voltages of diodes Dr1 and Dr4, and inductor Lr stores energy.

[0032] Furthermore, a current flows through the second winding TL2 of transformer T1, corresponding to the ratio of the number of windings in the second winding TL2 to the number of windings in the first winding TL1. This current flowing through the second winding TL2 of transformer T1 charges the capacitor Co through diode D2 and inductor Lo, and is also supplied to the load LD.

[0033] Next, we will explain the processing performed by the power supply circuit 1 during period B of the time chart shown in Figure 4. The power supply control unit 10 applies a high-level voltage, as shown in Figure 4, to the gates of MOS transistors M1 and M3. The power supply control unit 10 also applies a low-level voltage, as shown in Figure 4, to the gates of MOS transistors M2 and M4. As a result, MOS transistors M1 and M3 turn ON. MOS transistors M2 and M4 turn OFF. When MOS transistor M4 turns OFF during the switch from period A to period B, the output capacitor CQ4 is charged by the current flowing through MOS transistor M4. This charging slows down the rise time of the source-drain voltage of MOS transistor M4. During this period of slowed rise time, the source-drain voltage of MOS transistor M4 is almost zero. This causes MOS transistor M4 to enter a switching state due to zero-voltage switching. Zero-voltage switching, also known as ZVS (Zero Voltage Switching), is a method of switching when the voltage is zero. As a result, current flows through MOS transistor M4 when the source-drain voltage is zero, reducing the switching loss caused by MOS transistor M4.

[0034] When the output capacitor QC4 of MOS transistor M4 is charged and the source-drain voltage of MOS transistor M4 reaches the output voltage of the DC voltage source Vin, the parasitic diode DQ3 of MOS transistor M3 turns on. In this state (i.e., when the parasitic diode DQ3 is turned on), MOS transistor M3 switches from the off state to the on state, resulting in a zero-voltage switching state. As a result, current flows through MOS transistor M3 with zero source-drain voltage, reducing the switching loss of MOS transistor M3.

[0035] In period B of the time chart shown in Figure 4, the current flows in the following order: MOS transistor M1, diode Dr1, inductor Lr, diode Dr4, first winding TL1, and MOS transistor M3.

[0036] Furthermore, a current flows through the second winding TL2 of transformer T1, corresponding to the ratio of the number of windings in the second winding TL2 to the number of windings in the first winding TL1. This current flowing through the second winding TL2 of transformer T1 charges the capacitor Co through diode D2 and inductor Lo, and is also supplied to the load LD.

[0037] Next, we will explain the processing performed by the power supply circuit 1 during period C of the time chart shown in Figure 4. The power supply control unit 10 applies a high-level voltage, as shown in Figure 4, to the gates of MOS transistors M2 and M3. The power supply control unit 10 also applies a low-level voltage, as shown in Figure 4, to the gates of MOS transistors M1 and M4. As a result, MOS transistors M2 and M3 turn ON. MOS transistors M1 and M4 turn OFF. When MOS transistor M1 turns OFF during the transition from period B to period C, the output capacitor CQ1 of MOS transistor M1 is charged by the energy stored in the inductor Lr. This charging slows down the rise of the source-drain voltage of MOS transistor M1. During this period of slowed rise, the source-drain voltage of MOS transistor M1 is almost zero. As a result, MOS transistor M1 enters a state of switching by zero-voltage switching.

[0038] When the output capacitor QC1 of MOS transistor M1 is charged and the source-drain voltage of MOS transistor M1 reaches the output voltage of the DC voltage source Vin, the parasitic diode DQ2 of MOS transistor M2 turns on. In this state (i.e., when the parasitic diode DQ2 is turned on), MOS transistor M2 switches from the off state to the on state, resulting in a zero-voltage switching state. As a result, current flows through MOS transistor M2 with zero source-drain voltage, reducing the switching loss of MOS transistor M2.

[0039] During period C of the time chart shown in Figure 4, the current flows in the following order: MOS transistor M3, first winding TL1, diode Dr3, inductor Lr, diode Dr2, and MOS transistor M2.

[0040] Furthermore, a current flows through the second winding TL2 of transformer T1, corresponding to the ratio of the number of windings in the first winding TL1 to the number of windings in the second winding TL2. This current flowing through the second winding TL2 of transformer T1 charges the capacitor Co through diode D1 and inductor Lo, and is also supplied to the load LD.

[0041] Next, we will explain the processing performed by the power supply circuit 1 during period D of the time chart shown in Figure 4. The power supply control unit 10 applies a high-level voltage, as shown in Figure 4, to the gates of MOS transistors M2 and M4. The power supply control unit 10 also applies a low-level voltage, as shown in Figure 4, to the gates of MOS transistors M1 and M3. As a result, MOS transistors M2 and M4 turn ON. MOS transistors M1 and M3 turn OFF. When MOS transistor M3 turns OFF during the transition from period C to period D, the output capacitor CQ3 of MOS transistor M3 is charged by the energy stored in the inductor Lr. This charging slows down the rise time of the source-drain voltage of MOS transistor M3. During this period of slowed rise time, the source-drain voltage of MOS transistor M3 is almost zero. As a result, MOS transistor M3 enters a state of switching by zero-voltage switching.

[0042] When the output capacitor QC3 of MOS transistor M3 is charged and the source-drain voltage of MOS transistor M3 reaches the output voltage of the DC voltage source Vin, the parasitic diode DQ4 of MOS transistor M4 turns on. In this state (i.e., when the parasitic diode DQ4 is turned on), MOS transistor M4 switches from the off state to the on state, resulting in a zero-voltage switching state. As a result, current flows through MOS transistor M4 when the source-drain voltage of MOS transistor M4 is zero, and the switching loss by MOS transistor M4 is reduced.

[0043] In the time chart shown in Figure 4, during period D, the current flows in the following order: MOS transistor M4, first winding TL1, diode Dr3, inductor Lr, diode Dr2, and MOS transistor M2.

[0044] Furthermore, a current flows through the second winding TL2 of transformer T1, corresponding to the ratio of the number of windings in the first winding TL1 to the number of windings in the second winding TL2. This current flowing through the second winding TL2 of transformer T1 charges the capacitor Co through diode D1 and inductor Lo, and is also supplied to the load LD.

[0045] During the transition from period D to period A, when the MOS transistor M2 turns off, the energy stored in the inductor Lr charges the output capacitor CQ2 of the MOS transistor M2. This charging slows down the rise of the source-drain voltage of the MOS transistor M2. During this period of slowed rise, the source-drain voltage of the MOS transistor M2 is almost zero. As a result, the MOS transistor M2 enters a state of switching by zero-voltage switching.

[0046] When the output capacitor QC2 of MOS transistor M2 is charged and the source-drain voltage of MOS transistor M2 reaches the output voltage of the DC voltage source Vin, the parasitic diode DQ1 of MOS transistor M1 turns on. In this state (i.e., when the parasitic diode DQ1 is turned on), MOS transistor M1 switches from the off state to the on state, resulting in a zero-voltage switching state. As a result, current flows through MOS transistor M1 with zero source-drain voltage, reducing the switching loss of MOS transistor M1.

[0047] Furthermore, the power supply control unit 10 controls the gate voltages of MOS transistors M1, M2, M3, and M4, causing transitions to occur in the order of period A, period B, period C, and period D, and these transitions are repeated. In addition, the voltage Vo applied to the load LD is fed back to the power supply control unit 10, and the power supply control unit 10 stabilizes the output voltage Vo to a specified value by controlling the phase of the control signals that control the gates of MOS transistors M1, M2, M3, and M4 (i.e., the switching timing of MOS transistors M1, M2, M3, and M4).

[0048] (advantage) The power supply circuit 1 according to one embodiment of the present disclosure has been described above. The power supply circuit 1 comprises a transformer T1 (an example of a transformer) having a first winding TL1 (an example of a primary winding) and a second winding TL2 (an example of a secondary winding), a full bridge circuit having four switching elements Q1, Q2, Q3, and Q4 (an example of four switching elements), an inductor Lr (an example of an inductor) provided between the first winding TL1 and the full bridge circuit, and MOS transistors M1, M2, M3, and M4 (an example of a rectifier circuit) configured such that the current flowing through the inductor Lr is unidirectional.

[0049] This power supply circuit 1 causes a change in the magnetic flux of the core inside the inductor Lr to occur in the first quadrant. As a result, core losses are reduced, making it possible to use a core made of dust-based material such as Sendust. In other words, this power supply circuit 1 can reduce the losses in the core inside the inductor Lr.

[0050] Furthermore, when using a dust-based material core, it is easy to realize an inductor Lr with characteristics such that the inductance value increases when the inductor current is small and decreases when the inductor current is large. Also, under the condition of the same inductance value, an inductor using a dust-based material core has a higher saturation magnetic flux density than an inductor using a ferrite material core (for example, metallic dust cores (Sendust, Hyflux, etc.) have a higher saturation magnetic flux density as a material characteristic compared to cores using ferrite material (generally more than twice)), so the number of turns can be reduced compared to an inductor using a ferrite material core. As a result, the inductor Lr can be made smaller.

[0051] Furthermore, regarding the switching losses of switching elements Q1, Q2, Q3, and Q4, as the load current decreases, the inductance value of the inductor Lr increases, making it possible to reduce switching losses even with lighter loads LD.

[0052] <First modified example of the embodiment> (Power supply circuit configuration) Figure 5 shows an example of the configuration of a power supply circuit 1 according to several embodiments of the present disclosure. A first modified example of a power supply circuit 1 according to one embodiment of the present disclosure will be described with reference to the drawings.

[0053] The power supply circuit 1 according to the first modification of one embodiment of the present disclosure is the same as the power supply circuit 1 shown in Figure 2, but utilizes the midpoint of the inductor Lr and changes the four diodes Dr1, Dr2, Dr3, and Dr4 to two diodes Dr1 and Dr2. The power supply circuit 1 according to the first modification of one embodiment of the present disclosure, as shown in Figure 5, comprises a DC voltage source Vin, a capacitor Cin, switching elements Q1, Q2, Q3, and Q4, diodes Dr1 and Dr2, an inductor Lr, a transformer T1, diodes D1 and D2, an inductor Lo, a capacitor Co, a load LD, and a power supply control unit 10.

[0054] The first terminal of the DC voltage source Vin is connected to the first terminal of capacitor Cin, the drain of MOS transistor M1, and the drain of MOS transistor M3. The second terminal of the DC voltage source Vin is connected to the second terminal of capacitor Cin, the source of MOS transistor M2, and the source of MOS transistor M4.

[0055] The source of MOS transistor M1 is connected to the drain of MOS transistor M2, the anode of diode Dr1, and the cathode of diode Dr2. The source of MOS transistor M3 is connected to the drain of MOS transistor M4 and the first terminal of the first winding TL1.

[0056] The cathode of diode Dr1 is connected to the first terminal of inductor Lr. The anode of diode Dr2 is connected to the second terminal of inductor Lr. The third terminal of inductor Lr is connected to the second terminal of the first winding TL1. Note that the third terminal of inductor Lr is the terminal located at the midpoint of inductor Lr.

[0057] The first terminal of the second winding TL2 is connected to the anode of diode D1. The second terminal of the second winding TL2 is connected to the first terminal of capacitor Co and the first terminal of load LD. The third terminal of the second winding TL2 is connected to the anode of diode D2.

[0058] The cathode of diode D1 is connected to the cathode of diode D2 and to the first terminal of inductor Lo. The second terminal of inductor Lo is connected to the second terminal of capacitor Co, the second terminal of load LD, and the first terminal of power supply control unit 10.

[0059] The second terminal of the power control unit 10 is connected to the gate of MOS transistor M1. The third terminal of the power control unit 10 is connected to the gate of MOS transistor M2. The fourth terminal of the power control unit 10 is connected to the gate of MOS transistor M3. The fifth terminal of the power control unit 10 is connected to the gate of MOS transistor M4.

[0060] (Processing performed by the power supply circuit) Next, the processing performed by the power supply circuit 1 will be described. Each of the switching elements Q1, Q2, Q3, and Q4 is assumed to be an NMOS transistor (i.e., MOS transistors M1, M2, M3, and M4). Furthermore, MOS transistors M1 and M2 are provided with a dead time in which they are both in an off state under the control of the power supply control unit 10, and alternate between the on and off states with a duty cycle of approximately 50%. Similarly, MOS transistors M3 and M4 are provided with a dead time in which they are both in an off state under the control of the power supply control unit 10, and alternate between the on and off states with a duty cycle of approximately 50%.

[0061] Furthermore, the power supply control unit 10 controls the gate voltages of MOS transistors M1, M2, M3, and M4, causing transitions to occur in the order of period A, period B, period C, and period D, and these transitions are repeated. In addition, the voltage Vo applied to the load LD is fed back to the power supply control unit 10, and the power supply control unit 10 stabilizes the output voltage Vo to a specified value by controlling the phase of the control signals that control the gates of MOS transistors M1, M2, M3, and M4 (i.e., the switching timing of MOS transistors M1, M2, M3, and M4).

[0062] When MOS transistor M1 is ON, current flows in the following order: MOS transistor M1, diode Dr1, inductor Lr (from terminal 1 to terminal 3), and first winding TL1. When MOS transistor M2 is ON, current flows in the following order: first winding TL1, inductor Lr (from terminal 3 to terminal 2), diode Dr2, and MOS transistor M2.

[0063] (advantage) With this power supply circuit 1, the magnetic flux in the core of the inductor Lr is limited to the magnitude of the first quadrant only. As a result, the power supply circuit 1 according to the first modified embodiment of the present disclosure can achieve the same effects as the power supply circuit 1 according to the present disclosure embodiment.

[0064] <Second Modification of the Embodiment> (Power supply circuit configuration) Figure 6 shows an example of the configuration of a power supply circuit 1 according to several embodiments of the present disclosure. A second modified example of a power supply circuit 1 according to one embodiment of the present disclosure will be described with reference to the drawings.

[0065] The power supply circuit 1 according to a second modification of one embodiment of the present disclosure is obtained by replacing the four diodes Dr1, Dr2, Dr3, and Dr4 with four switching elements Qr1, Qr2, Qr3, and Qr4 compared to the power supply circuit 1 shown in Figure 2. Each of the four switching elements Qr1, Qr2, Qr3, and Qr4 is, for example, a transistor. As shown in Figure 6, the power supply circuit 1 according to a second modification of one embodiment of the present disclosure comprises a DC voltage source Vin, a capacitor Cin, switching elements Q1, Q2, Q3, and Q4, switching elements Qr1, Qr2, Qr3, and Qr4, an inductor Lr, a transformer T1, diodes D1 and D2, an inductor Lo, a capacitor Co, a load LD, and a power supply control unit 10.

[0066] The first terminal of the DC voltage source Vin is connected to the first terminal of capacitor Cin, the drain of MOS transistor M1, and the drain of MOS transistor M3. The second terminal of the DC voltage source Vin is connected to the second terminal of capacitor Cin, the source of MOS transistor M2, and the source of MOS transistor M4.

[0067] The source of MOS transistor M1 is connected to the drain of MOS transistor M2, the first terminal of switching element Qr1, and the first terminal of switching element Qr2. The source of MOS transistor M3 is connected to the drain of MOS transistor M4 and the first terminal of the first winding TL1.

[0068] The second terminal of switching element Qr1 is connected to the first terminal of switching element Qr3 and the first terminal of inductor Lr. The second terminal of switching element Qr2 is connected to the first terminal of switching element Qr4 and the second terminal of inductor Lr. The second terminal of switching element Qr3 is connected to the second terminal of switching element Qr4 and the second terminal of the first winding TL1.

[0069] The first terminal of the second winding TL2 is connected to the anode of diode D1. The second terminal of the second winding TL2 is connected to the first terminal of capacitor Co and the first terminal of load LD. The third terminal of the second winding TL2 is connected to the anode of diode D2.

[0070] The cathode of diode D1 is connected to the cathode of diode D2 and to the first terminal of inductor Lo. The second terminal of inductor Lo is connected to the second terminal of capacitor Co, the second terminal of load LD, and the first terminal of power supply control unit 10.

[0071] The second terminal of the power control unit 10 is connected to the gate of MOS transistor M1. The third terminal of the power control unit 10 is connected to the gate of MOS transistor M2. The fourth terminal of the power control unit 10 is connected to the gate of MOS transistor M3. The fifth terminal of the power control unit 10 is connected to the gate of MOS transistor M4.

[0072] (Processing performed by the power supply circuit) Next, the processing performed by the power supply circuit 1 will be explained. The power supply control unit 10 transmits control signals to the third terminals of each of the switching elements Qr1, Qr2, Qr3, and Qr4. As a result, switching elements Qr1 and Qr4 turn on or off at the same timing as MOS transistor M1. Switching elements Qr2 and Qr3 also turn on or off at the same timing as MOS transistor M2.

[0073] Furthermore, other processes performed by the power supply circuit 1 according to the second modified embodiment of this disclosure are the same as those performed by the power supply circuit 1 according to the embodiment of this disclosure.

[0074] (advantage) With this power supply circuit 1, even if the diodes Dr1, Dr2, Dr3, and Dr4 are replaced with switching elements Qr1, Qr2, Qr3, and Qr4, the power supply circuit 1 can reduce conduction losses.

[0075] <Third Modification of the Embodiment> (Power supply circuit configuration) Figure 7 shows an example of the configuration of a power supply circuit 1 according to several embodiments of the present disclosure. A third modified example of a power supply circuit 1 according to one embodiment of the present disclosure will be described with reference to the drawings.

[0076] The power supply circuit 1 according to a third modification of one embodiment of the present disclosure is obtained by replacing the two diodes Dr1 and Dr2 with two switching elements Qr1 and Qr2 compared to the power supply circuit 1 shown in Figure 5. Each of the two switching elements Qr1 and Qr2 is, for example, a transistor. As shown in Figure 7, the power supply circuit 1 according to a third modification of one embodiment of the present disclosure comprises a DC voltage source Vin, a capacitor Cin, switching elements Q1, Q2, Q3, Q4, switching elements Qr1 and Qr2, an inductor Lr, a transformer T1, diodes D1 and D2, an inductor Lo, a capacitor Co, a load LD, and a power supply control unit 10.

[0077] The first terminal of the DC voltage source Vin is connected to the first terminal of capacitor Cin, the drain of MOS transistor M1, and the drain of MOS transistor M3. The second terminal of the DC voltage source Vin is connected to the second terminal of capacitor Cin, the source of MOS transistor M2, and the source of MOS transistor M4.

[0078] The source of MOS transistor M1 is connected to the drain of MOS transistor M2, the first terminal of switching element Qr1, and the first terminal of switching element Qr2. The source of MOS transistor M3 is connected to the drain of MOS transistor M4 and the first terminal of the first winding TL1.

[0079] The second terminal of switching element Qr1 is connected to the first terminal of inductor Lr. The second terminal of switching element Qr2 is connected to the second terminal of inductor Lr. The third terminal of inductor Lr is connected to the second terminal of the first winding TL1. Note that the third terminal of inductor Lr is a terminal located at the midpoint of inductor Lr.

[0080] The first terminal of the second winding TL2 is connected to the anode of diode D1. The second terminal of the second winding TL2 is connected to the first terminal of capacitor Co and the first terminal of load LD. The third terminal of the second winding TL2 is connected to the anode of diode D2.

[0081] The cathode of diode D1 is connected to the cathode of diode D2 and to the first terminal of inductor Lo. The second terminal of inductor Lo is connected to the second terminal of capacitor Co, the second terminal of load LD, and the first terminal of power supply control unit 10.

[0082] The second terminal of the power control unit 10 is connected to the gate of MOS transistor M1. The third terminal of the power control unit 10 is connected to the gate of MOS transistor M2. The fourth terminal of the power control unit 10 is connected to the gate of MOS transistor M3. The fifth terminal of the power control unit 10 is connected to the gate of MOS transistor M4.

[0083] (Processing performed by the power supply circuit) Next, the processing performed by the power supply circuit 1 will be explained. The power supply control unit 10 transmits control signals to the third terminals of switching elements Qr1 and Qr2. As a result, switching element Qr1 turns on or off at the same timing as MOS transistor M1. Similarly, switching element Qr2 turns on or off at the same timing as MOS transistor M2.

[0084] Furthermore, other processes performed by the power supply circuit 1 according to the third modified example of one embodiment of this disclosure are the same as those performed by the power supply circuit 1 according to the first modified example of one embodiment of this disclosure.

[0085] (advantage) With this power supply circuit 1, even if diodes Dr1 and Dr2 are replaced with switching elements Qr1 and Qr2, the power supply circuit 1 can reduce conduction losses.

[0086] Figure 8 shows an example of the configuration of a power supply circuit 700 according to some embodiments of the present disclosure. As shown in Figure 8, the power supply circuit 700 comprises a transformer 701, a full-bridge circuit 702, an inductor 703, and a rectifier circuit 704. The transformer 701 has a primary winding and a secondary winding. The full-bridge circuit 702 has four switching elements. The inductor 703 is provided between the primary winding and the full-bridge circuit. The rectifier circuit 704 is configured so that the current flowing through the inductor is unidirectional.

[0087] The power supply circuit 700 can be realized, for example, using the functions of the power supply circuit 1 illustrated in Figures 1, 2, 5, 6, and 7. The transformer 701 can be realized, for example, using the functions of the transformer T1 illustrated in Figures 1, 2, 5, 6, and 7. The full-bridge circuit 702 can be realized, for example, using the functions of the switching elements Q1, Q2, Q3, and Q4 illustrated in Figures 1, 2, 5, 6, and 7. The inductor 703 can be realized, for example, using the functions of the inductor Lr illustrated in Figures 1, 2, 5, 6, and 7. The rectifier circuit 704 can be realized, for example, using the functions of the diodes Dr1, Dr2, Dr3, and Dr4, and the transistors Qr1, Qr2, Qr3, and Qr4 illustrated in Figures 1, 2, 5, 6, and 7.

[0088] Several embodiments of the power supply circuit 700 according to the present disclosure have been described above. This power supply circuit 700 can reduce the core loss in the inductor.

[0089] In addition, the order of the processes in each embodiment of this disclosure may be changed, as long as appropriate processing is performed.

[0090] Although each embodiment of this disclosure has been described, the power supply circuit 1, power supply control unit 10, and other control devices described above may have a computer system inside. The process described above is stored in the form of a program on a computer-readable recording medium, and the above process is performed when the computer reads and executes this program. A specific example of a computer is shown below.

[0091] Figure 9 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in Figure 9, the computer 5 includes a CPU (Central Processing Unit) 6, main memory 7, storage 8, and interface 9.

[0092] For example, the power supply circuit 1, power supply control unit 10, and other control devices described above are each implemented in the computer 5. The operation of each of the above-described processing units is stored in storage 8 in the form of a program. The CPU 6 reads the program from storage 8, loads it into main memory 7, and executes the above-described processing according to the program. The CPU 6 also allocates memory areas in main memory 7 corresponding to each of the above-described storage units according to the program.

[0093] Examples of storage 8 include HDDs (Hard Disk Drives), SSDs (Solid State Drives), magnetic disks, magneto-optical disks, CD-ROMs (Compact Disc Read Only Memory), DVD-ROMs (Digital Versatile Disc Read Only Memory), and semiconductor memory. Storage 8 may be an internal medium directly connected to the bus of computer 5, or an external medium connected to computer 5 via interface 9 or a communication line. Furthermore, if this program is distributed to computer 5 via a communication line, computer 5, upon receiving the program, may expand it into main memory 7 and execute the above processing. In at least one embodiment, storage 8 is a tangible storage medium that is not temporary.

[0094] Furthermore, the above program may implement some of the functions described above. Moreover, the above program may be a file that can implement the above functions in combination with a program already recorded in the computer system, a so-called differential file (differential program).

[0095] While several embodiments of this disclosure have been described, these embodiments are illustrative and do not limit the scope of the disclosure. These embodiments may be modified in various ways, without departing from the gist of the disclosure.

[0096] Furthermore, some or all of the above embodiments may also be described as follows, but are not limited to these.

[0097] (Note 1) A transformer having a primary winding and a secondary winding, A full bridge circuit having four switching elements, An inductor provided between the primary winding and the full bridge circuit, A rectifier circuit configured such that the current flowing through the inductor is unidirectional, A power supply circuit equipped with the following features.

[0098] (Note 2) The rectifier circuit described above is A first subcircuit in which a first element and a second element are connected in series, the first subcircuit connected in parallel with the inductor, A second subcircuit in which a third element and a fourth element are connected in series, and a second subcircuit connected in parallel with the inductor, Equipped with, The first terminal of the full-bridge circuit is, The first element and the second element are connected to a connecting node, The second terminal of the full-bridge circuit is Connected to the first terminal of the inductor, The second terminal of the inductor is The third element and the fourth element are connected to a connecting node, The power supply circuit described in Appendix 1.

[0099] (Note 3) Each of the first element, the second element, the third element, and the fourth element is: It is a diode. The power supply circuit described in Appendix 2.

[0100] (Note 4) Each of the first element, the second element, the third element, and the fourth element is: It is a transistor. The power supply circuit described in Appendix 2.

[0101] (Note 5) The rectifier circuit described above is A subcircuit in which a first element and a second element are connected in series, and a subcircuit connected in parallel with the inductor, Equipped with, The first terminal of the full-bridge circuit is, The first element and the second element are connected to a connecting node, The second terminal of the full-bridge circuit is Connected to the first terminal of the inductor, The second terminal of the inductor is Connected to the midpoint of the aforementioned inductor, The power supply circuit described in Appendix 1.

[0102] (Note 6) Each of the first element and the second element is, It is a diode. The power supply circuit described in Appendix 5.

[0103] (Note 7) Each of the first element and the second element is, It is a transistor. The power supply circuit described in Appendix 5.

[0104] (Note 8) The aforementioned inductor is Having a core made of metallic dust, The power supply circuit described in any one of the appendices 1 through 7.

[0105] (Note 9) The aforementioned metallic dust is Sendust or Hyflux The power supply circuit described in Appendix 8. [Explanation of Symbols]

[0106] 1...Power supply circuit 5. Computers 6..CPU 7. Main Memory 8. Storage 9. Interface 10. Power supply control unit Cin... Capacitor Co...capacitor D1, D2... Diodes DQ1, DQ2, DQ3, DQ4... Parasitic diodes Dr1, Dr2, Dr3, Dr4... Diodes LD...Load Lo, Lr... Inductor Q1, Q2, Q3, Q4... Switching elements T1...transformer TL1 ···First winding TL2 ···Second winding Vin... DC voltage source

Claims

1. A transformer having a primary winding and a secondary winding, A full bridge circuit having four switching elements, An inductor provided between the primary winding and the full bridge circuit, A rectifier circuit configured such that the current flowing through the inductor is unidirectional, A power supply circuit equipped with the following features.

2. The rectifier circuit described above is A first subcircuit in which a first element and a second element are connected in series, the first subcircuit connected in parallel with the inductor, A second subcircuit in which a third element and a fourth element are connected in series, and a second subcircuit connected in parallel with the inductor, Equipped with, The first terminal of the full-bridge circuit is, The first element and the second element are connected to a connecting node, The second terminal of the full-bridge circuit is Connected to the first terminal of the inductor, The second terminal of the inductor is The third element and the fourth element are connected to a connection node, The power supply circuit according to claim 1.

3. Each of the first element, the second element, the third element, and the fourth element is: It is a diode. The power supply circuit according to claim 2.

4. Each of the first element, the second element, the third element, and the fourth element is: It is a transistor. The power supply circuit according to claim 2.

5. The rectifier circuit described above is A subcircuit in which a first element and a second element are connected in series, and a subcircuit connected in parallel with the inductor, Equipped with, The first terminal of the full-bridge circuit is, The first element and the second element are connected to a connecting node, The second terminal of the full-bridge circuit is Connected to the first terminal of the inductor, The second terminal of the inductor is Connected to the midpoint of the aforementioned inductor, The power supply circuit according to claim 1.

6. Each of the first element and the second element is, It is a diode. The power supply circuit according to claim 5.

7. Each of the first element and the second element is, It is a transistor. The power supply circuit according to claim 5.

8. The aforementioned inductor is Having a core made of metallic dust, The power supply circuit according to claim 1.

9. The aforementioned metallic dust is Sendust or Hyflux The power supply circuit according to claim 8.

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