Shift register unit and its driving method, gate driving circuit and display device

Abstract

The shift register unit (10) includes a blanking input circuit (100), a display input circuit (200), and an output circuit (300). The blanking input circuit (100) is configured to input a blanking pull-up signal to a first control node (Q) during a blanking period based on a blanking input signal and a blanking control signal, thereby compensating the blanking input circuit (100). The display input circuit (200) is configured to input a display pull-up signal to the first control node (Q) during a display period in response to the display input signal. The output circuit (300) is configured to output a composite output signal to an output terminal (OP). The shift register unit (10) can improve threshold voltage loss when the blanking input circuit (100) controls (e.g., pulls up) the level of the first control node (Q), preventing it from affecting the potential of the first control node (Q).

Description

Technical Field

[0005] , ,

[0001] This application claims the priority of Chinese Patent Application No. 201810792877.7 filed on July 18, 2018, the entire content of which is incorporated herein by reference as part of this application.

[0002] Embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.

Background Art

[0003] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines arranged alternately with them. The gate lines can be driven by a gate driving circuit. The gate driving circuit is usually incorporated in a gate driving chip (Gate IC).

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure provides a shift register unit, including a blanking input circuit, a display input circuit, and an output circuit. The blanking input circuit inputs a blanking pull-up signal to a first control node during a blanking period based on a blanking input signal and a blanking control signal, and is arranged to compensate itself. The display input circuit is arranged to input a display pull-up signal to the first control node during a display period in response to a display input signal. The output circuit is arranged to output a composite output signal to an output terminal by controlling the level of the first control node.

[0005] For example, a shift register unit according to one embodiment of the present disclosure further includes a noise reduction circuit and a first control circuit, wherein the noise reduction circuit is configured to perform noise reduction on the first control node and the output terminal by controlling the level of the second control node, and the first control circuit is configured to control the level of the second control node by controlling the level of the first control node.

[0006] For example, in a shift register unit according to one embodiment of the present disclosure, the blanking input circuit includes a charging subcircuit arranged to input the blanking input signal to a first node in response to the blanking control signal; a compensation subcircuit arranged to store the blanking input signal input by the charging subcircuit, compensate the level of the first node in response to a first clock signal, and couple-control the level of a second node; and an isolation subcircuit arranged to input the blanking pull-up signal to the first control node in order to control the level of the second node.

[0007] For example, in a shift register unit according to one embodiment of the present disclosure, the blanking input circuit further includes a control subcircuit arranged to control the level of the second control node, in the control of the level of the second control node.

[0008] For example, in a shift register unit according to one embodiment of the present disclosure, the charging subcircuit includes a first transistor, the gate of which is connected to a random signal terminal to receive a random signal as the blanking control signal, the first pole of which is connected to a blanking input signal terminal to receive the blanking input signal, and the second pole of which is connected to the first node; the compensation subcircuit includes a second transistor and a first capacitor, the gate of which is connected to the first node, the first pole of which is connected to a first clock signal terminal to receive the first clock signal, and the second pole of which is connected to the second node; and the first The first pole of the capacitor is arranged to be connected to the first node, the second pole of the first capacitor is arranged to be connected to the second node, the isolation subcircuit includes a third transistor, the gate of the third transistor is arranged to be connected to the second node, the first pole of the third transistor is arranged to be connected to a first voltage terminal to receive a first voltage as the blanking pull-up signal, the second pole of the third transistor is arranged to be connected to the first control node, the control subcircuit includes a fourth transistor, the gate of the fourth transistor is arranged to be connected to the second control node, the first pole of the fourth transistor is arranged to be connected to the second node, and the second pole of the fourth transistor is arranged to be connected to a second voltage terminal to receive a second voltage.

[0009] For example, in a shift register unit according to one embodiment of the present disclosure, the display input circuit includes a fifth transistor, the gate of which is connected to a display input signal terminal to receive the display input signal, the first pole of which is connected to a first voltage terminal to receive a first voltage as the display pull-up signal, and the second pole of which is connected to a first control node.

[0010] For example, in a shift register unit according to one embodiment of the present disclosure, the output circuit includes at least one shift signal output terminal and at least one pixel scan signal output terminal.

[0011] For example, in a shift register unit according to one embodiment of the present disclosure, the output circuit includes a sixth transistor, a seventh transistor, and a second capacitor, wherein the gate of the sixth transistor is connected to the first control node, the first pole of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal as the composite output signal, the second pole of the sixth transistor is connected to the shift signal output terminal, the gate of the seventh transistor is connected to the first control node, the first pole of the seventh transistor is connected to the second clock signal terminal to receive the second clock signal as the composite output signal, the second pole of the seventh transistor is connected to the pixel scanning signal output terminal, the first pole of the second capacitor is connected to the first control node, and the second pole of the second capacitor is connected to the second pole of the sixth transistor or the second pole of the seventh transistor.

[0012] For example, in a shift register unit according to one embodiment of the present disclosure, the noise reduction circuit includes an eighth transistor, a ninth transistor, and a tenth transistor, wherein the gate of the eighth transistor is configured to be connected to the second control node, the first pole of the eighth transistor is configured to be connected to the first control node, the second pole of the eighth transistor is configured to be connected to a third voltage terminal for receiving a third voltage, the gate of the ninth transistor is configured to be connected to the second control node, the first pole of the ninth transistor is configured to be connected to the shift signal output terminal, the second pole of the ninth transistor is configured to be connected to the third voltage terminal for receiving a third voltage, the gate of the tenth transistor is configured to be connected to the second control node, the first pole of the tenth transistor is configured to be connected to the pixel scanning signal output terminal, and the second pole of the tenth transistor is configured to be connected to a fourth voltage terminal for receiving a fourth voltage.

[0013] For example, in a shift register unit according to one embodiment of the present disclosure, the first control circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor, wherein the gate of the eleventh transistor is connected to a first pole and is arranged to be connected to a fifth voltage terminal for receiving a fifth voltage, the second pole of the eleventh transistor is arranged to be connected to the second control node, the gate of the twelfth transistor is connected to a first pole and is arranged to be connected to a sixth voltage terminal for receiving a sixth voltage, the second pole of the twelfth transistor is arranged to be connected to the second control node, the gate of the thirteenth transistor is arranged to be connected to the first control node, the first pole of the thirteenth transistor is arranged to be connected to the second control node, and the second pole of the thirteenth transistor is arranged to be connected to a third voltage terminal for receiving a third voltage.

[0014] For example, a shift register unit according to one embodiment of the present disclosure further includes a blanking reset circuit arranged to reset the first control node in response to a blanking reset signal.

[0015] For example, in a shift register unit according to one embodiment of the present disclosure, the blanking reset circuit includes a 14th transistor, the gate of which is connected to a blanking reset signal terminal to receive the blanking reset signal, the first pole of which is connected to the first control node, and the second pole of which is connected to a third voltage terminal to receive a third voltage.

[0016] For example, a shift register unit according to one embodiment of the present disclosure further includes a display reset circuit arranged to reset the first control node in response to a display reset signal.

[0017] For example, in a shift register unit according to one embodiment of the present disclosure, the display reset circuit includes a 15th transistor, the gate of which is connected to a display reset signal terminal for receiving the display reset signal, the first pole of which is connected to a first control node, and the second pole of which is connected to a third voltage terminal for receiving a third voltage.

[0018] For example, a shift register unit according to one embodiment of the present disclosure further includes a second control circuit arranged to control the level of the second control node in response to a first clock signal or the display input signal.

[0019] For example, in a shift register unit according to one embodiment of the present disclosure, the second control circuit includes a 16th transistor and a 17th transistor, wherein the gate of the 16th transistor is configured to be connected to a first clock signal terminal for receiving the first clock signal, the first pole of the 16th transistor is configured to be connected to the second control node, the second pole of the 16th transistor is configured to receive the third voltage of the third voltage terminal, the gate of the 17th transistor is configured to be connected to a display input signal terminal for receiving the display input signal, the first pole of the 17th transistor is configured to be connected to the second control node, and the second pole of the 17th transistor is configured to be connected to the third voltage terminal for receiving the third voltage.

[0020] At least one embodiment of the present disclosure further provides a gate drive circuit including a shift register unit as described in any embodiment of the present disclosure.

[0021] For example, in a gate drive circuit according to one embodiment of the present disclosure, shift register units every four stages share the same charging subcircuit, the same compensation subcircuit, and the same control subcircuit, the random signal terminal of the 4n-3 stage shift register unit is connected to the random signal line, and the first clock signal terminal of the 4n-3 stage shift register unit is connected to the first clock line (where n is an integer greater than 0).

[0022] For example, a gate drive circuit according to one embodiment of the present disclosure further includes a first subclock signal line, a second subclock signal line, a third subclock signal line, and a fourth subclock signal line, wherein the second clock signal terminal of the 4n-3 stage shift register unit is connected to the first subclock signal line, the second clock signal terminal of the 4n-2 stage shift register unit is connected to the second subclock signal line, the second clock signal terminal of the 4n-1 stage shift register unit is connected to the third subclock signal line, and the second clock signal terminal of the 4n stage shift register unit is connected to the fourth subclock signal line (where n is an integer greater than 0).

[0023] For example, in a gate drive circuit according to one embodiment of the present disclosure, the blanking input signal terminal of the (n+1)th stage shift register unit is connected to the shift signal output terminal of the (n)th stage shift register unit, the display input signal terminal of the (n+2)th stage shift register unit is connected to the shift signal output terminal of the (n)th stage shift register unit, and the display reset signal terminal of the (n+3)th stage shift register unit is connected to the shift signal output terminal of the (n+3)th stage shift register unit (wherein n is an integer greater than 0).

[0024] At least one embodiment of the present disclosure further provides a display device comprising a shift register unit or a gate drive circuit as described in any embodiment of the present disclosure.

[0025] At least one embodiment of the present disclosure further provides a method for driving a shift register unit described in any embodiment of the present disclosure, including a display period and a blanking period for processing an image of one frame. The display period includes a first input stage in which the display input circuit inputs the display pull-up signal to the first control node in response to the display input signal, and a first output stage in which the output circuit outputs the composite output signal to the output terminal under the control of the level of the first control node. The blanking period includes a second input stage in which the blanking input circuit inputs the blanking pull-up signal to the first control node based on the blanking input signal and the blanking control signal and compensates the blanking input circuit itself, and a second output stage in which the output circuit outputs the composite output signal to the output terminal under the control of the level of the first control node.

[0026] To more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. It will be clear that the drawings in the following description are only related to some embodiments of the present disclosure and do not limit the present disclosure.

Brief Description of the Drawings

[0027] [Figure 1] It is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure. [Figure 2] It is a schematic block diagram of a blanking input circuit of a shift register unit according to some embodiments of the present disclosure. [Figure 3] It is a schematic block diagram of a blanking input circuit of another shift register unit according to some embodiments of the present disclosure. [Figure 4] It is a schematic block diagram of another shift register unit according to some embodiments of the present disclosure. [Figure 5] It is a schematic block diagram of another shift register unit according to some embodiments of the present disclosure. [Figure 6]Figure 4 is a circuit diagram of a specific implementation example of the shift register unit. [Figure 7] Figure 5 is a circuit diagram of a specific implementation example of the shift register unit. [Figure 8] Figure 5 is a circuit diagram of another specific implementation example of the shift register unit shown. [Figure 9A] This is a schematic diagram of a specific implementation example of a blanking input circuit for a shift register unit according to some embodiments of the present disclosure. [Figure 9B] This is a schematic diagram of a specific implementation example of a blanking input circuit for a shift register unit according to some embodiments of the present disclosure. [Figure 9C] This is a schematic diagram of a specific implementation example of a blanking input circuit for a shift register unit according to some embodiments of the present disclosure. [Figure 10] This is a circuit diagram of a specific implementation example of a display input circuit for a shift register unit according to some embodiments of the present disclosure. [Figure 11] This is a schematic diagram of a specific implementation example of a second control circuit of a shift register unit according to some embodiments of the present disclosure. [Figure 12] This is a signal timing diagram of a shift register unit according to some embodiments of the present disclosure. [Figure 13] This is a signal timing diagram of another shift register unit according to some embodiments of the present disclosure. [Figure 14] These are schematic block diagrams of gate drive circuits according to some embodiments of the disclosed figures. [Figure 15A] Figure 14 is a circuit diagram showing a specific implementation example of the blanking input circuit for an adjacent 4-stage shift register unit in the gate drive circuit. [Figure 15B] Figure 14 is a circuit diagram showing a specific implementation example of the blanking input circuit for an adjacent 4-stage shift register unit in the gate drive circuit. [Figure 15C] Figure 14 is a circuit diagram showing a specific implementation example of the blanking input circuit for an adjacent 4-stage shift register unit in the gate drive circuit. [Figure 16] This is a signal timing diagram of a gate drive circuit according to some embodiments of the present disclosure. [Figure 17] This is a schematic block diagram of a display device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0028] To further clarify the purpose, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure are described below clearly and completely, together with the drawings of the embodiments of this disclosure. Clearly, the embodiments described are not all embodiments, but rather a selection of the embodiments of this disclosure. All other embodiments that can be obtained by those skilled in the art without requiring any creative effort based on the embodiments of this disclosure described are within the scope of the protection of this disclosure.

[0029] Unless otherwise defined, technical or scientific terms used herein have their ordinary meanings as understood by those skilled in the art. The terms “first,” “second,” and similar terms used herein are not intended to indicate order, quantity, or importance, but are used solely to distinguish different components. Similarly, similar words such as “contains” and “includes” mean that the element or object appearing before the word covers the element or object and their equivalents appearing after the word without excluding other elements or objects. Similar words such as “connected” and “linked” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as “up,” “down,” “left,” and “right” are merely for indicating relative positional relationships, and if the absolute position of the subject matter changes, the relative positional relationships may change accordingly.

[0030] In typical OLED display panels, it is necessary to improve display quality through compensation technology. When compensating subpixel units in an OLED display panel, in addition to performing internal compensation by providing a pixel compensation circuit in the subpixel unit, external compensation can also be performed by providing a sensing transistor. When performing external compensation, a gate drive circuit consisting of a shift register unit needs to supply drive signals for the scanning transistor and drive signals for the sense transistor to the subpixel unit in the display panel, respectively. For example, a scanning drive signal (i.e., display output signal) for the scanning transistor is supplied during the display period of one frame, and a sense drive signal (i.e., blanking output signal) for the sense transistor is supplied during the blanking period of one frame.

[0031] In IC design, chip area is a major factor affecting chip cost, and how to effectively reduce chip area is a major consideration for technology developers. In OLED display panels, the shift register unit of the gate drive circuit generally includes a sense unit, a scan unit, and a connection unit (gate circuit or Hiz circuit) that outputs a composite pulse of the two. With this circuit configuration including the three parts, the shift register unit can output a composite waveform output pulse consisting of two waveforms with different widths and timings, supplying a display output signal to the scan transistor and a blanking output signal to the sense transistor. However, because the above shift register unit has a complex circuit configuration and is large in size, it does not contribute to achieving high resolution or a narrow bezel, nor does it contribute to reducing chip area and thus lowering costs.

[0032] Furthermore, in order to further reduce the size of the shift register unit and the gate drive circuit including the shift register unit, the circuit configuration can be simplified by integrating the detection unit, display unit and connection unit so that, for example, the blanking output signal for the blanking period of one frame and the display output signal for the display period are output through the same output circuit. However, in an integrated circuit, when level control (e.g., pull-up) is performed on the first control node (e.g., pull-up node) during the blanking period, the function is realized by a circuit consisting of multiple transistors, which leads to a large loss of threshold voltage. This affects the potential of the pull-up node, for example, preventing the potential of the pull-up node from reaching a predetermined high potential, and further affecting the output of the blanking output signal. In addition, gate drive circuits generally perform external compensation by sequential scanning, but if compensation is performed line by line for a long period of time, problems arise such as the scan lines moving line by line during display processing, resulting in large differences in brightness between different regions due to differences in compensation time.

[0033] At least one embodiment of the present disclosure provides a shift register unit and a method for driving the same, a gate drive circuit and a display device, the shift register unit having a simple circuit configuration, which improves the loss of threshold voltage when the level of a first control node (e.g., a pull-up node) is controlled by a blanking input circuit during the blanking period, so as not to affect the potential of the first control node, and thereby improves the accuracy of the blanking output signal.

[0034] Embodiments of this disclosure are described in detail below with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings refer to the same elements described.

[0035] At least one embodiment of the present disclosure provides a shift register unit comprising a blanking input circuit, a display input circuit, and an output circuit. The blanking input circuit is configured to input a blanking pull-up signal to a first control node during a blanking period based on a blanking input signal and a blanking control signal, and to compensate the blanking input circuit itself. The display input circuit is configured to input a display pull-up signal to the first control node during a display period in response to a display input signal. The output circuit is configured to output a composite output signal to an output terminal, with level control of the first control node.

[0036] Figure 1 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure. Referring to Figure 1, the shift register unit 10 includes a blanking input circuit 100, a display input circuit 200, and an output circuit 300. For example, in some examples, the shift register unit 10 further includes a noise reduction circuit 400 and a first control circuit 500. By cascading the multiple shift register units 10, a gate drive circuit according to any embodiment of the present disclosure can be constructed.

[0037] The blanking input circuit 100 is configured to compensate the blanking input circuit 100 itself by inputting a blanking pull-up signal to a first control node (e.g., pull-up node Q) during the blanking period based on the blanking input signal and the blanking control signal. For example, the blanking input circuit 100 is electrically connected to the blanking input signal terminal STU1, the blanking control signal terminal Bcon, the blanking pull-up signal terminal Bla_up, and the pull-up node Q. For example, the blanking input circuit 100 further includes a first node N1 and a second node N2 (not shown in Figure 1), and the blanking input circuit 100, in response to the blanking input signal supplied from the blanking input signal terminal STU1 and the blanking control signal supplied from the blanking control signal terminal Bcon, charges the first node N1 and compensates for the level of the first node N1, and coupled controls the level of the second node N2, thereby inputting the blanking pull-up signal supplied from the blanking pull-up signal terminal Bla_up to the pull-up node Q by controlling the level of the second node N2, and charging the pull-up node Q to a high level.

[0038] In the embodiments of this disclosure, a blanking input circuit 100 is provided in the shift register unit 10 to output a blanking output signal during a blanking period of one frame. The term "blanking" in the blanking input circuit 100 simply means that the circuit is related to the blanking period, and is not limited to operating only during the blanking period. The following embodiments are similar and will not be explained further. For example, the blanking input circuit 100 charges the first node N1 during the display period and maintains a high level of the first node N1 until the blanking period. During the blanking period, the blanking input circuit 100 compensates for the level of the first node N1, controls the level of the second node N2, and charges the pull-up node Q to a high level.

[0039] For example, by implementing the blanking input circuit 100 as multiple transistors, and compensating the level of the first node N1 while the pull-up node Q is charging, and coupledly controlling the level of the second node N2, the threshold voltage loss generated by the multiple transistors can be compensated, causing the level of the second node N2 to reach a predetermined value (e.g., a predetermined high level). By controlling the level of the second node N2, the level of the pull-up node Q can be set to a predetermined value (e.g., a predetermined high level), thereby avoiding threshold voltage loss that affects the level of the pull-up node Q.

[0040] For example, a random signal may be used as the blanking control signal. For instance, the random signal is supplied from a separately installed random signal generation circuit (e.g., an FPGA). When multiple shift register units 10 are cascaded as a gate drive circuit, the random signal supplied to the gate drive circuit is random or otherwise regular, rather than scanning line by line. Therefore, a random detection function, i.e., compensation detection of any pixel circuit in any line in any frame, can be realized. Consequently, when the gate drive circuit outputs a blanking output signal by controlling the random signal to externally compensate the pixel circuit, the random detection function can eliminate scan line and brightness shifts that appear on the screen.

[0041] The display input circuit 200 is configured to output a display pull-up signal to a first control node (e.g., pull-up node Q) during the display period in response to a display input signal. For example, the display input circuit 200 is electrically connected to a display input signal terminal STU2, a display pull-up signal terminal Dis_up, and a pull-up node Q, and is turned on in control of the display input signal supplied from the display input signal terminal STU2, and is configured to electrically connect the display pull-up signal terminal Dis_up to the pull-up node Q, thereby inputting the display pull-up signal supplied from the display pull-up signal terminal Dis_up to the pull-up node Q and pulling up the pull-up node Q to a high level.

[0042] The output circuit 300 is configured to output a composite output signal to the output terminal OP by controlling the level of a first control node (e.g., a pull-up node Q). For example, the output circuit 300 is electrically connected to a pull-up node Q, a composite output signal terminal Com, and an output terminal OP, and is configured to be turned on by controlling the level of the pull-up node Q, and to output a composite output signal supplied from the composite output signal terminal Com to the output terminal OP. For example, the output signal of the output terminal OP may include a display output signal and a blanking output signal, where the display output signal and the blanking output signal may be two mutually independent waveforms with different widths and timings. For example, during the display period, the output circuit 300 performs display by outputting a display output signal via the output terminal OP by controlling the level of the pull-up node Q to drive the scanning transistor in the pixel unit, while during the blanking period, the output circuit 300 performs compensation detection by outputting a blanking output signal via the output terminal OP by controlling the level of the pull-up node Q to drive the sensing transistor in the pixel unit.

[0043] The noise reduction circuit 400 is configured to perform noise reduction on the first control node (e.g., pull-up node Q) and output terminal OP by controlling the level of a second control node (e.g., pull-down node QB). For example, the noise reduction circuit 400 is connected to the pull-down node QB, the pull-up node Q, and the output terminal OP, and by controlling the level of the pull-down node QB, the pull-up node Q and output terminal OP are electrically connected to a separately provided voltage terminal (e.g., a low-voltage terminal), thereby pulling down the pull-up node Q and output terminal OP to a non-operating level (e.g., a low level) and achieving noise reduction.

[0044] The first control circuit 500 is configured to control the level of a second control node (e.g., a pull-down node QB) by controlling the level of a first control node (e.g., a pull-up node Q). For example, the first control circuit 500 is electrically connected to the pull-up node Q and the pull-down node QB, and is configured to pull down the pull-down node QB to a low level when the pull-up node Q is at a high level, and to pull up the pull-down node QB to a high level when the pull-up node Q is at a low level. For example, the first control circuit 500 may be an inverting circuit.

[0045] Figure 2 is a schematic block diagram of a blanking input circuit for a shift register unit according to some embodiments of the present disclosure. Referring to Figure 2, the blanking input circuit 100 includes a charging subcircuit 110, a compensation subcircuit 120, and an isolation subcircuit 130.

[0046] The charging subcircuit 110 is configured to input a blanking input signal to the first node N1 in response to a blanking control signal. For example, the charging subcircuit 110 is connected to a blanking input signal terminal STU1, a blanking control signal terminal Bcon, and the first node N1, and is turned on in control of the blanking control signal supplied from the blanking control signal terminal Bcon, electrically connecting the blanking input signal terminal STU1 and the first node N1, thereby configuring the charging subcircuit 110 to input a blanking input signal to the first node N1. For example, in some cases, the charging subcircuit 110 is turned on in control of the blanking control signal, and the blanking input signal is at a high level at this point, thereby charging the first node N1 and pulling the first node N1 up to a high level.

[0047] The compensation subcircuit 120 is configured to store the blanking input signal input to the charging subcircuit 110, compensate the level of the first node N1 in response to the first clock signal, and control the level of the second node N2. For example, the compensation subcircuit 120 is connected to the first node N1, the second node N2, and the first clock signal terminal CLKA, and stores the blanking input signal written to the first node N1. When the level of the first clock signal supplied from the first clock signal terminal CLKA changes (for example, from a low level to a high level), it compensates the level of the first node N1 (for example, by pulling up the level of the first node N1 to the first level), thereby controlling the level of the second node N2. For example, the compensation subcircuit 120 is sufficiently turned on by controlling the first level of the first node N1 so that the first clock signal is sufficiently written to the second node N2. For example, in some cases, the first clock signal is sufficiently written to the second node N2 so that the level of the second node N2 is equal to the high level of the first clock signal at that point, i.e., the level of the second node N2 reaches a predetermined value. Of course, embodiments of this disclosure are not limited thereto, and the level of the second node N2 may be slightly lower than the high level of the first clock signal, provided that the isolation subcircuit 130 is controlled to be on or sufficiently on.

[0048] The isolated subcircuit 130 is configured to input a blanking pull-up signal to the first control node (e.g., pull-up node Q) when the level of the second node N2 is controlled. For example, the isolated subcircuit 130 is connected to the second node N2, the pull-up node Q, and the blanking pull-up signal terminal Bla_up, and is turned on when the level of the second node N2 is controlled, electrically connecting the blanking pull-up signal terminal Bla_up and the pull-up node Q, thereby configuring the blanking pull-up signal supplied from the blanking pull-up signal terminal Bla_up to be input to the pull-up node Q. For example, in some cases, the isolated subcircuit 130 is turned on when the level of the second node N2 is controlled, and the blanking pull-up signal is at a high level at this point, thereby charging the pull-up node Q and pulling the pull-up node Q up to a high level. For example, the compensation subcircuit 120 causes the level of the second node N2 to reach a predetermined value, thereby fully turning on the isolation subcircuit 130, ensuring that the high level of the blanking pull-up signal is fully written to the pull-up node Q, and further causing the level of the pull-up node Q to reach a predetermined value.

[0049] As described above, the loss of threshold voltage when the pull-up node Q is pulled up by the blanking input circuit 100 during the blanking period can be improved, and the potential of the pull-up node Q can not be affected, thereby improving the accuracy of the blanking output signal.

[0050] Figure 3 is a schematic block diagram of a blanking input circuit for another shift register unit according to some embodiments of the present disclosure. Referring to Figure 3, in this embodiment the blanking input circuit 100 further includes a control subcircuit 140, the rest of the structure being essentially the same as the blanking input circuit 100 shown in Figure 2. The control subcircuit 140 is configured to control (e.g., pull down) the level of a second node N2 by controlling the level of a second control node (e.g., pull-down node QB). For example, the control subcircuit 140 is connected to the second node N2 and the pull-down node QB, is turned on by controlling the level of the pull-down node QB, and is configured such that the second node N2 is electrically connected to a separately provided voltage terminal (e.g., a low-voltage terminal) so that the second node N2 is pulled down to a low level. In the embodiments of this disclosure, the control subcircuit 140 is not limited to connection with the pull-down node QB, but may be connected to a separately provided clock signal terminal or other applicable signal terminal, so that the second node N2 is pulled down by control of the clock signal or other applicable signal.

[0051] By installing the control subcircuit 140, the second node N2 can always maintain a low level when a low level is required, thereby ensuring that the isolation subcircuit 130 is reliably closed so that the blanking pull-up signal does not affect the pull-up node Q. For example, in some cases, during the display period, the control subcircuit 140 pulls down the second node N2, preventing the blanking pull-up signal from affecting the potential of the pull-up node Q, thereby achieving normal display functionality.

[0052] In the embodiments of this disclosure, the blanking input circuit 100 may include any applicable subcircuits, not limited to the charging subcircuit 110, compensation subcircuit 120, isolation subcircuit 130, and control subcircuit 140 described above, as long as the corresponding function is achieved.

[0053] Figure 4 is a schematic block diagram of another shift register unit according to some embodiments of the present disclosure. Referring to Figure 4, in this embodiment the shift register unit 10 further includes a blanking reset circuit 600 and a display reset circuit 700, and the other components are essentially the same as the shift register unit 10 shown in Figure 1.

[0054] The blanking reset circuit 600 is configured to reset a first control node (e.g., pull-up node Q) in response to a blanking reset signal. For example, the blanking reset circuit 600 is connected to a blanking reset signal terminal TRST and a pull-up node Q, and is turned on by control of the blanking reset signal supplied from the blanking reset signal terminal TRST, and the pull-up node Q is electrically connected to a separately provided voltage terminal (e.g., a low voltage terminal), thereby resetting the pull-up node Q. For example, during the blanking period, when the output circuit 300 terminates its signal output, the blanking reset circuit 600 resets the pull-up node Q. In the embodiments of this disclosure, "blanking" in the blanking reset circuit 600 simply means that the circuit is related to the blanking period, and is not limited to operating only during the blanking period. The following embodiments are similar and will not be described further.

[0055] The display reset circuit 700 is configured to reset a first control node (e.g., pull-up node Q) in response to a display reset signal. For example, the display reset circuit 700 is connected to the display reset signal terminal STD and the pull-up node Q, and is turned on in control of the display reset signal supplied from the display reset signal terminal STD, and the pull-up node Q is electrically connected to a separately provided voltage terminal (e.g., a low voltage terminal), thereby resetting the pull-up node Q. For example, during the display period, when the output circuit 300 terminates its signal output, the display reset circuit 700 resets the pull-up node Q.

[0056] Figure 5 is a schematic block diagram of another shift register unit according to some embodiments of the present disclosure. Referring to Figure 5, in this embodiment the shift register unit 10 further includes a second control circuit 800, the other structure being essentially the same as the shift register unit 10 shown in Figure 4. The second control circuit 800 is configured to control the level of a second control node (e.g., a pull-down node QB) in response to a first clock signal or a display input signal. For example, the second control circuit 800 is connected to a first clock signal terminal CLKA, a display input signal terminal STU2 and a pull-down node QB, and is turned on in control of a first clock signal supplied from the first clock signal terminal CLKA or a display input signal supplied from the display input signal terminal STU2, and the pull-down node QB is electrically connected to a separately provided voltage terminal (e.g., a low voltage terminal) so that the pull-down node QB is pulled down to a low level.

[0057] For example, during the blanking period, the second control circuit 800 pulls down the pull-down node QB in response to the first clock signal. During the display period, the second control circuit 800 pulls down the pull-down node QB in response to the display input signal. Of course, the embodiments of this disclosure are not limited thereto, and the second control circuit 800 may pull down the pull-down node QB only during the blanking period or the display period. By providing the second control circuit 800, the pull-down node QB can be kept at a low level, which helps the blanking input circuit 100 or the display input circuit 200 to write a high level to the pull-up node Q, so that the level of the pull-up node Q reaches a predetermined value. This prevents the output signal from being affected after the transistor threshold voltage drifts, and improves the reliability of the circuit.

[0058] Figure 6 is a circuit diagram of a specific implementation example of the shift register unit shown in Figure 4. The following explanation will use the case where each transistor is an N-type transistor as an example, but this is not limited to the embodiments of this disclosure.

[0059] Referring to Figure 6, the shift register unit 10 includes first to fifteenth transistors M1 to M15, and further includes a first capacitor C1 and a second capacitor C2.

[0060] The blanking input circuit 100 includes a charging subcircuit 110, a compensation subcircuit 120, an isolation subcircuit 130, and a control subcircuit 140. The charging subcircuit 110 may be implemented as a first transistor M1. The gate of the first transistor M1 is configured to be connected to a random signal terminal OE to receive a random signal (here, the random signal terminal OE is the blanking control signal terminal Bcon, and the random signal is the blanking control signal), the first pole of the first transistor M1 is configured to be connected to a blanking input signal terminal STU1 to receive a blanking input signal, and the second pole of the first transistor M1 is configured to be connected to a first node N1. When the random signal reaches an effective level (e.g., a high level), the first transistor M1 is turned on, thereby writing the blanking input signal to the first node N1. For example, the blanking input signal at this time is set to a high level to charge the first node N1.

[0061] The compensation subcircuit 120 may be implemented as a second transistor M2 and a first capacitor C1. The gate of the second transistor M2 is positioned to be connected to the first node N1, the first pole of the second transistor M2 is positioned to be connected to the first clock signal terminal CLKA to receive the first clock signal, and the second pole of the second transistor M2 is positioned to be connected to the second node N2. The first pole of the first capacitor C1 is positioned to be connected to the first node N1, and the second pole of the first capacitor C1 is positioned to be connected to the second node N2. When the blanking input signal is written to the first node N1, the first node N1 is charged to a high level, and the first capacitor C1 stores this high level for use in a subsequent stage, keeping the first node N1 at a high level. Then, the second transistor M2 is turned on and writes the first clock signal to the second node N2. When the first clock signal changes from a low level to a high level, the bootstrap effect of the first capacitor C1 causes the level of the first node N1 to rise further to the first level, so that the second transistor M2 is sufficiently turned on, thereby allowing the high level of the first clock signal to be sufficiently written to the second node N2, causing the level of the second node N2 to reach a predetermined value, for example, equal to the high level of the first clock signal.

[0062] The isolation subcircuit 130 may be implemented as a third transistor M3. The gate of the third transistor M3 is positioned to be connected to the second node N2, the first pole of the third transistor M3 is positioned to be connected to the first voltage terminal VDD to receive the first voltage (here, the first voltage terminal VDD corresponds to the blanking pull-up signal terminal Bla_up, and the first voltage is the blanking pull-up signal), and the second pole of the third transistor M3 is positioned to be connected to the first control node (e.g., pull-up node Q). When the second node N2 goes high (e.g., when the high level reaches a predetermined value), the third transistor M3 is turned on sufficiently or nearly sufficiently, writing the first voltage to the pull-up node Q, thereby raising the level of the pull-up node Q.

[0063] The control subcircuit 140 may be implemented as a fourth transistor M4. The gate of the fourth transistor M4 is positioned to be connected to a second control node (e.g., a pull-down node QB), the first pole of the fourth transistor M4 is positioned to be connected to a second node N2, and the second pole of the fourth transistor M4 is positioned to be connected to a second voltage terminal VGL2 to receive a second voltage. When the pull-down node QB goes high, the fourth transistor M4 is turned on, pulling down the second node N2 to a low level, thereby ensuring that the third transistor M3 is turned off, so that the blanking pull-up signal (e.g., a first voltage at the first voltage terminal VDD) does not affect the pull-up node Q during the display period.

[0064] For example, the first voltage terminal VDD is configured to supply a DC high-level signal as the first voltage, and the second voltage terminal VGL2 is configured to supply a DC low-level signal as the second voltage, and is, for example, grounded. The following embodiments are similar and will not be described further.

[0065] The display input circuit 200 may be implemented as a fifth transistor M5. The gate of the fifth transistor M5 is connected to the display input signal terminal STU2 to receive the display input signal, the first pole of the fifth transistor M5 is connected to the first voltage terminal VDD to receive the first voltage (here, the first voltage terminal VDD corresponds to the display pull-up signal terminal Dis_up, and the first voltage is the display pull-up signal), and the second pole of the fifth transistor M5 is connected to the first control node (e.g., pull-up node Q). When the display input signal reaches an effective level (e.g., high level), the fifth transistor M5 is turned on, thereby writing the first voltage to the pull-up node Q and raising the pull-up node Q to a high level.

[0066] For example, in some cases, the output terminal OP of the output circuit 300 includes at least one shift signal output terminal CR and at least one pixel scan signal output terminal Out to improve the driving capability of the shift register unit 10. For example, the shift signal output terminal CR is used to supply a blanking input signal to the next stage shift register unit 10, and the pixel scan signal output terminal Out is used to supply a driving signal to the pixel circuit. The output signals of the shift signal output terminal CR and the pixel scan signal output terminal Out are the same.

[0067] The output circuit 300 may be implemented as a sixth transistor M6, a seventh transistor M7, and a second capacitor C2. The gate of the sixth transistor M6 is configured to be connected to a first control node (e.g., a pull-up node Q), the first pole of the sixth transistor M6 is configured to be connected to a second clock signal terminal CLKB to receive a second clock signal (here, the second clock signal terminal CLKB corresponds to a composite output signal terminal Com, and the second clock signal is the composite output signal), and the second pole of the sixth transistor M6 is configured to be connected to a shift signal output terminal CR. The gate of the seventh transistor M7 is configured to be connected to a first control node (e.g., a pull-up node Q), the first pole of the seventh transistor M7 is configured to be connected to a second clock signal terminal CLKB to receive a second clock signal as a composite output signal, and the second pole of the seventh transistor M7 is configured to be connected to a pixel scan signal output terminal Out. The first pole of the second capacitor C2 is positioned to be connected to a first control node (e.g., a pull-up node Q), and the second pole of the second capacitor C2 is positioned to be connected to the second pole of the sixth transistor M6. Of course, embodiments of this disclosure are not limited thereto, and in other examples, for example, the second pole of the second capacitor C2 may be connected to the second pole of the seventh transistor M7. When the pull-up node Q reaches an active level (e.g., a high level), the sixth transistor M6 and the seventh transistor M7 are both turned on, thereby outputting the second clock signal to the shift signal output terminal CR and the pixel scan signal output terminal Out, respectively.

[0068] The noise reduction circuit 400 may be implemented as an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The gate of the eighth transistor M8 is configured to be connected to a second control node (e.g., a pull-down node QB), the first pole of the eighth transistor M8 is configured to be connected to a first control node (e.g., a pull-up node Q), and the second pole of the eighth transistor M8 is configured to be connected to a third voltage terminal VGL1 to receive a third voltage. The gate of the ninth transistor M9 is configured to be connected to a second control node (e.g., a pull-down node QB), the first pole of the ninth transistor M9 is configured to be connected to a shift signal output terminal CR, and the second pole of the ninth transistor M9 is configured to be connected to a third voltage terminal VGL1 to receive a third voltage. The gate of the tenth transistor M10 is positioned to be connected to the second control node (e.g., the pull-down node QB), the first pole of the tenth transistor M10 is positioned to be connected to the pixel scanning signal output terminal Out, and the second pole of the tenth transistor M10 is positioned to be connected to the fourth voltage terminal to receive the fourth voltage (here, the second voltage terminal VGL2 is referred to as the fourth voltage terminal, and the second voltage as the fourth voltage).

[0069] For example, the third voltage terminal VGL1 is configured to supply a DC low-level signal, namely a third voltage, and is, for example, grounded. The following embodiments are similar and will not be described further. For example, in some examples, the third voltage at the third voltage terminal VGL1 is lower than the second voltage at the second voltage terminal VGL2, and in other examples, the third voltage at the third voltage terminal VGL1 is equal to the second voltage at the second voltage terminal VGL2. The third voltage and the second voltage may be the same or different, and can be determined as appropriate according to the actual needs.

[0070] When the pull-down node QB reaches an effective level (e.g., high level), the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are all turned on, causing the pull-up node Q and the shift signal output terminal CR to be electrically connected to the third voltage terminal VGL1, and the pixel scan signal output terminal Out to be electrically connected to the second voltage terminal VGL2, thereby performing noise reduction on the pull-up node Q, the shift signal output terminal CR, and the pixel scan signal output terminal Out. In the embodiments of this disclosure, if there are multiple shift signal output terminals CR and / or pixel scan signal output terminals Out, the noise reduction circuit 400 also includes multiple transistors corresponding to the shift signal output terminals CR and / or pixel scan signal output terminals Out to reduce noise on the multiple shift signal output terminals CR and / or pixel scan signal output terminals Out.

[0071] The first control circuit 500 may be implemented as an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The gate of the eleventh transistor M11 is connected to a first pole and is arranged to be connected to a fifth voltage terminal VDD_A to receive a fifth voltage, and the second pole of the eleventh transistor M11 is arranged to be connected to a second control node (e.g., a pull-down node QB). The gate of the twelfth transistor M12 is connected to a first pole and is arranged to be connected to a sixth voltage terminal VDD_B to receive a sixth voltage, and the second pole of the twelfth transistor M12 is arranged to be connected to a second control node (e.g., a pull-down node QB). The gate of the 13th transistor M13 is positioned to be connected to a first control node (e.g., a pull-up node Q), the first pole of the 13th transistor M13 is positioned to be connected to a second control node (e.g., a pull-down node QB), and the second pole of the 13th transistor M13 is positioned to be connected to a third voltage terminal VGL1 to receive a third voltage.

[0072] For example, in some cases, the fifth voltage terminal VDD_A and the sixth voltage terminal VDD_B are arranged to alternately supply high-level DC signals, thereby alternately turning on the eleventh transistor M11 and the twelfth transistor M12, thus avoiding performance drift due to long-term transistor on states. For example, when the fifth voltage terminal VDD_A supplies a high-level signal and the sixth voltage terminal VDD_B supplies a low-level signal, the eleventh transistor M11 is turned on and the twelfth transistor M12 is turned off. When the sixth voltage terminal VDD_B supplies a high-level signal and the fifth voltage terminal VDD_A supplies a low-level signal, the twelfth transistor M12 is turned on and the eleventh transistor M11 is turned off. For example, if the signal supplied from the fifth voltage terminal VDD_A is the fifth voltage and the signal supplied from the sixth voltage terminal VDD_B is the sixth voltage, the following embodiments are similar and will not be described further.

[0073] When the pull-up node Q reaches an active level (e.g., high level), the 13th transistor M13 is turned on, and the pull-down node QB can be pulled down to a low level by setting a channel width ratio between the 13th transistor M13 and the turned-on 11th transistor M11 or 12th transistor M12. When the pull-up node Q reaches a low level, the 13th transistor M13 is turned off, in which case the turned-on 11th transistor M11 or 12th transistor M12 writes a high-level signal supplied from the 5th voltage terminal VDD_A or the 6th voltage terminal VDD_B to the pull-down node QB, pulling the pull-down node QB up to a high level.

[0074] The blanking reset circuit 600 may be implemented as a 14th transistor M14. The gate of the 14th transistor M14 is configured to be connected to a blanking reset signal terminal TRST to receive a blanking reset signal, the first pole of the 14th transistor M14 is configured to be connected to a first control node (e.g., a pull-up node Q), and the second pole of the 14th transistor M14 is configured to be connected to a third voltage terminal VGL1 to receive a third voltage. For example, during the blanking period, when the blanking reset signal reaches an effective level (e.g., a high level), the 14th transistor M14 is turned on, causing the pull-up node Q to be electrically connected to the third voltage terminal VGL1, thereby resetting the pull-up node Q.

[0075] The display reset circuit 700 may be implemented as a 15th transistor M15. The gate of the 15th transistor M15 is configured to be connected to the display reset signal terminal STD to receive the display reset signal, the first pole of the 15th transistor M15 is configured to be connected to a first control node (e.g., a pull-up node Q), and the second pole of the 15th transistor M15 is configured to be connected to a third voltage terminal VGL1 to receive a third voltage. For example, during the display period, when the display reset signal reaches an active level (e.g., a high level), the 15th transistor M15 is turned on, causing the pull-up node Q to be electrically connected to the third voltage terminal VGL1, thereby resetting the pull-up node Q.

[0076] Figure 7 is a circuit diagram of a specific implementation example of the shift register unit shown in Figure 5. Referring to Figure 7, the shift register unit 10 includes the first to 17th transistors M1 to M17, and further includes the first capacitor C1 and the second capacitor C2. The connections of the first to 15th transistors M1 to M15, the first capacitor C1 and the second capacitor C2 are essentially the same as those of the shift register unit 10 shown in Figure 6, and are therefore omitted from this explanation.

[0077] The second control circuit 800 may be implemented as a 16th transistor M16 and a 17th transistor M17. The gate of the 16th transistor M16 is configured to be connected to a first clock signal terminal CLKA to receive a first clock signal, the first pole of the 16th transistor M16 is configured to be connected to a second control node (e.g., a pull-down node QB), and the second pole of the 16th transistor M16 is configured to be connected to a third voltage terminal VGL1 to receive a third voltage. The gate of the 17th transistor M17 is configured to be connected to a display input signal terminal STU2 to receive a display input signal, the first pole of the 17th transistor M17 is configured to be connected to a second control node (e.g., a pull-down node QB), and the second pole of the 17th transistor M17 is configured to be connected to a third voltage terminal VGL1 to receive a third voltage. During the blanking period, when the first clock signal reaches an effective level (e.g., high level), the 16th transistor M16 is turned on, electrically connecting the pull-down node QB to the third voltage terminal VGL1, thereby pulling down the pull-down node QB to a low level. During the display period, when the display input signal reaches an effective level (e.g., high level), the 17th transistor M17 is turned on, electrically connecting the pull-down node QB to the third voltage terminal VGL1, thereby pulling down the pull-down node QB to a low level.

[0078] In the embodiments of this disclosure, the specific implementation of the blanking input circuit 100, display input circuit 200, output circuit 300, noise reduction circuit 400, first control circuit 500, blanking reset circuit 600, display reset circuit 700, and second control circuit 800 is not limited to the embodiments described above, and any applicable implementation, such as conventional connection methods well known to those skilled in the art, may be used as long as the corresponding functions are reliably achieved.

[0079] Figure 8 is a schematic diagram of another specific implementation example of the shift register unit shown in Figure 5. Referring to Figure 8, the shift register unit 10 of this embodiment includes a plurality of leak prevention circuits, two second control nodes (e.g., a first pull-down node QB_A and a second pull-down node QB_B), and two pixel scan signal output terminals (a first pixel scan signal output terminal Out1 and a second pixel scan signal output terminal Out2), and the other structure is essentially the same as the shift register unit 10 shown in Figure 7.

[0080] In the shift register unit 10 shown in Figure 7, the first capacitor C1 maintains a high level at the first node N1, and the second capacitor C2 maintains a high level at the pull-up node Q. In this case, there are several transistors whose first pole is connected to the pull-up node Q and / or the first node N1, and whose second pole is connected to a low-level signal line. Even when a non-on signal is input to the gates of these transistors, leakage can occur due to the voltage difference between their first and second poles, thereby reducing the effectiveness of maintaining a high level at the pull-up node Q and / or the first node N1 in this circuit. Therefore, in the shift register unit 10 shown in Figure 8, multiple leakage prevention circuits are added to improve the effectiveness of maintaining a high level at the pull-up node Q and / or the first node N1.

[0081] For example, referring to Figure 8, the first leakage prevention circuit may be implemented as a first leakage prevention transistor M1_b and a second leakage prevention transistor M1_c, and are arranged to prevent charge at the first node N1 from leaking to the blanking input signal terminal STU1 via the first transistor M1 when the first node N1 is at a high level. The gate of the first leakage prevention transistor M1_b is connected to the gate (random signal terminal OE) of the first transistor M1, the first pole is connected to the second pole of the first transistor M1, and the second pole is connected to the first node N1. The gate of the second leakage prevention transistor M1_c is connected to the first node N1, the first pole is connected to the first voltage terminal VDD, and the second pole is connected to the first pole of the first leakage prevention transistor M1_b.

[0082] When the first node N1 is at a high level, the second leakage prevention transistor M1_c is turned on by the control of the first node N1, and a first voltage (high voltage) is written to the first pole of the first leakage prevention transistor M1_b so that both the first and second poles of the first leakage prevention transistor M1_b are at a high level, thereby preventing the charge at the first node N1 from leaking through the first leakage prevention transistor M1_b. In this case, the gate of the first transistor M1 is connected to the gate of the first leakage prevention transistor M1_b, so the combination of the first leakage prevention transistor M1_b and the first transistor M1 can achieve the same function as the first transistor M1 described above, and at the same time obtain a leakage prevention effect.

[0083] Similarly, the same leakage prevention circuit as described above can be used to achieve leakage prevention for the eighth transistor M8, the 14th transistor M14, the 15th transistor M15, and the 22nd transistor M22 connected to the pull-up node Q. For example, the second leakage prevention circuit may be implemented as the third leakage prevention transistor M8_b, the fourth leakage prevention transistor M14_b, the fifth leakage prevention transistor M15_b, the sixth leakage prevention transistor 22_b, and the seventh leakage prevention transistor M23. The second leakage prevention circuit is connected in the same manner as the first leakage prevention circuit described above, and its explanation is omitted here.

[0084] When the pull-up node Q is at a high level, the seventh leakage prevention transistor M23 is turned on, setting the leakage prevention node OFF to a high level. This causes the first and second poles of the third leakage prevention transistor M8_b, the fourth leakage prevention transistor M14_b, the fifth leakage prevention transistor M15_b, and the sixth leakage prevention transistor M22_b to be at a high level, preventing charge leakage at the pull-up node Q. In this case, the combination of the eighth transistor M8, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-second transistor M22 with the second leakage prevention circuit can achieve the same functionality as the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15 described above, while simultaneously providing a leakage prevention effect.

[0085] Those skilled in the art will understand that, according to the example of a circuit having a leak prevention function according to the embodiments of this disclosure, one or more transistors of the shift register unit 10 may be selected to add a leak prevention circuit configuration, depending on the situation. Figure 8 shows only an exemplary circuit configuration including a leak prevention circuit and is not limited to embodiments of this disclosure.

[0086] As shown in Figure 8, the shift register unit 10 includes, for example, two second control nodes: a first pull-down node QB_A and a second pull-down node QB_B. Accordingly, the 11th transistor M11 and the 13th transistor M13 jointly control the level of the first pull-down node QB_A, and the 12th transistor M12 and the 20th transistor M24 jointly control the level of the second pull-down node QB_B. Since the fifth voltage terminal VDD_A and the sixth voltage terminal VDD_B alternately supply high-level signals, when the pull-up node Q is low, the first pull-down node QB_A and the second pull-down node QB_B alternately become high-level, and when the pull-up node Q is high-level, both the first pull-down node QB_A and the second pull-down node QB_B become low-level. In this way, drift in the threshold voltage of the transistors can be prevented. The circuit connections and related operating principles of the two second control nodes described above can be found in the conventional double pull-down node shift register unit, and will not be explained here.

[0087] Accordingly, the second control circuit 800 is also implemented in two groups: one group consists of the 25th transistor M25, the 26th transistor M26, and the 27th transistor M27, and the other group consists of the 16th transistor M16, the 17th transistor M17, and the 28th transistor M28. The transistors in these two groups are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively, causing the first pull-down node QB_A and the second pull-down node QB_B to be pulled down, respectively. For example, the 16th transistor M16 and the 28th transistor M28 are connected in series between the second pull-down node QB_B and the third voltage terminal VGL1, the gate of the 16th transistor M16 is connected to the first clock signal terminal CLKA, and the gate of the 28th transistor M28 is connected to the first node N1.

[0088] When both the first clock signal and the first node N1 reach an effective level (e.g., high level), both the 16th transistor M16 and the 28th transistor M28 are turned on, thereby pulling down the second pull-down node QB_B to a low level. The second control circuit 800 controls the first pull-down node QB_A in the same way as the second pull-down node QB_B, and this will not be explained here. For example, if multiple shift register units 10 are cascaded, as described above, the first pull-down node QB_A and the second pull-down node QB_B of the outputting shift register unit 10 are pulled down, while the first pull-down node QB_A and the second pull-down node QB_B of the other shift register units 10 are not pulled down, thereby preventing the shift signal output terminal CR, the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 of the other shift register units 10 from being in a floating state, and reducing noise in the output signal.

[0089] The shift register unit 10 includes two pixel scan signal output terminals: a first pixel scan signal output terminal Out1 and a second pixel scan signal output terminal Out2. The first pixel scan signal output terminal Out1 is connected in the same way as the pixel scan signal output terminal Out described above. The second pixel scan signal output terminal Out2 is connected to the second pole of the 20th transistor M20, the gate of the 20th transistor M20 is connected to a pull-up node Q, and the first pole of the 20th transistor M20 is connected to a third clock signal terminal CLKC. A third capacitor C3 is connected between the gate and the second pole of the 20th transistor M20.

[0090] When the pull-up node Q is at a high level, the seventh transistor M7 and the twentieth transistor M20 are turned on, the second clock signal from the second clock signal terminal CLKB is output to the first pixel scan signal output terminal Out1, and the third clock signal from the third clock signal terminal CLKC is output to the second pixel scan signal output terminal Out2. For example, in some cases, by supplying the same clock signal to the second clock signal terminal CLKB and the third clock signal terminal CLKC, the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 can output the same signal, further improving the driving capability. For example, in other cases, by supplying different signals to the second clock signal terminal CLKB and the third clock signal terminal CLKC, the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 can output different signals, supplying a variety of driving signals to the pixel unit.

[0091] Accordingly, two transistors M21_a and M21_b are required to perform pull-down noise reduction on the second pixel scanning signal output terminal Out2, with their gates connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively. Similarly, the gates of transistors M9 and M18 are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively, to perform pull-down noise reduction on the shift signal output terminal CR. The gates of transistors M10 and M19 are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively, to perform pull-down noise reduction on the first pixel scanning signal output terminal Out1. Accordingly, the gates of transistors M4_a and M4_b are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively, to perform pull-down control on the second node N2.

[0092] Figures 9A to 9C are schematic diagrams of specific implementation examples of blanking input circuits for shift register units according to some embodiments of the present disclosure. Referring to Figure 9A, the blanking input circuit 100 has a leakage prevention circuit to prevent leakage of the first node N1, and the operating principle of the leakage prevention circuit is the same as that of the leakage prevention circuit described above, and will not be explained here. In this embodiment, unlike the embodiment shown in Figure 7, the gate of the fourth transistor M4 is connected to the fourth clock signal terminal CLKD to receive the fourth clock signal, and is arranged to pull down the second node N2 by controlling the fourth clock signal. However, the embodiments of the present disclosure are not limited thereto, and the gate of the fourth transistor M4 may be connected to the pull-down node QB, the fourth clock signal terminal CLKD, or other applicable signal terminals, as long as the gate of the fourth transistor M4 can be controlled to turn on the fourth transistor M4 and pull down the second node N2. Referring to Figure 9B, in this embodiment, the gate of the fourth transistor M4 is controlled differently compared to the blanking input circuit 100 shown in Figure 9A. When the fourth clock signal terminal CLKD supplies a high level through the circuit configuration formed by transistors M4_1 and M4_2, the gate of the fourth transistor M4 becomes high level, turning on the fourth transistor M4 and thereby pulling down the second node N2. Referring to Figure 9C, and comparing it with the blanking input circuit 100 shown in Figure 9A, the blanking input circuit 100 of this embodiment further includes a leakage prevention circuit for the third transistor M3 to prevent leakage of the pull-up node Q. The operating principle of the leakage prevention circuit is the same as that of the leakage prevention circuit described above and will not be explained here. In this embodiment, the first pole of the third transistor M3 is connected to the fifth clock signal terminal CLKE to receive the fifth clock signal as a blanking pull-up signal.

[0093] Figure 10 is a schematic diagram of a specific implementation example of the display input circuit of a shift register unit according to some embodiments of the present disclosure. Referring to Figure 10(1), in some examples, the gate of the fifth transistor M5 is connected to the first pole and is positioned to be connected to the display input signal terminal STU2. Referring to Figure 10(2), in this embodiment, a leakage prevention circuit is added to prevent leakage of the pull-up node Q compared to the connection method shown in Figure 10(1). Referring to Figure 10(3), compared to the display input circuit 200 in the shift register unit 10 shown in Figure 6, a diode-connected transistor M5_b is connected in series between the fifth transistor M5 and the pull-up node Q, also serving as a leakage prevention measure.

[0094] Figure 11 is a circuit diagram of a specific implementation example of a second control circuit of a shift register unit according to some embodiments of the present disclosure. Referring to Figure 11(1), compared with the second control circuit 800 in the shift register unit 10 shown in Figure 8, in this embodiment, transistors M26 (26) and M28 (28) in Figure 8 are omitted. In the second control circuit 800 of this embodiment, the corresponding functions can be realized and the circuit configuration can be simplified. Referring to Figure 11(2), compared with the circuit shown in Figure 11(1), in this embodiment, transistors M25 and M16 are omitted. Therefore, the second control circuit 800 of this embodiment only pulls down the first pull-down node QB_A and the second pull-down node QB_B in response to the display input signal supplied from the display input signal terminal STU2 during the display period, and does not pull them down during the blanking period, so the display effect is not affected and the circuit configuration can be simplified.

[0095] In the embodiments of this disclosure, the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be capacitor elements manufactured by processes such as fabricating dedicated capacitor electrodes, and each electrode of the capacitor may be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), and the first capacitor C1, the second capacitor C2, and the third capacitor C3 may also be parasitic capacitors between each element, or may be realized by the transistor itself or other elements or circuits. The method of connecting the first capacitor C1, the second capacitor C2, and the third capacitor C3 is not limited to the method described above, and other applicable connection methods may be used as long as they can store the corresponding levels.

[0096] Furthermore, in the description of each embodiment of the present disclosure, the first control node, the second control node, the first node N1, the second node N2, the pull-up node Q, the pull-down node QB, the first pull-down node QB_A, the second pull-down node QB_B, and the leak-proof node OFF may also refer to a point in the schematic where the relevant electrical connections converge, or a single wire or multiple interconnection wires in the schematic where the relevant electrical connections converge, and the embodiments of the present disclosure are not limited thereto.

[0097] The transistors used in the embodiments of this disclosure may all be thin-film transistors, field-effect transistors, or switching elements having the same characteristics, and in the embodiments of this disclosure, thin-film transistors will be described as examples. The transistors used here have a structurally symmetrical source and drain, so their source and drain are structurally indistinguishable. In the embodiments of this disclosure, in order to distinguish between the two poles of the transistor other than the gate, one electrode is directly described as the first pole and the other electrode as the second pole.

[0098] Furthermore, all transistors in the embodiments of this disclosure are N-type transistors, where the first pole of the transistor is the drain and the second pole is the source. However, this disclosure includes, but is not limited to, N-type transistors. For example, one or more transistors in the shift register unit 10 according to the embodiments of this disclosure may also be P-type transistors, where the first pole of the transistor is the source and the second pole is the drain, and the poles of the selected transistors may be connected as appropriate by referring to the poles of the corresponding transistors in the embodiments of this disclosure, so that the corresponding voltage terminals supply the corresponding high or low voltage. When N-type transistors are used, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin-film transistor, which allows for effective miniaturization of the transistor and prevention of leakage current compared to when low-temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) is used as the active layer of the thin-film transistor.

[0099] In the description of each embodiment of the present disclosure, for example, when each circuit is implemented as an N-type transistor, the term “pull-up” means charging the node or electrode of the transistor so that the absolute value of the node or electrode level increases in order to achieve the operation of the corresponding transistor (e.g., on), and “pull-down” means discharging the node or electrode of the transistor so that the absolute value of the node or electrode level decreases in order to achieve the operation of the corresponding transistor (e.g., off). Or, for example, when each circuit is implemented as a P-type transistor, the term “pull-up” means discharging the node or electrode of a transistor so that the absolute value of the node or electrode level decreases in order to achieve the operation of the corresponding transistor (e.g., on), and “pull-down” means charging the node or electrode of the transistor so that the absolute value of the node or electrode level increases in order to achieve the operation of the corresponding transistor (e.g., off).

[0100] Figure 12 is a signal timing diagram of a shift register unit according to some embodiments of the present disclosure. The operating principle of the shift register unit 10 shown in Figure 6 will be explained below in conjunction with the signal timing diagram shown in Figure 12. Hereinafter, the case in which each transistor is an N-type transistor is given as an example, but the embodiments of the present disclosure are not limited to this.

[0101] In Figure 12 and the following description, 1F indicates the timing of the operation of the shift register unit 10 during the display of one frame by the gate drive circuit, DS indicates the display period of one frame, and B indicates the blanking period of one frame. STU1, STU2, TRST, OE, VDD_A, VDD_B, CLKA, CLKB, Out, CR, etc., are used to represent both the corresponding signal terminal and the corresponding signal. The following embodiments are similar and are therefore omitted from description.

[0102] In the initial stage 0 (not shown), the random signal OE and the blanking reset signal TRST are both at high levels. When the first transistor M1 is turned on, the blanking input signal STU1 goes low, thereby resetting the first node N1. The 14th transistor M14 is turned on, thereby resetting the pull-up node Q. For example, if multiple shift register units 10 are cascaded, at this stage the first node N1 and pull-up node Q of the multiple shift register units 10 can be reset globally.

[0103] During the display period DS, in the first stage 1, the display input signal STU2 and the sixth voltage VDD_B are at a high level. The fifth transistor M5 is turned on, pulling up the pull-up node Q to a high level. The sixth transistor M6 and the seventh transistor M7 are turned on in control of the pull-up node Q, and output the second clock signal CLKB to the shift signal output terminal CR and the pixel scan signal output terminal Out. At this time, since the second clock signal CLKB is at a low level, both the shift signal output terminal CR and the pixel scan signal output terminal Out output low levels. The thirteenth transistor M13 is turned on, and the twelfth transistor M12 is turned on, causing a voltage division between the thirteenth transistor M13 and the twelfth transistor M12, so that the pull-down node QB goes to a low level.

[0104] In the second stage 2, the random signal OE and the blanking input signal STU1 become high, turning on the first transistor M1, pulling up the first node N1 to a high level, and storing it with the first capacitor C1. The second transistor M2 is turned on by the control of the first node N1 and writes the first clock signal CLKA to the second node N2. At this time, since the first clock signal CLKA is low level, the second node N2 also becomes low level, and the third transistor M3 is turned off. In this stage, the first capacitor C1 stores the high-level signal of the first node N1 and maintains it until the end of the display period of one frame, and uses it for the blanking period. The pull-up node Q remains high level, and the sixth transistor M6 and the seventh transistor M7 remain on, continuing to output low-level signals.

[0105] In the third stage, step 3, the second clock signal CLKB changes from a low level to a high level, and the bootstrap effect of the second capacitor C2 further increases the potential of the pull-up node Q, fully turning on the sixth transistor M6 and the seventh transistor M7, and outputting the high level of the second clock signal CLKB to the shift signal output terminal CR and the pixel scan signal output terminal Out.

[0106] In the fourth stage, the second clock signal CLKB changes to a low level, and due to the bootstrap effect of the second capacitor C2, the potential of the pull-up node Q decreases, but it still remains at a high level. The sixth transistor M6 and the seventh transistor M7 remain ON, and the low level of the second clock signal CLKB is output to the shift signal output terminal CR and the pixel scan signal output terminal Out, completing the reset of the output signals.

[0107] In the fifth stage, step 5, the display reset signal STD (not shown) goes high, turning on the 15th transistor M15, which resets the pull-up node Q and lowers it to a low level. The 6th transistor M6 and the 7th transistor M7 are turned off. The 13th transistor M13 is turned off, and the 12th transistor M12, which is turned on, pulls up the pull-down node QB to a high level. The 8th transistor M8 is turned on under the high-level action of the pull-down node QB, further reducing the noise of the pull-up node Q. The 9th transistor M9 and the 10th transistor M10 are turned on under the high-level action of the pull-down node QB, thus reducing the noise of the shift signal output terminal CR and the pixel scan signal output terminal Out. The 4th transistor M4 is turned on under the high-level action of the pull-down node QB, so that the 3rd transistor M3 is turned off, pulling down the 2nd node N2. In the subsequent stage following the display period DS, the pull-down node QB remains at a high level and the fourth transistor M4 remains on. Therefore, the third transistor M3 is turned off to prevent noise from being written to the pull-up node Q via the third transistor M3.

[0108] In each of the above stages, the second node N2 always maintains a low level, so the third transistor M3 is in the off state, thereby isolating the first voltage terminal VDD from the pull-up node Q, so that the first voltage of the first voltage terminal VDD does not affect the level of the pull-up node Q, and furthermore, does not affect the output signal during the display period. The level of the pull-up node Q is a tower waveform, the pull-up and reset of the output signal of the shift signal output terminal CR is realized by the sixth transistor M6, the pull-up and reset of the output signal of the pixel scan signal output terminal Out is realized by the seventh transistor M7, and the ninth transistor M9 and the tenth transistor M10 play an auxiliary pull-down role for the output signals of the shift signal output terminal CR and the pixel scan signal output terminal Out, so the size of the ninth transistor M9 and the tenth transistor M10 can be reduced, contributing to a reduction in circuit layout area.

[0109] During the blanking period BL, in the sixth stage 6, the first node N1 maintains the high level written during the display period, and the second transistor M2 remains ON. The first clock signal CLKA changes to a high level, and due to the bootstrap effect of the first capacitor C1, the level of the first node N1 rises further to the first level, for example, the first level is higher than the first voltage VDD. Thus, the threshold voltage lost by the first transistor M1 when charging the first node N1 during the display period is compensated. The high level of the first node N1 sufficiently turns on the second transistor M2, and the high level of the first clock signal CLKA is sufficiently written to the second node N2, for example, so that the level of the second node N2 becomes equal to the high level of the first clock signal CLKA. The third transistor M3 is turned on in control of the high level of the second node N2, pulling up the pull-up node Q to a high level. The sixth transistor M6 and the seventh transistor M7 are turned on, and the second clock signal CLKB is output to the shift signal output terminal CR and the pixel scan signal output terminal Out. At this time, since the second clock signal CLKB is low level, both the shift signal output terminal CR and the pixel scan signal output terminal Out output low levels. The thirteenth transistor M13 is turned on, and the twelfth transistor M12 is turned on, causing a voltage division between the thirteenth transistor M13 and the twelfth transistor M12, so that the pull-down node QB becomes low level.

[0110] In the seventh stage, the first clock signal CLKA changes to a low level, turning off the third transistor M3 and preventing the pull-up node Q from leaking through the third transistor M3. The sixth transistor M6 and the seventh transistor M7 remain on. The second clock signal CLKB changes to a high level, and due to the bootstrap effect of the second capacitor C2, the potential of the pull-up node Q rises further, turning on the sixth transistor M6 and the seventh transistor M7 sufficiently, outputting the high level of the second clock signal CLKB to the shift signal output terminal CR and the pixel scan signal output terminal Out.

[0111] In the eighth stage, the second clock signal CLKB changes to a low level, and due to the bootstrap effect of the second capacitor C2, the potential of the pull-up node Q decreases, but it still remains at a high level. The sixth transistor M6 and the seventh transistor M7 remain ON, and the low level of the second clock signal CLKB is output to the shift signal output terminal CR and the pixel scan signal output terminal Out, completing the reset of the output signals.

[0112] In the ninth stage (the final stage of the blanking period BL), the blanking reset signal TRST and the random signal OE become high, turning on the 14th transistor M14 and the first transistor M1, thereby resetting the pull-up node Q and the first node N1. This allows the first node N1 to be kept high for a short time to reduce the risk of transistor threshold voltage drift (e.g., positive drift) connected to the first node N1, thereby improving the reliability of this circuit.

[0113] In this embodiment, the blanking input circuit 100 compensates for the threshold voltage loss that occurs during the charging of the first node N1 by controlling the level of the second node N2 so that the level of the second node N2 becomes a predetermined value (for example, equal to or slightly less than the high level of the first clock signal CLKA). By controlling the level of the second node N2, the level of the pull-up node Q is also set to a predetermined value (for example, equal to or slightly less than the first voltage VDD), thereby avoiding threshold voltage loss that affects the level of the pull-up node Q and further improving the accuracy of the blanking output signal. According to software simulation, if the threshold voltage of each transistor is set to +10V and the high level of the first clock signal CLKA is set to +24V, the level of the second node N2 of the shift register unit 10 shown in Figure 6 can reach +24V, that is, it becomes equal to the high level of the first clock signal CLKA. The level of the first node N1 can be raised to over +35V due to the bootstrap effect of the first capacitor C1.

[0114] Figure 13 is a signal timing diagram of another shift register unit according to some embodiments of the present disclosure. For example, in this embodiment, the blanking input circuit 100 of the shift register unit 10 is implemented as the circuit configuration shown in Figure 9A, and the other structure of the shift register unit 10 is essentially the same as that of the shift register unit 10 shown in Figure 6. The gate of the fourth transistor M4 is connected to the fourth clock signal terminal CLKD to receive the fourth clock signal. For example, in Figure 13 and the following description, CLKD is used to represent both the fourth clock signal terminal and the fourth clock signal. As shown in Figure 13, during the display period DS, the fourth clock signal CLKD remains at a high level and the fourth transistor M4 remains in the ON state, so the second node N2 is continuously pulled down so that the third transistor M3 is in the OFF state during the display period. During the blanking period, the fourth clock signal CLKD changes to a low level and the fourth transistor M4 is turned OFF. Therefore, the first clock signal CLKA can pull up the second node N2, which in turn turns on the third transistor M3 and pulls up the pull-up node Q to a high level. The operating principle of the shift register unit 10 at the timing shown in Figure 13 is essentially the same as the operating principle described above, and is therefore omitted from this explanation.

[0115] At least one embodiment of the present disclosure further provides a gate drive circuit, which includes a shift register unit as described in any embodiment of the present disclosure. The gate drive circuit has a simple circuit configuration and can improve the loss of threshold voltage when the level control (e.g., pull-up) of a first control node (e.g., a pull-up node) is performed by a blanking input circuit during the blanking period, so as not to affect the potential of the first control node, thereby improving the accuracy of the blanking output signal.

[0116] Figure 14 is a schematic block diagram of a gate driver circuit according to several embodiments of the present disclosure. Referring to Figure 14, the gate driver circuit 20 includes a plurality of cascaded shift register units (A1, A2, A3, A4, etc.). The number of the plurality of shift register units is not particularly limited and can be appropriately determined according to the actual needs. For example, the shift register units may be the shift register units 10 described in any embodiment of the present disclosure. For example, in the gate driver circuit 20, some or all of the shift register units may be the shift register units 10 described in any embodiment of the present disclosure. For example, the gate driver circuit 20 may be directly integrated onto the array substrate of a display device using a fabrication process similar to that of thin-film transistors to form a GOA (Gate Driver On Array) and realize a progressive scan driving function.

[0117] For example, in some cases, shift register units every four stages share the same charging subcircuit 110, the same compensation subcircuit 120, and the same control subcircuit 140, thereby simplifying the circuit configuration and contributing to the realization of a narrow bezel. For example, when the shift register unit is implemented as the circuit shown in Figure 8, the shift register units every four stages share transistors M1, M1_b, M1_c, M2, M4_a, M4_b and a first capacitor C1, and each of the shift register units has a third transistor M3 (isolation subcircuit 130), and a second node N2 is connected to the gate of each third transistor M3 in the four-stage shift register unit. During the blanking period, when the second node N2 is high level, the four-stage shift register unit simultaneously outputs a blanking output signal, i.e., simultaneously performs compensation detection.

[0118] For example, referring to Figures 14 and 15A, the first stage shift register unit A1 includes transistors M1, M1_b, M1_c, M2, M4_a, M4_b and a first capacitor C1, and further includes a third transistor M3 <n>This includes the third transistor M3 in the second to fourth stage shift register units A2 to A4, respectively.<n+1> M3<n+2> and M3<n+3> The gates, including the first stage shift register unit A1, are all connected to the second node N2. When the second node N2 is high level, the third transistor M3 in the four shift register units A1 to A4 described above <n>M3<n+1> M3<n+2> and M3<n+3> Since all of these are turned on, the pull-up node Q in the four shift register units A1 to A4 mentioned above <n>Q<n+1> Q<n+2> and Q<n+3> All of these are pulled up to a high level, thereby further outputting the blanking output signal.

[0119] Figure 15B is a schematic of another implementation example for the shared case, where the charging subcircuit 110, compensation subcircuit 120, and control subcircuit 140 are implemented as shown in the circuit configuration in Figure 9A, and the other parts are essentially the same as the circuit shown in Figure 15A, and are omitted from this explanation. Figure 15C is a schematic of a further implementation example for the shared case, and compared to the example in Figure 15B, the isolation subcircuit 130 of each stage shift register unit has a pull-up node Q <n>Q<n+1> Q<n+2> and Q<n+3> A leakage prevention circuit has been added to prevent leakage. And the third transistor M3 of each stage shift register unit <n>M3<n+1> M3<n+2> and M3<n+3> All of the first poles are connected to the fifth clock signal terminal CLKE to receive the fifth clock signal as a blanking pull-up signal.

[0120] In the embodiments of this disclosure, the number of shift register units sharing the same charging subcircuit 110, the same compensation subcircuit 120, and the same control subcircuit 140 is not particularly limited and may be any number, as explained in the four examples above, but this does not limit the disclosure. Furthermore, the multiple shift register units sharing the above subcircuits may or may not be adjacent, and the embodiments of this disclosure are not limited to these.

[0121] In the gate drive circuit 20 shown in Figure 14, every four stages of shift register units share the same charging subcircuit 110, the same compensation subcircuit 120, and the same control subcircuit 140. Each shared subcircuit is provided in the 4n-3 stage shift register unit, where n is an integer greater than 0. Each shift register unit uses the circuit configuration shown in Figure 8. The specific cascade relationship of the gate drive circuit 20 will be described later.

[0122] For example, each shift register unit has a blanking input signal terminal STU1, a display input signal terminal STU2, a display reset signal terminal STD, a shift signal output terminal CR, a first pixel scan signal output terminal Out1, a second pixel scan signal output terminal Out2, a blanking reset signal terminal TRST, a second clock signal terminal CLKB, and a third clock signal terminal CLKC. The 4n-3 stage shift register unit further has a random signal terminal OE and a first clock signal terminal CLKA. For example, the random signal terminal OE of the 4n-3 stage shift register unit is connected to the random signal line OE_1, and the first clock signal terminal CLKA of the 4n-3 stage shift register unit is connected to the first clock line CLKA_1. The blanking reset signal terminal TRST of each stage shift register unit is connected to the blanking reset line TRST_1.

[0123] Except for the first stage, the blanking input signal terminal STU1 of the (n+1)th stage shift register unit is connected to the shift signal output terminal CR of the (n)th stage shift register unit. Except for the first and first stages, the display input signal terminal STU2 of the (n+2)th stage shift register unit is connected to the shift signal output terminal CR of the (n)th stage shift register unit. Except for the last three stages, the display reset signal terminal STD of the (n)th stage shift register unit is connected to the shift signal output terminal CR of the (n+3)th stage shift register unit. For example, the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first stage shift register unit A1 are connected to the trigger signal line STU, and the display input signal terminal STU2 of the second stage shift register unit A2 is also connected to the trigger signal line STU. The display reset signal terminal STD of the last three stages shift register units is connected to a separately provided reset signal line. The first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 of each shift register unit are connected to the pixel unit of the corresponding row, and are configured to output a drive signal to the pixel unit of that row.

[0124] For example, the gate drive circuit 20 further includes a first sub-clock signal line CLKB_1, a second sub-clock signal line CLKB_2, a third sub-clock signal line CLKB_3, and a fourth sub-clock signal line CLKB_4, and the connection between each stage shift register unit and each of the above-mentioned sub-clock signal lines will be described later. The second clock signal terminal CLKB of the 4n-3 stage shift register unit is connected to the first sub-clock signal line CLKB_1, the second clock signal terminal CLKB of the 4n-2 stage shift register unit is connected to the second sub-clock signal line CLKB_2, the second clock signal terminal CLKB of the 4n-1 stage shift register unit is connected to the third sub-clock signal line CLKB_3, and the second clock signal terminal CLKB of the 4n stage shift register unit is connected to the fourth sub-clock signal line CLKB_4.

[0125] For example, the gate drive circuit 20 further includes a fifth sub-clock signal line CLKC_1, a sixth sub-clock signal line CLKC_2, a seventh sub-clock signal line CLKC_3, and an eighth sub-clock signal line CLKC_4, and the connections between each stage shift register unit and each of the above-mentioned sub-clock signal lines will be described later. The third clock signal terminal CLKC of the 4n-3 stage shift register unit is connected to the fifth sub-clock signal line CLKC_1, the third clock signal terminal CLKC of the 4n-2 stage shift register unit is connected to the sixth sub-clock signal line CLKC_2, the third clock signal terminal CLKC of the 4n-1 stage shift register unit is connected to the seventh sub-clock signal line CLKC_3, and the third clock signal terminal CLKC of the 4n stage shift register unit is connected to the eighth sub-clock signal line CLKC_4.

[0126] For example, the gate drive circuit 20 may further include a timing controller T-CON, which is configured to supply the aforementioned clock signals to each of the stage shift register units, and the timing controller T-CON may further be configured to supply trigger and reset signals. The phase relationship between the multiple clock signals supplied by the timing controller T-CON can be appropriately determined according to the actual needs. In different examples, depending on the configuration, additional clock signals may be supplied to the gate drive circuit 20. For example, the gate drive circuit 20 may further include multiple voltage lines for supplying multiple voltage signals to each stage shift register unit.

[0127] For example, when the gate drive circuit 20 drives a display panel, the gate drive circuit 20 may be located on one side of the display panel. For example, the display panel may include a plurality of gate lines, and the first pixel scanning signal output terminal Out1 and the second pixel scanning signal output terminal Out2 of each stage shift register unit in the gate drive circuit 20 may be arranged to be sequentially connected to the plurality of gate lines in order to output drive signals. Of course, it is also possible to provide the gate drive circuit 20 on both sides of the display panel to achieve bidirectional drive, and the embodiments of this disclosure do not limit the manner in which the gate drive circuit 20 is provided.

[0128] Figure 16 shows a signal timing diagram of a gate drive circuit according to some embodiments of the present disclosure, which represents the timing of the gate drive circuit 20 shown in Figure 14. The operating principle of the gate drive circuit 20 can be found by referring to the corresponding description of the shift register unit 10 in the embodiments of the present disclosure, and is therefore omitted here.

[0129] Referring to Figure 16, the output signal Out2 of the second pixel scanning signal output terminal Out2 of the third and fourth stage shift register units A3 and A4. <3> and Out2 <4> The waveform is the output signal Out1 of the first pixel scanning signal output terminal Out1 during the display period of one frame. <3> and Out1 <4> The waveform is the same as the first pixel scanning signal output terminal Out1, and is sequentially shifted during the blanking period of each frame. <3> and Out1 <4> Unlike other waveforms, this allows it to meet the needs of various applications.

[0130] For example, the waveforms of the first sub-clock signal CLKB_1, the second sub-clock signal CLKB_2, the third sub-clock signal CLKB_3, and the fourth sub-clock signal CLKB_4 are sequentially superimposed to 50% of the effective pulse width during the display period of one frame, and are sequentially shifted during the blanking period of each frame. Output signal Out1 of the first pixel scanning signal output terminal Out1 of the third and fourth stage shift register units A3 and A4. <3> and Out1 <4> The waveforms of the gate drive circuit 20 overlap sequentially with 50% of the effective pulse width during the display period of one frame and are sequentially shifted during the blanking period of each frame. Because the output signal of the gate drive circuit 20 has overlapping timing during the display period, a pre-charge function is realized, the charging time of the pixel circuit can be shortened, and a high refresh rate can be achieved. The waveforms of the 5th to 8th sub-clock signals CLKC_1 to CLKC_4 overlap sequentially with 50% of the effective pulse width during the display period of one frame and are sequentially shifted during the blanking period of each frame, so the output signal of the second pixel scanning signal output terminal Out2 also has a portion where the timing overlaps during the display period.

[0131] In the embodiments of this disclosure, the gate drive circuit 20 is not limited to the cascade shown in Figure 14, but may be any applicable cascade. By changing the cascade method or clock signal, the waveforms of the output signals of the first pixel scan signal output terminal Out1 or the second pixel scan signal output terminal Out2 of each stage shift register unit change accordingly, including the overlapping portion during the display period, for example, by 33% or 0% (i.e., no overlap), thereby meeting the needs of various applications.

[0132] At least one embodiment of the present disclosure further provides a display device, which includes a shift register unit as described in any embodiment of the present disclosure, or a gate drive circuit as described in any embodiment of the present disclosure. The shift register unit or gate drive circuit of the display device has a simple circuit configuration and can improve the loss of threshold voltage when the level control (e.g., pull-up) of a first control node (e.g., a pull-up node) is performed by the blanking input circuit during the blanking period, so as not to affect the potential of the first control node, thereby improving the accuracy of the blanking output signal.

[0133] Figure 17 is a schematic block diagram of a display device according to some embodiments of the present disclosure. Referring to Figure 17, the display device 30 includes a gate drive circuit 20, and the gate drive circuit 20 is a gate drive circuit described in any embodiment of the present disclosure. For example, the display device 30 may be an OLED display panel, an OLED television, an OLED display, a liquid crystal display panel, a liquid crystal television, etc., or it may be a product or component having a display function such as an e-reader, mobile phone, tablet computer, notebook computer, digital photo frame, or navigation device, and the embodiments of the present disclosure are not limited to these. The technical effects of the display device 30 can be found by referring to the corresponding descriptions of the shift register unit 10 and the gate drive circuit 20 in the embodiments described above, and are omitted here.

[0134] For example, in some examples, the display device 30 includes a display panel 3000, a gate driver 3010, a timing controller 3020, and a data driver 3030. The display panel 3000 includes multiple pixel units P defined by the intersection of multiple scan lines GL and multiple data lines DL, the gate driver 3010 is used to drive the multiple scan lines GL, the data driver 3030 is used to drive the multiple data lines DL, and the timing controller 3020 is used to process image data RGB input from outside the display device 30 and supply the processed image data RGB to the data driver 3030, as well as to output scan control signals GCS and data control signals DCS to the gate driver 3010 and the data driver 3030 to control them.

[0135] For example, the gate driver 3010 includes a gate drive circuit 20 provided in any embodiment described above. The pixel scan signal output terminals Out of a plurality of shift register units 10 in the gate drive circuit 20 are connected to correspond to a plurality of scan lines GL. The plurality of scan lines GL are connected to correspond to a plurality of pixel units P arranged in a plurality of columns. During the display period, the pixel scan signal output terminals Out of each stage shift register unit 10 in the gate drive circuit 20 sequentially output signals to the plurality of scan lines GL so that the plurality of columns of pixel units P in the display panel 3000 can be scanned progressively. During the blanking period, the pixel scan signal output terminals Out of each stage shift register unit 10 in the gate drive circuit 20 randomly output signals to one or more scan lines GL so that compensation detection of one or more columns of pixel units P in the display panel 3000 can be enabled. For example, the gate driver 3010 may be implemented as a semiconductor chip or may be incorporated into the display panel 3000 to form a GOA circuit.

[0136] For example, the data driver 3030 converts the digital image data RGB input from the timing controller 3020 into a data signal using a reference gamma voltage based on a plurality of data control signals DCS supplied from the timing controller 3020. The data driver 3030 supplies the converted data signal to a plurality of data lines DL. For example, the data driver 3030 may be implemented as a semiconductor chip.

[0137] For example, the timing controller 3020 processes the RGB of externally input image data to match the size and resolution of the display panel 3000, and supplies the processed image data to the data driver 3030. The timing controller 3020 generates multiple scan control signals GCS and multiple data control signals DCS using synchronization signals (e.g., dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from outside the display device 30. The timing controller 3020 supplies the generated scan control signals GCS and data control signals DCS to the gate driver 3010 and the data driver 3030, respectively, in order to control them.

[0138] The display device 30 may further include other components such as a signal decoding circuit and a voltage conversion circuit, and these components may, for example, use existing components, which will not be described in detail here.

[0139] At least one embodiment of the present disclosure further provides a method for driving a shift register unit, which may be used to drive a shift register unit according to any embodiment of the present disclosure, and a plurality of such shift register units may be cascaded to form a gate drive circuit for driving a display panel to display at least one frame of a screen. The driving method improves the loss of threshold voltage when the level control (e.g., pull-up) of a first control node (e.g., a pull-up node) is performed by the blanking input circuit during the blanking period, so as not to affect the potential of the first control node, and thereby improves the accuracy of the blanking output signal.

[0140] For example, in some cases, the driving method of the shift register unit 10 includes a display period and a blanking period for processing one frame of image, the display period includes a first input stage and a first output stage, and the blanking period includes a second input stage and a second output stage. In each of the above stages, the driving method of the shift register unit 10 includes the following operations.

[0141] The display period is, The display input circuit 200 has a first input stage in which it inputs a display pull-up signal to a first control node (e.g., pull-up node Q) in response to the display input signal, The output circuit 300 includes a first output stage in which a composite output signal is output to the output terminal OP by controlling the level of a first control node (e.g., a pull-up node Q).

[0142] The blanking period is The blanking input circuit 100 inputs a blanking pull-up signal to a first control node (e.g., pull-up node Q) based on the blanking input signal and the blanking control signal, and a second input stage compensates the blanking input circuit 100 itself. The output circuit 300 includes a second output stage which outputs a composite output signal to the output terminal OP, with control of the level of a first control node (e.g., a pull-up node Q).

[0143] For a detailed explanation of the driving method and its technical effects, please refer to the corresponding descriptions of the shift register unit 10 and gate drive circuit 20 in the embodiments of this disclosure, and the explanation will be omitted here.

[0144] The following points need to be explained.

[0145] (1) The drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure, and other structures may refer to conventional designs.

[0146] (2) Where there is no contradiction, new embodiments can be obtained by combining the embodiments and features of the embodiments of this disclosure with each other.

[0147] As stated above, this is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and the scope of protection of the present disclosure shall be subject to the scope of protection of the claims described herein. [Explanation of Symbols]

[0148] 10 Shift register unit 100 Blanking input circuit 200 Display Input Circuit 300 output circuit 400 Noise Reduction Circuit 500 First control circuit< / n> < / n> < / n> < / n> < / n>

Claims

1. A shift register unit including a blanking input circuit, a display input circuit, and an output circuit, The blanking input circuit is configured to input the active level of the blanking pull-up signal to the first control node during the blanking period based on the active level of the blanking input signal and the active level of the blanking control signal, and to compensate for the loss of threshold voltage of the blanking input circuit. The display input circuit is configured to input the active level of the display pull-up signal to the first control node during the display period in response to the active level of the display input signal. The output circuit is configured to output a composite output signal to the output terminal by controlling the active level of the first control node. The shift register unit further includes a noise reduction circuit and a first control circuit, The noise reduction circuit is configured to set the first control node and the output terminal to a non-operating level in response to the active level of the second control node in order to achieve noise reduction. The first control circuit is configured to set the second control node to a non-operating level in response to the active level of the first control node. The blanking input circuit described above is A charging subcircuit is arranged to input the active level of the blanking input signal to a first node in response to the active level of the blanking control signal, A compensation subcircuit is configured to store the active level of the blanking input signal input by the charging subcircuit, compensate the level of the first node in response to the active level of the first clock signal to compensate for the loss of the threshold voltage, and couple to control the level of the second node, The system includes an isolated subcircuit arranged to input the blanking pull-up signal to the first control node in response to the active level of the second node, The blanking input circuit further includes a control subcircuit that, in response to the active level of the second control node, is configured to set the level of the second node to a non-operating level. The charging subcircuit includes a first transistor, The gate of the first transistor is arranged to be connected to a random signal terminal to receive a random signal as the blanking control signal. The first pole of the first transistor is arranged to be connected to the blanking input signal terminal in order to receive the blanking input signal, The second pole of the first transistor is arranged to be connected to the first node, The compensation subcircuit includes a second transistor and a first capacitor. The gate of the second transistor is positioned to be connected to the first node, The first pole of the second transistor is arranged to be connected to the first clock signal terminal to receive the first clock signal, The second pole of the second transistor is positioned to be connected to the second node, The first pole of the first capacitor is arranged to be connected to the first node, The second pole of the first capacitor is positioned to be connected to the second node. The isolation subcircuit includes a third transistor, The gate of the third transistor is positioned to be connected to the second node, The first pole of the third transistor is arranged to be connected to the first voltage terminal to receive the first voltage as the blanking pull-up signal. The second pole of the third transistor is arranged to be connected to the first control node. The control subcircuit includes a fourth transistor, The gate of the fourth transistor is positioned to be connected to the second control node. The first pole of the fourth transistor is arranged to be connected to the second node, A shift register unit in which the second pole of the fourth transistor is connected to a second voltage terminal to receive a second voltage.

2. The display input circuit includes a fifth transistor, The gate of the fifth transistor is positioned to be connected to the display input signal terminal in order to receive the display input signal. The first pole of the fifth transistor is arranged to be connected to the first voltage terminal to receive the first voltage as the indicator pull-up signal. The shift register unit according to claim 1, wherein the second pole of the fifth transistor is arranged to be connected to the first control node.

3. The shift register unit according to claim 1, wherein the output circuit includes at least one shift signal output terminal and at least one pixel scanning signal output terminal.

4. The output circuit includes a sixth transistor, a seventh transistor, and a second capacitor. The gate of the sixth transistor is positioned to be connected to the first control node. The first pole of the sixth transistor is arranged to be connected to the second clock signal terminal in order to receive the second clock signal as the composite output signal. The second pole of the sixth transistor is arranged to be connected to the shift signal output terminal. The gate of the seventh transistor is positioned to be connected to the first control node. The first pole of the seventh transistor is arranged to be connected to the second clock signal terminal in order to receive the second clock signal as the composite output signal. The second pole of the seventh transistor is arranged to be connected to the pixel scanning signal output terminal. The first pole of the second capacitor is arranged to be connected to the first control node. The shift register unit according to claim 3, wherein the second pole of the second capacitor is connected to the second pole of the sixth transistor or the second pole of the seventh transistor.

5. The noise reduction circuit includes an eighth transistor, a ninth transistor, and a tenth transistor. The gate of the eighth transistor is positioned to be connected to the second control node. The first pole of the eighth transistor is arranged to be connected to the first control node. The second pole of the eighth transistor is arranged to be connected to the third voltage terminal to receive the third voltage, The gate of the ninth transistor is positioned to be connected to the second control node, The first pole of the ninth transistor is arranged to be connected to the shift signal output terminal. The second pole of the ninth transistor is arranged to be connected to the third voltage terminal to receive the third voltage, The gate of the tenth transistor is positioned to be connected to the second control node, The first pole of the tenth transistor is arranged to be connected to the pixel scanning signal output terminal. The shift register unit according to claim 3, wherein the second pole of the tenth transistor is arranged to be connected to a fourth voltage terminal for receiving a fourth voltage.

6. The first control circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor, The gate of the 11th transistor is connected to the first pole and is arranged to be connected to the fifth voltage terminal to receive the fifth voltage, The second pole of the 11th transistor is arranged to be connected to the second control node, The gate of the 12th transistor is connected to the first pole and is arranged to be connected to the sixth voltage terminal to receive the sixth voltage, The second pole of the 12th transistor is arranged to be connected to the second control node, The gate of the 13th transistor is positioned to be connected to the first control node. The first pole of the 13th transistor is arranged to be connected to the second control node. The shift register unit according to claim 1, wherein the second pole of the 13th transistor is arranged to be connected to a third voltage terminal for receiving a third voltage.

7. The circuit further includes a blanking reset circuit arranged to reset the first control node in response to the active level of the blanking reset signal. The shift register unit according to claim 1.

8. The blanking reset circuit includes a 14th transistor, The gate of the 14th transistor is arranged to be connected to the blanking reset signal terminal in order to receive the blanking reset signal. The first pole of the 14th transistor is arranged to be connected to the first control node. The shift register unit according to claim 7, wherein the second pole of the 14th transistor is arranged to be connected to a third voltage terminal for receiving a third voltage.

9. The circuit further includes a display reset circuit arranged to reset the first control node in response to the active level of the display reset signal. The shift register unit according to claim 1.

10. The display reset circuit includes a 15th transistor, The gate of the 15th transistor is arranged to be connected to the display reset signal terminal in order to receive the display reset signal. The first pole of the 15th transistor is arranged to be connected to the first control node. The shift register unit according to claim 9, wherein the second pole of the 15th transistor is arranged to be connected to a third voltage terminal for receiving a third voltage.

11. The system further includes a second control circuit configured to set the level of the second control node to a non-operating level in response to the active level of the first clock signal or the active level of the display input signal. The shift register unit according to claim 1.

12. The second control circuit includes a 16th transistor and a 17th transistor, The gate of the 16th transistor is arranged to be connected to the first clock signal terminal in order to receive the first clock signal. The first pole of the 16th transistor is arranged to be connected to the second control node. The second pole of the 16th transistor is positioned to receive the third voltage at the third voltage terminal. The gate of the 17th transistor is positioned to be connected to the display input signal terminal in order to receive the display input signal. The first pole of the 17th transistor is arranged to be connected to the second control node, The shift register unit according to claim 11, wherein the second pole of the 17th transistor is arranged to be connected to the third voltage terminal for receiving the third voltage.

13. A gate drive circuit including a shift register unit according to any one of claims 1 to 12.

14. Each shift register unit, every four stages, shares the same charging subcircuit, the same compensation subcircuit, and the same control subcircuit. The random signal terminal of the 4n-3 stage shift register unit is connected to the random signal line, and the first clock signal terminal of the 4n-3 stage shift register unit is connected to the first clock line. (wherein n is an integer greater than 0) The gate drive circuit according to claim 13.

15. It further includes a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line. The second clock signal terminal of the 4n-3 stage shift register unit is connected to the first sub-clock signal line. The second clock signal terminal of the 4n-2 stage shift register unit is connected to the second sub-clock signal line. The second clock signal terminal of the 4n-1 stage shift register unit is connected to the third sub-clock signal line. The second clock signal terminal of the 4n-th stage shift register unit is connected to the fourth sub-clock signal line. (wherein n is an integer greater than 0) The gate drive circuit according to claim 13.

16. The blanking input signal terminal of the (n+1)th stage shift register unit is connected to the shift signal output terminal of the nth stage shift register unit. The display input signal terminal of the (n+2)th stage shift register unit is connected to the shift signal output terminal of the nth stage shift register unit. The display reset signal terminal of the nth shift register unit is connected to the shift signal output terminal of the (n+3)th shift register unit. (wherein n is an integer greater than 0) The gate drive circuit according to claim 13.

17. A shift register unit according to any one of claims 1 to 12, A display device comprising a gate drive circuit according to any one of claims 13 to 16.

18. A method for driving the shift register unit according to claim 1, This includes a display period and a blanking period for processing one frame of image, The aforementioned display period is, The display input circuit includes a first input step in which the active level of the display pull-up signal is input to the first control node in response to the active level of the display input signal, The output circuit has a first output stage in which it outputs the composite output signal to the output terminal by controlling the active level of the first control node, Includes, The aforementioned blanking period is The blanking input circuit inputs the active level of the blanking pull-up signal to the first control node based on the active level of the blanking input signal and the active level of the blanking control signal, and a second input step compensates for the loss of threshold voltage of the blanking input circuit. The output circuit includes a second output stage in which the composite output signal is output to the output terminal by controlling the active level of the first control node, A method for driving a shift register unit, including the following.

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