System and method for defragmentation of memory devices

Abstract

In an aspect, the memory controller includes a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to the file, and a controller processor configured to control the memory device, receive a mapping update command, and update the L2P address mapping table in accordance with the mapping update command by replacing original logical addresses of the logical block address (LBA) segments of the file with new contiguous logical addresses of the merged LBA segment of the file, and changing original mapping relationships between the original logical addresses of the LBA segments of the file and the physical addresses of the file to new mapping relationships between the new contiguous logical addresses of the merged LBA segment of the file and the physical addresses of the file.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for defragmenting memory devices.

Background Art

[0002] Data stored in systems and memory devices becomes fragmented over time. This degrades the performance of the system and memory devices by reducing access and processing speeds. Sometimes, it further causes unwanted corruption and data loss. Defragmentation is a process that reduces the degree of fragmentation by reorganizing the data in the storage device for faster access and better system performance.

Summary of the Invention

Means for Solving the Problems

[0003] In one aspect, a memory controller includes a controller memory for storing a logical-physical (L2P) address mapping table corresponding to a file, and a controller processor configured to control a memory device, receive a mapping update command, replace an original logical address of a logical block address (LBA) segment of a file with a new consecutive logical address of a merged LBA segment of the file, and change an original mapping relationship between the original logical address of the LBA segment of the file and the physical address of the file to a new mapping relationship between the new consecutive logical address of the merged LBA segment of the file and the physical address of the file, so as to update the L2P address mapping table according to the mapping update command.

[0004] In some implementations, the controller memory includes a volatile controller memory for storing an L2P address mapping table corresponding to a file.

[0005] In some implementations, the controller memory further includes non-volatile controller memory. The controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

[0006] In some implementations, the controller processor is configured to send an instruction to the host confirming that the L2P address mapping table has been updated.

[0007] In some implementations, the controller processor is configured to generate a merge log by recording a new mapping relationship between the new contiguous logical addresses of the file merge LBA segment and the physical addresses of the files.

[0008] In some implementations, in response to a sudden power loss, the controller processor is configured to reconstruct the volatile L2P address mapping table according to a merge log that records the new mapping relationships between the new contiguous logical addresses of the file's merged LBA segment and the file's physical addresses after the memory system has been restored.

[0009] In some implementations, the controller processor is configured to scan the physical-to-logical (P2L) address mapping table and merge log of the metadata block, and in response to updates to the merge log, the controller processor is configured to rebuild the L2P address mapping table according to the merge log.

[0010] In another embodiment, the memory system includes a memory device containing physical data blocks, a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a memory controller which includes a controller processor configured to control the memory device, receive mapping update commands, and update the L2P address mapping table in accordance with the mapping update command by replacing the original logical addresses of the logical block address (LBA) segments of the file with new contiguous logical addresses of the merged LBA segments of the file, and changing the original mapping relationship between the original logical addresses of the LBA segments of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file.

[0011] In some implementations, the controller memory includes volatile controller memory for storing L2P address mapping tables corresponding to files.

[0012] In some implementations, the controller memory further includes non-volatile controller memory. The controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

[0013] In some implementations, the controller processor is configured to send an instruction to the host confirming that the L2P address mapping table has been updated.

[0014] In some implementations, the controller processor is configured to generate a merge log by recording a new mapping relationship between the new contiguous logical addresses of the file merge LBA segment and the physical addresses of the files.

[0015] In some implementations, in response to a sudden power loss, the controller processor is configured to reconstruct the L2P address mapping table according to a merge log that records the new mapping relationships between the new contiguous logical addresses of the file's merged LBA segment and the physical addresses of the file after the memory system has been restored.

[0016] In some implementations, the controller processor is configured to scan the physical-to-logical (P2L) address mapping table and merge log of the metadata block, and in response to updates to the merge log, the controller processor is configured to rebuild the L2P address mapping table according to the merge log.

[0017] In yet another embodiment, the system includes a host comprising host memory configured to store files, a host processor configured to execute merge LBA commands to remap the original logical addresses of the logical block address (LBA) segments of a file to the new contiguous logical addresses of the merged LBA segments of the file, and to send mapping update commands, a memory device comprising physical data blocks, a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a memory controller comprising a controller processor configured to control the memory device, receive mapping update commands, and update the L2P address mapping table in accordance with the mapping update command by replacing the original logical addresses of the LBA segments of the file with the new contiguous logical addresses of the merged LBA segments of the file, and by changing the original mapping relationship between the original logical addresses of the LBA segments of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file.

[0018] In some implementations, the controller memory includes volatile controller memory for storing L2P address mapping tables corresponding to files.

[0019] In some implementations, the host processor is configured to remap the original logical addresses of the LBA segments of a file to the new logical addresses of the merged LBA segments of the file by rewriting all the logical addresses of the LBA segments of the file to available or unused LBA segments in a contiguous order of logical addresses so that they become the new contiguous logical addresses of the merged LBA segments of the file.

[0020] In some implementations, the host processor is configured to send a mapping update command to the memory controller, causing it to update the L2P address mapping table according to the new contiguous logical addresses of the merged LBA segments of the file.

[0021] In some implementations, the host processor is configured to receive instructions from the memory controller confirming that the L2P address mapping table has been updated.

[0022] In some implementations, the host processor is configured to update the file's index node after confirming that the L2P address mapping table has been updated.

[0023] In some implementations, the host processor is configured to update the file's index node by pointing the new LBA segment to a new contiguous logical address in the merged LBA segment.

[0024] In yet another aspect, a method for operating a memory controller includes receiving a mapping update command from a host, replacing the original logical address of an LBA segment of a file with a new consecutive logical address of a merged LBA segment of the file, and changing an original mapping relationship between the original logical address of the LBA segment of the file and the physical address of the file to a new mapping relationship between the new consecutive logical address of the merged LBA segment of the file and the physical address of the file, thereby updating a logical-physical (L2P) address mapping table according to the mapping update command.

[0025] In some implementations, the method further includes sending an indication to the host to confirm that the L2P address mapping table has been updated.

[0026] In some implementations, the method further includes recording a new mapping relationship between the new consecutive logical address of the merged LBA segment of the file and the physical address of the file in a merge log, and reconstructing the L2P address mapping table according to the merge log after the memory system is restarted in response to a sudden power loss.

[0027] In some implementations, the step of reconstructing the L2P address mapping table includes scanning a physical-logical (P2L) address mapping table of a metadata block and the merge log, and reconstructing the L2P address mapping table according to the merge log in response to a determination that the merge log has been updated.

[0028] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate aspects of the disclosure and, together with the description, serve to further explain the disclosure and enable a person skilled in the art to make and use the disclosure.

Brief Description of the Drawings

[0029] [Figure 1] A block diagram of an exemplary system having a host and a memory system, according to some aspects of the present disclosure. [Figure 2A] A diagram of an exemplary memory card having a memory device, according to some aspects of the present disclosure. [Figure 2B] A diagram of an exemplary solid state drive (SSD) having a memory device, according to some aspects of the present disclosure. [Figure 3] A schematic diagram of an exemplary memory device including peripheral circuits, according to some aspects of the present disclosure. [Figure 4A] A block diagram of an exemplary memory system including a memory controller and a memory device, according to some aspects of the present disclosure. [Figure 4B] A block diagram of an exemplary memory system including a memory controller and a memory device, according to some aspects of the present disclosure. [Figure 5] A block diagram of an exemplary system including a host and a memory controller, according to some aspects of the present disclosure. [Figure 6] A block diagram showing an exemplary defragmentation method, according to some aspects of the present disclosure. [Figure 7] A block diagram showing an exemplary defragmentation method, according to some aspects of the present disclosure. [Figure 8] A block diagram showing an exemplary defragmentation method under sudden power loss, according to some aspects of the present disclosure. [Figure 9] A flowchart of an exemplary method for operating a memory controller, according to some aspects of the present disclosure. [Figure 10] A flowchart of an exemplary method for operating a host, according to some aspects of the present disclosure.

MODE FOR CARRYING OUT THE INVENTION

[0030] Aspects of the present disclosure will be described with reference to the accompanying drawings.

[0031] While specific configurations and arrangements are described, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be applied to various other applications. Functional and structural features described in this disclosure can be combined, adjusted, and modified with respect to each other, and in ways not specifically depicted in the drawings, and such combinations, adjustments, and modifications are within the scope of this disclosure.

[0032] In general, technical terms can be understood, at least partially, from their usage in context. For example, depending at least partially on the context, the term “one or more” as used herein may be used in a singular sense to describe any feature, structure, or property, or in a plural sense to describe a combination of features, structures, or properties. Similarly, terms such as “a,” “an,” or “the” can also be understood, at least partially on the context, to convey either a singular or plural usage. In addition, the term “based on” may not necessarily be understood as intended to describe an exclusive set of factors, but rather, at least partially on the context, may allow for the existence of additional factors that are not necessarily explicitly described.

[0033] Disk defragmentation is a technique that allows users to defragment not only hard disk drives (HDDs) but also other removable storage. For example, Windows systems such as Windows 7 include a disk defragmentation utility called Microsoft Drive Optimizer or Disk Defragmenter, which allows users to defragment their hard disks, increasing data access speed and improving overall computer performance by rearranging files stored on the disk to occupy adjacent storage locations. Disk defragmentation, however, is not considered effective for solid-state drives (SSDs). In fact, defragmenting an SSD is generally not recommended because it can exhaust the SSD's write cycles, potentially leading to premature failure of the SSD. Nevertheless, with the development of SSDs and the increase in their storage capacity, the software input / output stack (I / O stack) becomes a system bottleneck. That is, files fragmented at the logical level degrade system performance.

[0034] One solution to resolve fragmentation at the logical level is to use a defragmenter such as e2defrag. e2defrag can read each segment of a file's logical address and select contiguous logical address blocks to write. However, while e2defrag updates logical address blocks, it can also update physical blocks each time a logical address block is updated, thereby increasing the effects of write amplification, an undesirable phenomenon associated with flash memory and solid-state drives where the actual amount of information physically written to the storage medium is a multiple of the logical amount intended to be written. This write amplification can wear out an SSD faster than expected, shortening its lifespan. Furthermore, conventional e2defrag wastes time due to its redundant process of routinely updating physical address blocks each time a segment is read and a logical address block is updated. It is not sufficiently effective to solve the fragmentation problem at the logical level.

[0035] Furthermore, conventional defragmentation tools often lack adequate power loss protection to ensure that data is not lost while an SSD is writing data in the event of a sudden power failure. A sudden power loss while the defragmentation process is underway can cause significant system corruption or data loss. Mechanisms to prevent data loss from sudden power losses during defragmentation are highly desirable.

[0036] To address one or more of the aforementioned problems, this disclosure presents a solution in which the Merge Logical Block Address (LBA) command is designed to merge segments of LBAs in a file into a merged LBA segment in the file, and then update the logical-to-physical (L2P) address mapping table according to the merged LBA segment in the file. Furthermore, a merge log is created to record the mapping relationships between the L2P address mapping table and the physical-to-logical (P2L) address mapping table before updating the L2P address mapping table. Thus, after a sudden power loss, L2P can be reconstructed or restored by using the merge log and the P2L address mapping table.

[0037] Figure 1 shows a block diagram of an exemplary system 100 having a memory device according to certain aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having internal storage. As shown in Figure 1, system 100 may include a host 108 having host memory 110 and a host processor 112, and a memory system 102 having one or more memory devices 104 and a memory controller 106.

[0038] The host 108 may be a processor of an electronic device such as a central processing unit (CPU), or a system-on-a-chip (SoC) such as an application processor (AP). The host 108 may be coupled to a memory controller 106 and configured to send or receive data to or from a memory device 104 through the memory controller 106. For example, the host 108 may send program data in a program operation or receive read data in a read operation. The host processor 112 may be a control unit (CU) or an arithmetic logic unit (ALU). The host memory 110 may be a memory unit including registers or cache memory. The host 108 may receive and send instructions and commands to and from the memory controller 106 of the memory system 102, and may be configured to perform or do the multiple functions and operations provided in this disclosure, which will be described later.

[0039] The memory device 104 may be any of the memory devices disclosed herein, such as a NAND flash memory device, which includes a page buffer having multiple parts, for example, four quotas. It should be noted that NAND flash is merely an example of a memory device for illustrative purposes. It may include any suitable solid-state, non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), spin-transfer-write magnetic random-access memory (STT-RAM), or resistive random-access memory (RRAM). In some implementation examples, the memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0040] The memory controller 106 can be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gate logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform various functions as detailed below.

[0041] In some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low-duty-cycle environments such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in high-duty-cycle environments such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations, by providing the memory device 104 with commands such as read commands. For example, the memory controller 106 may be configured to control read operations by providing read commands to the peripheral circuits of the memory device 104. The memory controller 106 may also be configured to manage various functions related to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 106 is further configured to process error correction codes (ECC) for data read from or written to the memory device 104. The memory controller 106 may also perform any other appropriate functions, such as formatting the memory device 104.

[0042] The memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device through at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0043] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices contained in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. In other words, the memory system 102 can be implemented and packaged into different types of final electronic products. In one example, as illustrated in Figure 2A, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include PC cards (PCMCIA, International Personal Computer Memory Card Association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 that connects the memory card 202 to a host (e.g., host 108 in Figure 1). In another example, as illustrated in Figure 2B, the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 206. The SSD206 may further include an SSD connector 208 that connects the SSD206 to a host (for example, host 108 in Figure 1). In some implementations, the storage capacity and / or operating speed of the SSD206 are greater than those of the memory card 202.

[0044] The memory controller 106 is configured to receive and send commands to and from the host 108, and to perform or do the multiple functions and operations provided in this disclosure, which will be described later.

[0045] Figure 3 shows a schematic circuit diagram of an exemplary memory device 300, including peripheral circuits, relating to certain aspects of the present disclosure. The memory device 300 may be an example of the memory device 104 in Figure 1. It should be noted that the NAND flash disclosed herein is merely an example of a memory device for illustrative purposes. It may include any suitable solid-state, non-volatile memory, such as NOR flash, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically above a substrate (not shown). In some implementation examples, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog quantity, such as voltage or charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 can be either a floating-gate type memory cell including a floating-gate transistor or a charge-trap type memory cell including a charge-trap transistor.

[0046] In some implementations, each memory cell 306 is a single-level cell (SLC) capable of storing one bit of data, having two possible memory states. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing two or more bits of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0047] As shown in Figure 3, each NAND memory string 308 may include a source selection gate (SSG) transistor 310 at its source end and a drain selection gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 can be configured to activate a selected NAND memory string 308 (a column in the array) during read and program operations. In some implementations, the sources of NAND memory strings 308 within the same block 304 are coupled through the same source line (SL) 314, for example, a common SL. In other words, all NAND memory strings 308 within the same block 304 have an array common source (ACS), according to some implementations. The drain of the DSG transistor 312 of each NAND memory string 308 is coupled, according to some implementations, to a respective bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., exceeding the threshold voltage of the DSG transistor 312) or a deselection voltage (e.g., 0V) to the gate of each DSG transistor 312 through one or more DSG lines 313 and / or by applying a selection voltage (e.g., exceeding the threshold voltage of the SSG transistor 310) or a deselection voltage (e.g., 0V) to the gate of each SSG transistor 310 through one or more SSG lines 315.

[0048] As shown in Figure 3, the NAND memory string 308 can be organized into multiple blocks 304, each of which may have a common source line 314 connected to, for example, ACS. In some implementations, each block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase the memory cells 306 in a selected block 304, a source line 314 connected to the selected block 304, as well as to an unselected block 304 on the same plane as the selected block 304, can be biased with an erase voltage (Vers), such as a positive high voltage (e.g., 20V or higher). Memory cells 306 in adjacent NAND memory strings 308 can be connected via word lines 318 that select which rows of memory cells 306 are affected by read and program operations. In some implementations, each word line 318 is connected to a page 320 of the memory cell 306, which is a basic data unit for program and read operations. The bit size of one page 320 can relate to the number of NAND memory strings 308 coupled by word lines 318 within one block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupling the control gates in each memory cell 306 within each page 320. Peripheral circuits 302 can be coupled to the memory cell array 301 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuits 302 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuits 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0049] Figure 4A shows a block diagram of an exemplary memory system 102, including a memory controller 106 and a memory device 104, relating to certain aspects of the present disclosure. As shown in Figure 4A, the memory controller 106 may include a controller processor 408, such as a memory chip controller (MCC) or memory controller unit (MCU). The controller processor 408 is configured to control a module that executes commands or instructions to perform the functions disclosed in the present disclosure. The controller processor 408 may also be configured to control the operation of each peripheral circuit by generating and sending various control signals, such as read commands for read operations. The controller processor 408 may also send clock signals to other peripheral circuits 302 at desired frequencies, periods, and duty cycles to control the operation of each peripheral circuit 302, for example, for synchronization. The memory controller 106 may further include a volatile controller memory 411 and a non-volatile controller memory. The volatile controller memory 411 may include registers or cache memory so that it does not have to retain the stored information after power is removed, while allowing it to read, write, or erase the data stored internally at faster access and processing speeds. In some implementations, the volatile controller memory 411 includes dynamic random access memory (DRAM) and static random access memory (SRAM). The non-volatile controller memory 413 can retain the stored information even after power is removed. In some implementations, the non-volatile controller memory 413 includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device 104 may include a memory cell array, such as the memory cell array 301 in Figure 3. In some implementations, the non-volatile controller memory 413 cannot be located on the memory controller 106; for example, the non-volatile controller memory 413 is moved outside the memory controller 106 but is coupled to it.In some implementations, controller memory (e.g., 411 or 413) is configured to store L2P address mapping tables (e.g., 4271, 4273) corresponding to files (e.g., 129).

[0050] Figure 4B shows a block diagram of an exemplary memory system 102, including a memory controller 106 and a memory device 104, relating to certain aspects of the present disclosure. As shown in Figure 4B, the memory controller 106 may include a memory controller interface 429 configured to receive and send commands or instructions to and from a host (e.g., host 108 in Figure 1). In some implementations, the memory controller interface 429 is coupled to a controller processor 408 to receive and send commands or instructions causing the controller processor 408 to perform the functions disclosed herein.

[0051] The memory controller 106 may also include an update module 421 configured to generate and update the volatile L2P address mapping table 4271, the volatile merge log 4251, the non-volatile L2P mapping table 4273, and the non-volatile merge log 4253. The update module 421 may be implemented in the firmware of the controller processor 408 through a firmware program. In some implementations, the update module 421 is configured to update the physical data block 431 and / or metadata block 433 in the memory device 104. In some implementations, the update module 421 may reside in or be coupled to the controller processor 408 and be controlled by the controller processor 408 to execute commands and instructions from the host 108. For example, the update module 421 is configured to execute mapping update commands received from the host 108 and update the volatile L2P address mapping table 4271 according to the mapping update commands. In some implementations, the update module 421 is configured to update the volatile L2P address mapping table 4271 by rewriting the file's merged LBA segment's contiguous logical addresses into the volatile L2P address mapping table 4271. In some implementations, the update module 421 is configured to update the volatile L2P address mapping table 4271 by replacing the original logical addresses of the file's LBA segment with the new contiguous logical addresses of the file's merged LBA segment, and by changing the original mapping relationship between the file's LBA segment's original logical addresses and the file's physical addresses to a new mapping relationship between the file's merged LBA segment's new contiguous logical addresses and the file's physical addresses. The process of forming the contiguous logical addresses of the file's merged LBA segment will be described later.Then, after updating the L2P address mapping table 4271, the update module 421 in the controller processor 408 will send an instruction to the host 108 to confirm that the volatile L2P address mapping table 4271 has been updated, and as a result the host 108 may update the index node of the file in the host memory 110.

[0052] In some implementations, the volatile L2P address mapping table 4271 is stored and processed in the volatile controller memory 411 and is configured to be sent to and updated in the non-volatile L2P address mapping table 4273 stored in the physical data block 431, so that the data is not erased after a power off. In some implementations, after the system is restarted, the volatile L2P address mapping table 4271 in the volatile controller memory 411 can be loaded from the non-volatile L2P address mapping table 4273 in the physical data block 431 for faster access and processing speeds than usual. In some implementations, the non-volatile L2P address mapping table 4273 can also be stored in the non-volatile controller memory 413 of the memory controller 106.

[0053] The merge logs (e.g., volatile merge log 4251 and non-volatile merge log 4253) are configured to record the mapping relationships between the L2P address mapping table (e.g., 4271 or 4273) and the physical addresses of the physical data block 431 prior to the update of the L2P address mapping table. In some implementations, the merge logs are configured to record the new mapping relationships between the new contiguous logical addresses of the merged LBA segments of file 129 that each updated the L2P address mapping table and the physical addresses of file 129. Thus, after a sudden power loss, the volatile L2P address mapping table 4271 may not yet be updated and can be reconstructed or restored by using the non-volatile merge log 4253 and the physical addresses of the physical data block 431 after the system (e.g., 100) is restarted. In some implementations, it should be noted that the update rate of the non-volatile merge log 4253 is faster than that of the non-volatile L2P address mapping table 4273, as it contains relatively small amounts of data compared to the non-volatile L2P address mapping table 4273, while it has already been recorded during the sudden power loss, thus avoiding excessive write amplification. Specifically, in response to a sudden power loss, the recovery module 423 in the controller processor 408 may scan the physical-logical (P2L) address mapping table 435 and the non-volatile merge log 4253 in the metadata block 433 in the memory device 104, and in response to the non-volatile merge log 4253 being updated, reconstruct the volatile L2P address mapping table 4271 according to the non-volatile merge log 4253 and the physical addresses of the physical data block 431 held before the sudden power loss. Then, in response to the non-volatile merge log 4253 not being updated, the volatile L2P address mapping table 4271 is reconstructed according to the physical-to-logical (P2L) address mapping table 435 of the metadata block 433 and the physical addresses of the physical data block 431 that were retained before the sudden power loss.It should be noted that the metadata block 433 is a relatively small portion of the data blocks in the memory cell array 301. The metadata block 433 is configured to store logical address information for the data stored in the physical data block 431. The logical address information is written to the metadata block 433 simultaneously when data is written to the physical data block 431, so that the data can be recovered after a sudden power loss. In some implementations, the volatile merge log 4251 is configured to be stored and processed in the volatile controller memory 411 and then sent to and updated in the non-volatile merge log 4253 stored in the physical data block 431, so that the data is not erased after a power off. In some implementations, after the system is restarted, the volatile merge log 4251 in the volatile controller memory 411 can be loaded from the non-volatile merge log 4253 in the physical data block 431 for faster access and processing speeds than usual. In some implementations, the non-volatile merge log 4253 can also be stored in the non-volatile controller memory 413 of the memory controller 106. The recovery module 423 may be implemented in the firmware of the controller processor 408 through a firmware program.

[0054] Figure 5 shows a block diagram of an exemplary system 100, including a host 108 and a memory controller 106, relating to certain aspects of the present disclosure. As shown in Figure 5, the host 108 may include a host interface 125, host memory 110, and a host processor 112. The host interface 125 is configured to receive commands or instructions from a user to perform or execute a particular function or operation. The host memory 110 may store the logical addresses of files (e.g., file 129), such as logical block addresses (LBAs), and the index nodes 127 of the files (e.g., inodes). The host processor 112 may include, or be combined with, an index node update module 121 (e.g., an inode update module) and a merge LBA module 123. The index node update module 121 is configured to update the index nodes 127 of the files after the controller processor 408 of the memory controller 106 (e.g., in Figure 4A) sends an instruction to the host 108 confirming that the volatile L2P address mapping table 4271 has been updated. The index node update module 121 can update the file's index node 127 even after receiving an instruction that the physical data block 431 (e.g., in Figure 4B) has been updated. It should be noted that an index node (e.g., an inode) can be a data structure in a Unix-style filesystem that describes a filesystem object such as a file or directory. It can be a file data structure that stores information about any Linux® file except its name and data. It stores the file's metadata, including the file size, the device on which the file is stored, the user and group IDs associated with the file, or the permissions required to access the file. In some implementation examples, the host processor 112 is configured to update the file's index node 127 by pointing a new LBA segment to a contiguous logical address in the merged LBA segment.

[0055] A merge LBA module 123, included in or combined with the host processor 112, is configured to execute a merge LBA command to rearrange LBA segments (e.g., fragments of logical addresses in logical blocks) of file 129 into merge LBA segments. For example, as shown in Figure 6, file A129 may contain one or more LBA segments (e.g., LBA segment 1, LBA segment 2, LBA segment 3..., LBA segment N). Each time the file is modified in the operating system, the number of LBA segments increases, and the file is subdivided. Using a conventional e2defrag tool, as described above, it may be necessary to read multiple LBA segments one by one and find a contiguous logical address block to which the new segments of the file should be written. The e2defrag tool then updates the physical data blocks according to the new segments of the file. Therefore, each time the logical address block is updated, the physical data block is updated, thereby causing excessive write amplification. The merge LBA module 123 may, as provided in this disclosure, execute a merge LBA command to rearrange the LBA segments of file 129 into a merge LBA segment. Specifically, rearranging the LBA segments of file 129 involves rewriting all logical addresses of the LBA segments of file 129 to consecutive, sequential, available or unused logical address blocks (e.g., available or unused LBA segments) so that they form a contiguous logical address block (e.g., a merge LBA segment). Unlike conventional e2defrag tools, the merge LBA segment is not used to update physical data blocks (e.g., physical data block 431 in Figure 4B). The merge LBA segment is used only to update the volatile L2P address mapping table 4271 in Figure 4B. By doing so, write amplification is minimized because the physical data blocks are not updated every time the logical address blocks are updated.

[0056] After executing the merge LBA command, the host processor 112 may send a mapping update command to the controller processor in the memory controller 106 (e.g., 408 in Figure 4A) to update the volatile L2P address mapping table 4271 according to the merge LBA segment. As shown in Figure 7, the volatile L2P address mapping table 4271, which originally had discontinuous and discrete logical addresses (e.g., LBA9, LBA11, LBA13, LBA18) corresponding to the logical addresses of the LBA segment in file 129 (e.g., LBA9, LBA11, LBA13, LBA18), is updated to form a contiguous logical address block (e.g., LBA114, LBA115, LBA116, LBA117). The physical addresses (e.g., PA333, PA337, PA339, PA440) of the updated volatile L2P address mapping table 4271 destined for the corresponding physical addresses of the physical data block 431 remain unchanged during the update process described above. Therefore, after the defragmentation process, physical data block 431 remains unchanged and undeleted.

[0057] Figure 8 shows a block diagram illustrating an exemplary defragmentation scheme under sudden power loss, relating to certain aspects of the present disclosure. As described above, when sudden power loss occurs, the volatile L2P address mapping table 4271 may not be updated or may not be able to complete its current update, and therefore the physical data may not be updated, potentially leading to data loss. A metadata block of a memory device (e.g., memory device 104) (e.g., metadata block 433 in Figure 4B) may have an old, incorrect P2L mapping table (e.g., P2L address mapping table 435 in Figure 4B) that records the physical addresses (e.g., LBA9, LBA11, LBA13, LBA18) of the old L2P address mapping table. The non-volatile merge log 4253 stores the mapping relationships between the P2L address mapping table 435 and the volatile L2P address mapping table 4271 after each update of the volatile L2P address mapping table 4271 (for example, LBA9 of the P2L points to LBA114 of the new L2P, LBA11 of the P2L points to LBA115 of the new L2P, LBA13 of the P2L points to LBA116 of the new L2P, and LBA18 of the P2L points to LBA117 of the new L2P). Therefore, the new volatile L2P address mapping table 4271 can be reconstructed using the non-volatile merge log 4253 and the retained P2L address mapping table 435 according to the mapping relationships.

[0058] Figure 9 shows a flowchart illustrating an exemplary method for operating a memory controller according to certain aspects of the present disclosure. The memory controller may be any suitable memory controller disclosed herein, for example, memory controller 106 in Figure 4B. Method 900 may be partially or fully implemented by memory controller 106 as shown in Figure 4A. It is understood that the operations shown in Method 900 do not have to be exhaustive, and that other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in a different order than shown in Figure 9.

[0059] Referring to Figure 9, method 900 begins with operation 902, in which the memory controller (for example, memory controller 106 as shown in Figure 4A) receives a mapping update command from the host (for example, host 108 as shown in Figure 5). In some implementations, the mapping update command may cause the memory controller 106 to activate the update module 421.

[0060] Method 900 proceeds to operation 904, as shown in Figure 9, in which the L2P address mapping table stored in the memory controller 106 (e.g., volatile L2P address mapping table 4271 in Figure 4B) is updated according to the mapping update command. In some implementation examples, updating the L2P address mapping table involves rewriting the contiguous logical addresses of the merged LBA segment in a file (e.g., file 129 in Figures 5-7) into the L2P address mapping table.

[0061] Method 900 proceeds to operation 906, as shown in Figure 9, to update the L2P address mapping table, after which an instruction is sent to the host confirming that the L2P address mapping table has been updated. In some implementations, once the L2P address mapping table update is complete, the update module is configured to send instructions to the host through an interface (e.g., the memory controller interface 429 in Figure 4B). The host may then update the index nodes of the files stored in host memory.

[0062] Furthermore, method 900 may further include operations that implement protection against sudden power loss. Specifically, method 900 may also include recording in a merge log (e.g., a non-volatile merge log 4253 in Figure 4B) the mapping relationships between the P2L address mapping table (e.g., the P2L mapping table in Figure 4B) and the L2P address mapping table in a metadata block (e.g., the metadata block 433 in Figure 4B). After a sudden power loss, when the system is restarted, method 900 may further include scanning the P2L address mapping table in the metadata block and the merge log. Then, in response to a determination that the merge log has been updated, the L2P address mapping table is reconstructed according to the merge log and the P2L address mapping table in the metadata block. Also, in response to a determination that the merge log has not been updated, the L2P address mapping table is restored according to the P2L address mapping table in the metadata block. These operations can be implemented by a recovery module 423 as shown in Figure 4B.

[0063] Figure 10 shows a flowchart of an exemplary method for operating a host according to certain aspects of this disclosure. The host may be any suitable host disclosed herein. Method 1000 may be partially or completely implemented by a host 108 as shown in Figure 5. It is understood that the operations shown in Method 1000 do not have to be exhaustive, and that other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in a different order than shown in Figure 10.

[0064] Referring to Figure 10, method 1000 begins with operation 1002, in which a merge LBA command is executed to rearrange the LBA segments of a file (e.g., file 129 as in Figure 5) stored in host memory (e.g., host memory 110 in Figure 5) into a merge LBA segment. In some implementations, the merge LBA command may cause the host processor (e.g., host processor 112 in Figure 5) to invoke a merge LBA module (e.g., merge LBA module 123 in Figure 5). In some implementations, rearranging the LBA segments of a file into a merge LBA segment includes rewriting the LBA segments of the file, which have discontinuous or discrete logical addresses, into a merge LBA segment with contiguous logical addresses. In some implementations, rearranging the LBA segments of a file into a merge LBA segment includes sequentially reading the logical addresses of the LBA segments of the file before rewriting the logical addresses of the merge LBA segment, so that the merge LBA segment contains all of the LBA segments of the file.

[0065] Method 1000 proceeds to operation 1004, as shown in Figure 10, in which a mapping update command is sent to the memory controller (e.g., memory controller 106 in Figure 4A) to cause the memory controller's controller processor (e.g., controller processor 408 in Figure 4A) to update the L2P address mapping table (e.g., volatile L2P address mapping table 4271 in Figure 4B) according to the merged LBA segment. In some implementation examples, updating the L2P address mapping table involves rewriting the contiguous logical addresses of the merged LBA segment of the file into the L2P address mapping table.

[0066] Method 1000 proceeds to operation 1006, as shown in Figure 10, where an instruction is received from the controller processor confirming that the L2P address mapping table has been updated. In some implementations, after receiving the instruction, an index node update module (e.g., index node update module 121) is activated.

[0067] Method 1000 proceeds to operation 1008, as shown in Figure 10, where the file index node is updated after confirming that the L2P address mapping table has been updated.

[0068] The above description of specific implementation examples can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementation examples, based on the teachings and guidance presented herein.

[0069] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be determined solely in accordance with the appended claims and their equivalents. [Explanation of Symbols]

[0070] 100 Systems 102 memory systems 104 Memory Devices 106 Memory Controller 108 hosts 110 Host memory 112 host processors 121 Index Node Update Module 123 Merge LBA Module 125 Host Interface 127 Index Nodes 129 files 202 memory card 204 Memory card connector 206 SSD 208 SSD connectors 300 memory devices 301 memory cell array 302 Peripheral Circuits 304 blocks 306 memory cells 308 NAND memory string 310 Source Select Gate (SSG) Transistor 312 Drain-Selected Gate (DSG) Transistor 313 DSG line 314 Common Source Line 315 SSG Line 316-bit line 318 Word lines 320 pages 408 Controller Processor 411 Volatile Controller Memory 413 Non-volatile controller memory 421 Update Module 423 Recovery Module 4251 Volatile Merge Log 4253 Non-volatile merge log 4271 Volatile Logical-to-Physical (L2P) Address Mapping Table 4273 Non-volatile L2P address mapping table 429 Memory Controller Interface 431 physical data blocks 433 Metadata Blocks 435 Physical-to-Logical (P2L) Address Mapping Table

Claims

1. Controller memory for storing logical-to-physical (L2P) address mapping tables corresponding to files, Control memory devices, receive mapping update commands, Replacing the original logical address of the logical block address (LBA) segment of the aforementioned file with a new contiguous logical address of the merged LBA segment of the aforementioned file, The original mapping relationship between the original logical address of the logical block address (LBA) segment of the file and the physical address of the file is changed to a new mapping relationship between the new contiguous logical address of the merged LBA segment of the file and the physical address of the file. The L2P address mapping table is updated according to the mapping update command, A controller processor configured to generate a merge log by recording the new mapping relationship between the new contiguous logical addresses of the merge LBA segment of the file and the physical addresses of the file. A memory controller comprising, The aforementioned controller processor In response to a sudden power outage, Scan the physical-to-logical (P2L) address mapping table and the merge log within the metadata block, If the merge log has been updated, the L2P address mapping table is reconstructed according to the merge log and the physical address. If the merge log has not been updated, the system is configured to restore the physical-logical (P2L) address mapping table and the L2P address mapping table according to the physical addresses in the metadata block. Memory controller.

2. The memory controller according to claim 1, wherein the controller memory comprises a volatile controller memory for storing the L2P address mapping table corresponding to the file.

3. The controller memory, The memory controller according to claim 2, further comprising a non-volatile controller memory, wherein the controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

4. The memory controller according to claim 1, wherein the controller processor is configured to send an instruction to the host confirming that the L2P address mapping table has been updated.

5. The memory controller according to claim 1, wherein the reconstruction of the L2P address mapping table is performed according to the merge log which records the new mapping relationships between the new contiguous logical addresses of the merged LBA segment of the file and the physical addresses of the file.

6. A memory device comprising physical data blocks, It is a memory controller, Controller memory for storing logical-to-physical (L2P) address mapping tables corresponding to files, Control the aforementioned memory device and receive mapping update commands. Replacing the original logical address of the logical block address (LBA) segment of the aforementioned file with a new contiguous logical address of the merged LBA segment of the aforementioned file, The original mapping relationship between the original logical address of the logical block address (LBA) segment of the file and the physical address of the file is changed to a new mapping relationship between the new contiguous logical address of the merged LBA segment of the file and the physical address of the file. A memory controller comprising a controller processor configured to update the L2P address mapping table in accordance with the mapping update command and generate a merge log by recording the new mapping relationship between the new contiguous logical addresses of the merged LBA segment of the file and the physical addresses of the file. A memory system comprising, The aforementioned controller processor In response to a sudden power outage, Scan the physical-to-logical (P2L) address mapping table and the merge log within the metadata block, If the merge log has been updated, the L2P address mapping table is reconstructed according to the merge log and the physical address. If the merge log has not been updated, the system is configured to restore the physical-logical (P2L) address mapping table and the L2P address mapping table according to the physical addresses in the metadata block. Memory system.

7. The memory system according to claim 6, wherein the controller memory comprises a volatile controller memory for storing the L2P address mapping table corresponding to the file.

8. The controller memory, The memory system according to claim 6, further comprising a non-volatile controller memory, wherein the controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

9. The memory system according to claim 6, wherein the controller processor is configured to send an instruction to the host confirming that the L2P address mapping table has been updated.

10. The memory system according to claim 6, wherein the reconstruction of the L2P address mapping table is performed according to the merge log which records the new mapping relationships between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file.

11. The memory system according to claim 6, wherein the memory device comprises a three-dimensional (3D) NAND flash memory device.

12. The steps include receiving a mapping update command from the host, Replacing the original logical address of the LBA segment of the file with the new contiguous logical address of the merged LBA segment of the said file, The original mapping relationship between the original logical address of the LBA segment of the file and the physical address of the file is changed to a new mapping relationship between the new contiguous logical address of the merged LBA segment of the file and the physical address of the file. The steps include updating the logical-to-physical (L2P) address mapping table corresponding to the file in accordance with the mapping update command, The steps include recording in the merge log the new mapping relationship between the new contiguous logical address of the merge LBA segment of the file and the physical address of the file, In response to a sudden power outage, The steps include scanning the physical-to-logical (P2L) address mapping table and the merge log within the metadata block, If the merge log has been updated, the step of reconstructing the L2P address mapping table according to the merge log and the physical address, If the merge log has not been updated, the steps include restoring the physical-logical (P2L) address mapping table in the metadata block and the L2P address mapping table according to the physical address, A method for operating a memory controller, How to operate the memory controller.

13. Steps to send an instruction to the host confirming that the L2P address mapping table has been updated. The method according to claim 12, further comprising:

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