Protection circuits and hazards

Abstract

This protection circuit comprises a first insulated gate field-effect transistor, a first main electrode of which is connected between an external terminal and an internal circuit, a second main electrode and a gate electrode of which are connected to a standard power source, and in which a charge accumulation unit capable of accumulating hot carriers is provided to a gate insulating film.

Description

Technical Field

[0001] The present disclosure relates to a protection circuit and a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a high-frequency integrated circuit with an electrostatic protection element. The electrostatic protection element electrically connects a depletion-type field-effect transistor and an enhancement-type field-effect transistor in series, and further electrically connects a capacitor in parallel to the enhancement-type field-effect transistor. The field-effect transistor is composed of a MESFET, a gate junction FET, a HEMT, etc. When noise or a high-voltage pulse is input from the outside, in the electrostatic protection element, the enhancement-type field-effect transistor undergoes a breakdown operation, and its impedance is lowered, so that the noise or high-voltage pulse can be discharged.

[0003] Also, Patent Document 2 discloses a surge protection element and a semiconductor device. The surge protection element is composed of a pnp bipolar transistor. This bipolar transistor is configured with a p-type GaN layer as a collector region, an AlGaN layer and a GaN layer as a base region, and a p-type GaN layer as an emitter region. In the surge protection element, the surge is absorbed as a punch-through current.

[0004] Furthermore, Patent Document 3 discloses a semiconductor integrated circuit provided with an electrostatic breakdown protection circuit. The electrostatic breakdown protection circuit is composed of a diode-connected transistor. A bipolar transistor or a MOSFET is used for the transistor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

[0006] High-frequency power amplifiers operating in the millimeter-wave band are being developed for next-generation mobile devices. These high-frequency power amplifiers utilize insulated-gate field-effect transistors (MISFETs) made from GaN-based wide-bandgap materials. Specifically, metal-insulator-semiconductor field-effect transistors (MISFETs) are being used. The electrostatic discharge (ESD) protection element disclosed in Patent Document 1, the surge protection element disclosed in Patent Document 2, and the electrostatic discharge (ESD) protection circuit disclosed in Patent Document 3 all utilize a p-type layer. In GaN-based processes, the activation rate of p-type impurities is very low, making it difficult to manufacture p-type GaN, resulting in poor process compatibility (mass production capability) in the manufacturing process. In other words, realizing protection elements using p-type GaN is difficult. For this reason, there is a need for protection circuits and semiconductor devices with excellent electrostatic discharge (ESD) resistance or avalanche resistance.

[0007] This technology provides protective circuits and semiconductor devices with excellent ESD withstand capability or avalanche withstand capability.

[0008] The protection circuit according to the first embodiment of this disclosure includes a first insulated gate field-effect transistor in which a first main electrode is connected between an external terminal and an internal circuit, a second main electrode and a gate electrode are connected to a reference power supply, and a charge storage unit capable of accumulating hot carriers is disposed in the gate insulating film.

[0009] A semiconductor device according to a second embodiment of the present disclosure comprises an external terminal disposed on a substrate, an internal circuit disposed on the substrate and connected to the external terminal, and a protection circuit disposed on the substrate, having a first insulated gate field-effect transistor in which a first main electrode is connected between the external terminal and the internal circuit, a second main electrode and a gate electrode are connected to a reference power supply, and a charge storage unit capable of accumulating hot carriers is disposed in the gate insulating film. [Brief explanation of the drawing]

[0010] [Figure 1] This is a layout diagram (plan view) of a high-frequency power amplifier module on which a semiconductor device equipped with a protection circuit and internal circuit according to the first embodiment of this disclosure is mounted. [Figure 2] Figure 1 is a circuit block diagram of the protection circuit and internal circuit of the semiconductor device shown. [Figure 3] Figures 1 and 2 show the cross-sectional structure of the MISFETs that make up the protection circuit and internal circuitry. Figure 4 shows a cross-sectional view of the main part of the semiconductor device (a cross-sectional view cut along line AA shown in Figure 4). [Figure 4] Figures 1 and 2 are plan views of the main components of a semiconductor device illustrating the planar structure of the MISFET that constitutes the protection circuit and internal circuitry shown. [Figure 5] This is a first step cross-sectional view corresponding to Figure 3, illustrating a method for manufacturing a semiconductor device equipped with a protection circuit and internal circuit according to the first embodiment. [Figure 6] This is a cross-sectional view of the second process illustrating the manufacturing method of a semiconductor device. [Figure 7] This is a cross-sectional view of the third step in the manufacturing process of a semiconductor device. [Figure 8] This is a cross-sectional view of the fourth step in the manufacturing process of a semiconductor device. [Figure 9] This is a cross-sectional view of the fifth step in the manufacturing process of a semiconductor device. [Figure 10] This is a cross-sectional view of the sixth step in the manufacturing process of a semiconductor device. [Figure 11] This is a cross-sectional view of the seventh step in the manufacturing process of a semiconductor device. [Figure 12] It is a cross-sectional view of the eighth step for explaining a method of manufacturing a semiconductor device. [Figure 13] It is a flowchart for explaining a method of adjusting the threshold voltage of the protection circuit shown in FIGS. 2 to 4. [Figure 14] It is a timing chart for explaining a method of adjusting the threshold voltage of the protection circuit based on the flowchart shown in FIG. 13. [Figure 15] It is a cross-sectional view of a main part of a semiconductor device corresponding to FIG. 3 for explaining a cross-sectional structure of a MISFET that constructs a protection circuit and an internal circuit according to the second embodiment of the present disclosure. [Figure 16] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the third embodiment of the present disclosure. [Figure 17] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the fourth embodiment of the present disclosure. [Figure 18] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the fifth embodiment of the present disclosure. [Figure 19] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the sixth embodiment of the present disclosure. [Figure 20] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the seventh embodiment of the present disclosure. [Figure 21] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the eighth embodiment of the present disclosure. [Figure 22] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the ninth embodiment of the present disclosure. [Figure 23] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the tenth embodiment of the present disclosure. [Figure 24] It is a circuit block diagram of a protection circuit and an internal circuit corresponding to FIG. 2 of a semiconductor device according to the eleventh embodiment of the present disclosure. [Figure 25]This is a circuit block diagram of the protection circuit and internal circuit corresponding to Figure 2 of the semiconductor device according to the twelfth embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be given in the following order. 1. First Embodiment The first embodiment describes a first example of applying this technology to a radio frequency (RF) power amplifier module that implements a semiconductor device equipped with a protection circuit and an internal circuit. Here, the configuration of the RF power amplifier module, the layout of the semiconductor device, the configuration of the circuit blocks of the protection circuit and the internal circuit, the longitudinal cross-sectional structure, the planar structure, the manufacturing method, and the method for adjusting the threshold voltage of the protection circuit are described. 2. Second Embodiment The second embodiment describes a second example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment. 3. Third Embodiment The third embodiment describes a third example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment. 4. Fourth Embodiment The fourth embodiment describes a fourth example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment. 5. Fifth Embodiment The fifth embodiment describes a fifth example that combines the semiconductor device according to the third embodiment and the semiconductor device according to the fourth embodiment. 6. Sixth Embodiment The sixth embodiment describes a sixth example in which the configuration of the protection circuit is changed in the semiconductor device according to the fourth embodiment. 7. Seventh Embodiment The seventh embodiment describes a seventh example that combines the semiconductor device according to the fifth embodiment and the semiconductor device according to the sixth embodiment. 8. Eighth Embodiment The eighth embodiment describes an eighth example in which the configuration of the protection circuit is changed in the semiconductor device according to the sixth embodiment. 9. Ninth Embodiment The ninth embodiment describes a ninth example that combines the semiconductor device according to the seventh embodiment and the semiconductor device according to the eighth embodiment. 10. Tenth Embodiment The tenth embodiment describes a tenth example in which the configuration of the protection circuit is changed in the semiconductor device according to the eighth embodiment. 11. Eleventh Embodiment The 11th embodiment describes an 11th example that combines the semiconductor device according to the 9th embodiment and the semiconductor device according to the 10th embodiment. 12. Twelfth Embodiment The twelfth embodiment describes a twelfth example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment. 13. Other Embodiments

[0012] <1. First Embodiment> The protection circuit 22, protection circuit 23, and semiconductor device 2 according to the first embodiment of this disclosure will be explained with reference to Figures 1 to 14. Here, the arrow X direction, as shown in the figure, conveniently indicates one planar direction of the semiconductor device 2 placed on a plane. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates the upward direction, perpendicular to both the arrow X and arrow Y directions. In other words, the arrow X, arrow Y, and arrow Z directions coincide precisely with the X-axis, Y-axis, and Z-axis directions of the three-dimensional coordinate system, respectively. These directions are provided to aid in understanding the explanation and do not limit the directions of this technology.

[0013] [Configuration of protection circuit 22 and semiconductor device 2] (1) Planar layout configuration of RF power amplifier module 1 Figure 1 shows the planar layout of RF power amplifier module 1. The RF power amplifier module 1 comprises an input matching circuit 3, a semiconductor device 2, an output matching circuit 4, and a DC bias circuit 5. These input matching circuits 3 and others are mounted on a circuit board 10. For mounting, solder is used, for example.

[0014] The substrate 10 is formed as a module substrate. When viewed from the direction of arrow Z (hereinafter simply referred to as "in a plan view"), the substrate 10 is formed in a rectangular shape, for example. The input matching circuit 3 is mounted on the upper left side of the circuit board 10. The RF signal is input to the input matching circuit 3 from outside the RF power amplifier module 1.

[0015] The semiconductor device 2 is mounted in the center of the substrate 10. The semiconductor device 2 includes a protection circuit 22, an internal circuit 24, and a protection circuit 23. The protection circuit 22 is configured as an input-side protection circuit. The protection circuit 22 is connected to the input matching circuit 3 and the internal circuit 24, respectively. In the first embodiment, the internal circuit 24 includes an RF power amplifier. For example, the internal circuit 24 includes an RF power amplifier that operates in the millimeter-wave band for fifth-generation or later-generation mobile terminals. The protection circuit 23 is configured as an output-side protection circuit. The protection circuit 23 is connected to both the internal circuit 24 and the output matching circuit 4. Since the configuration of the protection circuit 23 is the same as that of the protection circuit 22, further explanation is omitted.

[0016] The output matching circuit 4 is mounted on the lower right side of the circuit board 10. The output matching circuit 4 outputs the RF signal to the outside of the RF power amplifier module 1. The DC bias circuit 5 is mounted on the underside of the circuit board 10. The DC bias circuit 5 is connected to the semiconductor device 2. The DC bias circuit 5 is supplied with DC power from outside the RF power amplifier module 1. Furthermore, a reference power supply GND is supplied to the power supply wiring (not shown) arranged on the circuit board 10. The reference power supply GND is, for example, 0V.

[0017] (2) Circuit block configuration of the protection circuit 22 and semiconductor device 2 Figure 2 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2.

[0018] The semiconductor device 2 includes an external terminal 201 as an input-side external terminal and an internal circuit 24 connected to this external terminal 201. The external terminal 201 and the internal circuit 24 are formed on a semiconductor substrate 21. The external terminal 201 is connected to the input matching circuit 3. The internal circuit 24 is, in this case, an RF power amplifier. A coupling capacitor 202 is electrically connected in series between the external terminal 201 and the internal circuit 24. One end of a DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24, and the other end of the DC bias resistor 203 is connected to the external power supply terminal 208. A DC bias circuit 5 is connected to the external power supply terminal 208, and a DC negative bias power supply, for example, is supplied from the DC bias circuit 5. Furthermore, one electrode of a decoupling capacitor 207 is connected between the other end of the DC bias resistor 203 and the external power supply terminal 208. The other electrode of the decoupling capacitor 207 is connected to the reference power supply GND.

[0019] The semiconductor device 2 further includes a protection circuit 22 as an input-side protection circuit. In the first embodiment, the protection circuit 22 includes one MISFET 221. The MISFET 221 corresponds to the "first insulated gate field-effect transistor" in this technology. The MISFET221 is equipped with a charge storage section (see reference numeral 219 in Figure 3) capable of accumulating hot carriers in the gate insulating film. When no hot carriers are stored in the charge storage section, the MISFET221 is adjusted to a depletion-type threshold voltage. On the other hand, when hot carriers are stored in the charge storage section, the MISFET221 is adjusted to an enhancement-type threshold voltage. When operating as the protection circuit 22, the MISFET221 is adjusted to an enhancement-type threshold voltage.

[0020] One of the first main electrodes of the MISFET221 (e.g., the drain electrode) is connected between the external terminal 201 and the internal circuit 24 via a DC bias resistor 203. More specifically, the first main electrode is connected between the coupling capacitor 202 and the internal circuit 24. The other second main electrode of the MISFET221 (e.g., the source electrode) and the gate electrode are connected to the reference power supply GND. The protection circuit 22 further includes a resistor 222. The resistor 222 is electrically connected in series between the second main electrode and the gate electrode of the MISFET 221. The resistor 222 corresponds to the "resistor" in this technology. The resistor 222 is set to a resistance value of, for example, 100Ω or more and 10MΩ or less. The DC bias resistor 203 is set to a resistance value of, for example, 10Ω or more and 10MΩ or less, similar to the resistor 222.

[0021] The protection circuit 22 is equipped with a first external terminal 204, a second external terminal 205, and a third external terminal 206 for injecting hot carriers into the charge storage area of ​​the MISFET 221. In this case, the hot carriers are hot electrons. The first external terminal 204, the second external terminal 205, and the third external terminal 206 are arranged on the semiconductor substrate 21. The first external terminal 204 is connected to the first main electrode of the MISFET 221. The first external terminal 204 corresponds to the "first external terminal" in this technology. The second external terminal 205 is connected to the second main electrode. The second external terminal 205 corresponds to the "second external terminal" in this technology. The third external terminal 206 is connected to the gate electrode. The third external terminal 206 corresponds to the "third external terminal" in this technology.

[0022] (3) Longitudinal cross-sectional structure and planar structure of the protection circuit 22 and internal circuit 24 Figure 3 shows the longitudinal cross-sectional structure of the protection circuit 22 and the internal circuit 24. Figure 4 shows the planar structure of the protection circuit 22 and the internal circuit 24. The internal circuit 24 includes a MISFET 241 that constructs it.

[0023] The MISFET 221, which constructs the protection circuit 22, and the MISFET 241, which constructs the internal circuit 24, are formed on the semiconductor substrate 21 with a buffer layer 211 in between. For example, a Si substrate is used for the semiconductor substrate 21. For example, in the case of a 6-inch Si wafer, the Si substrate is formed to a thickness of 600 μm to 700 μm. For example, AlGaN is used for the buffer layer 211. The AlGaN is formed to a thickness of 0.3 μm to 1.0 μm using, for example, an epitaxial growth method. Furthermore, a ceramic substrate such as a sapphire substrate can be used instead of the semiconductor substrate 21.

[0024] (3-1) Configuration of MISFET241 First, the MISFET 241, which constructs the internal circuit 24, is arranged on the buffer layer 211 within a region surrounded by the element isolation section 212. The MISFET 241 comprises a semiconductor layer 213, a two-dimensional electron gas (hereinafter simply referred to as "2DEG") 214, a gate insulating film 215, a gate electrode 216, and a pair of main electrodes 217. The MISFET 241 corresponds to the "second insulated gate field-effect transistor" in this technology.

[0025] The element isolation section 212 amorphousizes the semiconductor layer 213 between adjacent MISFETs 241, eliminating the conductivity of 2DEG214. The element isolation section 212 is formed, for example, using ion implantation. In ion implantation, for example, B ions are used as the implanted ions. More specifically, for example, the acceleration energy is 50 keV and the dose is 1 × 10⁻⁶ 15 ions / cm 2 Under certain conditions, B ions are implanted.

[0026] The semiconductor layer 213 here comprises a GaN layer 213A, a GaN channel layer 213B, an AlN layer 213C, and an InAlN layer 213D. The GaN layer 213A is stacked on the buffer layer 211. The GaN layer 213A is formed to a thickness of, for example, 0.8 μm to 1.5 μm. The GaN channel layer 213B is stacked on top of the GaN layer 213A. The GaN channel layer 213B is formed to a thickness of, for example, 100 nm to 500 nm. The AlN layer 213C is stacked on the GaN channel layer 213B. The AlN layer 213C is formed to a thickness of, for example, 0.5 nm to 1.5 nm. The InAlN layer 213D is stacked on top of the AlN layer 213C. The InAlN layer 213D is formed to a thickness of, for example, 5 nm to 15 nm.

[0027] 2DEG214 is generated in the GaN channel layer 213B near the interface between the GaN channel layer 213B and the InAlN layer 213D, extending from one main electrode 217 to the other main electrode 217. Since 2DEG214 is constantly generated when no gate voltage is supplied to the gate electrode 216, the MISFET 214 is in a conductive state. In other words, the MISFET 214 is a depletion type. The MISFET241 is constructed using a high-electron-mobility transistor (HEMT) structure utilizing compound semiconductor materials. In particular, an InAlN layer 213D is stacked in the generation of 2DEG214, and the spontaneous polarization of the InAlN layer 213D is utilized, which increases the carrier concentration of 2DEG214. Therefore, because the MISFET241 employs a HEMT structure, the RF output of the internal circuit 24, i.e., the RF power amplifier, can be enhanced.

[0028] The gate insulating film 215 is formed on the semiconductor layer 213. The gate insulating film 215 here comprises a first oxide film 215A and a second oxide film 215B laminated on the first oxide film 215A. The oxide film is formed by containing at least one selected from Al2O3, HfO2, Ta2O5, ZrO2, Y2O3, and SiO2. In the first embodiment, Al2O3 is used for the first oxide film 215A. The first oxide film 215A is formed to a thickness of, for example, 1 nm to 10 nm. In addition, HfO2 is used for the second oxide film 215B. The second oxide film 215B is formed to a thickness of, for example, 1 nm to 10 nm.

[0029] The gate electrode 216 is stacked on the gate insulating film 215. Here, the gate electrode 216 is formed by a multilayer film of, for example, Ni and Au stacked on top of Ni. The Ni layer is formed to a thickness of, for example, 30 nm to 50 nm. The Au layer is formed to a thickness of, for example, 400 nm to 500 nm. Furthermore, the gate length dimension of the MISFET241 is set to, for example, 0.1 μm or more and 0.3 μm or less. Here, the gate length dimension is the length of the gate electrode 216 in the direction (arrow X direction) that coincides with the direction in which the pair of main electrodes 217 are arranged.

[0030] A pair of main electrodes 217 are stacked on the GaN channel layer 213B in contact with or on the 2DEG 214. In the pair of main electrodes 217, one main electrode 217 is used as a first main electrode, for example, a drain electrode. The other main electrode 217 is used as a second main electrode, for example, a source electrode. The main electrode 217 is formed by a thermal diffusion method of a multilayer film including, for example, Ti, Al layered on Ti, Ni layered on Al, and Au layered on Ni. The main electrode 217 is an ohmic electrode. The Ti layer is formed to a thickness of, for example, 5 nm to 15 nm. The Al layer is formed to a thickness of, for example, 50 nm to 150 nm. The Ni layer is formed to a thickness of, for example, 15 nm to 25 nm. The Au layer is formed to a thickness of, for example, 5 nm to 15 nm.

[0031] Furthermore, an insulator 218 is disposed between the gate insulating film 215, the gate electrode 216, and the main electrode 217. The insulator 218 is also disposed on the element isolation portion 212. The insulator 218 is made of, for example, Al2O3.

[0032] (3-2) Configuration of MISFET221 On the other hand, the MISFET 221, which constructs the protection circuit 22, is disposed on the buffer layer 211 within a region surrounded by the element isolation section 212, similar to the MISFET 241. The MISFET 221 comprises a semiconductor layer 213, a 2DEG 214, a gate insulating film 215, a charge storage section 219, a gate electrode 216, and a pair of main electrodes 217. In the semiconductor layer 213, an InAlN layer 213E is provided instead of an InAlN layer 213D.

[0033] Hot carriers can be stored in the charge storage section 219. In the MISFET 221, hot carriers are injected from 2DEG 214 into the charge storage section 219 near the main electrode 217, which serves as the drain electrode, and the injected hot carriers are stored in the charge storage section 219. When no hot carriers are accumulated in the charge storage section 219, 2DEG214 is generated in the GaN channel layer 213B near the interface between the GaN channel layer 213B and the InAlN layer 213E, extending from one main electrode 217 to the other main electrode 217. In other words, the MISFET 221 is fabricated as a depletion type. On the other hand, when hot carriers are accumulated in the charge storage unit 219, the 2DEG214 below the charge storage unit 219 disappears, and the threshold voltage shifts in the positive direction. In other words, the MISFET221 is adjusted to an enhancement-type threshold voltage.

[0034] The thickness of the InAlN layer 213E of MISFET221 is thinner than the thickness of the InAlN layer 213D of MISFET241. For example, the thickness of the InAlN layer 213E of MISFET221 is between 1 nm and 9 nm, which is between 1 / 5 and 3 / 5 the thickness of the InAlN layer 213D of MISFET241. When the thickness of the InAlN layer 213E is reduced, the efficiency of hot carrier injection into the charge storage section 219 can be improved.

[0035] The gate insulating film 215 of the MISFET221 comprises a first oxide film 215A, a second oxide film 215B laminated on the first oxide film 215A, a nitride film 215C laminated on the second oxide film 215B, and a third oxide film 215D laminated on the nitride film 215C. For example, SiN is used for the nitride film 215C. The nitride film 215C is formed to a thickness of, for example, 1 nm to 10 nm. For example, SiO2 is used for the third oxide film 215D. The third oxide film 215D is formed to a thickness of, for example, 1 nm to 10 nm. Specifically, the gate insulating film 215 employs an ONO (Oxide-Nitride-Oxide) structure in which oxide films, nitride films, and oxide films are sequentially stacked. In addition, the MISFET 221 employs a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure, including the semiconductor layer 213 and the gate electrode 216. The charge storage section 219 is configured to include a nitride film 215C having a trapping level for hot carriers. The charge storage section 219 may further include an interface between the nitride film 215C and the second oxide film 215B.

[0036] The gate length dimension of the MISFET221 is set to, for example, 0.05 μm or more and 0.3 μm or less. The gate width dimension of the MISFET221 is set to, for example, 10 μm or more and 10000 μm or less. Here, the gate width dimension is the length of the gate electrode 216 in the gate width direction (arrow Y direction) perpendicular to the gate length direction.

[0037] (4) Configuration of the first external terminal 204, the second external terminal 205, and the third external terminal 206 As shown in Figure 4, the first external terminal 204, the second external terminal 205, and the third external terminal 206 are formed by wiring on the same layer arranged on the MISFET 241 and MISFET 221. Here, the first external terminal 204, the second external terminal 205, and the third external terminal 206 are arranged in a line in the direction of arrow Y on the surface of the semiconductor substrate 21. These first external terminals 204, etc., are formed on the same layer as the external terminal 201 (not shown) shown in Figure 2.

[0038] The first external terminal 204 is integrally formed with the wiring (not shown in numerals) connected to the main electrode (first main electrode) 217 ​​of the MISFET 221 of the protection circuit 22, the DC bias resistor 203, and the external power supply terminal 208 (see Figure 2). The second external terminal 205 is integrally formed with the wiring (not shown in the symbols) connected to the resistor 222 and the main electrode (second main electrode) 217 ​​of the MISFET 221, respectively. The third external terminal 206 is integrally formed with the wiring (sign omitted) connected to the resistor 222 and the gate electrode 216 of the MISFET 221, respectively. As shown in Figure 4, in a plan view, MISFET221 and MISFET241 are arranged with their gate lengths aligned in the direction of arrow X. However, MISFET221 and MISFET241 may be arranged without their gate lengths being aligned.

[0039] (5) Configuration of resistor 222 and DC bias resistor 203 As shown in Figure 4, resistors 222 and DC bias resistor 203 are located on the MISFET 221 and below the first external terminal 204. Resistors 222 and DC bias resistor 203 are formed from, for example, Ta cermet resistors.

[0040] [Manufacturing method for protection circuit 22 and semiconductor device 2] Next, we will briefly explain the manufacturing method of the protection circuit 22 and the semiconductor device 2. Figures 5 to 12 show cross-sections of each step in the manufacturing process of the protection circuit 22 and the semiconductor device 2.

[0041] First, a semiconductor substrate 21 is prepared (see Figure 5). A buffer layer 211 is formed on this semiconductor substrate 21 (see Figure 5). As shown in Figure 5, a semiconductor layer 213 is formed over the entire surface of the buffer layer 211. As described above, the semiconductor layer 213 is formed by sequentially stacking a GaN layer 213A, a GaN channel layer 213B, an AlN layer 213C, and an InAlN layer 213D. Once the semiconductor layer 213 is formed, 2DEG214 is generated.

[0042] An insulator 218 is formed over the entire surface of the semiconductor layer 213 (see Figure 6). Next, as shown in Figure 6, a pair of main electrodes 217 are formed in the respective formation regions of MISFET 241 and MISFET 221. The main electrodes 217 are formed by creating an opening in the insulator 218 in which the surface of the semiconductor layer 213 is exposed, and embedding the electrode material in this opening. The electrode material is deposited using, for example, a vacuum deposition method. The deposited electrode material is then subjected to heat treatment at a temperature of 500°C to 700°C, for example, by a thermal diffusion method. As a result, ohmic properties are obtained for the main electrodes 217.

[0043] As shown in Figure 7, element isolation sections 212 are formed in the semiconductor layer 213 between MISFET 221 and MISFET 241, and between MISFET 241. The element isolation sections 212 are formed by implanting ions into the semiconductor layer 213 using the ion implantation method, as described above.

[0044] In the region where the gate insulating film 215 of the MISFET 221 is formed, an opening 218A is formed in the insulator 218 (see Figure 8). The opening 218A is formed, for example, using photolithography and etching techniques. As shown in Figure 8, following the formation of the opening 218A, a portion of the InAlN layer 213D in the thickness direction of the semiconductor layer 213 exposed through the opening 218A is etched. This forms an InAlN layer 213E having a thickness thinner than the InAlN layer 213D. As shown in Figure 9, the opening 218A is filled with an insulator 218.

[0045] In the gate insulating film 215 formation region of MISFET221 and the gate insulating film 215 formation region of MISFET241, an opening 218B is formed in the insulator 218 (see Figure 10). The opening 218B is formed using photolithography and etching techniques.

[0046] As shown in Figure 10, within the opening 218B, a gate insulating film 215 is formed on the InAlN layer 213E in the formation region of the MISFET 221. Furthermore, using the same manufacturing process, a gate insulating film 215 is formed on the InAlN layer 213D in the formation region of the MISFET 241 within the opening 218B. The gate insulating film 215 is formed by sequentially stacking a first oxide film 215A, a second oxide film 215B, a nitride film 215C, and a third oxide film 215D. The gate insulating film 215 is formed using, for example, atomic layer deposition. In the MISFET221, the gate insulating film 215 has an ONO structure, so a charge storage section 219 is formed. Also, at this point, no hot carriers are stored in the charge storage section 219, so the MISFET221 is formed at a depletion-type threshold voltage.

[0047] As shown in Figure 11, in the formation region of the MISFET 241, the third oxide film 215D and the nitride film 215C of the gate insulating film 215 are selectively removed. Photolithography and etching techniques are used for this removal. In other words, the charge storage region 219 is not formed in the MISFET 241. The MISFET 241 is formed at a depletion-type threshold voltage.

[0048] As shown in Figure 12, in the formation region of MISFET 221 and the formation region of MISFET 241, a gate electrode 216 is formed on the gate insulating film 215. Once the gate electrode 216 is formed, MISFET 221 and MISFET 241 are completed.

[0049] Resistors 222 and DC bias resistors 203 are formed on MISFETs 221 and 241, and external terminals 201, first external terminals 204 to third external terminals 206 and wiring are formed on the upper layer (see Figures 2 and 4). Once these processes are complete, the semiconductor device 2 equipped with the protection circuit 22 and internal circuit 24 is finished.

[0050] [Method for storing charge in the charge storage unit 219] In the protection circuit 22 shown in Figures 2 to 4, the method for accumulating charge in the charge storage unit 219 of the MISFET 221 is as follows. Once the manufacturing method for the semiconductor device 2 shown in Figures 5 to 12 is complete, hot carriers are injected into the charge storage unit 219 of the MISFET 221 before mounting the RF power amplifier module 1. Here, "before mounting" includes the period immediately after the completion of the pre-processing steps for the semiconductor device 2, and immediately after the completion of the characteristic inspection steps for the semiconductor device 2. The injection of hot carriers may be performed after the semiconductor device 2 is mounted onto the RF power amplifier module 1.

[0051] Figure 13 is a flowchart illustrating the charge accumulation method. Figure 14 is a timing chart showing the relationship between injection voltage and injection time, illustrating the charge accumulation method. In Figure 14, the horizontal axis represents time [ms] and the vertical axis represents voltage [V]. When hot carrier injection begins, hot carriers are injected into the charge storage unit 219 of the MISFET 221 of the protection circuit 22 (step S1 in Figure 13). During carrier injection, a first power supply is supplied to the main electrode 217 of the MISFET 221 from the first external terminal 204 shown in Figures 2 and 4. This main electrode 217 is the first main electrode and corresponds to the drain electrode. The first power supply is the drain power supply. A second power supply is supplied to the main electrode 217 of the MISFET 221 from the second external terminal 205. This main electrode 217 is the second main electrode and corresponds to the source electrode. The second power supply is the source power supply. A third power supply is supplied to the gate electrode 216 of the MISFET 221 from the third external terminal 206. The third power supply is the gate power supply.

[0052] Here, Vdsw is the drain-source electrode voltage, BVpth is the punch-through voltage, Vt is the threshold voltage, Vgsw is the gate-source electrode voltage, BVg is the gate breakdown voltage, and BVj is the junction breakdown voltage. In this case, the following equation <1> ~ expression <3> The hot carrier is injected when the conditions are met. Vdsw <BVpth<Vt≦Vgsw<BVg … <1> Vdsw ≈ Vgsw / 2 … <2> BVpth ≤ BVj … <3> Specifically, for example, the above formula <1> The formula is as follows: <4> It is calculated as follows. 3.25[V]<5.5[V]<6.0[V]≦6.5[V]<15[V]… <4>

[0053] In step S1, the above formula <4> Based on this, for example, 3.25[V] is supplied to the first external terminal 204, 0[V] to the second external terminal 205, and 6.5[V] to the third external terminal 206 (see Figure 14). The power supply cycle is performed 50 times, for example, with a pulse width of 1[ms]. At this time, the hot carrier injection time is set to, for example, 100[ms], taking reproducibility into consideration. Furthermore, voltage conditions such as the drain-source electrode voltage Vdsw are as follows, for example. Vdsw: 1[V]~5[V] BVpth: 3.5[V]~7.5[V] Vt (after hot carrier injection): 4[V]~8[V] Vgsw: 4.5[V]~8.5[V] BVg: 13[V]~17[V] BVj: 8[V]~12[V]

[0054] After step S1 is completed, the threshold voltage Vt of MISFET221 is measured (step S2). Based on the measurement result, the threshold voltage Vt is calculated using the above formula. <1> Step S3 determines whether the threshold voltage Vt is equal to or greater than a predetermined value (in this case, 6.0[V]). If the threshold voltage Vt is equal to or greater than the predetermined value, the injection of the hot carrier is terminated. On the other hand, in step S3, if the threshold voltage Vt is less than a predetermined value, the number of power supply cycles is increased (step S4). The number of additional power supply cycles is n, for example, n is set to 10 times. According to this increased number of power supply cycles, the process returns to step S1 and the injection of hot carriers continues. Then, after steps S2 and S3, when the threshold voltage Vt exceeds a predetermined value, the injection of hot carriers is terminated. Once the injection of hot carriers is complete, the MISFET221 changes from a depletion type to an enhancement type threshold voltage Vt.

[0055] [Circuit operation of protection circuit 22] In the MISFET 221 of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes 217 of the MISFET 221 exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201.

[0056] As shown in Figure 2, an external DC bias circuit 5 is connected to the external power terminal 208 of the semiconductor device 2. When the DC bias circuit 5 is positively charged, a positive surge current Iesd flows from the DC bias circuit 5 to the semiconductor device 2 through the external power terminal 208. The surge current Iesd flows through the DC bias resistor 203 and the main electrode 217, which is used as the drain electrode of the MISFET 221. When the surge voltage is greater than or equal to the protection voltage Vesd, the resistance on the drain electrode side of the MISFET 221 is lower. Therefore, the surge current Iesd flows through the drain electrode and source electrode of the MISFET 221 to the reference power supply GND. The pair of main electrodes 217 of the MISFET221 are adjusted to a constant punch-through voltage BVpth by adjusting the gate length dimension. As a result, the surge voltage is reduced to the protection voltage Vesd, providing ESD protection.

[0057] On the other hand, when the DC bias circuit 5 is negatively charged, a surge current Iesd flows from the reference power supply GND through the MISFET 221 and the external power supply terminal 208, the opposite to when it is positively charged. A resistor 222 is placed between the gate electrode 216 and the main electrode 217 used as the source electrode of the MISFET 221. As a result, the gate capacitance of the gate electrode 216 is charged through the resistor 222, and the gate potential of the gate electrode 216 rises. At this time, the punch-through voltage BVpth between the pair of main electrodes 217 of the MISFET 221 becomes constant by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the destruction of the gate insulating film 215 can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0058] [Effects and Effects] The protection circuit 22 according to the first embodiment includes a MISFET 221, as shown in Figures 2 to 4. The MISFET 221 has a main electrode (first main electrode) 217 ​​connected between the external terminal 201 and the internal circuit 24, and a main electrode (second main electrode) 217 ​​connected to the reference power supply GND. A charge storage unit 219 capable of accumulating hot carriers is provided in the gate insulating film 215. In the MISFET221, a depletion type is formed, and hot carriers can be accumulated in the charge storage section 219 to form an enhancement type threshold voltage. Therefore, a protection circuit 22 with excellent ESD withstand capability or avalanche withstand capability can be constructed using the MISFET221, which has high process compatibility and does not use a pn junction. In addition, the MISFET211 does not use pn junctions or Schottky junctions. Therefore, a protection circuit 22 can be realized without surge damage at the junction.

[0059] Furthermore, as shown in Figures 2 and 4, the protection circuit 22 includes a resistor 222 electrically connected in series between the gate electrode 216 of the MISFET 22 and the main electrode (second main electrode) 217 ​​used as the source electrode. Therefore, disconnection of the main electrodes 217 is unnecessary when injecting hot carriers into the charge storage unit 219. In addition, the charge storage unit 219 can be operated as a protection circuit 22 immediately after the injection of hot carriers. Furthermore, even if a negative surge is input to, for example, the external power supply terminal 208, the gate potential of the MISFET 221 does not rise immediately due to the CR delay operation, and punch-through occurs between the pair of main electrodes 217 during this time. As a result, the gate insulating film 215 is not destroyed, and the MISFET 221 alone can protect against positive and negative surges.

[0060] Furthermore, as shown in Figures 2 and 4, the protection circuit 22 includes a first external terminal 204, a second external terminal 205, and a third external terminal 206. The first external terminal 204 is connected between the external terminal 201 and the main electrode (first main electrode) 217 ​​of the MISFET 221, and a first power supply for generating hot carriers is supplied to the first external terminal 204. The second external terminal 205 is connected to the main electrode (second main electrode) 217 ​​of the MISFET 221, and a second power supply for generating hot carriers is supplied to the second external terminal 205. The third external terminal 206 is connected to the gate electrode 216 of the MISFET 221, and a third power supply for generating hot carriers is supplied to the third external terminal 206. The first external terminal 204, the second external terminal 205, and the third external terminal 206 are dedicated external terminals for injecting hot carriers into the MISFET 221. Therefore, immediately after the fabrication of the protection circuit 22, or thereafter, hot carriers can be injected into the charge storage unit 219 as needed to initiate the protection function of the protection circuit 22.

[0061] Furthermore, as shown in Figures 1 to 4, the semiconductor device 2 includes an external terminal 201, an internal circuit 24, and a protection circuit 22. The protection circuit 22 is disposed on a semiconductor substrate 21 and includes a MISFET 221. The MISFET 221 has a main electrode (first main electrode) 217 ​​connected between the external terminal 201 and the internal circuit 24, a main electrode (second main electrode) 217 ​​and a gate electrode 216 connected to a reference power supply GND, and is provided with a charge storage unit 219 capable of accumulating hot carriers. Therefore, the same effects and benefits as those obtained by the aforementioned protection circuit 22 can be obtained. In addition, the MISFET 221 of the protection circuit 22 can be easily constructed using substantially the same structure as the MISFET 241 that constructs the internal circuit 24, or using substantially the same manufacturing process.

[0062] Furthermore, in the semiconductor device 2, the MISFET 221 of the protection circuit 22 further includes a resistor 222 electrically connected in series between the gate electrode 216 and the main electrode (second main electrode) 217. Therefore, the semiconductor device 2 can obtain the same effects as those obtained by the aforementioned protection circuit 22.

[0063] Furthermore, as shown in Figures 2 and 4, the semiconductor device 2 includes a first external terminal 204, a second external terminal 205, and a third external terminal 206. Therefore, the semiconductor device 2 can obtain the same effects as those obtained by the aforementioned protection circuit 22.

[0064] Furthermore, in the semiconductor device 2, as shown in Figure 3, the charge storage section 219 of the MISFET 221 of the protection circuit 22 is composed of a structure in which oxide films, nitride films, and oxide films are sequentially stacked. More specifically, the charge storage section 219 is composed of an ONO structure in which a first oxide film 215A, a second oxide film 215B, a nitride film 215C, and a third oxide film 215D are sequentially stacked. The nitride film contains SiN. The oxide film contains at least one selected from Al2O3, HfO2, Ta2O5, ZrO2, Y2O3, and SiO2. In the first embodiment, the charge storage section 219 includes Al2O3, HfO2 stacked on Al2O3, SiN stacked on HfO2, and SiO2 stacked on SiN. Therefore, by adopting an ONO structure for the gate insulating film 215, the charge storage unit 219 can be easily constructed.

[0065] Furthermore, in semiconductor device 2, as shown in Figure 3, the MISFET221 is made of a compound semiconductor. More specifically, the compound semiconductor includes GaN or GaAs. In addition, the MISFET221 includes InAlN. Therefore, the protection circuit 22 can be constructed using the MISFET 221 having a HEMT structure. In particular, the protection circuit 22 can be easily constructed using a structure that is substantially identical to that of the MISFET 241 that constructs the internal circuit 24.

[0066] Furthermore, in semiconductor device 2, the MISFET 221 of the protection circuit 22 accumulates hot carriers in the charge storage section 219, shifting the threshold voltage from a depletion type to an enhancement type. Therefore, since the MISFET 221 of the protection circuit 22 is formed using substantially the same structure or substantially the same manufacturing process as the MISFET 241 of the internal circuit 24, the protection circuit 22 can be easily constructed.

[0067] Furthermore, in semiconductor device 2, the gate length of the MISFET 221 of the protection circuit 22 shown in Figures 3 and 4 is formed to be between 0.05 μm and 0.3 μm. In addition, the gate width of the MISFET 221 is formed to be between 10 μm and 10,000 μm. Furthermore, the resistor 222 of the protection circuit 22 is formed to be between 100 Ω and 10 MΩ. Therefore, when a surge is input, the MISFET221 can properly generate punch-through.

[0068] Furthermore, as shown in Figures 3 and 4, the semiconductor device 2 includes an RF power amplifier in its internal circuitry 24 that contains a depletion-type MISFET 241. Therefore, the protection circuit 22 can be easily fabricated by utilizing the structure and manufacturing process of the depletion-type MISFET 241.

[0069] Furthermore, in semiconductor device 2, as shown in Figure 3, the thickness of the InAlN213E of the MISFET221 of the protection circuit 22 is thinner than the thickness of the InAlN213D of the MISFET241 of the internal circuit 24. Therefore, the efficiency of hot carrier injection into the charge storage section 219 of the MISFET 221 can be improved.

[0070] <2. Second Embodiment> The protection circuit 22 and semiconductor device 2 according to the second embodiment of this disclosure will now be described. In the second embodiment and subsequent embodiments, components that are the same as, or substantially the same as, the components of the protection circuit 22 and semiconductor device 2 according to the first embodiment will be denoted by the same reference numerals, and redundant descriptions will be omitted.

[0071] [Configuration of protection circuit 22 and semiconductor device 2] Figure 15 shows the longitudinal cross-sectional structure of the protection circuit 22 and the internal circuit 24. In the protection circuit 22 and semiconductor device 2 according to the second embodiment, the MISFET 221 of the protection circuit 22 has an InAlN layer 213E that is thinner than the InAlN layer 213D disposed on a part of the InAlN layer 213D of the semiconductor layer 213. More specifically, the InAlN layer 213E is disposed in the vicinity of the main electrode (first main electrode) 217 ​​used as a drain electrode in the gate length direction. The hot carriers injected into the charge storage unit 219 are generated near the drain electrode where the electric field strength increases.

[0072] Other than the above, the configuration is the same as that of the protection circuit 22 and semiconductor device 2 according to the first embodiment.

[0073] [Effects and Effects] According to the protection circuit 22 and semiconductor device 2 of the second embodiment, the same effects and benefits as those obtained with the protection circuit 22 and semiconductor device 2 of the first embodiment can be obtained. Furthermore, as shown in Figure 15, in the protection circuit 22 and semiconductor device 2, a thin InAlN layer 213E is provided on a portion of the InAlN layer 213D in the semiconductor layer 213 of the MISFET 221. Therefore, the MISFET 221 equipped with the charge storage unit 219 can be constructed with minimal processing.

[0074] <3. Third Embodiment> The protection circuit 22 and semiconductor device 2 according to the third embodiment of this disclosure will be described. The third embodiment is a modified example of the protection circuit 22 and internal circuit 24 according to the first embodiment.

[0075] [Configuration of protection circuit 22 and semiconductor device 2] Figure 16 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the third embodiment, the main electrode (first main electrode) of the MISFET 221 is connected between the external terminal 201 and the coupling capacitor 202, with a surge induction resistor 223 interposed between them. Furthermore, one end of the DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24, and the other end of the DC bias resistor 203 is connected to the decoupling capacitor 207 and the DC bias circuit 25. The DC bias circuit 25 is built into the semiconductor device 2 instead of the external DC bias circuit 5.

[0076] Other than the above, the configuration is the same as that of the protection circuit 22 and semiconductor device 2 according to the first embodiment.

[0077] [Circuit operation of protection circuit 22] In the MISFET 221 of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes of the MISFET 221 exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201.

[0078] As shown in Figure 16, when a "positive" surge voltage is applied to the external terminal 201, the surge current Iesd flows through the surge induction resistor 223 and the pair of main electrodes of the MISFET 221 of the protection circuit 22 to the reference power supply GND side. The punch-through voltage BVpth between the pair of main electrodes of the MISFET221 is constant by adjusting the gate length. As a result, the surge voltage is reduced to the protection voltage Vesd, providing ESD protection.

[0079] Conversely, when a negative surge voltage is applied to the external terminal 201, the surge current Iesd flows from the reference power supply GND side through the pair of main electrodes of the MISFET 221 and the surge induction resistor 223 to the external terminal 201. A resistor 222 is placed between the gate electrode and the main electrode used as the source electrode of the MISFET221. As a result, the gate capacitance of the gate electrode is charged through the resistor 222, and the gate potential of the gate electrode rises. At this time, the punch-through voltage BVpth between the pair of main electrodes of the MISFET221 becomes constant by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the breakdown of the gate insulating film can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0080] [Effects and Effects] According to the protection circuit 22 and semiconductor device 2 of the third embodiment, the same effects and benefits as those obtained with the protection circuit 22 and semiconductor device 2 of the first embodiment can be obtained. Furthermore, the protection circuit 22 and the semiconductor device 2 can be protected against positive and negative surges by the MISFET 221 alone.

[0081] <4. Fourth Embodiment> A protection circuit 22 and semiconductor device 2 according to a fourth embodiment of this disclosure will be described. The fourth embodiment is a modified example of the protection circuit 22 and semiconductor device 2 according to the first embodiment.

[0082] [Configuration of protection circuit 22 and semiconductor device 2] Figure 17 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the fourth embodiment, the protection circuit 22 is connected between the coupling capacitor 202 and the internal circuit 24 with a DC bias resistor 203 interposed between them.

[0083] The protection circuit 22 includes two electrically connected MISFETs 221A and 221B that share a main electrode (in this case, the second main electrode) used as a drain electrode. The second main electrodes of MISFETs 221A and 221B are connected to the first external terminal 204. The DC bias resistor 203 is connected to the main electrode (in this case, the first main electrode) used as the source electrode of the MISFET221B.

[0084] A resistor 222A is electrically connected in series between the first main electrode and the gate electrode of MISFET221A. The first main electrode of MISFET221A is connected to the second external terminal 205A and the reference power supply GND. The gate electrode is connected to the third external terminal 206A. On the other hand, resistor 222B is electrically connected in series between the first main electrode and the gate electrode of MISFET221B. The first main electrode of MISFET221B is connected to the second external terminal 205B. The gate electrode is connected to the third external terminal 206B. In other words, MISFET221A and MISFET221B are arranged symmetrically with respect to the second main electrode. An external DC bias circuit 5 is connected to the external power terminal 208.

[0085] In the protection circuit 22, the injection sequence of hot carriers into the charge storage unit 219 is either MISFET221A followed by MISFET221B, or in the reverse order, or both simultaneously.

[0086] [Circuit operation of protection circuit 22] In the MISFETs 221A and 221B of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes of MISFETs 221A and 221B exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201. The protection circuit 22 consists of two MISFETs, MISFET 221A and MISFET 221B, stacked in a two-stage configuration. The second main electrodes of MISFET 221A and MISFET 221B are shared. The first main electrode of MISFET 221B is connected to the external power supply terminal 208. The first main electrode of MISFET 221A is connected to the reference power supply GND. Therefore, the protection voltage Vesd of the protection circuit 22 according to the fourth embodiment is approximately twice that of the protection circuit 22 according to the first embodiment. Furthermore, in the protection circuit 22 according to the first embodiment, slight differences can be observed in the response characteristics for protection against positive and negative surges. In contrast, in the protection circuit 22 according to the fourth embodiment, since MISFET221A and MISFET221B are arranged symmetrically, the response characteristics for protection are substantially the same.

[0087] As shown in Figure 17, an external DC bias circuit 5 is connected to the external power terminal 208 of the semiconductor device 2. When the DC bias circuit 5 is positively charged, a positive surge current Iesd flows from the DC bias circuit 5 to the semiconductor device 2 through the external power terminal 208. The surge current Iesd flows to the reference power supply GND through the MISFET 221B and MISFET 221A of the protection circuit 22.

[0088] On the other hand, when the DC bias circuit 5 is negatively charged, a surge current Iesd flows from the reference power supply GND through MISFET221A, MISFET221B, and the external power supply terminal 208 to the DC bias circuit 5, in the opposite case to when it is positively charged.

[0089] A resistor 222A is placed between the gate electrode of MISFET221A and the first main electrode used as the source electrode. A resistor 222B is placed between the gate electrode of MISFET221B and the main electrode used as the source electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through resistor 222A or resistor 222B. At this time, the punch-through voltage BVpth between the pair of main electrodes of MISFET221A and MISFET221B becomes constant by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the breakdown of the gate insulating film can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0090] [Effects and Effects] According to the protection circuit 22 and semiconductor device 2 of the fourth embodiment, the same effects and benefits as those obtained with the protection circuit 22 and semiconductor device 2 of the first embodiment can be obtained. Furthermore, since the protection circuit 22 has MISFET221A and MISFET221B arranged symmetrically, it can handle both positive and negative surge voltages. The protection voltage Vesd is approximately twice that of the protection circuit 22 according to the first embodiment, but the polarity variation of the punch-through voltage BVpth is suppressed, and the transient response characteristics are the same for both positive and negative surge voltages. Furthermore, in the protection circuit 22, the protection voltage Vesd is approximately twice that of the standalone unit, doubling the withstand voltage of the RF signal and enabling higher RF output power.

[0091] <5. Fifth Embodiment> The protection circuit 22 and semiconductor device 2 according to the fifth embodiment of this disclosure will be described. The fifth embodiment is a modified example combining the third and fourth embodiments.

[0092] [Configuration of protection circuit 22 and semiconductor device 2] Figure 18 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the fifth embodiment, the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with a surge induction resistor 223 interposed between them. The protection circuit 22 is composed of symmetrically arranged MISFETs 221A and 221B, similar to the protection circuit 22 according to the fourth embodiment. Furthermore, one end of the DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24, and the other end of the DC bias resistor 203 is connected to the decoupling capacitor 207 and the DC bias circuit 25. The DC bias circuit 25 is built into the semiconductor device 2 instead of the external DC bias circuit 5.

[0093] Other than the above, the configuration is the same as that of the protection circuit 22 and semiconductor device 2 according to the third and fourth embodiments.

[0094] [Circuit operation of protection circuit 22] In the MISFETs 221A and 221B of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes of MISFETs 221A and 221B exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201. The protection circuit 22 consists of two MISFETs, MISFET 221A and MISFET 221B, stacked in two stages. The second main electrodes of MISFET 221A and MISFET 221B are shared. The first main electrode of MISFET 221B is connected to the external terminal 201 through the surge induction resistor 223. The first main electrode of MISFET 221A is connected to the reference power supply GND. Therefore, the protection voltage Vesd of the protection circuit 22 according to the fifth embodiment is approximately twice that of the protection circuit 22 according to the first embodiment. Furthermore, in the protection circuit 22 according to the first embodiment, slight differences can be observed in the response characteristics to protection against positive and negative surges. In contrast, in the protection circuit 22 according to the fifth embodiment, since MISFET221A and MISFET221B are arranged symmetrically, the response characteristics to protection are substantially the same.

[0095] As shown in Figure 18, when a "positive" surge voltage is applied to the external terminal 201, the surge current Iesd flows through the surge induction resistor 223 and the MISFETs 221B and 221A of the protection circuit 22 to the reference power supply GND side. The pair of main electrodes of MISFET221A and MISFET221B achieve a constant punch-through voltage BVpth by adjusting the gate length. As a result, the surge voltage is reduced to the protection voltage Vesd, providing ESD protection.

[0096] Conversely, when a negative surge voltage is applied to the external terminal 201, the surge current Iesd flows from the reference power supply GND side through MISFET221A, MISFET221B, and surge induction resistor 223 to the external terminal 201.

[0097] A resistor 222A is placed between the gate electrode of MISFET221A and the main electrode used as the source electrode. A resistor 222B is placed between the gate electrode of MISFET221B and the main electrode used as the source electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through resistor 222A or resistor 222B. At this time, the punch-through voltage BVpth between the pair of main electrodes of MISFET221A and MISFET221B becomes constant by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the breakdown of the gate insulating film can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0098] [Effects and Effects] According to the fifth embodiment of the protection circuit 22 and semiconductor device 2, it is possible to obtain combined effects of the effects obtained by the protection circuit 22 and semiconductor device 2 according to the third embodiment and the effects obtained by the protection circuit 22 and semiconductor device 2 according to the fourth embodiment.

[0099] <6. Sixth Embodiment> The protection circuit 22 and semiconductor device 2 according to the sixth embodiment of this disclosure will now be described. The sixth embodiment is a modified example of the protection circuit 22 and semiconductor device 2 according to the fourth embodiment.

[0100] [Configuration of protection circuit 22 and semiconductor device 2] Figure 19 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the sixth embodiment, the protection circuit 22 includes two MISFETs 221A and 221B that are electrically connected in series and share a main electrode (here, a second main electrode) used as a source electrode. The second main electrodes of MISFETs 221A and 221B are connected to the second external terminal 205. The main electrode (in this case, the first main electrode) used as the drain electrode of the MISFET221B is connected to the DC bias resistor 203.

[0101] A common resistor 222 is electrically connected in series between the second main electrode and the gate electrode of MISFET221A, and between MISFET221B and its second main electrode. The first main electrode of MISFET221A is connected to the first external terminal 204A and the reference power supply GND. The gate electrode is connected to the gate electrode of MISFET221B and the common third external terminal 206. On the other hand, the first main electrode of the MISFET221B is connected to the first external terminal 204B. MISFET221A and MISFET221B are arranged symmetrically with respect to the second main electrode. An external DC bias circuit 5 is connected to the external power terminal 208.

[0102] [Circuit operation of protection circuit 22] In the MISFETs 221A and 221B of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes of MISFETs 221A and 221B exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201. The protection circuit 22 consists of two MISFETs, MISFET 221A and MISFET 221B, stacked in a two-stage configuration. The second main electrodes of MISFET 221A and MISFET 221B are shared. The first main electrode of MISFET 221B is connected to the external power supply terminal 208. The first main electrode of MISFET 221A is connected to the reference power supply GND. Therefore, the protection voltage Vesd of the protection circuit 22 according to the sixth embodiment is approximately twice that of the protection circuit 22 according to the first embodiment. Furthermore, in the protection circuit 22 according to the first embodiment, slight differences can be observed in the response characteristics for protection against positive and negative surges. In contrast, in the protection circuit 22 according to the sixth embodiment, since MISFET221A and MISFET221B are arranged symmetrically, the response characteristics for protection are substantially the same.

[0103] As shown in Figure 19, an external DC bias circuit 5 is connected to the external power terminal 208 of the semiconductor device 2. When the DC bias circuit 5 is positively charged, a positive surge current Iesd flows from the DC bias circuit 5 to the semiconductor device 2 through the external power terminal 208. The surge current Iesd flows to the reference power supply GND through the MISFET 221B and MISFET 221A of the protection circuit 22.

[0104] On the other hand, when the DC bias circuit 5 is negatively charged, a surge current Iesd flows from the reference power supply GND through MISFET221A, MISFET221B, and the external power supply terminal 208 to the DC bias circuit 5, in the opposite case to when it is positively charged.

[0105] A resistor 222 is placed between the gate electrodes of MISFET221A and MISFET221B and the second main electrode, which is used as the source electrode. Therefore, the surge current flowing from the source electrode side charges the gate capacitance of the gate electrode through resistor 222, while raising the gate potential of the gate electrode. At this time, the punch-through voltage BVpth between the pair of main electrodes of MISFET221A and MISFET221B becomes constant due to the adjustment of the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the breakdown of the gate insulating film can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0106] [Effects and Effects] According to the protection circuit 22 and semiconductor device 2 of the sixth embodiment, the same effects and benefits as those obtained with the protection circuit 22 and semiconductor device 2 of the fourth embodiment can be obtained.

[0107] <7. Seventh Embodiment> The seventh embodiment of the present disclosure, comprising a protection circuit 22 and a semiconductor device 2, is described below. The seventh embodiment is an example of combining the protection circuit 22 and semiconductor device 2 according to the fifth embodiment with the protection circuit 22 and semiconductor device 2 according to the sixth embodiment.

[0108] [Configuration of protection circuit 22 and semiconductor device 2] Figure 20 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the seventh embodiment, the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with a surge induction resistor 223 interposed between them. The protection circuit 22 is composed of symmetrically arranged MISFETs 221A and 221B, similar to the protection circuit 22 according to the sixth embodiment. Furthermore, one end of the DC bias resistor 203 is connected between the coupling capacitor 202 and the internal circuit 24, and the other end of the DC bias resistor 203 is connected to the decoupling capacitor 207 and the DC bias circuit 25. The DC bias circuit 25 is built into the semiconductor device 2 instead of the external DC bias circuit 5.

[0109] Other than the above, the configuration is the same as that of the protection circuit 22 and semiconductor device 2 according to the fifth and sixth embodiments.

[0110] [Circuit operation of protection circuit 22] In the MISFETs 221A and 221B of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes of MISFETs 221A and 221B exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201. The protection circuit 22 consists of two MISFETs, MISFET 221A and MISFET 221B, stacked in a two-stage configuration. The second main electrodes of MISFET 221A and MISFET 221B are shared. The first main electrode of MISFET 221B is connected to the external terminal 201 through the surge induction resistor 223. The first main electrode of MISFET 221A is connected to the reference power supply GND. Therefore, the protection voltage Vesd of the protection circuit 22 according to the seventh embodiment is approximately twice that of the protection circuit 22 according to the first embodiment. Furthermore, in the protection circuit 22 according to the first embodiment, slight differences can be observed in the response characteristics for protection against positive and negative surges. In contrast, in the protection circuit 22 according to the seventh embodiment, since MISFET221A and MISFET221B are arranged symmetrically, the response characteristics for protection are substantially the same.

[0111] As shown in Figure 20, when a "positive" surge voltage is applied to the external terminal 201, the surge current Iesd flows through the surge induction resistor 223 and the MISFETs 221B and 221A of the protection circuit 22 to the reference power supply GND side. The pair of main electrodes of MISFET221A and MISFET221B achieve a constant punch-through voltage BVpth by adjusting the gate length. As a result, the surge voltage is reduced to the protection voltage Vesd, providing ESD protection.

[0112] Conversely, when a negative surge voltage is applied to the external terminal 201, the surge current Iesd flows from the reference power supply GND side through MISFET221A, MISFET221B, and surge induction resistor 223 to the external terminal 201.

[0113] A resistor 222 is placed between the gate electrode of MISFET221A and MISFET221B and the main electrode used as the source electrode. Therefore, the surge current flowing from the source electrode side charges the gate capacitance of the gate electrode through resistor 222, while raising the gate potential of the gate electrode. At this time, the punch-through voltage BVpth between the pair of main electrodes of MISFET221A and MISFET221B becomes constant due to the adjustment of the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the breakdown of the gate insulating film can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0114] [Effects and Effects] According to the seventh embodiment of the protection circuit 22 and semiconductor device 2, it is possible to obtain combined effects of the effects obtained by the protection circuit 22 and semiconductor device 2 according to the fifth embodiment and the effects obtained by the protection circuit 22 and semiconductor device 2 according to the sixth embodiment.

[0115] <8. Eighth Embodiment> The protection circuit 22 and semiconductor device 2 according to the eighth embodiment of this disclosure will be described. The eighth embodiment is a modified version of the protection circuit 22 and semiconductor device 2 according to the sixth embodiment.

[0116] [Configuration of protection circuit 22 and semiconductor device 2] Figure 21 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the eighth embodiment, the protection circuit 22 is connected between the coupling capacitor 202 and the internal circuit 24 with a DC bias resistor 203 interposed between them.

[0117] The protection circuit 22 includes two MISFETs 221A and 221B that are electrically connected in parallel. The first main electrode, used as the drain region of the MISFET221A, is connected to the first external terminal 204A and also to the DC bias resistor 203 via a current relaxation resistor 224A. The second main electrode, used as the source electrode, is connected to the second external terminal 205A and also to the reference power supply GND via a current relaxation resistor 224B. The gate electrode is connected to the third external terminal 206A. A resistor 222A is electrically connected in series between the second main electrode and the gate electrode. Current relaxation resistors 224A and 224B each relax the current flow when a hot carrier is injected. The first main electrode, used as the drain region of MISFET221B, is connected to the first external terminal 204B and also to the reference power supply GND via a current relaxation resistor 224C. The second main electrode, used as the source electrode, is connected to the second external terminal 205B and also to the DC bias resistor 203 via a current relaxation resistor 224D. The gate electrode is connected to the third external terminal 206B. A resistor 222B is electrically connected in series between the second main electrode and the gate electrode. Current relaxation resistors 224C and 224D each relax the current flow when a hot carrier is injected.

[0118] MISFET221A and MISFET221B are configured such that the polarities of the first main electrode and the second main electrode are opposite to each other. An external DC bias circuit 5 is connected to the external power terminal 208.

[0119] [Circuit operation of protection circuit 22] In the MISFETs 221A and 221B of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes of MISFETs 221A and 221B exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201. Since MISFET221A and MISFET221B are arranged with opposite polarities, the protection voltage Vesd of the protection circuit 22 is equivalent to the protection voltage Vesd of the protection circuit 22 according to the first embodiment. In the protection circuit 22 according to the first embodiment, slight differences are observed in the response characteristics for protection against positive and negative surges. In contrast, in the protection circuit 22 according to the eighth embodiment, the polarity of MISFET221A and MISFET221B is reversed, so the response characteristics for protection are substantially the same.

[0120] As shown in Figure 21, an external DC bias circuit 5 is connected to the external power terminal 208 of the semiconductor device 2. When the DC bias circuit 5 is positively charged, a positive surge current Iesd flows from the DC bias circuit 5 to the semiconductor device 2 through the external power terminal 208. The surge current Iesd flows to the reference power supply GND through the MISFET 221A of the protection circuit 22.

[0121] On the other hand, when the DC bias circuit 5 is negatively charged, a surge current Iesd flows from the reference power supply GND through the MISFET221B and the external power supply terminal 208 to the DC bias circuit 5, the opposite to when it is positively charged.

[0122] A resistor 222A is placed between the gate electrode of MISFET221A and the second main electrode. A resistor 222B is placed between the gate electrode of MISFET221B and the second main electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through resistor 222A or resistor 222B. At this time, the punch-through voltage BVpth between the pair of main electrodes of MISFET221A and MISFET221B becomes constant by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the breakdown of the gate insulating film can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0123] [Effects and Effects] According to the protection circuit 22 and semiconductor device 2 of the eighth embodiment, the same effects and benefits as those obtained with the protection circuit 22 and semiconductor device 2 of the first embodiment can be obtained. Furthermore, since the protection circuit 22 includes MISFET221A and MISFET221B arranged with opposite polarities, it can effectively suppress variations in surge polarity. In addition, it can make the transient response characteristics equal for positive and negative surges.

[0124] <9. Ninth Embodiment> The protection circuit 22 and semiconductor device 2 according to the ninth embodiment of this disclosure will be described. The ninth embodiment is an example of combining the protection circuit 22 and semiconductor device 2 according to the seventh embodiment and the protection circuit 22 and semiconductor device 2 according to the eighth embodiment.

[0125] [Configuration of protection circuit 22 and semiconductor device 2] Figure 22 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as the input-side protection circuit for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the ninth embodiment, the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with a surge induction resistor 223 interposed between them. The protection circuit 22, like the protection circuit 22 according to the eighth embodiment, includes two MISFETs 221A and 221B that are electrically connected in parallel.

[0126] The configuration and circuit operation other than those described above are substantially the same as those of the protection circuit 22 according to the seventh embodiment and the protection circuit 22 according to the eighth embodiment, so their explanation is omitted here.

[0127] [Effects and Effects] According to the protection circuit 22 and semiconductor device 2 of the ninth embodiment, it is possible to obtain an effect that combines the effects obtained by the protection circuit 22 and semiconductor device 2 of the seventh embodiment with the effects obtained by the protection circuit 22 and semiconductor device 2 of the eighth embodiment.

[0128] <10. Tenth Embodiment> The protection circuit 22 and semiconductor device 2 according to the tenth embodiment of this disclosure will be described. The tenth embodiment is a modified version of the protection circuit 22 and semiconductor device 2 according to the eighth embodiment.

[0129] [Configuration of protection circuit 22 and semiconductor device 2] Figure 23 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the 10th embodiment, the protection circuit 22 is connected between the coupling capacitor 202 and the internal circuit 24 with a DC bias resistor 203 interposed between them.

[0130] The protection circuit 22 includes two MISFETs 221A and 221B that are electrically connected in parallel. The first main electrode, used as the drain region of the MISFET221A, is connected to the first external terminal 204A and also to the DC bias resistor 203. The second main electrode, used as the source electrode, is connected to the first external terminal 204B and also to the reference power supply GND. The gate electrode is connected to the third external terminal 206A. A resistor 222A is electrically connected in series between the second main electrode and the gate electrode. The first main electrode, used as the drain region of MISFET221B, is connected to the first external terminal 204B and also to the reference power supply GND. The first external terminal 204B is also connected to the second main electrode of MISFET221A. The second main electrode, used as the source electrode, is connected to the first external terminal 204A and also to the DC bias resistor 203. The first external terminal 204A is also connected to the first main electrode of MISFET221A. The gate electrode is connected to the third external terminal 206B. A resistor 222B is electrically connected in series between the second main electrode and the gate electrode.

[0131] MISFET221A and MISFET221B are configured such that the polarities of the first main electrode and the second main electrode are opposite to each other. An external DC bias circuit 5 is connected to the external power terminal 208.

[0132] [Circuit operation of protection circuit 22] In the MISFETs 221A and 221B of the protection circuit 22, charge is accumulated in the charge storage unit 219, and the threshold voltage Vt is set higher than the protection voltage Vesd (punch-through voltage VBpth). Therefore, when the voltage is less than the protection voltage Vesd, the pair of main electrodes of MISFETs 221A and 221B exhibit high resistance. In other words, the protection circuit 22 does not affect the operation of the internal circuit 24 with respect to the signal voltage input to the external terminal 201. Since MISFET221A and MISFET221B are arranged with opposite polarities, the protection voltage Vesd of the protection circuit 22 is equivalent to the protection voltage Vesd of the protection circuit 22 according to the first embodiment. In the protection circuit 22 according to the first embodiment, slight differences are observed in the response characteristics for protection against positive and negative surges. In contrast, in the protection circuit 22 according to the tenth embodiment, the polarity of MISFET221A and MISFET221B is reversed, so the response characteristics for protection are substantially the same.

[0133] As shown in Figure 23, an external DC bias circuit 5 is connected to the external power terminal 208 of the semiconductor device 2. When the DC bias circuit 5 is positively charged, a positive surge current Iesd flows from the DC bias circuit 5 to the semiconductor device 2 through the external power terminal 208. The surge current Iesd flows to the reference power supply GND through the MISFET 221A of the protection circuit 22.

[0134] On the other hand, when the DC bias circuit 5 is negatively charged, a surge current Iesd flows from the reference power supply GND through the MISFET221B and the external power supply terminal 208 to the DC bias circuit 5, the opposite to when it is positively charged.

[0135] A resistor 222A is placed between the gate electrode of MISFET221A and the second main electrode. A resistor 222B is placed between the gate electrode of MISFET221B and the second main electrode. Therefore, the surge current flowing from the source electrode side increases the gate potential of the gate electrode while charging the gate capacitance of the gate electrode through resistor 222A or resistor 222B. At this time, the punch-through voltage BVpth between the pair of main electrodes of MISFET221A and MISFET221B becomes constant by adjusting the gate length dimension, so the surge voltage is reduced to the protection voltage Vesd. In other words, the gate potential does not rise above the protection voltage Vesd, so the breakdown of the gate insulating film can be effectively suppressed or prevented. Thus, ESD protection is obtained.

[0136] [Effects and Effects] According to the protection circuit 22 and semiconductor device 2 of the 10th embodiment, the same effects and benefits as those obtained with the protection circuit 22 and semiconductor device 2 of the 8th embodiment can be obtained. Furthermore, in the protection circuit 22, the first external terminal 204A is also used as an external terminal connecting the first main electrode of MISFET 221A and the second main electrode of MISFET 221B. Similarly, the second external terminal 204B is also used as an external terminal connecting the second main electrode of MISFET 221A and the first main electrode of MISFET 221B. As a result, the number of external terminals to which the hot carrier is injected can be reduced.

[0137] <11. Eleventh Embodiment> The protection circuit 22 and semiconductor device 2 according to the 11th embodiment of this disclosure will be described. The 11th embodiment is an example of combining the protection circuit 22 and semiconductor device 2 according to the 9th embodiment and the protection circuit 22 and semiconductor device 2 according to the 10th embodiment.

[0138] [Configuration of protection circuit 22 and semiconductor device 2] Figure 24 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the 11th embodiment, the protection circuit 22 is connected between the external terminal 201 and the coupling capacitor 202 with a surge induction resistor 223 interposed between them. The protection circuit 22, like the protection circuit 22 according to the tenth embodiment, includes two MISFETs 221A and 221B that are electrically connected in parallel.

[0139] The configuration and circuit operation other than those described above are substantially the same as those of the protection circuit 22 according to the ninth embodiment and the protection circuit 22 according to the tenth embodiment, so their explanation is omitted here.

[0140] [Effects and Effects] According to the 11th embodiment of the protection circuit 22 and semiconductor device 2, it is possible to obtain an effect that combines the effects obtained by the protection circuit 22 and semiconductor device 2 according to the 9th embodiment and the effects obtained by the protection circuit 22 and semiconductor device 2 according to the 10th embodiment.

[0141] <12. Twelfth Embodiment> The protection circuit 22 and semiconductor device 2 according to the twelfth embodiment of this disclosure will now be described. The twelfth embodiment is a modified example of the protection circuit 22 and semiconductor device 2 according to the first embodiment.

[0142] [Configuration of protection circuit 22 and semiconductor device 2] Figure 25 shows the circuit block configuration of the protection circuit 22 and internal circuit 24, which serve as input-side protection circuits for the semiconductor device 2. In the protection circuit 22 and semiconductor device 2 according to the twelfth embodiment, an external protection element 6 is electrically connected in parallel to the DC bias circuit 5 at the external power supply terminal 208. The external protection element 6 has an ESD protection withstand capability even higher than that of the protection circuit 22. For example, a GGnMOS-Tr (Gate Grounded n-type MOSFET), a pn diode, etc., can be practically used as the external protection element 6.

[0143] The configuration and circuit operation other than those described above are substantially the same as those of the protection circuit 22 according to the first embodiment, so their explanation is omitted here.

[0144] [Effects and Effects] According to the twelfth embodiment of the protection circuit 22 and semiconductor device 2, the same effects and benefits as those obtained with the protection circuit 22 and semiconductor device 2 according to the first embodiment can be obtained. Furthermore, since an external protection element 6 is provided, the ESD resistance of the semiconductor device 2 can be further improved.

[0145] <13. Other Embodiments> This technology is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. For example, two or more protection circuits and semiconductor devices from the first to twelfth embodiments described above may be combined. Furthermore, although this technology was explained using an input-side protection circuit as an example, it may also be applied to an output-side protection circuit. Furthermore, this technology is not limited to insulated-gate field-effect transistors formed from compound semiconductor materials, but may also be applied to protection circuits and semiconductor devices that include insulated-gate field-effect transistors formed from Si semiconductor materials.

[0146] The protection circuit according to the first embodiment of this disclosure includes a MISFET. The MISFET has a first main electrode connected between its external terminals and internal circuitry, and a second main electrode connected to a reference power supply. A charge storage unit capable of accumulating hot carriers is provided in the gate insulating film. MISFETs are formed as depletion-type transistors, and hot carriers can be accumulated in the charge storage area to create an enhancement-type threshold voltage. Therefore, by using MISFETs, which have high process compatibility and do not use pn junctions, it is possible to construct protection circuits with excellent ESD withstand capability or avalanche withstand capability.

[0147] Furthermore, the semiconductor device according to the second embodiment of this disclosure includes an external terminal, an internal circuit, and a protection circuit. The protection circuit is disposed on a semiconductor substrate and includes a MISFET. The MISFET has a first main electrode connected between the external terminal and the internal circuit, a second main electrode and a gate electrode connected to a reference power supply, and is provided with a charge storage unit capable of accumulating hot carriers. Therefore, the same effects and benefits as those obtained by the aforementioned protection circuit can be obtained.

[0148] <Structure of this technology> This technology has the following configuration. With this technology configured as described below, it is possible to construct protection circuits and semiconductor devices with excellent ESD withstand capability or avalanche withstand capability using MISFETs with high process compatibility. (1) A first insulated gate field-effect transistor in which a first main electrode is connected between an external terminal and an internal circuit, a second main electrode and a gate electrode are connected to a reference power supply, and a charge storage unit capable of accumulating hot carriers is disposed in the gate insulating film. A protective circuit equipped with this feature. (2) Further comprising a resistor electrically connected in series between the gate electrode and the second main electrode The protection circuit described in (1) above. (3) A first external terminal connected between the external terminal and the first main electrode, to which a first power supply for generating a hot carrier is supplied, A second external terminal connected to the second main electrode and supplied with a second power supply that generates a hot carrier, The system further includes a third external terminal connected to the gate electrode, to which a third power supply is supplied for generating a hot carrier. The protection circuit described in (1) or (2) above. (4) External terminals arranged on the circuit board, An internal circuit disposed on the aforementioned substrate and connected to the aforementioned external terminal, A protection circuit having a first insulated gate field-effect transistor disposed on the substrate, with a first main electrode connected between the external terminal and the internal circuit, a second main electrode and gate electrode connected to a reference power supply, and a charge storage unit capable of accumulating hot carriers disposed in the gate insulating film, A semiconductor device equipped with the following features. (5) The protection circuit further comprises a resistor electrically connected in series between the gate electrode and the second main electrode. The semiconductor device described in (4) above. (6) A first external terminal connected between the external terminal and the first main electrode, to which a first power supply for generating a hot carrier is supplied, A second external terminal connected to the second main electrode and supplied with a second power supply that generates a hot carrier, The system further includes a third external terminal connected to the gate electrode, to which a third power supply is supplied for generating a hot carrier. The semiconductor device described in (4) or (5) above. (7) The charge storage section is configured with a structure in which an oxide film, a nitride film, and an oxide film are sequentially stacked. A semiconductor device as described in any one of (4) to (6) above. (8) The nitride film comprises SiN, The oxide film comprises at least one selected from Al2O3, HfO2, Ta2O5, ZrO2, Y2O3, and SiO2. The semiconductor device described in (7) above. (9) The charge storage unit includes Al2O3, HfO2 laminated on the Al2O3, SiN laminated on the HfO2, and SiO2 laminated on the SiN. The semiconductor device described in (7) above. (10) The first insulated gate field-effect transistor is made of a compound semiconductor. A semiconductor device as described in any one of (4) to (9) above. (11) The compound semiconductor includes GaN or GaAs The semiconductor device described in (10) above. (12) The first insulated gate field-effect transistor comprises InAlN The semiconductor device described in (11) above. (13) The first insulated gate field-effect transistor is formed into an enhancement type by accumulating hot carriers in the charge storage unit and shifting the threshold voltage from a depletion type to an enhancement type. A semiconductor device as described in any one of (4) to (12) above. (14) The gate length of the first insulated gate field-effect transistor in the direction in which the first main electrode and the second main electrode are arranged is formed to be 0.05 μm or more and 0.3 μm or less. The gate width in the direction intersecting the gate length is formed to be between 10 μm and 10,000 μm. A semiconductor device as described in any one of (4) to (13) above. (15) The resistor is formed to be between 100Ω and 10MΩ. The semiconductor device described in (5) above. (16) Further comprising a power amplifier including a second insulated gate field-effect transistor formed in a depletion type configuration. A semiconductor device as described in any one of (4) to (15) above. (17) Each of the first insulated gate field-effect transistor and the second insulated gate field-effect transistor comprises InAlN, At least a portion of the thickness of the InAlN in the first insulated gate field-effect transistor is thinner than the thickness of the InAlN in the second insulated gate field-effect transistor. The semiconductor device described in (16) above. (18) The external terminal and the first main electrode are further provided with an inductive resistor electrically connected in series. A semiconductor device as described in any one of (4) to (17) above. (19) The internal circuit is further provided with a coupling capacitor electrically connected in series between the external terminal and the internal circuit. A semiconductor device as described in any one of (4) to (18) above. (20) The first insulated gate field-effect transistors are arranged symmetrically in multiple locations. A semiconductor device according to any one of (4) to (19) above.

[0149] This application claims priority based on Japanese Patent Application No. 2021-114604, filed with the Japan Patent Office on 9 July 2021, and all contents of that application are incorporated herein by reference.

[0150] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A first insulated gate field-effect transistor in which a first main electrode is connected between an external terminal and an internal circuit, a second main electrode and a gate electrode are connected to a reference power supply, and a charge storage unit capable of accumulating hot carriers is disposed in the gate insulating film. A protective circuit equipped with this feature.

2. The device further comprises a resistor electrically connected in series between the gate electrode and the second main electrode. The protection circuit according to claim 1.

3. A first external terminal is connected between the external terminal and the first main electrode, and is supplied with a first power supply that generates a hot carrier. A second external terminal connected to the second main electrode and supplied with a second power supply for generating a hot carrier, The system further includes a third external terminal connected to the gate electrode, to which a third power supply for generating a hot carrier is supplied. The protection circuit according to claim 2.

4. External terminals arranged on the circuit board, An internal circuit disposed on the aforementioned substrate and connected to the aforementioned external terminal, A protection circuit having a first insulated gate field-effect transistor disposed on the substrate, with a first main electrode connected between the external terminal and the internal circuit, a second main electrode and gate electrode connected to a reference power supply, and a charge storage unit capable of accumulating hot carriers disposed in the gate insulating film, A semiconductor device equipped with the following features.

5. The protection circuit further comprises a resistor electrically connected in series between the gate electrode and the second main electrode. The semiconductor device according to claim 4.

6. A first external terminal is connected between the external terminal and the first main electrode, and is supplied with a first power supply that generates a hot carrier. A second external terminal connected to the second main electrode and supplied with a second power supply for generating a hot carrier, The system further includes a third external terminal connected to the gate electrode, to which a third power supply for generating a hot carrier is supplied. The semiconductor device according to claim 5.

7. The charge storage section is composed of a structure in which oxide films, nitride films, and oxide films are sequentially stacked. The semiconductor device according to claim 4.

8. The nitride film comprises SiN, The oxide film is Al ２ O ３ , HfO ２ , Ta ２ O ５ , ZrO ２ , Y ２ O ３ [[ID=十六]]and SiO[[ID=十七]] ２ and contains at least one selected from The semiconductor device according to claim 7.

9. The charge storage unit is Al ２ O ３ And, the aforementioned Al ２ O ３ HfO layered on top ２ And the aforementioned HfO ２ SiN stacked on top of the SiN, and SiO stacked on top of the SiN ２ and The semiconductor device according to claim 7.

10. The first insulated gate field-effect transistor is made of a compound semiconductor. The semiconductor device according to claim 4.

11. The compound semiconductor includes GaN or GaAs. The semiconductor device according to claim 10.

12. The first insulated gate field-effect transistor includes InAlN. The semiconductor device according to claim 11.

13. The first insulated gate field-effect transistor accumulates hot carriers in the charge storage section and shifts the threshold voltage from a depletion type to an enhancement type. The semiconductor device according to claim 4.

14. The gate length of the first insulated gate field-effect transistor in the direction in which the first main electrode and the second main electrode are arranged is formed to be 0.05 μm or more and 0.3 μm or less. The gate width in the direction intersecting the gate length is formed to be between 10 μm and 10,000 μm. The semiconductor device according to claim 4.

15. The aforementioned resistance is formed to be between 100 Ω and 10 MΩ. The semiconductor device according to claim 5.

16. It further includes a power amplifier containing a second insulated-gate field-effect transistor formed in a depletion type configuration. The semiconductor device according to claim 4.

17. Each of the first insulated-gate field-effect transistor and the second insulated-gate field-effect transistor contains InAlN, At least a portion of the thickness of the InAlN in the first insulated gate field-effect transistor is thinner than the thickness of the InAlN in the second insulated gate field-effect transistor. The semiconductor device according to claim 16.

18. The device further includes an inductive resistor electrically connected in series between the external terminal and the first main electrode. The semiconductor device according to claim 4.

19. The system further includes a coupling capacitor electrically connected in series between the external terminal and the internal circuit. The semiconductor device according to claim 4.

20. Multiple of the first insulated gate field-effect transistors are arranged symmetrically. The semiconductor device according to claim 4.

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