Solid-state imaging device and imaging system

Abstract

To suppress deterioration in image quality of image data in a solid-state imaging device in which a plurality of semiconductor substrates are laminated.SOLUTION: A plurality of first circuits are provided on a first semiconductor substrate out of first and second semiconductor substrates bonded on the bonding surface where atoms terminating dangling bonds of silicon are included in the vicinity. A second circuit is provided in the second semiconductor substrate. A first via connects a part of a plurality of first circuits to a predetermined joint area in the joint surface. A second via connects the second circuit to the first via. A third via connects the balance of the plurality of first circuits with a dummy area which does not correspond to the joint area in the joint surface.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present technology relates to a solid-state imaging device and an imaging system. More specifically, it relates to a solid-state imaging device and an imaging system in which noise due to dark current occurs.

Background Art

[0002] Conventionally, in order to reduce the scale and area of circuits per semiconductor substrate, a technique of laminating and bonding a plurality of semiconductor substrates has been used in solid-state imaging devices. For example, a solid-state imaging device has been proposed in which copper electrode pads are exposed on the bonding surfaces of a pair of semiconductor substrates, and the electrode pads are bonded to each other to achieve electrical conduction (see, for example, Patent Document 1). In this way, the bonding method of bonding copper electrode pads to each other is called Cu (copper)-Cu bonding. In the above-described solid-state imaging device, in addition to electrode pads, pads that are not used for electrical conduction are further provided as dummy pads on the bonding surfaces below a plurality of pixel circuits.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above-described conventional technology, in addition to electrode pads, dummy pads are also bonded to each other to improve the bonding strength. However, there is a problem that a difference occurs between the dark current of the pixel circuit on the electrode pad and the dark current of the pixel circuit on the dummy pad, and noise occurs in the image data due to this difference, resulting in a deterioration of the image quality. It is presumed that one of the reasons for the difference in dark current is that there is a difference in the amount of hydrogen supplied to the pixel circuit on the electrode pad and the amount of hydrogen supplied to the pixel circuit on the dummy pad.

[0005] This technology was developed in light of these circumstances, and aims to suppress the degradation of image data quality in a solid-state imaging device that stacks multiple semiconductor substrates and has dummy pads. [Means for solving the problem]

[0006] This technology was developed to solve the above-mentioned problems, and its first aspect comprises a first semiconductor substrate having a plurality of photoelectric conversion units and a first wiring layer, and a second semiconductor substrate having a second wiring layer and a signal processing circuit, wherein the first wiring layer has a first electrode pad, a first via connected to the first electrode pad, and a second electrode pad, and the second wiring layer has a third electrode pad, a fourth electrode pad, and a second via connected to the third electrode pad, and the first wiring layer or the second wiring layer has the second electrode pad and the fourth electrode pad The solid-state image sensor has a third via connected to either one of the first electrode pads, a portion of the first electrode pad and a portion of the third electrode pad are joined to each other, a portion of the second electrode pad and a portion of the fourth electrode pad are joined to each other, and the pixel signal generated by at least one of the plurality of photoelectric conversion units is transmitted to the signal processing circuit via the first via, the first electrode pad, the third electrode pad and the third via, and the second electrode pad or the fourth electrode pad connected to the third via is electrically connected to an arbitrary potential via the third via. This results in the uniform supply of hydrogen through the first and third vias.

[0007] Furthermore, in this first aspect, the first semiconductor substrate may have a transfer transistor and a floating diffusion. This results in the uniform supply of hydrogen to each pixel, including the transfer transistor, etc.

[0008] Furthermore, in this first aspect, the first semiconductor substrate may have a reset transistor and an amplifying transistor. This results in the uniform supply of hydrogen to each pixel, including the reset transistor and the amplifying transistor.

[0009] Furthermore, in this first aspect, the signal processing circuit may include an analog-to-digital signal conversion circuit. This results in the signal processing circuit converting the analog signal into a digital signal.

[0010] Furthermore, in this first aspect, the first wiring layer may have a third via connected to the second electrode pad, and the second wiring layer may have a fourth via connected to the fourth electrode pad. This results in the uniform supply of hydrogen through the vias provided in the wiring layer.

[0011] Furthermore, a second aspect of this technology is that of first and second semiconductor substrates joined at a junction surface containing atoms that terminate silicon dangling bonds, the first semiconductor substrate has a plurality of first circuits, the second semiconductor substrate has a plurality of second circuits, a first via connecting a portion of the plurality of first circuits to a predetermined junction region within the junction surface, a second via connecting the second circuits to the junction region, and a third via connecting the remainder of the plurality of first circuits to a dummy region within the junction surface that does not correspond to the junction region. This results in the uniform supply of hydrogen through the first and third vias.

[0012] Furthermore, in this second aspect, electrode pads may be placed in the junction region, dummy pads may be placed in the dummy region, the first via may connect a portion of the plurality of first circuits to the junction region via the electrode pad, and the third via may connect the remainder of the plurality of first circuits to the dummy region via the dummy pad. This results in the uniform supply of hydrogen through the electrode pads, dummy pads, and first and third vias.

[0013] Furthermore, in this second aspect, a predetermined number of the first vias may be connected to the electrode pad, and a different number of the third vias may be connected to the dummy pad. This results in the uniform supply of hydrogen through the first and third vias, which are of different numbers.

[0014] Furthermore, in this second aspect, a predetermined number of the first vias may be connected to the electrode pad, and a predetermined number of the third vias may be connected to the dummy pad. This results in the uniform supply of hydrogen through the same number of first and third vias.

[0015] Furthermore, in this second aspect, the dummy pad may include a first dummy pad to which the third via is not connected and a second dummy pad to which the third via is connected. This results in the effect of adjusting the hydrogen supply to the dummy region to be uniform.

[0016] Furthermore, in this second aspect, the dummy pad may include first and second dummy pads to which different numbers of the third vias are connected. This results in the effect of adjusting the hydrogen supply to the dummy area to be uniform.

[0017] Furthermore, in this second aspect, the cross-sectional area of ​​the third via may differ from that of the first via. This results in the effect of adjusting the amount of hydrogen supplied through the first and third vias.

[0018] Furthermore, in this second aspect, the cross-sectional shapes of the first and third vias may be circular or rectangular. This results in the uniform supply of hydrogen through the circular or rectangular vias.

[0019] Furthermore, in this second aspect, the third via may connect the remainder of the plurality of first circuits to the dummy region via a predetermined medium for transmitting the atoms and the dummy pad. This results in a uniform supply of hydrogen via the predetermined medium and the dummy pad.

[0020] Furthermore, in this second aspect, each of the plurality of first circuits is a pixel circuit that generates a predetermined pixel signal, the second circuit is a circuit that processes the pixel signal, and the first semiconductor substrate may be a light-receiving substrate. This results in the uniform supply of hydrogen to the plurality of pixel circuits.

[0021] Furthermore, in this second aspect, a fourth via is further provided, wherein the second semiconductor substrate is a circuit board, and the dummy pad includes a light-receiving dummy pad located on the light-receiving substrate and a circuit-side dummy pad located on the circuit board, the third via is connected to the light-receiving dummy pad, and the fourth via is connected to the circuit-side dummy pad. This results in the supply of hydrogen from the circuit side as well.

[0022] Furthermore, in this second aspect, the second circuit is a pixel circuit that generates a predetermined pixel signal, each of the plurality of first circuits is a circuit that processes the pixel signal, and the first semiconductor substrate may be a circuit board. This results in the uniform supply of hydrogen to the plurality of circuits on the circuit side.

[0023] Furthermore, in this second aspect, the device may further include a fourth via connected to the third via without a dummy pad, and the first and second vias may be connected without an electrode pad. This results in a uniform supply of hydrogen without the need for a pad.

[0024] Also, in this second aspect, in the bonding region, a silicon nitride film and an electrode pad penetrating the silicon nitride film are formed, and in the dummy region, a dummy pad penetrating the silicon nitride film may be formed. This brings about the effect of increasing the supply amount of hydrogen.

[0025] Further, the third aspect of the present technology is a first semiconductor substrate provided with a plurality of first circuits joined at a bonding surface containing atoms that terminate silicon dangling bonds in the vicinity, a second circuit provided on the second semiconductor substrate, a first via connecting a part of the plurality of first circuits and a predetermined bonding region in the bonding surface, a second via connecting the second circuit and the bonding region, a third via connecting the remaining of the plurality of first circuits and a dummy region not corresponding to the bonding region in the bonding surface, and a signal processing circuit that performs predetermined signal processing on a signal generated by the second circuit. An imaging system. This brings about the effect that hydrogen is uniformly supplied through the first and third vias and signal processing is performed.

Brief Description of Drawings

[0026] [Figure 1] It is a block diagram showing a configuration example of an imaging system in the first embodiment of the present technology. [Figure 2] It is a diagram showing an example of the stacked structure of a solid-state imaging device in the first embodiment of the present technology. [Figure 3] It is a block diagram showing a configuration example of a solid-state imaging device in the first embodiment of the present technology. [Figure 4] It is a plan view showing an example of the bonding surface of a light-receiving substrate in the first embodiment of the present technology. [Figure 5] It is a circuit diagram showing a configuration example of a pixel circuit on a VSL (Vertical Signal Line) bonding region in the first embodiment of the present technology. [Figure 6] It is a circuit diagram showing a configuration example of a pixel circuit on a dummy region in the first embodiment of the present technology. [Figure 7] This is a plan view showing an example of the VSL bonding region and dummy region in the first embodiment of this technology. [Figure 8] This is an example of a cross-sectional view of a solid-state imaging device in the first embodiment of this technology. [Figure 9] This is an example of a cross-sectional view of a comparative example solid-state imaging device. [Figure 10] This is an enlarged view showing an example of the vicinity of the bonding surface in the first embodiment of this technology and a comparative example. [Figure 11] This figure shows an example of image data in the first embodiment and comparative example of this technology. [Figure 12] This is a plan view showing an example of a VSL bonding region and a dummy region in a first modified example of the first embodiment of this technology. [Figure 13] This is a plan view showing an example of a VSL bonding region and a dummy region in a second modified example of the first embodiment of this technology. [Figure 14] This is an example of a cross-sectional view of a solid-state imaging device in a second modified example of the first embodiment of this technology. [Figure 15] This is a plan view showing an example of a VSL bonding region and a dummy region in a third modified example of the first embodiment of this technology. [Figure 16] This is an example of a cross-sectional view of a solid-state imaging device in a third modified example of the first embodiment of this technology. [Figure 17] This is a plan view showing an example of the VSL bonding region and dummy region in the second embodiment of this technology. [Figure 18] This is a plan view showing an example of a dummy area in a modified example of the second embodiment of this technology. [Figure 19] This is a plan view showing an example of the VSL bonding region and dummy region in the third embodiment of this technology. [Figure 20] This is an example of a cross-sectional view of a solid-state imaging device in a third embodiment of this technology. [Figure 21] This is a plan view showing an example of the VSL bonding region and dummy region in the fourth embodiment of this technology. [Figure 22] This is an example of a cross-sectional view of a solid-state imaging device in the fifth embodiment of this technology. [Figure 23] This is an example of a cross-sectional view of a solid-state imaging device in the sixth embodiment of this technology. [Figure 24] This is an example of a cross-sectional view of a solid-state imaging device in the seventh embodiment of this technology. [Figure 25] This is an example of a cross-sectional view of a solid-state imaging device in the eighth embodiment of this technology. [Figure 26] This is an example of a cross-sectional view of a solid-state imaging device in the ninth embodiment of this technology. [Figure 27] This is a plan view showing an example of the bonding surface of a light-receiving substrate in the tenth embodiment of this technology. [Figure 28] This figure illustrates the configuration of a solid-state imaging device in the eleventh embodiment of this technology. [Figure 29] This figure illustrates the light-receiving substrate and the circuitry arranged on the circuit board in the eleventh embodiment of this technology. [Figure 30] This is a plan view showing an example of the bonding surface of a light-receiving substrate in the eleventh embodiment of this technology. [Figure 31] This figure shows the circuit configuration of the solid-state imaging device in the eleventh embodiment of this technology. [Figure 32] This is an example of a cross-sectional view of a solid-state imaging device in the twelfth embodiment of this technology. [Figure 33] This is an example of a cross-sectional view of a solid-state imaging device in the thirteenth embodiment of this technology. [Figure 34] This is an example of a perspective view of a solid-state imaging device in the 14th embodiment of this technology. [Figure 35] This is a plan view showing an example of the bonding surface of a light-receiving substrate in the 14th embodiment of this technology. [Figure 36] This is another example of a perspective view of a solid-state imaging device in the 14th embodiment of this technology. [Figure 37] This is a plan view showing another example of the bonding surface of the light-receiving substrate in the 14th embodiment of this technology. [Figure 38] This is another example of a perspective view of a solid-state imaging device in the 14th embodiment of this technology. [Figure 39] This is another example of a perspective view of a solid-state imaging device in the 14th embodiment of this technology. [Figure 40] This is an enlarged view showing an example of the vicinity of the bonding surface in an embodiment of this technology and a comparative example. [Figure 41] This is an example of a cross-sectional view of a solid-state imaging device in the 15th embodiment of this technology. [Figure 42] This is an example of a cross-sectional view of a solid-state imaging device in the 16th embodiment of this technology. [Figure 43] This is another example of a cross-sectional view of a solid-state imaging device in the 16th embodiment of this technology. [Figure 44] This is a block diagram illustrating a schematic configuration example of a vehicle control system. [Figure 45] This is an explanatory diagram showing an example of the installation location of the imaging unit. [Modes for carrying out the invention]

[0027] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (Example of uniformly supplying hydrogen via vias) 2. Second Embodiment (An example in which vias are connected to a portion of the dummy pad to uniformly supply hydrogen) 3. Third Embodiment (Example of uniformly supplying hydrogen through multiple vias with different cross-sectional areas) 4. Fourth Embodiment (Example of uniformly supplying hydrogen via circular vias) 5. Fifth Embodiment (Example of uniformly supplying hydrogen to the circuit side via vias) 6. Sixth Embodiment (Example of uniformly supplying hydrogen via vias on the light-receiving side and the circuit side) 7. Seventh Embodiment (Example of Uniformly Supplying Hydrogen via a Medium and Vias) 8. Eighth Embodiment (Example of uniformly supplying hydrogen through vias penetrating the joint surface) 9. The ninth embodiment (an example of uniformly supplying hydrogen via vias in areas other than the pixel region) 10. Tenth Embodiment (An example in which a dummy pad is placed within the pixel area and hydrogen is uniformly supplied via vias) 11. Eleventh Embodiment (An example of uniform hydrogen supply via vias after analog-to-digital conversion for each area) 12. Twelfth Embodiment (An example of uniformly supplying hydrogen via vias in a three-layer stacked structure including a memory substrate) 13. Thirteenth Embodiment (An example of uniformly supplying hydrogen via vias in a three-layer stacked structure including a pixel substrate) 14. Fourteenth Embodiment (An example in which multiple vertical drive circuits are arranged and hydrogen is uniformly supplied via vias) 15. Fifteenth Embodiment (An example in which electrode pads are placed in addition to the pixel array section, and hydrogen is uniformly supplied via vias) 16. Sixteenth Embodiment (An example of uniformly supplying hydrogen via vias in a three-layer laminated structure) 17. Examples of applications to mobile devices

[0028] <1. First Embodiment> [Example of imaging device configuration] Figure 1 is a block diagram showing an example configuration of an imaging system 100 in a first embodiment of this technology. This imaging system 100 is for capturing image data and comprises an optical unit 110, a solid-state imaging device 200, and a DSP (Digital Signal Processing) circuit 120. Furthermore, the imaging system 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Examples of imaging systems 100 include cameras mounted on smartphones and in-vehicle cameras.

[0029] The optical unit 110 collects light from the subject and guides it to the solid-state imaging device 200. The solid-state imaging device 200 generates image data by photoelectric conversion. The solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.

[0030] The DSP circuit 120 performs predetermined signal processing on the image data. The DSP circuit 120 outputs the processed image data to a frame memory 160 or the like via the bus 150. The DSP circuit 120 is an example of a signal processing circuit described in the claims.

[0031] The display unit 130 displays image data. The display unit 130 could be, for example, a liquid crystal panel or an organic EL (Electro-Luminescence) panel. The operation unit 140 generates operation signals according to user input.

[0032] Bus 150 is a common path for the optical unit 110, solid-state imaging device 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with each other.

[0033] The frame memory 160 stores image data. The storage unit 170 stores various data, including image data. The power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.

[0034] [Example of a solid-state imaging device configuration] Figure 2 shows an example of the stacked structure of a solid-state imaging device 200 in the first embodiment of this technology. This solid-state imaging device 200 comprises a circuit board 202 and a light-receiving substrate 201 stacked on the circuit board 202.

[0035] Hereinafter, a predetermined axis parallel to the substrate plane of the light-receiving substrate 201 and the circuit board 202 will be defined as the X-axis, and an axis perpendicular to the substrate plane will be defined as the Z-axis. Furthermore, an axis perpendicular to the X-axis and Z-axis will be defined as the Y-axis.

[0036] Multiple vertical signal lines (VSLs) are routed along the Y-axis on the light-receiving substrate 201. These vertical signal lines (VSLs) are electrically connected to circuits in the circuit board 202 via vias and Cu-Cu junctions.

[0037] Figure 3 is a block diagram showing an example configuration of a solid-state imaging device 200 in the first embodiment of this technology. This solid-state imaging device 200 includes a vertical drive circuit 210, a timing control circuit 220, a north-side horizontal drive circuit 231, a north-side column signal processing circuit 241, a pixel array unit 250, a south-side column signal processing circuit 242, and a south-side horizontal drive circuit 232. It also further includes a power supply circuit 270 and an output unit 280 for the solid-state imaging device 200.

[0038] Multiple pixel circuits 260 are arranged in a two-dimensional grid within the pixel array section 250. A set of pixel circuits 260 arranged in the X-axis direction will be referred to as a "row," and a set of pixel circuits 260 arranged in the Y-axis direction will be referred to as a "column."

[0039] The pixel circuit 260 generates a pixel signal by photoelectric conversion of incident light.

[0040] The vertical drive circuit 210 sequentially selects and drives the rows, outputting pixel signals. The pixel circuits 260 of one of the odd-numbered rows (e.g., odd-numbered rows) output pixel signals to the north column signal processing circuit 241, while the pixel circuits 260 of the other row (e.g., even-numbered rows) output pixel signals to the south column signal processing circuit 242.

[0041] The timing control circuit 220 controls the operating timing of the vertical drive circuit 210, the north-side horizontal drive circuit 231, the north-side column signal processing circuit 241, the south-side column signal processing circuit 242, and the south-side horizontal drive circuit 232.

[0042] The northern column signal processing circuit 241 performs signal processing such as AD (Analog to Digital) conversion and CDS (Correlated Double Sampling) on ​​the pixel signals from the corresponding rows (odd-numbered rows, etc.) on a column-by-column basis. The northern column signal processing circuit 241 outputs the processed pixel signals to the output unit 280 according to the control of the northern horizontal drive circuit 231.

[0043] The south column signal processing circuit 242 performs signal processing such as AD conversion and CDS processing on the pixel signals from the corresponding rows (even-numbered rows, etc.) on a column-by-column basis. The south column signal processing circuit 242 outputs the processed pixel signals to the output unit 280 according to the control of the south horizontal drive circuit 232.

[0044] The north-side horizontal drive circuit 231 controls the north-side column signal processing circuit 241 to sequentially output the pixel signals within a row. The south-side horizontal drive circuit 232 controls the south-side column signal processing circuit 242 to sequentially output the pixel signals within a row.

[0045] The power supply circuit 270 supplies power to the pixel array unit 250 and the like. The output unit 280 outputs image data, which is an array of pixel signals, to the DSP circuit 120.

[0046] Furthermore, the pixel array section 250 is located on the light-receiving substrate 201, while other circuits such as the vertical drive circuit 210 are located on the circuit board 202. The dashed lines in the figure indicate the junction surfaces of these substrates. Although the pixel array section 250 is located on the light-receiving substrate 201 and the other circuits are located on the circuit board 202, the circuits located on each substrate are not limited to this configuration. For example, the comparators in the north column signal processing circuit 241 and the south column signal processing circuit 242 could also be located on the light-receiving substrate 201.

[0047] Furthermore, while both the north column signal processing circuit 241 and the south column signal processing circuit 242 are provided, it is also possible to provide only one of them. In this case, only the corresponding north horizontal drive circuit 231 and the south horizontal drive circuit 232 are provided.

[0048] Figure 4 is a plan view showing an example of the bonding surface of the light-receiving substrate 201 in the first embodiment of this technology. Here, of the two surfaces of the light-receiving substrate 201, the surface facing the bonding surface will be referred to as the "light-receiving surface." The aforementioned plurality of pixel circuits 260 are arranged on this light-receiving surface.

[0049] The bonding surface of the light-receiving substrate 201 is provided with drive line bonding regions 311 and 312, power line bonding regions 313 and 316, VSL bonding region 314, and dummy regions 321 and 322. The VSL bonding region 314 is positioned between the dummy regions 321 and 322. Also, with the light-receiving surface facing upwards, the VSL bonding region 314 and the dummy regions 321 and 322 are positioned below the pixel array section 250. The bonding surface configuration of the circuit board 202 is the same as that of the light-receiving substrate 201.

[0050] Multiple electrode pads 431, for example, made of copper, are arranged in the VSL junction region 314. Each electrode pad 431 is positioned below a different pixel circuit 260. The electrode pads 431 are also connected to vertical signal lines and power lines via vias. Furthermore, the electrode pads 431 are bonded to electrode pads on the circuit board 202 side, and the light-receiving substrate 201 and the circuit board 202 are electrically connected via these electrode pads. The north column signal processing circuit 241 and the south column signal processing circuit 242 are connected to the electrode pads 431 of the VSL junction region 314. Note that the material of the electrode pads is not limited to copper, but may be other metal materials such as gold, or conductive materials. Also, although the diameter of the vias is smaller than that of the pads in the figure viewed from the X direction, the configuration is not limited to this. When viewed from the X or Y direction, the diameter of the vias may be larger than or the same as the pads, or smaller.

[0051] Multiple electrode pads are also formed in the drive line junction regions 311 and 312, and these electrode pads are connected to the drive lines via vias. Here, the drive lines are signal lines that transmit drive signals for driving the pixel circuit 260.

[0052] Multiple electrode pads are also formed in the power line junction regions 313 and 316, and these electrode pads are connected to the power line and ground line via vias.

[0053] Multiple copper dummy pads 441 are arranged in each of the dummy regions 321 and 322. Each dummy pad 441 is positioned below a different pixel circuit 260. The dummy pads 441 are joined to the dummy pads on the circuit board 202, but unlike the electrode pads 431, they are not used for electrical connection between the light-receiving substrate 201 and the circuit board 202. The dummy pads 441 can be fixed to potentials other than VSL, such as VDD or ground power, and can also be electrically floating. Although the dummy pads 441 are not used for electrical connection, joining the dummy pads 441 to each other, in addition to the electrode pads 431, improves the bonding strength and prevents warping of the substrate.

[0054] [Example of pixel circuit configuration] Figure 5 is a circuit diagram showing one example configuration of a pixel circuit 260 on a VSL junction region 314 in a first embodiment of the present technology. This pixel circuit 260 comprises a photoelectric conversion element 261, a transfer transistor 262, a reset transistor 263, a floating diffusion layer 264, an amplification transistor 265, and a selection transistor 266.

[0055] Furthermore, a pair of vertical signal lines VSL are wired along the Y-axis direction for each row on the light-receiving surface of the pixel array section 250. One of the pair of vertical signal lines VSL is connected to odd-numbered rows, and the other is connected to even-numbered rows. In addition, drive lines 217 to 219 are wired along the X-axis direction for each row on the light-receiving surface of the pixel array section 250.

[0056] The photoelectric conversion element 261 generates electric charge by photoelectric conversion of incident light. The transfer transistor 262 transfers the charge from the photoelectric conversion element 261 to the floating diffusion layer 264 according to the drive signal TRG. This drive signal TRG is supplied from the vertical drive circuit 210 via the drive line 218.

[0057] The reset transistor 263 initializes itself by extracting charge from the floating diffusion layer 264 according to the drive signal RST. This drive signal RST is supplied from the vertical drive circuit 210 via the drive line 217.

[0058] The floating diffusion layer 264 accumulates electric charge and generates a voltage corresponding to the amount of charge. The amplifying transistor 265 amplifies the voltage of the floating diffusion layer 264.

[0059] The selection transistor 266 outputs an amplified voltage signal as a pixel signal to the north column signal processing circuit 241 and the south column signal processing circuit 242 via the vertical signal line VSL, according to the drive signal SEL. This drive signal SEL is supplied from the vertical drive circuit 210 via the drive line 219.

[0060] Furthermore, the pixel circuit 260 on the VSL junction region 314 is connected to the electrode pad 431 via vertical signal lines VSL and vias. This electrode pad 431 is joined to the electrode pad 432 on the circuit board 202 side. Through these pads and vias, one end of the pair of vertical signal lines VSL is connected to the north column signal processing circuit 241, and the other end is connected to the south column signal processing circuit 242. Note that if only one of the north column signal processing circuit 241 or the south column signal processing circuit 242 is provided, only one vertical signal line VSL is wired per column.

[0061] Furthermore, the connection node between the power line 279, which supplies the power supply voltage VDD, and the pixel circuit 260 is connected to the power supply circuit 270 on the circuit board 202 side via vias and electrode pads 431 and 432.

[0062] Figure 6 is a circuit diagram showing one example configuration of a pixel circuit 260 on a dummy region 322 in the first embodiment of this technology. Vias are also placed at the connection nodes between the pixel circuit 260 at the top of this dummy region 322 and the vertical signal line VSL. However, unlike the vias in the VSL junction region 314, these vias in the dummy region 322 are not electrically connected to the circuit board 202.

[0063] Furthermore, the pixel circuit 260 on the dummy region 322 is connected to the dummy pad 441 via the power line 279 and vias. This dummy pad 441 is joined to the dummy pad 442 on the circuit board 202 side. Note that the configuration of the pixel circuit 260 is not limited to the circuits exemplified in Figures 5 and 6. For example, it is also possible to have a configuration in which a selection transistor is not placed within the pixel circuit 260.

[0064] Figure 7 is a plan view showing an example of a VSL junction region 314 and a dummy region 322 in the first embodiment of this technology. Multiple electrode pads 431 are arranged in the VSL junction region 314, and a predetermined number (for example, 4) vias 423 are connected to each electrode pad 431. Note that the number of vias 423 per electrode pad 431 is not limited to 4.

[0065] On the other hand, multiple dummy pads 441 are arranged in the dummy region 322, and each dummy pad 441 is connected to a different number of vias 424 (e.g., two) than the electrode pads 431.

[0066] Furthermore, all dummy pads 441 have the same number of vias connected to them. Also, the cross-sectional area and cross-sectional shape of vias 423 and 424 are identical. For example, all of them have a rectangular cross-sectional shape.

[0067] When multiple films are stacked on the light-receiving substrate 201, the films themselves may contain hydrogen. Additionally, hydrogen may be introduced during the hydrogen sintering process. Depending on these circumstances, the number of vias in the electrode pads 431 and dummy pads 441 is adjusted so that the hydrogen supply to each of the multiple pixel circuits 260 is equal.

[0068] Figure 8 is an example of a cross-sectional view of the solid-state imaging device 200 in the first embodiment of this technology. The cross-sectional view in Figure 8 is a cross-sectional view obtained by cutting the solid-state imaging device 200 along the line segment Y1-Y2 in Figure 7.

[0069] On the light-receiving substrate 201, with the light-receiving surface facing upwards, a wiring layer 420 is provided above the electrode pads 431. The wiring layer 420 consists of a single or multi-layer insulating film and a single or multi-layer wiring. In areas where the electrode pads are not joined together, the upper and lower insulating films are connected to each other. In addition, metal wiring 421, such as vertical signal lines and power lines, is routed along the Y-axis direction on the wiring layer 420, and transistors 417, such as transfer transistors, are arranged therein. The vertical signal lines, etc., are connected to the electrode pads 431 by vias 423. A photodiode 415 is formed above the vias 423, and a color filter 413 is formed above the photodiode 415, and above the color filter 413. An on-chip lens 411 is formed above the color filter 413. The photodiode 415 and transistors 417 form a pixel circuit 260.

[0070] Meanwhile, a wiring layer 420 is also provided on top of the dummy pad 441. In this wiring layer 420, metal wiring 422 such as power lines are routed along the Y-axis and X-axis, and transistors 418 such as transfer transistors are arranged. The power lines and the dummy pad 441 are connected by vias 424. A photodiode 416 is formed on top of the vias 424, and a color filter 414 is formed above the photodiode 416, and above the color filter 414. An on-chip lens 412 is formed above the color filter 414. The photodiode 416 and transistors 418 form a pixel circuit 260.

[0071] On the circuit board 202, with the light-receiving surface facing upwards, a wiring layer 450 is provided below the electrode pad 432. Metal wiring 451 is routed on this wiring layer 450, and a transistor 456 is provided. Vias 453 are connected to the electrode pad 432. Below the via 453, downstream circuits 461, such as the ADC in the north column signal processing circuit 241, are arranged. Vias 453 connect the electrode pad 432 to the downstream circuits 461 and other circuits.

[0072] Meanwhile, a wiring layer 450 is also provided below the dummy pad 442. Metal wiring 452 is routed in this wiring layer 450, and a transistor 456 and vias 454 are placed there. However, vias 454 are not connected to the dummy pad 442. Also, downstream circuits 462, such as the ADC in the north column signal processing circuit 241, are located below vias 454.

[0073] As described above, multiple pixel circuits 260 are arranged on the light-receiving surface of the light-receiving substrate 201 that faces the bonding surface. Here, hydrogen or the like may be introduced near the bonding surface during the bonding process (such as the hydrogen sintering process) between the light-receiving substrate 201 and the circuit board 202. As described in Japanese Patent Application Publication No. 2001-267547, this hydrogen or the like is known to terminate the dangling bonds of silicon. Due to this property, when hydrogen or the like is supplied to semiconductor elements (photoelectric conversion elements and transistors) in the pixel circuits 260, the dark current generated in those pixel circuits 260 is suppressed in proportion to the amount supplied.

[0074] As illustrated in the figure, via 423 connects the electrode pad 431 to the pixel circuit 260 above it to transmit the pixel signal, and via 424 connects the dummy pad 441 to the pixel circuit 260 above it. In other words, via 423 connects the pixel circuit 260 above it to the VSL junction region 314 of the junction surface via the electrode pad 431, and via 424 connects the pixel circuit 260 above it to the dummy region 322 of the junction surface via the dummy pad 441.

[0075] Because hydrogen is present near the bonding surface due to the bonding process, hydrogen is supplied to the pixel circuit 260 above the electrode pad 431 via via 423, and further supplied to the pixel circuit 260 above the dummy pad 441 via via 424. This ensures that the amount of hydrogen supplied to each of the multiple pixel circuits 260 is uniform, resulting in uniform dark current generation in each circuit. Furthermore, by connecting via 424 to the dummy pad 441, the uniformity of the via opening is improved, suppressing process variations. This also helps to suppress plasma damage and improve yield.

[0076] Furthermore, if vias are not provided, the electrode pads for dummy junctions will float. By adding vias, it becomes possible to connect the electrode pads for dummy junctions (such as dummy pad 441) to, for example, a fixed potential (VDD), an arbitrary potential, or ground potential (GND). This makes the electrodes for dummy junctions potentialally stable and improves their electrical characteristics. As for how to connect to a fixed potential, an arbitrary potential, or ground potential, vias can be directly connected to those potentials. Alternatively, by adding vias, the electrode pads can be connected to other wiring via vias. It is also possible to configure the electrode pads to be connected to arbitrary potentials by connecting the wiring connected to the terminal of the via opposite to the electrode pad to an arbitrary potential.

[0077] The light-receiving substrate 201 is an example of the first semiconductor substrate described in the claims, and the circuit board 202 is an example of the second semiconductor substrate described in the claims. The pixel circuit 260 is an example of the first circuit described in the claims. The subsequent circuit 461 is an example of the second circuit described in the claims. The electrode pad 431 is an example of the first electrode pad described in the claims, and the dummy pad 441 is an example of the second electrode pad. The electrode pad 432 is an example of the third electrode pad described in the claims, and the dummy pad 442 is an example of the fourth electrode pad. The wiring layer 420 is an example of the first wiring layer described in the claims, and the wiring layer 450 is an example of the second wiring layer. The via 423 is an example of the first via described in the claims, and the via 453 is an example of the second via described in the claims. The via 424 is an example of the third via described in the claims.

[0078] Furthermore, while hydrogen is assumed to be the atom that terminates silicon dangling bonds, other atoms may also have the property of terminating silicon dangling bonds. For this reason, the number of vias can be adjusted so that the supply of atoms other than hydrogen that terminate silicon dangling bonds is uniform. Examples of atoms that terminate silicon dangling bonds include elements such as hydrogen (H), fluorine (F), nitrogen (N), oxygen (O), and carbon (C). Other examples include elements from groups 13 to 17 of the periodic table, but are not limited to these.

[0079] Next, let's consider a comparative example where via 424 is not connected to dummy pad 441.

[0080] Figure 9 shows an example of a cross-sectional view of a comparative solid-state imaging device. As illustrated in the figure, when via 424 is not connected to dummy pad 441, the amount of hydrogen supplied to the pixel circuit 260 above dummy pad 441 is less than that supplied to the upper part of electrode pad 431. As a result, the amount of hydrogen supplied to each of the multiple pixel circuits 260 becomes uneven, causing differences in the amount of dark current generated in each circuit. Consequently, noise caused by the difference in dark current occurs, degrading the image quality of the image data.

[0081] Figure 10 is an enlarged view showing an example of the vicinity of the joint surface in the first embodiment of the present technology and a comparative example. In the figure, a is an enlarged view showing an example of the vicinity of the joint surface in the first embodiment of the present technology, and b is an enlarged view showing an example of the vicinity of the joint surface in the comparative example.

[0082] As illustrated in figure a, a SiN (Silicon Nitride) film 471 is formed on the light-receiving bonding surface to prevent warping of the light-receiving substrate 201. The electrode pad 431 is formed by breaking through the SiN film 471. In other words, the electrode pad 431 penetrates the SiN film 471.

[0083] Similarly, a SiN film 472 is formed on the circuit side, and the electrode pad 432 is formed by breaking through the SiN film 472.

[0084] As described in Japanese Patent Publication No. 2018-078305, SiN films 471 and 472 are used to prevent warping. However, as described in Japanese Patent Publication No. 2004-165236, these SiN films 471, etc., have the property of blocking hydrogen. Therefore, if the SiN film 472, etc. is not broken through, as illustrated in Figure b, hydrogen may not be supplied to the pixel circuit 260, and the dark current may not be sufficiently suppressed. For this reason, when forming a SiN film, it is preferable that the electrode pad breaks through the SiN film.

[0085] Figure 11 shows examples of image data in the first embodiment and comparative example of the present technology. Figure a shows an example of image data 500 captured in dark conditions in the first embodiment of the present technology. Figure b shows an example of image data 501 captured in dark conditions in a comparative example in which the via is not connected to a dummy pad.

[0086] When a via is connected to a dummy pad, hydrogen is also supplied to the pixel circuit 260 above it via the via, resulting in a uniform hydrogen supply to each of the multiple pixel circuits 260 and a uniform dark current generation in each circuit. As a result, as illustrated in figure a, streaks do not appear in the image data 500, and image quality can be improved.

[0087] In contrast, if the via is not connected to the dummy pad, hydrogen is not supplied to the pixel circuit 260 above it. As a result, the amount of hydrogen supplied to each of the multiple pixel circuits 260 becomes uneven, and the amount of dark current generated in each circuit becomes uneven. This causes streaky noise to appear in the VSL junction region 314 of the image data 501, as illustrated in figure b, resulting in a decrease in image quality.

[0088] Thus, according to the first embodiment of this technology, since the via 424 connects the pixel circuit 260 above it and the dummy region 322 of the junction surface via the dummy pad 441, the amount of hydrogen supplied to each of the multiple pixel circuits 260 can be made uniform. As a result, the amount of dark current generated becomes uniform, and the image quality of the image data can be improved.

[0089] [First variation] In the first embodiment described above, the number of vias in the dummy pad 441 was set to two to ensure a uniform hydrogen supply. However, with only two vias, the hydrogen supply can sometimes be excessive. The solid-state imaging device 200 in the first modification of this first embodiment differs from the first embodiment in that the number of vias in the dummy pad 441 is reduced to decrease the hydrogen supply.

[0090] Figure 12 is a plan view showing an example of a VSL junction region 314 and a dummy region 322 in a first modification of the first embodiment of the present technology. This modification of the first embodiment of the solid-state imaging device 200 differs in that the dummy pad 441 has one via. By reducing the number of vias in the dummy pad 441 by one, the amount of hydrogen supplied to the pixel circuit 260 above it can be reduced.

[0091] Thus, according to the first modification of the first embodiment of this technology, the number of vias in the dummy pad 441 is reduced, which makes it possible to reduce the amount of hydrogen supplied to the pixel circuit 260 above the dummy pad 441.

[0092] [Second variation] In the first embodiment described above, the number of vias in the dummy pad 441 was set to two to ensure a uniform hydrogen supply. However, with only two vias, the hydrogen supply may be insufficient. The solid-state imaging device 200 in the second modification of the first embodiment differs from the first embodiment in that the number of vias in the dummy pad 441 is increased to increase the hydrogen supply.

[0093] Figure 13 is a plan view showing an example of the VSL bonding region 314 and dummy region 322 in a second modification of the first embodiment of the present technology.

[0094] Figure 14 is an example of a cross-sectional view of a solid-state imaging device 200 in a second modified example of the first embodiment of the present technology.

[0095] As illustrated in Figures 13 and 14, the solid-state imaging device 200 of the second modification of the first embodiment differs in that the number of vias on the dummy pad 441 is four, similar to the electrode pad 431. By increasing the number of vias on the dummy pad 441, the amount of hydrogen supplied to the pixel circuit 260 above it can be increased.

[0096] Furthermore, the number of vias per dummy pad 441 is not limited to one, two, or four; it may also be three.

[0097] Thus, according to the second modification of the first embodiment of this technology, the number of vias in the dummy pad 441 is increased, which makes it possible to increase the amount of hydrogen supplied to the pixel circuit 260 above the dummy pad 441.

[0098] [Third variation] In the second modification of the first embodiment described above, the number of vias in the dummy pad 441 was increased to four, but with four vias, the hydrogen supply may be insufficient. The solid-state imaging device 200 in this third modification of the first embodiment differs from the second modification of the first embodiment in that the number of vias in the dummy pad 441 is further increased.

[0099] Figure 15 is a plan view showing an example of the VSL bonding region 314 and dummy region 322 in a third modified example of the first embodiment of the present technology.

[0100] Figure 16 is an example of a cross-sectional view of a solid-state imaging device 200 in a third modified example of the first embodiment of the present technology.

[0101] As illustrated in Figures 15 and 16, the solid-state imaging device 200 of the modified embodiment of the first embodiment differs in that the dummy pad 441 has 9 vias. By increasing the number of vias of the dummy pad 441, the amount of hydrogen supplied to the pixel circuit 260 on it can be increased.

[0102] Furthermore, the number of vias per dummy pad 441 is not limited to 1 to 4 or 9; it may also be 5 to 8, for example.

[0103] Thus, according to the third modification of the first embodiment of this technology, the number of vias in the dummy pad 441 is further increased, thereby further increasing the amount of hydrogen supplied to the pixel circuit 260 above the dummy pad 441.

[0104] <2. Second Embodiment> In the first embodiment described above, the number of vias connected to all dummy pads 441 was the same, but depending on the position of the dummy pad, vias may not be necessary. The solid-state imaging device 200 in this second embodiment differs from the first embodiment in that it has both dummy pads to which vias are connected and dummy pads to which vias are connected.

[0105] Figure 17 is a plan view showing an example of a VSL bonding region 314 and a dummy region 322 in a second embodiment of the present technology. The dummy region 322 in this second embodiment differs from that of the first embodiment in that a plurality of dummy pads 441 and a plurality of dummy pads 442 are arranged therein.

[0106] The location of dummy pad 441 does not require hydrogen supply, and no vias are connected to this pad. On the other hand, the location of dummy pad 442 requires hydrogen supply, and this pad has four vias, for example. By adjusting the number of vias in this way, the amount of hydrogen supplied can be made uniform.

[0107] Dummy pad 441 is an example of the first dummy pad described in the claims, and dummy pad 442 is an example of the second dummy pad described in the claims.

[0108] Thus, according to the second embodiment of this technology, since a dummy pad 441 to which vias are not connected and a dummy pad 442 to which vias are connected are arranged, the hydrogen supply amount can be adjusted and made uniform.

[0109] [Differentiation] In the second embodiment described above, dummy pads without vias and dummy pads with vias were arranged, but there is a risk that the hydrogen supply to the dummy pads without vias will be insufficient. The solid-state imaging device 200 in this modified version of the second embodiment differs from the second embodiment in that it arranges two or more types of dummy pads with different numbers of vias.

[0110] Figure 18 is a plan view showing an example of dummy regions 321, 322, and 323 in a modified example of the second embodiment of the present technology. In the figure, a is a plan view showing an example of dummy region 321. In the figure, b is a plan view showing an example of dummy region 322. In the figure, c is a plan view showing an example of dummy region 323.

[0111] The number of vias for each dummy pad is adjusted to ensure a uniform hydrogen supply. For example, as illustrated in figure a, dummy pads 441 and 442 are arranged in dummy region 321. Dummy pad 441 is connected to, for example, four vias, while dummy pad 442 is connected to a different number of vias (e.g., one via).

[0112] Dummy pad 441 is an example of the first dummy pad described in the claims, and dummy pad 442 is an example of the second dummy pad described in the claims.

[0113] As illustrated in figure b, dummy pads 443 and 444 are arranged in the dummy area 322. For example, dummy pad 443 has one via connected to it, while dummy pad 444 has a different number of vias connected to it (e.g., two).

[0114] As illustrated in figure c, dummy pads 445 and 446 are arranged in dummy area 323. No vias are connected to dummy pad 445, and the number of vias to dummy pad 446 is one, for example.

[0115] Thus, according to a modification of the second embodiment of this technology, since multiple types of dummy pads, each connected to a different number of vias, are arranged, the hydrogen supply can be made uniform by adjusting the number of vias.

[0116] <3. Third Embodiment> In the first embodiment described above, the cross-sectional area of ​​the via 423 of the electrode pad 431 and the cross-sectional area of ​​the via 424 of the dummy pad 441 were the same. However, in this configuration, the hydrogen supply amount may be uneven. The solid-state imaging device 200 of this third embodiment differs from the first embodiment in that the cross-sectional area of ​​the via 423 of the electrode pad 431 and the cross-sectional area of ​​the via 424 of the dummy pad 441 are different.

[0117] Figure 19 is a plan view showing an example of the VSL bonding region 314 and dummy region 322 in a third embodiment of the present technology.

[0118] Figure 20 is an example of a cross-sectional view of a solid-state imaging device 200 in a third embodiment of this technology.

[0119] As illustrated in Figures 19 and 20, the cross-sectional area of ​​via 423 on electrode pad 431 differs from the cross-sectional area of ​​via 424 on dummy pad 441. For example, via 424 has a larger cross-sectional area than via 423. Also, electrode pad 431 has four vias, while dummy pad 441 has one via. The number and cross-sectional area of ​​vias 423 and 424 are adjusted to ensure a uniform hydrogen supply.

[0120] Thus, according to the third embodiment of this technology, since the cross-sectional area of ​​the via 423 of the electrode pad 431 and the cross-sectional area of ​​the via 424 of the dummy pad 441 are different, the hydrogen supply amount can be made uniform by adjusting the cross-sectional area.

[0121] <4. Fourth Embodiment> In the first embodiment described above, vias with a rectangular cross-sectional shape were used, but the cross-sectional shape of the via is not limited to a rectangle and may be circular. The solid-state imaging device 200 of this fourth embodiment differs from the first embodiment in that it uses vias with a circular cross-sectional shape.

[0122] Figure 21 is a plan view showing an example of a VSL joint region 314 and a dummy region 322 in a fourth embodiment of this technology. The vias 423 and 424 in this fourth embodiment differ from those in the first embodiment in that their cross-sectional shapes are circular. However, the cross-sectional shape of the vias is not limited to circular or rectangular. For example, it may be elliptical.

[0123] Thus, according to the fourth embodiment of this technology, since the cross-sectional shape of the via is circular, hydrogen can be supplied by the circular via to make the dark current uniform.

[0124] <5. Fifth Embodiment> In the first embodiment described above, the dark current of each of the multiple pixel circuits 260 on the light-receiving side was made uniform, but the dark current of the multiple circuits (such as ADCs) on the circuit side may be uneven. The solid-state imaging device 200 of this fifth embodiment differs from the first embodiment in that it makes the dark current on the circuit side uniform by connecting vias on the circuit side to dummy pads.

[0125] Figure 22 is an example of a cross-sectional view of a solid-state imaging device 200 in the fifth embodiment of this technology. The solid-state imaging device 200 in this fifth embodiment differs from the first embodiment in that a via 424 is not connected to the light-receiving dummy pad 441, and a via 454 is connected to the circuit-side dummy pad 442. It is assumed that the dark current on the light-receiving side is uniform even if the via 424 is not connected to the light-receiving dummy pad 441.

[0126] On the plane of the circuit board 202 facing the bonding surface, multiple circuits such as the subsequent circuits 461 and 462 are arranged as described above. Via 453 connects the subsequent circuit 461 to the electrode pad 432, and via 454 connects the subsequent circuit 462 to the dummy pad 442. The subsequent circuits 461 and 462 are, for example, ADCs. This makes it possible to equalize the amount of hydrogen supplied to each of the subsequent circuits 461, etc. on the circuit side, and to equalize the dark current on the circuit side.

[0127] Thus, according to the fifth embodiment of this technology, since the via 454 on the circuit side connects the subsequent circuit 462 and the dummy pad 442, the amount of hydrogen supplied to each of the multiple circuits on the circuit side can be made uniform. As a result, the amount of dark current generated becomes uniform, and the image quality of the image data can be improved.

[0128] <6. Sixth Embodiment> In the first embodiment described above, the dummy pad on the circuit side was not connected to a via, but this configuration may result in insufficient hydrogen supply. The solid-state imaging device 200 of this sixth embodiment differs from the first embodiment in that it further connects vias to the dummy pad on the circuit side to increase the hydrogen supply.

[0129] Figure 23 is an example of a cross-sectional view of a solid-state imaging device 200 in the sixth embodiment of this technology. The solid-state imaging device 200 in this sixth embodiment differs from the first embodiment in that vias 454 are also connected to the dummy pad 442 on the circuit side. However, vias 454 are not connected to the power supply circuit 270, and dummy pads 441 and 442 are not used for electrical connections.

[0130] As illustrated in the figure, by connecting vias not only to the dummy pad 441 on the light-receiving side but also to the dummy pad 442 on the circuit side, hydrogen in the circuit board 202 can also be supplied to the pixel circuit 260 above it. This increases the amount of hydrogen supplied compared to the case where vias are connected only to the dummy pad 441 on the light-receiving side.

[0131] Dummy pad 441 is an example of a light-receiving dummy pad as described in the claims, and dummy pad 442 is an example of a circuit-side dummy pad as described in the claims. Via 454 is an example of a fourth via as described in the claims.

[0132] Thus, according to the sixth embodiment of this technology, since vias are also connected to the dummy pad 442 on the circuit side, the amount of hydrogen supplied can be increased compared to the case where vias are connected only to the dummy pad 441 on the light-receiving side.

[0133] <7. Seventh Embodiment> In the first embodiment described above, via 424 was directly connected to dummy pad 441, but since hydrogen vaporizes, it can also be supplied through a cavity path. The solid-state imaging device 200 of this seventh embodiment differs from the first embodiment in that it supplies hydrogen through a cavity path.

[0134] Figure 24 is an example of a cross-sectional view of a solid-state imaging device 200 in the seventh embodiment of this technology. The solid-state imaging device 200 of this seventh embodiment differs from the first embodiment in that the via 424 and the dummy pad 441 are connected by a cavity 425, which is a hollow path. In other words, the via 424 connects the bonding surface and the pixel circuit 260 via the air (hydrogen-transmitting medium) in the cavity 425 and the dummy pad 441. This allows the length of the via 424 to be shortened by the amount of the cavity 425. Note that the cavity 425 can also be filled with a filler material such as organic matter, as long as it is a medium that can transmit hydrogen.

[0135] Thus, according to the seventh embodiment of this technology, since the via 424 connects the bonding surface and the pixel circuit 260 via the cavity 425 and the dummy pad 441, the length of the via 424 can be shortened by the amount of the cavity 425.

[0136] <8. Eighth Embodiment> In the first embodiment described above, a pad was provided on the bonding surface for each pixel circuit 260 and the pads were bonded together. However, if the precision of the bonding position is sufficiently high, the pads become unnecessary. The solid-state imaging device 200 of this eighth embodiment differs from the first embodiment in that it eliminates the need for pads by supplying hydrogen through vias that penetrate the bonding surface.

[0137] Figure 25 is an example of a cross-sectional view of a solid-state imaging device 200 in the eighth embodiment of this technology. In this eighth embodiment, the via 424 on the light-receiving side is connected to the via 454 on the circuit side without a dummy pad. However, one end of the via 424 is connected to the power line on the light-receiving side, but the other end is not connected to a circuit, and this via is not used for electrical connection.

[0138] Furthermore, via 423 on the light-receiving side is also connected to via 453 on the circuit side without going through an electrode pad.

[0139] Since vias are placed in both the dummy region 322 and the VSL junction region 314, hydrogen can be uniformly supplied to the multiple pixel circuits 260 above through these vias.

[0140] Thus, according to the eighth embodiment of this technology, since the via on the light-receiving side and the via on the circuit side are directly connected, the hydrogen supply can be made uniform without using pads.

[0141] <9. The ninth embodiment> In the first embodiment described above, the dummy pad 441 and via 424 were placed within the pixel area where the pixel circuit 260 is located, but they can also be placed outside the pixel area. The solid-state imaging device 200 of this ninth embodiment differs from the first embodiment in that the dummy pad 441 and via 424 are also placed outside the pixel area.

[0142] Figure 26 is an example of a cross-sectional view of a solid-state imaging device in the ninth embodiment of this technology. The configuration of the pixel area in the ninth embodiment is the same as in the first embodiment. As illustrated in the figure, the solid-state imaging device 200 of the ninth embodiment differs from the first embodiment in that dummy pads 441 and vias 424 are also arranged outside the pixel area.

[0143] Thus, in the ninth embodiment of this technology, dummy pads 441 and vias 424 are also arranged outside the pixel area.

[0144] <10. Tenth Embodiment> In the first embodiment described above, the VSL junction region 314 was located within the pixel region where the pixel circuit 260 was arranged, but the configuration is not limited to this. The solid-state imaging device 200 of this tenth embodiment differs from the first embodiment in that the VSL junction region 314 is located outside the pixel region.

[0145] Figure 27 is a plan view showing an example of the bonding surface of a light-receiving substrate in the tenth embodiment of this technology. The bonding surface of the light-receiving substrate 201 in the tenth embodiment is provided with power line / drive line bonding regions 318 and 319, VSL bonding regions 314 and 315, and a dummy region 321. In addition, the dummy region 321 is positioned below the pixel array section 250 (pixel region) with the light-receiving surface side facing upwards. The configuration of the bonding surface of the circuit board 202 is the same as that of the bonding surface of the light-receiving substrate 201.

[0146] Furthermore, the VSL junction regions 314 and 315 are located outside the pixel region.

[0147] Thus, in the tenth embodiment of this technology, the VSL junction regions 314 and 315 are located outside the pixel region.

[0148] <11. Eleventh Embodiment> In the first embodiment described above, AD conversion was performed for each column, but it is also possible to perform AD conversion for each area consisting of multiple pixel circuits 260. The solid-state imaging device 200 of this eleventh embodiment differs from the first embodiment in that it performs AD conversion for each area.

[0149] Figure 28 shows the configuration of a solid-state imaging device 200 in the eleventh embodiment of this technology. This technology can be applied to stacked imaging devices. In a stacked imaging device, a chip on which a signal processing circuit is formed is used instead of a support substrate for the pixel portion, and the pixel portion is stacked on top of it. This configuration makes it possible to miniaturize the imaging device.

[0150] As shown in the figure, pixels 21 are arranged in a matrix on the light-receiving substrate 10, and a pixel driving circuit 22 is arranged to drive each pixel 21. On the lower substrate 11, ADCs (A / D Converters) 31 are arranged in a matrix at positions corresponding to the pixels 21. In the example shown in the figure, 2 x 2 = 4 pixels are considered as one block (area), and one ADC 31 processes the 4 pixels 21 of one block. In this configuration, the ADCs 31 are operated in parallel, and each ADC 31 performs A / D conversion while scanning the 4 pixels.

[0151] The circuit board 11 also includes an output circuit 32, a sense amplifier 33, a V-scanning circuit 34, a timing generation circuit 35, and a DAC (D / A Converter). The output from the ADC 31 is configured to be output externally via the sense amplifier 33 and the output circuit 32. The processing related to reading from the pixel 21 is performed by the pixel driving circuit 22 and the V-scanning circuit 34, and is controlled by the timing generated by the timing generation circuit 35. The DAC 36 is a circuit that generates a ramp signal.

[0152] The ramp signal is the signal supplied to the comparator of the ADC31. The internal configuration of the ADC31 will be explained with reference to Figure 2. Figure 29 is a block diagram showing the configuration of the ADC31 and one block (area) of pixels 21. The signal from one block of pixels 21, which consists of 4 pixels in a 2x2 arrangement, is compared with the ramp voltage of the ramp signal by the comparator 51 of the ADC31.

[0153] The ramp voltage is a voltage that gradually decreases from a predetermined voltage. The system is configured to invert the output of the comparator 51 when the ramp voltage starts to decrease and a signal from pixel 21 crosses it (when the voltage of the signal from pixel 21 and the ramp voltage become the same). The output of the comparator 51 is input to the latch circuit 52. The latch circuit 52 is input with a code value indicating the time at that time, and the code value when the output of the comparator 51 inverted is stored thereafter. This is the structure in which it is read.

[0154] Figure 30 is a plan view showing an example of the bonding surface of a light-receiving substrate in the eleventh embodiment of this technology. On the bonding surface, the same number of pads as the number of pixels are arranged for each block (area). When 2x2 pixels constitute one area, four pads are arranged. One of these is an electrode pad 431, and the remaining three are dummy pads 441.

[0155] Figure 31 shows the circuit diagram of the imaging device including the ADC31. Figure 3 illustrates the circuits included in the light-receiving substrate 10 and the circuit board 11 shown in Figure 1. The light-receiving substrate 10 contains pixels 21, and its circuit has the configuration shown on the left side of Figure 3. Here, we will explain using a configuration in which four pixels share one FD (Floating Diffusion) as an example.

[0156] The photodiodes (PDs) 101-1 to 101-4, which function as the photoelectric conversion unit, are each connected to transfer transistors (Trf) 102-1 to 102-4. Hereafter, unless it is necessary to distinguish between the photodiodes 101-1 to 101-4 individually, they will simply be referred to as photodiode 101. The same applies to other parts.

[0157] Transfer transistors 102-1 to 102-4 are each connected to a floating diffusion (FD) 103. Transfer transistor 102 converts the signal charge stored by photoelectric conversion in photodiode 101 and transfers it to the floating diffusion 103 at the timing when a transfer pulse is applied.

[0158] The floating diffusion 103 functions as a charge-to-voltage converter that converts signal charge into a voltage signal. The reset transistor (Rst) 104 has its drain electrode connected to the pixel power supply with a power supply voltage Vdd, and its source electrode connected to the floating diffusion 103. Prior to the transfer of signal charge from the photodiode 101 to the floating diffusion 103, the reset transistor 104 applies a reset pulse RST to its gate electrode, resetting the voltage of the floating diffusion 103 to the reset voltage.

[0159] The amplifying transistor (Amp) 105 has its gate electrode connected to the floating diffusion 103 and its drain electrode connected to the pixel power supply with power supply voltage Vdd. The voltage of the floating diffusion 103 after it has been reset by the reset transistor 104 is output as the reset level, and the voltage of the floating diffusion 103 after the signal charge has been transferred by the transfer transistor 102 is output as the signal level.

[0160] The amplifier transistor 105 and the load MOS 121 provided on the lower board 11 act as a source follower, transferring an analog signal representing the voltage of the floating diffusion 103 to the comparator 51 on the lower board 11.

[0161] The comparator 51 can be constructed using a differential amplifier circuit. It comprises a differential transistor pair having transistors 141 and 144, a load transistor pair located on the power supply side having transistors 142 and 143 which serve as the output load for the differential transistor pair, and a current source 145 located on the ground (GND) side which supplies a constant operating current.

[0162] The sources of transistors 141 and 144 are commonly connected to the drains of the transistors in the current source section 145, and the drains (output terminals) of transistors 141 and 144 are connected to the corresponding drains of transistors 142 and 143 in the load transistor pair section.

[0163] The output of the differential transistor pair (the drain of transistor 144 in the illustrated example) passes through buffer 146, undergoes sufficient amplification, and is then output to latch circuit 52.

[0164] The gate (input terminal) of transistor 141 is supplied with the pixel signal transferred from the pixel 21, and the gate (input terminal) of transistor 144 is supplied with the ramp signal from the DAC 36.

[0165] The latch circuit 52 consists of 10 latch rows 161-1 to 161-10. Each of the latch rows 161-1 to 161-10 is input with Code D0 to D9 (hereinafter referred to as Code Value D). These Code Values ​​D0 to D9 are code values ​​that indicate the time at that moment.

[0166] Each latch array 161 is a dynamic circuit for miniaturization. The gate of the transistor 171 that turns each latch array 161 on and off is powered by the output from the comparator 51. In this latch circuit 52, the code value when the output of the comparator 51 is inverted is held, then read out and output to the sense amplifier 33 (Figure 1).

[0167] In this configuration, pixels 21 are arranged on the light-receiving substrate 10, and circuits are arranged on the circuit board 11. The light-receiving substrate 10 and the circuit board 11 can be joined, for example, by a Cu-Cu junction. This Cu-Cu junction can be performed using the technology disclosed in Japanese Patent Application Publication No. 2011-54637, which was previously filed by the present applicant.

[0168] Thus, in the eleventh embodiment of this technology, AD conversion is performed area by area, which improves the image data readout speed compared to the first embodiment, where AD conversion is performed column by column.

[0169] <12. Twelfth Embodiment> In the first embodiment described above, the solid-state imaging device 200 had a two-layer stacked structure in which circuits were arranged on a light-receiving substrate 201 and a circuit board 202, but a three-layer stacked structure can also be used. The solid-state imaging device 200 of this twelfth embodiment differs from the first embodiment in that it has a three-layer stacked structure.

[0170] Figure 32 is an example of a cross-sectional view of a solid-state imaging device 200 in the twelfth embodiment of this technology. In the twelfth embodiment, a memory board 203 is inserted between a light-receiving substrate 201 and a circuit board 202. Dummy pads and electrode pads are used for Cu-Cu connections between the light-receiving substrate 201 and the memory board 203. Memory for holding image data is also arranged on the memory board.

[0171] Thus, in the twelfth embodiment of this technology, a three-layer laminated structure is applied.

[0172] <13. The 13th Embodiment> In the first embodiment described above, the solid-state imaging device 200 had a two-layer stacked structure in which circuits were arranged on a light-receiving substrate 201 and a circuit board 202, but a three-layer stacked structure can also be used. The solid-state imaging device 200 of this twelfth embodiment differs from the first embodiment in that it has a three-layer stacked structure.

[0173] Figure 33 is an example of a cross-sectional view of a solid-state imaging device 200 in the twelfth embodiment of this technology. In the twelfth embodiment, a pixel substrate 204 is inserted between a light-receiving substrate 201 and a circuit board 202. Dummy pads and electrode pads are used for Cu-Cu connections between the pixel substrate 204 and the circuit board 202. The light-receiving substrate 201 is equipped with a photodiode 415, a color filter 413, an on-chip lens 411, and the optical system above it. Various transistors other than the photodiodes in the pixel circuit 260 are arranged on the pixel substrate 204. The photodiodes are connected to transistors and the like via wiring, as illustrated in the figure.

[0174] Thus, in the thirteenth embodiment of this technology, a three-layer laminated structure is applied.

[0175] <14. The 14th Embodiment> In the first embodiment described above, only one vertical drive circuit was placed in the solid-state imaging device 200, but it is also possible to place more vertical drive circuits. The solid-state image sensor 200 of this 14th embodiment differs from the first embodiment in that it has multiple vertical drive circuits.

[0176] Figure 34 is an example of a perspective view of a solid-state imaging device 200 in the 14th embodiment of this technology. The circuit board 202 of the 14th embodiment has vertical drive circuits 211 to 214, a plurality of AD units 243, and a plurality of memory units 244 arranged on it. The surface between the circuit board 201 and the light-receiving substrate 202 represents a bonding surface. The plan view of this bonding surface is the same as that illustrated in Figure 4. Furthermore, the AD unit 243 and the memory unit 244 form a pair of circuit units. As shown in Figure 34, the memory unit 244-a and the AD unit 243-a form a pair of circuit units. Similarly, adjacent circuit units form a pair of AD unit 243-b and memory unit 244-b. The vertical signal line VSL is initially connected to the AD unit. Similar configurations of AD unit 243 and memory unit 244 are illustrated in Figures 36, 38, and 39. In the 14th embodiment, it is possible to arrange other circuit units, such as control circuits or processing circuits (not shown), on the circuit board 202.

[0177] A predetermined number of ADCs are arranged within the AD unit 243. A predetermined number of memory units are arranged in the memory unit 244 to hold the digital signals from the AD unit. Static Random Access Memory (SRAM) or the like is used for these memories.

[0178] As illustrated in Figure 34, by positioning the VSL junction region 314 in the central part of the solid-state imaging device 200, the capacitance difference between the edges and the center can be reduced, and the occurrence of shading can be suppressed. It is also possible to suppress variations in the characteristics of the device. Furthermore, by using four vertical drive circuits, high-speed driving and complex driving can be achieved.

[0179] Figure 35 is a plan view showing another example of the bonding surface of the light-receiving substrate 201 in the 14th embodiment of the present technology. As illustrated in the figure, the central portion may also have VSL bonding regions 314 and 315, with a dummy region 324 placed between them.

[0180] Figure 36 is a perspective view corresponding to Figure 35.

[0181] Figure 37 is a plan view showing another example of the bonding surface of the light-receiving substrate 201 in the 14th embodiment of this technology. As illustrated in the figure, each region of Figure 35 can also be divided into two. For example, between drive line bonding regions 311-1 and 311-2, dummy region 321-1, VSL bonding region 314-1, dummy region 323-1, VSL bonding region 315-1, and dummy region 322-1 can be arranged in this order. Furthermore, between drive line bonding regions 312-1 and 312-2, dummy region 321-2, VSL bonding region 314-2, dummy region 323-2, VSL bonding region 315-2, and dummy region 322-2 can be arranged in this order.

[0182] Figure 38 is a perspective view corresponding to Figure 37.

[0183] Figure 39 is another example of a perspective view of a solid-state imaging device in the 14th embodiment of the present technology. As illustrated in the figure, two vertical drive circuits can also be arranged.

[0184] Here, we will provide additional information regarding the bonding surface on which the dummy pad is placed in the first embodiment. Figure 40 is an enlarged view showing an example of the vicinity of the bonding surface on which the dummy pad is placed in the first embodiment of this technology and in a comparative example. In the figure, a is an enlarged view showing an example of the vicinity of the bonding surface in the first embodiment of this technology, and b is an enlarged view showing an example of the vicinity of the bonding surface in a comparative example. As illustrated in figure a, the dummy pad, like the electrode pad, is formed by breaking through the SiN film 471. The same applies to each embodiment from the second embodiment onward.

[0185] Thus, in the 14th embodiment of this technology, vertical drive circuits 211 to 214 are arranged, enabling high-speed driving and complex driving.

[0186] <15. The 15th Embodiment> In the first embodiment described above, electrode pads were arranged in the pixel array section 250, but electrode pads can also be arranged in areas other than the pixel array section 250. This 15th embodiment differs from the first embodiment in that electrode pads are also arranged in areas other than the pixel array section 250.

[0187] Figure 41 is an example of a cross-sectional view of a solid-state imaging device 200 in the 15th embodiment of this technology. In this 15th embodiment of the solid-state imaging device 200, electrode pads 431 and 432 are also arranged in areas other than the pixel array section 250. For example, signal lines can be drawn out and wired from the pixel array section 250 to an area outside of it.

[0188] Thus, in the 15th embodiment of this technology, electrode pads are also arranged in areas other than the pixel array section 250.

[0189] <16. Embodiment 16> In the first embodiment described above, the solid-state imaging device 200 had a two-layer stacked structure in which circuits were arranged on a light-receiving substrate 201 and a circuit board 202, but a three-layer stacked structure can also be used. The solid-state imaging device 200 of this sixteenth embodiment differs from the first embodiment in that it has a three-layer stacked structure.

[0190] Figure 42 is an example of a cross-sectional view of a solid-state imaging device 200 in the 16th embodiment of this technology. In the 16th embodiment, a memory board 203 is inserted between a light-receiving substrate 201 and a circuit board 202. As illustrated in the figure, the substrates are connected by Cu-Cu connections and TSVs (Through Silicon Vias). For example, the circuit board 202 and the memory board 203 are joined by Cu-Cu connections. The circuit board 202 and the light-receiving substrate 201 are connected by a TSV 481, and the circuit board 202 and the memory board 203 are connected by a TSV 482.

[0191] Figure 43 is another example of a cross-sectional view of the solid-state imaging device 200 in the 16th embodiment of this technology. As illustrated in the figure, the substrates can also be joined using only Cu-Cu connections without using TSV.

[0192] Thus, in the 16th embodiment of this technology, a three-layer laminated structure is applied, and the substrates are joined by TSV or the like.

[0193] <17. Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0194] Figure 44 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0195] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 44, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is also shown, consisting of a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0196] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0197] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0198] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0199] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0200] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0201] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0202] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0203] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0204] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example in Figure 44, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0205] Figure 45 shows an example of the installation position of the imaging unit 12031.

[0206] In Figure 45, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0207] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0208] Figure 45 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0209] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0210] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0211] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0212] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0213] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, the imaging system 100 in Figure 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, noise caused by dark current can be reduced, and a clearer image can be generated, thereby reducing driver fatigue.

[0214] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0215] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0216] Furthermore, this technology can also be configured as follows. (1) A first semiconductor substrate having a plurality of photoelectric conversion units and a first wiring layer, A second semiconductor substrate having a second wiring layer and a signal processing circuit, Equipped with, The first wiring layer comprises a first electrode pad, a first via connected to the first electrode pad, and a second electrode pad. It has, The aforementioned second wiring layer includes a third electrode pad, a fourth electrode pad, and a second via connected to the third electrode pad. It has, The first or second wiring layer has a third via connected to either the second electrode pad or the fourth electrode pad. A portion of the first electrode pad and a portion of the third electrode pad are joined together. A portion of the second electrode pad and a portion of the fourth electrode pad are joined together. The pixel signal generated by at least one of the plurality of photoelectric conversion units is transmitted to the signal processing circuit via the first via, the first electrode pad, the third electrode pad, and the second via. The second electrode pad or the fourth electrode pad connected to the third via is a solid-state image sensor electrically connected to any potential via the third via. (2) The first semiconductor substrate has a transfer transistor and a floating diffusion The solid-state image sensor described in (1) above. (3) The first semiconductor substrate has a reset transistor and an amplification transistor The solid-state image sensor described in (2) above. (4) The signal processing circuit includes an analog-to-digital signal conversion circuit. A solid-state image sensor as described in any of (1) to (3) above. (5) The first wiring layer has the third via connected to the second electrode pad, The solid-state image sensor according to any one of (1) to (4), wherein the second wiring layer has a fourth via connected to the fourth electrode pad. (6) A plurality of first circuits provided on the first semiconductor substrate, among the first and second semiconductor substrates joined at a junction surface in which atoms terminating silicon dangling bonds are nearby, A second circuit provided on the second semiconductor substrate, A first via connecting a portion of the plurality of first circuits to a predetermined bonding region within the bonding surface, A second via connecting the second circuit and the junction region, A third via connects the remaining parts of the plurality of first circuits to a dummy region within the junction surface that does not correspond to the junction region. A solid-state imaging device equipped with the following. (7) An electrode pad is placed in the bonding region, A dummy pad is placed in the aforementioned dummy area. The first via connects a portion of the plurality of first circuits and the junction region via the electrode pad. The third via connects the remainder of the plurality of first circuits to the dummy area via the dummy pad. The solid-state imaging device described in (6) above. (8) A predetermined number of the first vias are connected to the electrode pad, The dummy pad is connected to a number of the third vias that is different from the predetermined number. The solid-state imaging device described in (7) above. (9) A predetermined number of the first vias are connected to the electrode pad, The dummy pad is connected to the predetermined number of the third vias. The solid-state imaging device described in (7) above. (10) The dummy pad includes a first dummy pad to which the third via is not connected and a second dummy pad to which the third via is connected. The solid-state imaging device described in (7) above. (11) The dummy pad includes first and second dummy pads to which different numbers of the third vias are connected. The solid-state imaging device described in (7) above. (12) The cross-sectional area of ​​the third via is different from the cross-sectional area of ​​the first via. A solid-state imaging device as described in any of (7) to (11) above. (13) The cross-sectional shape of the first and third vias is circular or rectangular. A solid-state imaging device as described in any of (7) to (12) above. (14) The third via connects the remainder of the plurality of first circuits to the dummy region via a predetermined medium for transmitting the atoms and the dummy pad. A solid-state imaging device as described in any of (7) to (13) above. (15) Each of the plurality of first circuits is a pixel circuit that generates a predetermined pixel signal, The second circuit is a circuit that processes the pixel signal, The first semiconductor substrate is a light-receiving substrate. A solid-state imaging device as described in any of (7) to (14) above. (16) Further comprising a fourth via, The second semiconductor substrate is a circuit board, The dummy pad includes a light-receiving dummy pad placed on the light-receiving substrate and a circuit-side dummy pad placed on the circuit board. The third via is connected to the light-receiving dummy pad, The fourth via is connected to the circuit-side dummy pad. The solid-state imaging device described in (15) above. (17) The second circuit is a pixel circuit that generates a predetermined pixel signal, Each of the plurality of first circuits is a circuit that processes the pixel signal, The first semiconductor substrate is a circuit board. The solid-state imaging device described in (6) above. (18) Further comprising a fourth via connected to the third via without a dummy pad, The first and second vias are connected without electrode pads. The solid-state imaging device described in (6) above. (19) The bonding region has a silicon nitride film and an electrode pad that penetrates the silicon nitride film, The dummy region is formed with the silicon nitride film and a dummy pad that penetrates the silicon nitride film. The solid-state imaging device described in (6) above. (20) A plurality of first circuits provided on the first semiconductor substrate, among first and second semiconductor substrates which are joined at a junction surface in which atoms terminating silicon dangling bonds are nearby, A second circuit provided on the second semiconductor substrate, A first via connecting a portion of the plurality of first circuits to a predetermined bonding region within the bonding surface, A second via connecting the second circuit and the junction region, A third via connecting the remaining parts of the plurality of first circuits to a dummy region within the junction surface that does not correspond to the junction region, A signal processing circuit that performs predetermined signal processing on the signal generated by the second circuit, An imaging system equipped with the following features. [Explanation of Symbols]

[0217] 100 Imaging Systems 110 Optics Department 120 DSP circuits 130 Display section 140 Operation section 150 bus 160 frames memory 170 Storage section 180 Power supply section 200 Solid State Imaging Devices 201 Light-receiving substrate 202 Circuit board 210 Vertical drive circuit 220 Timing control circuit 231 North side horizontal drive circuit 232 South side horizontal drive circuit 241 North-side Column Signal Processing Circuit 242 South-side Column Signal Processing Circuit 250 Pixel Array Section 260 Pixel Circuit 261 Photoelectric Conversion Element 262 Transfer Transistor 263 Reset Transistor 264 Floating Diffusion Layer 265 Amplification Transistor 266 Selection Transistor 270 Power Supply Circuit 280 Output Section 311, 312, 311-1, 311-2, 312-1, 312-2 Drive Line Bonding Region 313, 316 Power Line Bonding Region 314, 315, 314-1, 314-2, 315-1, 315-2 VSL Bonding Region 321~323, 321-1, 321-2, 322-1, 322-2, 323-1, 323-2Dummy Region 411, 412 On-chip Lens 413, 414 Color Filter 415, 416 Photodiode 417, 418, 455, 456 Transistor 420 Wiring Layer 421, 422, 451, 452 Metal Wiring 423, 424, 453, 454 Via 425 Cavity 431, 432 Electrode Pad 441~446 Dummy Pad 450 Wiring Layer 461, 462 Subsequent-stage Circuit 471, 472 SiN (Silicon Nitride) Film 12031 Imaging Section

Claims

1. A first semiconductor substrate having multiple pixel circuits, each including a photoelectric conversion unit, and a first wiring layer, A second semiconductor substrate having a second wiring layer and a signal processing circuit, Equipped with, The first and second semiconductor substrates are joined at a junction surface that contains atoms in the vicinity that terminate the silicon dangling bond. The first wiring layer comprises a first electrode pad, a first via connected to the first electrode pad, and a first dummy pad. It has, The second wiring layer comprises a second electrode pad, a second dummy pad, and a second via connected to the second electrode pad. It has, The first wiring layer further comprises a cavity and a third via. A portion of the first electrode pad and a portion of the second electrode pad are joined to each other. A portion of the first dummy pad and a portion of the second dummy pad are joined together. The pixel signals generated by a portion of the plurality of pixel circuits are transmitted to the signal processing circuit via the first via, the first electrode pad, the second electrode pad, and the second via. The remaining parts of the plurality of pixel circuits are connected to one end of the third via, The other end of the third via is connected to one end of the cavity, The other end of the cavity is connected to the first dummy pad. Solid-state image sensor.

2. Each of the aforementioned plurality of pixel circuits has a transfer transistor and a floating diffusion. The solid-state image sensor according to claim 1.

3. Each of the aforementioned plurality of pixel circuits has a reset transistor and an amplification transistor. The solid-state image sensor according to claim 2.

4. The signal processing circuit includes an analog-to-digital signal conversion circuit. The solid-state image sensor according to claim 1.

5. A first semiconductor substrate having multiple pixel circuits, each including a photoelectric conversion unit, and a first wiring layer, A second semiconductor substrate having a second wiring layer and a signal processing circuit, Equipped with, The first and second semiconductor substrates are joined at a junction surface that contains atoms in the vicinity that terminate the silicon dangling bond. The first wiring layer comprises a first electrode pad, a first via connected to the first electrode pad, and a first dummy pad. It has, The second wiring layer comprises a second electrode pad, a second dummy pad, and a second via connected to the second electrode pad. It has, The first wiring layer further comprises a cavity and a third via. A portion of the first electrode pad and a portion of the second electrode pad are joined to each other. A portion of the first dummy pad and a portion of the second dummy pad are joined together. The pixel signals generated by a portion of the plurality of pixel circuits are transmitted to the signal processing circuit via the first via, the first electrode pad, the second electrode pad, and the second via. The remaining parts of the plurality of pixel circuits are connected to one end of the third via, The other end of the third via is connected to one end of the cavity, The other end of the cavity is connected to the first dummy pad. Solid-state imaging device.

6. The number of the first vias is different from the number of the third vias. The solid-state imaging apparatus according to claim 5.

7. The first dummy pad includes a dummy pad to which the other end of the cavity is not connected and a dummy pad to which the other end of the cavity is connected. The individual imaging device according to claim 5.

8. The first dummy pad includes a plurality of dummy pads to which different numbers of the third vias are connected. The solid-state imaging apparatus according to claim 5.

9. The cross-sectional area of ​​the third via is different from the cross-sectional area of ​​the first via. The solid-state imaging apparatus according to claim 5.

10. The cross-sectional shapes of the first and third vias are circular or rectangular. The solid-state imaging apparatus according to claim 5.

11. The signal processing circuit includes an analog-to-digital converter. The first semiconductor substrate is a light-receiving substrate. The solid-state imaging apparatus according to claim 5.

12. A silicon nitride film is formed on the bonding surface. The first and second electrode pads penetrate the silicon nitride film, The first and second dummy pads penetrate the silicon nitride film. The solid-state imaging apparatus according to claim 5.

13. A first semiconductor substrate having multiple pixel circuits, each including a photoelectric conversion unit, and a first wiring layer, A second semiconductor substrate having a second wiring layer and a signal processing circuit, Equipped with, The first and second semiconductor substrates are joined at a junction surface that contains atoms in the vicinity that terminate the silicon dangling bond. The first wiring layer comprises a first electrode pad, a first via connected to the first electrode pad, and a first dummy pad. It has, The second wiring layer comprises a second electrode pad, a second dummy pad, and a second via connected to the second electrode pad. It has, The first wiring layer further comprises a cavity and a third via. A portion of the first electrode pad and a portion of the second electrode pad are joined to each other. A portion of the first dummy pad and a portion of the second dummy pad are joined together. The pixel signals generated by a portion of the plurality of pixel circuits are transmitted to the signal processing circuit via the first via, the first electrode pad, the second electrode pad, and the second via. The remaining parts of the plurality of pixel circuits are connected to one end of the third via, The other end of the third via is connected to one end of the cavity, The other end of the cavity is connected to the first dummy pad. Imaging system.

Images