Imaging device

Abstract

The present invention provides an imaging device that can suppress the formation of charge transfer barriers within a pixel. [Solution] An imaging device, a semiconductor layer, and a 2 × 10 15 / cm 3 ~1 × 10 16 / cm 3 The device comprises a plurality of photoelectric conversion units containing a first conductivity type impurity of a certain concentration, and element isolation units provided between a plurality of adjacent photoelectric conversion units or inside each photoelectric conversion unit. In a cross-section of a semiconductor layer cut parallel to a first direction in which light is incident, each of the plurality of photoelectric conversion units has a taper on its side surface such that the width in the second direction perpendicular to the first direction narrows as it moves from the first surface of the semiconductor layer on the side opposite to the side in which light is incident to the second surface of the semiconductor layer on the side in which light is incident.

Description

[Technical Field]

[0001] This disclosure relates to an imaging device. [Background technology]

[0002] Imaging devices such as back-illuminated CIS (CMOS (Complementary Metal Oxide Semiconductor) Image Sensor) form a potential profile based on the gradient of impurity concentration in the photodiode of the pixel, and perform charge transfer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-46719 [Patent Document 2] Japanese Patent Publication No. 2023-79834 [Patent Document 3] Japanese Patent Publication No. 2023-24342 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, the potential profile based on impurity concentration had the problem of creating a potential barrier in charge transfer. Furthermore, it was difficult to inject impurities deep into the semiconductor layer of the pixel, and this also resulted in significant damage to the semiconductor layer.

[0005] This technology was developed in consideration of these challenges and provides an imaging device that can suppress the formation of charge transfer barriers within pixels. [Means for solving the problem]

[0006] One aspect of this disclosure includes an imaging device, a semiconductor layer, and a 2 × 10 15 / cm 3~1×10 16 / cm 3 A plurality of photoelectric conversion units including a first conductive type impurity with a concentration of 16 / cm 3 , and an element isolation part provided between a plurality of mutually adjacent photoelectric conversion units or inside each photoelectric conversion unit. In a cross section of the semiconductor layer cut parallel to the first direction in which light is incident, each of the plurality of photoelectric conversion units has a taper on its side surface such that the width in the second direction perpendicular to the first direction becomes narrower as it goes from the first surface of the semiconductor layer on the side opposite to the light incident side to the second surface of the semiconductor layer on the light incident side.

[0007] In a cross section of the semiconductor layer cut parallel to the first direction, the element isolation part has a taper on its side surface such that the width in the second direction becomes wider as it goes from the first surface to the second surface.

[0008] The plurality of photoelectric conversion units have a substantially uniform impurity concentration between the first surface and the second surface. [[ID=1)3]]

[0009] The first direction is the charge transfer direction in the plurality of photoelectric conversion units.

[0010] The plurality of photoelectric conversion units have the shape of a truncated cone, a truncated elliptical cone, or a truncated pyramid.

[0011] The side surfaces of the plurality of photoelectric conversion units have a taper angle of 2 degrees to 8 degrees from the first direction.

[0012] The taper angle of the side surfaces of the plurality of photoelectric conversion units changes in the middle of the side surface.

[0013] The side surfaces of the plurality of photoelectric conversion units are bent in the middle of the side surface so as to protrude toward the element isolation part.

[0014] The side surfaces of the plurality of photoelectric conversion units include a first side surface part extending in the first direction and a second side surface part inclined with respect to the first direction.

[0015] In a cross section of the semiconductor layer cut parallel to the first direction, the taper angles of the side surfaces on both sides of the plurality of photoelectric conversion units are different from each other.

[0016] The imaging device is provided on the first surface side of the semiconductor layer and further comprises a first diffusion layer containing a first conductivity type impurity at a higher concentration than the photoelectric conversion section. The taper angle of the first side surface, which is relatively far from the first diffusion layer, is greater than the taper angle of the second side surface, which is relatively close to the first diffusion layer.

[0017] The element isolation section is provided inside each of the multiple photoelectric conversion sections, and in a cross-section of the semiconductor layer cut parallel to the first direction, the element isolation section located inside the multiple photoelectric conversion sections has a taper on its side surface such that the width in the second direction increases as you move from the first surface to the second surface.

[0018] The impurity concentrations in the multiple photoelectric conversion sections decrease as you move from the first surface to the second surface.

[0019] Each of the multiple photoelectric conversion sections has a first side surface extending in a first direction and a second side surface inclined with respect to the first direction. The impurity concentration of each of the multiple photoelectric conversion sections gradually decreases from the first surface to the second surface up to the position of the first side surface, and is substantially uniform from the position of the first side surface to the second surface.

[0020] The imaging device is provided between multiple photoelectric conversion units and element isolation units and further comprises a first semiconductor region containing a second conductivity type impurity.

[0021] The imaging device further comprises a first diffusion layer provided on the first surface side of the semiconductor layer and containing a first conductivity type impurity at a higher concentration than the photoelectric conversion section, a second semiconductor region provided on the first surface side of the semiconductor layer and containing a second conductivity type impurity, and a first transistor provided between the first diffusion layer and the second semiconductor region.

[0022] The element isolation section penetrates between the first and second surfaces of the semiconductor layer.

[0023] The imaging device is provided on the second surface side of the semiconductor layer and further comprises a third semiconductor region containing a second conductivity type impurity, while the element isolation section is provided from the first surface of the semiconductor layer to the third semiconductor region. [Brief explanation of the drawing]

[0024] [Figure 1] A block diagram showing an example configuration of an imaging device according to the first embodiment. [Figure 2] A conceptual diagram showing an example of an imaging device in which semiconductor chips for the pixel region and semiconductor chips for the processing circuit are stacked. [Figure 3] A plan view showing an example of the configuration of a single pixel according to the first embodiment. [Figure 4] A cross-sectional view showing an example of the configuration of a single pixel according to the first embodiment. [Figure 5] A plan view showing an example of the configuration of a single pixel according to a modification of the first embodiment. [Figure 6] A cross-sectional view showing an example of the configuration of a single pixel according to a modification of the first embodiment. [Figure 7] A diagram showing an example of the planar shape of the photoelectric conversion section. [Figure 8] A diagram showing an example of the planar shape of the photoelectric conversion section. [Figure 9] A diagram showing an example of the planar shape of the photoelectric conversion section. [Figure 10] A diagram showing an example of the planar shape of the photoelectric conversion section. [Figure 11] A graph showing the relationship between the taper angle of the photoelectric conversion section and the potential of the photoelectric conversion section. [Figure 12] A graph showing the relationship between the impurity concentration in the photoelectric conversion section and the potential of the photoelectric conversion section. [Figure 13] A cross-sectional view showing an example of the configuration of a single pixel according to the second embodiment. [Figure 14] A cross-sectional view showing an example of the configuration of a single pixel according to the third embodiment. [Figure 15] A cross-sectional view showing an example of the configuration of a single pixel according to the fourth embodiment. [Figure 16] A cross-sectional view showing an example of the configuration of two adjacent pixels according to the fifth embodiment. [Figure 17] A schematic plan view showing an example of the configuration of two adjacent pixels according to the fifth embodiment. [Figure 18] A schematic plan view showing an example of the configuration of two adjacent pixels according to the fifth embodiment. [Figure 19]A cross-sectional view showing an example of the configuration of two adjacent pixels according to a modification of the fifth embodiment. [Figure 20] A schematic plan view showing an example of the configuration of two adjacent pixels according to a modification of the fifth embodiment. [Figure 21] A schematic plan view showing an example of the configuration of two adjacent pixels according to a modification of the fifth embodiment. [Figure 22] A cross-sectional view showing an example of the configuration of a single pixel according to the sixth embodiment. [Figure 23] A schematic plan view showing an example of the configuration of one adjacent pixel according to the sixth embodiment. [Figure 24] A cross-sectional view showing an example of the configuration of a single pixel according to the seventh embodiment. [Figure 25] A schematic plan view showing an example of the configuration of one adjacent pixel according to the seventh embodiment. [Figure 26] A cross-sectional view showing an example of the configuration of two pixels according to the eighth embodiment. [Figure 27] A schematic plan view showing an example configuration of four adjacent pixels according to the eighth embodiment. [Figure 28] A cross-sectional view showing an example of the configuration of a single pixel according to the ninth embodiment. [Figure 29] A cross-sectional view showing an example of the configuration of a single pixel according to the 10th embodiment. [Figure 30] A cross-sectional view showing an example of the configuration of a single pixel according to the 11th embodiment. [Figure 31] A block diagram showing an example of a general configuration of a vehicle control system. [Figure 32] An explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit. [Modes for carrying out the invention]

[0025] The following describes specific embodiments of this technology with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0026] (First Embodiment) Figure 1 is a block diagram showing an example configuration of the imaging device 1 according to the first embodiment. The imaging device 1 in this embodiment is, for example, a back-illuminated CIS (CMOS (Complementary Metal Oxide Semiconductor) Image Sensor). However, the imaging device 1 in this embodiment may also be a front-illuminated CIS.

[0027] The imaging device 1 comprises a pixel area 3, a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

[0028] Each pixel 2 consists of a photoelectric conversion unit made of a photodiode and a plurality of pixel transistors, which are arranged regularly in a two-dimensional array on the substrate 11. The pixel transistors constituting each pixel 2 may consist of four MOS transistors: a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor, or they may consist of three transistors excluding the selection transistor.

[0029] The pixel region 3 has a plurality of pixels 2 arranged regularly in a two-dimensional array on a substrate 11 (for example, a silicon substrate). The pixel region 3 consists of an effective pixel region that actually receives light, amplifies the signal charge generated by photoelectric conversion and reads it out to the column signal processing circuit 5, and a black reference pixel region (not shown) that outputs an optical black that serves as a reference for the black level. The black reference pixel region is usually formed on the outer periphery of the effective pixel region.

[0030] The control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The clock signals and control signals generated by the control circuit 8 are input to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0031] The vertical drive circuit 4 is composed of, for example, a shift register, and sequentially selects and scans each pixel 2 of the pixel region 3 vertically in row by row. As a result, the pixel signal based on the signal charge generated in the photodiode of each pixel 2 according to the amount of light received is transmitted to the column signal processing circuit 5 through the vertical signal line.

[0032] The column signal processing circuit 5 is arranged, for example, for each column of pixels 2, and performs signal processing such as noise reduction, AD (Analogue-to-Digital) conversion, and signal amplification on the signal output from one row of pixels 2 for each pixel column using the signal from the black reference pixel area. The black reference pixel area is not shown, but is formed around the effective pixel area. A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

[0033] The horizontal drive circuit 6 is composed of, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses, thereby sequentially selecting each of the column signal processing circuits 5 and causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 10.

[0034] The output circuit 7 processes the signals that are sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal lines 10 and outputs the results.

[0035] The imaging device 1 shown in Figure 1 may be configured as a single semiconductor chip, or it may be configured as multiple semiconductor chips. When the imaging device 1 is configured as multiple semiconductor chips, the pixel area 3 and the other processing circuits may be formed as separate semiconductor chips 511 and 512, respectively, and semiconductor chip 511 and semiconductor chip 512 may be stacked.

[0036] For example, Figure 2 is a conceptual diagram showing an example of an imaging device 1 in which a semiconductor chip 511 for the pixel region 3 and a semiconductor chip 512 for processing circuits (vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, output circuit 7, control circuit 8) are stacked. As shown in Figure 2, the imaging device 1 is composed of two stacked semiconductor chips 511 and 512. Note that the number of stacked semiconductor chips may be three or more.

[0037] The semiconductor chip 511 includes a pixel region 3 formed on a semiconductor substrate. The semiconductor chip 512 includes an ADC group 105, a logic circuit 516, and a peripheral circuit 517 formed on another semiconductor substrate. The logic circuit 516 and peripheral circuit 517 constitute processing circuits such as a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

[0038] Each pixel in the pixel region 3 of semiconductor chip 511 and the elements of the processing circuit of semiconductor chip 512 may be electrically connected using through-electrodes such as TSVs (Through Silicon Vias) provided in via regions 513 and 514. Alternatively, both semiconductor chips may be bonded together so that the wiring of semiconductor chip 511 and the wiring of semiconductor chip 512 are in contact (Cu-Cu junction). Furthermore, although not shown, the pixel region 3 and a part of the processing circuit (vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, output circuit 7, control circuit 8) may be configured as a single semiconductor chip 511, and the remaining components may be configured as other semiconductor chips 512.

[0039] Figure 3 is a plan view showing an example of the configuration of one pixel 2 according to the first embodiment. Figure 4 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the first embodiment. Figure 3 shows the plane of pixel 2 as seen from the first surface F1 side. Figure 4 shows a cross-section along line 4-4 in Figure 3.

[0040] The pixel 2 of the first embodiment is provided in a semiconductor layer (epitaxial layer) EPI. The semiconductor layer EPI may be, for example, a semiconductor substrate such as a silicon substrate, or an epitaxial layer formed on a semiconductor substrate. The semiconductor layer EPI contains, for example, N-type impurities (for example, phosphorus, arsenic). The impurity concentration of the semiconductor layer EPI is, for example, 2×10 15 / cm 3 ~1×10 16 / cm 3 . As shown in FIG. 4, the semiconductor layer includes a first surface F1 and a second surface F2 on the side opposite to the first surface F1. The second surface F2 (back surface) serves as the light incident surface.

[0041] The pixel 2 includes a photoelectric conversion part PD, element isolation parts TI, STI, a floating layer FD, transistors Tr1 to Tr3, a pinning layer PN, a well layer PW, and a well contact CNPW.

[0042] The photoelectric conversion part PD is provided in the semiconductor layer EPI. The photoelectric conversion part PD is composed of, for example, an N-type semiconductor layer. The photoelectric conversion part PD has a substantially uniform impurity concentration between the first surface F1 and the second surface F2. The impurity concentration of the photoelectric conversion part PD is the same as that of the semiconductor layer EPI, and is, for example, 2×10 15 / cm 3 ~1×10 16 / cm 3 . That is, no impurities are intentionally introduced into the photoelectric conversion part PD.

[0043] The photoelectric conversion part PD generates charges (for example, electrons) according to the amount of light incident from the second surface F2 side. The photoelectric conversion part PD moves the generated charges to the first surface F1 side by potential (electric potential) and accumulates them in the floating layer FD. The charge transfer direction in the photoelectric conversion part PD is the -Z direction. The charges accumulated in the floating layer FD are transferred as pixel signals to the vertical signal line 9 in FIG. 1 via pixel transistors such as transistor Tr1. This pixel signal is AD-converted by the ADC group 105 in the column signal processing circuit 5 or subjected to CDS (Correlated Double Sampling) processing and then output to the outside.

[0044] As shown in Figure 4, the photoelectric conversion unit PD has a taper on its side surface. In a cross-section of the photoelectric conversion unit PD cut parallel to the first direction (-Z direction) in which light is incident, the width Wpd1 in the X or Y direction perpendicular to the Z direction narrows as you move from the first surface F1 to the second surface F2. That is, the photoelectric conversion unit PD is narrowest on the side of the second surface F2 in which light is incident, and gradually widens as you approach the side of the first surface F1 where the floating layer FD is provided. As a result, the photoelectric conversion unit PD can form a potential gradient in the Z direction inside itself. The photoelectric conversion unit PD can move charge from the second surface F2 to the first surface F1 in the -Z direction by this potential gradient. The side surface of the photoelectric conversion unit PD according to this embodiment is substantially flat, and the taper angle θ is substantially constant.

[0045] The element isolation sections TI and STI are provided between a plurality of adjacent photoelectric conversion sections PD. The element isolation sections TI and STI are provided so as to penetrate the semiconductor layer EPI between the first surface F1 and the second surface F2. That is, the element isolation sections TI and STI are provided as FTI (Full Trench Isolation). The element isolation sections TI and STI are made of an insulating material such as a silicon oxide film.

[0046] The element isolation section TI is provided from the second surface F2 to the element isolation section STI on the first surface F1 side. The element isolation section TI electrically isolates the photoelectric conversion section PD between adjacent pixels 2. The element isolation section TI has a taper on its side surface. In a cross-section cut parallel to the Z direction, the width Wti1 in the X or Y direction of the element isolation section TI widens from the first surface F1 to the second surface F2. That is, the element isolation section TI is widest on the second surface F2 side and gradually narrows as it approaches the first surface F1 side. The side surfaces of the element isolation section TI face the side surfaces of the photoelectric conversion section PD, are arranged alternately in the X or Y direction, and have opposite tapers.

[0047] The element isolation section STI is provided on the first surface F1 side and extends from the first surface F1 to the element isolation section TI. The element isolation section STI electrically isolates the well layers PW of adjacent pixels 2. Since the element isolation section STI is formed from the first surface F1, the taper of its side surface has an inclination in the opposite direction to that of the element isolation section TI.

[0048] The pinning layer PN, which serves as the first semiconductor region, is provided between the photoelectric conversion unit PD and the device isolation unit TI. The pinning layer PN contains a P-type impurity (e.g., boron). The pinning layer PN suppresses the generation of charge from crystal defects at the interface between the photoelectric conversion unit PD and the device isolation unit TI. This suppresses the generation of dark current.

[0049] The well layer PW is provided on the first surface F1 side of the semiconductor layer EPI and is a diffusion layer containing P-type impurities. The well layer PW is provided to electrically isolate transistors Tr2 and Tr3 and the floating layer FD from the photoelectric conversion unit PD. As shown in Figure 3, in a plan view taken in the Z direction from the first surface F1 side, the well layer PW is provided so as to overlap the photoelectric conversion unit PD. Transistors Tr2 and Tr3 are also provided on the well layer PW.

[0050] The well contact CNPW shown in Figure 3 is provided to obtain an electrical connection to the well layer PW. The well contact CNPW has a P layer with a higher impurity concentration than the well layer PW. + It is a type of diffusion layer.

[0051] The floating layer FD, which serves as the first diffusion layer, is provided on the first surface F1 side of the semiconductor layer EPI, N + This is a diffusion layer containing N-type impurities. The floating layer FD is located within the well layer PW and has a higher N-type impurity concentration than the photoelectric conversion section PD. The floating layer FD is provided to accumulate the charge generated in the photoelectric conversion section PD. As shown in Figure 3, in a plan view from the first surface F1 side, the floating layer FD is located at the corners of the pixel 2 and the well layer PW.

[0052] The first transistor, Tr1, is located on the first surface F1 side of the semiconductor layer EPI. Transistor Tr1 is located between the floating layer FD and the well layer PW. Transistor Tr1 is connected between the floating layer FD and the gate electrode of transistor Tr3, transferring the charge from the floating layer FD to the gate electrode of transistor Tr3. This causes transistor Tr3 to become conductive according to the pixel signal, enabling it to transmit the amplified pixel signal to the vertical signal line 9. Transistor Tr2 resets pixel 2 by discharging the charge from the photoelectric conversion unit PD, the floating layer FD, and the gate electrode of transistor Tr3. The arrangement of transistors Tr1 to Tr3 is as shown in Figure 3.

[0053] Figure 5 is a plan view showing an example of the configuration of one pixel 2 according to a modification of the first embodiment. Figure 6 is a cross-sectional view showing an example of the configuration of one pixel 2 according to a modification of the first embodiment. Figure 5 shows the plane of pixel 2 as seen from the first surface F1 side. Figure 6 shows a cross-section along line 6-6 in Figure 5.

[0054] In this modified version of pixel 2, a well layer PW is provided as a third semiconductor region instead of the element isolation region STI. The well layer PW is, for example, a diffusion layer containing P-type impurities. The element isolation region TI is provided from the second surface F2 to the well layer PW. The well layer PW is provided together with the element isolation region TI as an element isolation region. That is, in this modified version, the element isolation region TI is provided as a DTI (Deep Trench Isolation).

[0055] In this modified example, the pinning layer PN2 is provided on the first surface F1 side of the semiconductor layer EPI, thereby suppressing the generation of charge from crystal defects on the first surface F1. The pinning layer PN1 may be the same as the pinning layer PN in the first embodiment.

[0056] Other components of this modified example may be the same as those of the first embodiment. Note that transistors Tr2 and Tr3 are located in other regions of the well layer PW, which are not shown in Figures 5 and 6.

[0057] As shown in Figure 6, the photoelectric conversion unit PD has a taper on its side surface, similar to that of the first embodiment. This allows the photoelectric conversion unit PD to form a potential gradient in the Z direction within itself. The photoelectric conversion unit PD can move charge from the second surface F2 to the first surface F1 in the -Z direction by this potential gradient.

[0058] Figures 7 to 10 show examples of the planar shape of the photoelectric conversion unit PD according to the first embodiment. In a planar view from the Z direction, the photoelectric conversion unit PD may be approximately square, as shown in Figure 7, or approximately rectangular, as shown in Figure 8. In this case, the photoelectric conversion unit PD has the shape of a truncated square pyramid. The photoelectric conversion unit PD may also be approximately circular, as shown in Figure 9, or approximately elliptical, as shown in Figure 10. In this case, the photoelectric conversion unit PD has the shape of a truncated cone or an elliptical truncated pyramid. The planar shape of the photoelectric conversion unit PD may be arbitrary and may be other polygons. In this case, the photoelectric conversion unit PD may have the shape of a truncated polygonal pyramid, for example.

[0059] Next, the taper angle θ of the photoelectric conversion unit PD and the impurity concentration of the photoelectric conversion unit PD according to the first embodiment will be described.

[0060] Figure 11 is a graph showing the relationship between the taper angle θ of the photoelectric conversion unit PD and the potential (electric potential) of the photoelectric conversion unit PD. The taper angle θ represents the inclination angle of the side surface of the photoelectric conversion unit PD, which is inclined from the Z direction, as shown in Figure 4. The vertical axis represents the potential of the photoelectric conversion unit PD. The horizontal axis represents the position of the photoelectric conversion unit PD in the Z direction (first surface F1 to second surface F2). In this simulation, the impurity concentration of the photoelectric conversion unit PD is 1 × 10⁻⁶. 16 cm -3 It was set to be uniform.

[0061] When the taper angle θ is 0 degrees, a flat region with almost no potential gradient exists. A small potential gradient makes it difficult for electrons to move due to the electric field, preventing them from reaching the stray layer FD and resulting in transfer failure. Therefore, a taper angle θ of 0 degrees is undesirable.

[0062] On the other hand, when the taper angle θ is between 2 and 8 degrees, a potential gradient is obtained in the Z direction, allowing for a faster charge transfer rate. Furthermore, the amount of charge accumulated in the floating layer FD increases. Therefore, a taper angle θ between 2 and 8 degrees is preferable. Within the range of 2 to 8 degrees, the larger the taper angle θ, the steeper the potential gradient becomes. However, when the taper angle θ exceeds 8 degrees, the potential gradient on the second surface F2 side approaches flatness. Therefore, it is preferable to limit the taper angle θ to 8 degrees. In other words, a taper angle θ greater than 8 degrees is undesirable.

[0063] Thus, according to this embodiment, even if the impurity concentration of the photoelectric conversion unit PD is uniform, an appropriate potential gradient can be formed in the photoelectric conversion unit PD by tapering the side surface of the photoelectric conversion unit PD. The taper angle θ of the side surface of the photoelectric conversion unit PD is preferably 2 to 8 degrees.

[0064] Figure 12 is a graph showing the relationship between the impurity concentration of the photoelectric conversion unit (PD) and the potential (electric potential) of the photoelectric conversion unit (PD). The impurity concentration is, for example, N-type impurities such as phosphorus or arsenic. The vertical axis represents the potential of the photoelectric conversion unit (PD). The horizontal axis represents the position of the photoelectric conversion unit (PD) in the Z direction (first surface F1 to second surface F2). In this simulation, the taper angle θ of the side surface of the photoelectric conversion unit (PD) was set to 2 degrees.

[0065] The impurity concentration is 1 × 10 14 cm -3 and 1 × 10 15 cm -3 In some cases, there exists a flat region with almost no potential gradient. Therefore, 1 × 10 15 cm -3 The following impurity concentrations are undesirable.

[0066] On the other hand, the impurity concentration is 2 × 10 15 cm -3In the above case, a potential gradient in the Z direction is obtained, and the charge transfer rate can be increased. Also, the amount of charge accumulated in the floating layer FD increases. Therefore, the impurity concentration is 2 × 10⁻⁶. 15 cm -3 It is preferable that the above conditions are met.

[0067] However, the impurity concentration is 2 × 10 16 cm -3 Beyond this point, the potential gradient on the first surface F1 side approaches flatness. Therefore, the impurity concentration of the photoelectric conversion section PD is 2 × 10 16 cm -3 It is preferable to set the upper limit to 2 × 10⁻¹⁰. That is, the impurity concentration of the photoelectric conversion unit PD is 2 × 10⁻¹⁰. 15 cm -3 ~2×10 16 cm -3 It is preferable that the impurity concentration of the photoelectric conversion unit PD be within the range of 2 × 10. 16 cm -3 Even with the above, a potential gradient can be formed by increasing the taper angle θ on the side surface of the photoelectric conversion unit PD. Therefore, the upper limit of the impurity concentration of the photoelectric conversion unit PD is 2 × 10 16 cm -3 Not limited to that.

[0068] (Second Embodiment) Figure 13 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the second embodiment. In the second embodiment, the taper angle of the side surface of the photoelectric conversion unit PD changes midway along the side surface. For example, in the second embodiment, the side surface of the photoelectric conversion unit PD is bent so as to protrude toward the element isolation unit TI. The taper angle θ1 of the side surface Fs1 of the photoelectric conversion unit PD that is close to the first surface F1 is different from the taper angle θ2 of the side surface Fs2 that is close to the second surface F2. The taper angle θ2 is larger than the taper angle θ1. That is, as you go from the first surface F1 to the second surface F2 in the +Z direction, the taper angle increases and the side surface of the photoelectric conversion unit PD becomes steeper.

[0069] The potential gradient of the photoelectric conversion unit PD on the second surface F2 side, where light is incident, becomes steeper, and the potential gradient becomes gentler towards the first surface F1 side. This allows charges generated far from the floating layer FD to be quickly moved closer to the floating layer FD.

[0070] By adjusting the taper angles θ1 and θ2, the potential gradient of the photoelectric conversion unit PD can be controlled. Therefore, charge can be efficiently transferred to the floating layer FD in the photoelectric conversion unit PD.

[0071] The other configurations of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment. The side surface of the photoelectric conversion unit PD may be bent at multiple points. This allows for more precise setting of the potential gradient of the photoelectric conversion unit PD.

[0072] (Third embodiment) Figure 14 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the third embodiment. The third embodiment is the same as the second embodiment in that the taper angle of the side surface of the photoelectric conversion unit PD changes midway along the side surface. However, in the third embodiment, the side surface Fs1 of the photoelectric conversion unit PD that is close to the first surface F1 does not have a taper and extends in the Z direction (perpendicular to the first and second surfaces F1 and F2). That is, the taper angle θ1 is approximately 0 degrees. The taper angle θ2 of the side surface Fs2 that is close to the second surface F2 is greater than the taper angle θ1 (θ1 = approximately 0). In other words, the photoelectric conversion unit PD includes a side surface Fs1 that extends in the Z direction and a side surface Fs2 that is inclined with respect to the Z direction at a taper angle θ2.

[0073] In the third embodiment, similar to the second embodiment, the potential gradient of the photoelectric conversion unit PD on the second surface F2 side becomes steeper, and the potential gradient becomes gentler toward the first surface F1 side. The other configurations of the third embodiment may be the same as those of the second embodiment. Therefore, the third embodiment can obtain the same effects as the second embodiment.

[0074] (Fourth Embodiment) Figure 15 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the fourth embodiment. In the fourth embodiment, in the cross-section of the semiconductor layer EPI cut in the Z direction, the taper angles of the sides of the photoelectric conversion unit PD are different on the left and right sides Fs11 and Fs12. For example, the taper angle θ1 of side Fs11 is larger than the taper angle θ2 of side Fs12. It is preferable that both taper angles θ1 and θ2 are between 2 and 8 degrees.

[0075] When comparing the first side surface Fs11, which is relatively far from the floating layer FD, with the second side surface Fs12, which is relatively close, the taper angle θ1 of the first side surface Fs11 is larger than the taper angle θ2 of the second side surface Fs12. As explained with reference to Figure 11, the larger the taper angle of the side surface of the photoelectric conversion unit PD, the steeper the potential gradient. The center of gravity of the photoelectric conversion unit PD is biased towards the floating layer FD. Therefore, because the taper angle θ1 is larger than the taper angle θ2, the potential gradient of the photoelectric conversion unit PD is steep around the first side surface Fs11, which is relatively far from the floating layer FD. Around the second side surface Fs12, which is relatively close to the floating layer FD, the potential gradient of the photoelectric conversion unit PD is gentler. As a result, the charge of the entire photoelectric conversion unit PD can be efficiently transferred to the floating layer FD.

[0076] In the second to fourth embodiments, the element isolation sections TI and STI are FTIs as shown in Figures 3 and 4. However, the element isolation section TI may also be a DTI as shown in Figures 5 and 6.

[0077] (Fifth embodiment) Figure 16 is a cross-sectional view showing an example of the configuration of two adjacent pixels 2 according to the fifth embodiment. In the fifth embodiment, two adjacent pixels 2 share a floating layer FD and one element isolation section TI. Two adjacent pixels 2 that share the floating layer FD and the element isolation section TI have the same configuration and are substantially symmetric with respect to the central axis in the Z direction, shown by the dashed line. The side surface of each photoelectric conversion section PD has a taper. The outer side surface Fs11 of two adjacent pixels 2 has a taper angle θ1. The inner side surfaces Fs12 of two adjacent pixels 2 that face each other have a taper angle θ2. The taper angles θ1 and θ2 may be equal or different. Note that in Figure 16, the element isolation section TI is the DTI in Figures 5 and 6, but it may also be the FTI in Figures 3 and 4.

[0078] The two pixels 2 can operate as individual pixels or as a single pixel by sharing the floating layer FD. This increases the saturation charge amount (Qs), enabling HDR (High Dynamic Range).

[0079] Figures 17 and 18 are schematic plan views showing an example configuration of two adjacent pixels 2 according to the fifth embodiment. Figure 17 shows the plan view of the photoelectric conversion unit PD and element isolation unit TI on the first surface F1 side. Figure 18 shows the plan view of the photoelectric conversion unit PD and element isolation unit TI on the second surface F2 side. Figure 16 shows a cross-section along line 16-16 in Figures 17 and 18.

[0080] As shown in Figures 17 and 18, the photoelectric converters PDs of adjacent pixels 2 are electrically connected in part by a path Pov. The path Pov is located above the photoelectric converter PD in the +Z direction and is made of the same material as the photoelectric converter PD. When charge overflows in one photoelectric converter PD, the path Pov allows the overflowed charge to pass through to the other photoelectric converter PD and be stored there. In other words, the path Pov functions as an overflow path. Therefore, when the two pixels 2 operate as one pixel, the amount of charge that can be stored corresponds to the capacitance of the two adjacent photoelectric converter PDs. As a result, even when the amount of light is high, the pixel 2 can generate a pixel signal corresponding to that amount of light. In other words, the imaging device 1 according to the fifth embodiment can realize HDR.

[0081] When the taper angles θ1 and θ2 are equal, as shown in Figures 17 and 18, two element isolation sections TI adjacent in the Y direction across the path Pov are approximately equal in width in the X direction. Comparing Figures 17 and 18, it can be seen that the width of the element isolation section TI increases from the first surface F1 to the second surface F2. That is, it can be seen that the sides Fs11 and Fs12 of the photoelectric conversion section PD and the element isolation section TI have a taper.

[0082] Figure 19 is a cross-sectional view showing an example of the configuration of two adjacent pixels 2 according to a modification of the fifth embodiment. In this modification, the taper angles θ1 and θ2 of the side surfaces Fs11 and Fs12 of each photoelectric conversion unit PD are different from each other. Taper angle θ1 is larger than taper angle θ2. Therefore, the potential gradient in the photoelectric conversion unit PD far from the floating layer FD can be made steeper than the potential gradient in the photoelectric conversion unit PD close to the floating layer FD. This allows charge to be efficiently transferred to the floating layer FD.

[0083] Figures 20 and 21 are schematic plan views showing an example configuration of two adjacent pixels 2 according to a modification of the fifth embodiment. Figure 20 shows the plan view of the photoelectric conversion unit PD and element isolation unit TI on the first surface F1 side. Figure 21 shows the plan view of the photoelectric conversion unit PD and element isolation unit TI on the second surface F2 side. Figure 19 shows a cross-section along line 19-19 in Figures 20 and 21.

[0084] As shown in Figures 20 and 21, the photoelectric conversion unit PD of adjacent pixels 2 is similar to that of the fifth embodiment in that it is electrically connected in part by a path Pov. The path Pov functions as an overflow path. Therefore, the imaging device 1 according to this modified example can also realize HDR.

[0085] Two element isolation sections TI adjacent to each other in the Y direction, separated by path Pov, may both have a taper. In this case, the planar shape will be the same as in Figures 17 and 18.

[0086] On the other hand, in this modified example, one of the two element isolation sections TI adjacent in the Y direction across the path Pov does not have a taper, while the other does. In this case, as shown in Figures 20 and 21, the width of one of the two element isolation sections TI does not change, while the width of the other changes. For example, in this modified example, the element isolation section TIa closer to the floating layer FD does not have a taper, while the element isolation section TIb further from the floating layer FD has a taper. In this case, as shown in Figures 20 and 21, the width of the element isolation section TIa in the X direction remains almost constant across the first surface F1 to the second surface F2 of the photoelectric conversion section PD. The width of the element isolation section TIb in the X direction changes across the first surface F1 to the second surface F2 of the photoelectric conversion section PD. That is, the side surface Fs12 of the photoelectric conversion section PD facing the element isolation section TIa closer to the floating layer FD does not have a taper, while the side surface Fs12 of the photoelectric conversion section PD facing the element isolation section TIb further from the floating layer FD has a taper. This allows the potential gradient in the photoelectric conversion unit PD, which is far from the floating layer FD, to be steeper than the potential gradient in the photoelectric conversion unit PD, which is close to the floating layer FD. This enables efficient transfer of charge to the floating layer FD.

[0087] Furthermore, since the taper angle θ1 is larger than the taper angle θ2, the potential gradient in the photoelectric conversion unit PD, which is farther from the floating layer FD, can be made steeper than the potential gradient in the photoelectric conversion unit PD, which is closer to the floating layer FD. This allows for more efficient transfer of charge to the floating layer FD.

[0088] Furthermore, the sides of each photoelectric conversion unit PD may be bent midway and have multiple taper angles. That is, the fifth embodiment and its modifications can be applied to any of the first to fourth embodiments. As a result, the fifth embodiment and its modifications can also obtain the effects of any of the first to fourth embodiments.

[0089] (Sixth Embodiment) Figure 22 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the sixth embodiment. In the sixth embodiment, an element isolation section TI2 is provided in the center of the photoelectric conversion section PD of each pixel 2. The element isolation section TI1 provided on the outer circumference of the photoelectric conversion section PD of each pixel 2 extends substantially parallel to the Z direction. Therefore, the outer side surface Fs11 of the photoelectric conversion section PD is substantially parallel to the Z direction, and the taper angle is approximately 0 degrees.

[0090] On the other hand, the side surface of the element isolation section TI2 has a taper. Therefore, the inner side surface Fs12 of the photoelectric conversion section PD, which is opposite the side surface of the element isolation section TI2, has a taper angle greater than 0 degrees. The taper angle of side surface Fs12 is preferably 2 to 8 degrees. This taper of side surface Fs12 generates a potential gradient in the photoelectric conversion section PD. This makes it easier for the charge of the photoelectric conversion section PD to be transferred to the floating layer FD.

[0091] Figure 23 is a schematic plan view showing an example of the configuration of one pixel 2 according to the sixth embodiment. Figure 22 shows a cross-section along line 22-22 in Figure 23. As shown in Figure 23, an element isolation section TI2 is provided inside the photoelectric conversion section PD of pixel 2. In a plan view from the Z direction, the element isolation section TI2 has a roughly cross shape. All sides of the element isolation section TI2 have a taper, as shown in Figure 22. This generates a potential gradient in the photoelectric conversion section PD, making it easier for charge to be transferred to the floating layer FD. Other configurations of the sixth embodiment may be the same as those of the first embodiment.

[0092] (Seventh Embodiment) Figure 24 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the seventh embodiment. In the seventh embodiment, a plurality of element isolation sections TI2 are provided inside the photoelectric conversion section PD of each pixel 2. The element isolation sections TI1 provided on the outer circumference of the photoelectric conversion section PD of each pixel 2 extend substantially parallel to the Z direction. Therefore, the outer side surface Fs11 of the photoelectric conversion section PD is substantially parallel to the Z direction, and the taper angle is approximately 0 degrees.

[0093] On the other hand, the side surface of the element isolation section TI2 has a taper. Therefore, the inner side surface Fs12 of the photoelectric conversion section PD, which is opposite the side surface of the element isolation section TI2, has a taper angle greater than 0 degrees. The taper angle of side surface Fs12 is preferably 2 to 8 degrees. This taper of side surface Fs12 generates a potential gradient in the photoelectric conversion section PD. This makes it easier for the charge of the photoelectric conversion section PD to be transferred to the floating layer FD.

[0094] Figure 25 is a schematic plan view showing an example of the configuration of one adjacent pixel 2 according to the seventh embodiment. Figure 24 shows a cross-section along line 24-24 in Figure 25. As shown in Figure 25, four element isolation sections TI2 are provided inside the photoelectric conversion section PD of pixel 2. In a plan view from the Z direction, each element isolation section TI2 has a roughly rectangular shape and is provided near the four corners of the photoelectric conversion section PD. All sides of the element isolation sections TI2 have a taper, as shown in Figure 24. This generates a potential gradient in the photoelectric conversion section PD, making it easier for charge to be transferred to the floating layer FD. The other configurations of the seventh embodiment may be the same as those of the first embodiment.

[0095] In the sixth and seventh embodiments, the element isolation sections TI and STI are FTIs as shown in Figures 3 and 4. However, the element isolation section TI may also be a DTI as shown in Figures 5 and 6.

[0096] (Eighth embodiment) Figure 26 is a cross-sectional view showing an example configuration of two adjacent pixels 2 according to the eighth embodiment. Figure 27 is a schematic plan view showing an example configuration of four adjacent pixels 2 according to the eighth embodiment. Note that Figure 26 shows a cross-section along line 26-26 in Figure 27. In the eighth embodiment, four adjacent pixels 2 share a floating layer FD and an element isolation section TI2. The four pixels 2 that share the floating layer FD and the element isolation section TI2 each have the same configuration and are substantially symmetric with respect to the central axis in the Z direction shown by the dashed line in Figure 26.

[0097] The element isolation section TI2 is composed of a P-type semiconductor layer with reverse conductivity from the photoelectric conversion section PD. This electrically isolates adjacent photoelectric conversion sections PD. The four photoelectric conversion sections PD are distributed almost evenly around the floating layer FD and the element isolation section TI2.

[0098] The four pixels can operate as individual pixels, or they can operate as a single pixel by sharing the floating layer FD. This increases the saturation charge (Qs), enabling HDR.

[0099] As shown in Figure 26, the photoelectric conversion units PD of adjacent pixels 2 are electrically connected in part by a path Pov. The path Pov is located above the element isolation unit TI2 in the +Z direction, and has a lower impurity concentration than the element isolation unit TI2. - It is composed of a semiconductor layer. The path Pov allows the overflowing charge in one photoelectric conversion unit PD to pass through and be stored in another photoelectric conversion unit PD. In other words, the path Pov functions as an overflow path. Therefore, when four pixels operate as one pixel, the amount of charge that can be stored corresponds to the capacity of the four adjacent photoelectric conversion units PD. As a result, even when the amount of light is high, pixel 2 can generate a pixel signal corresponding to that amount of light. In other words, the imaging device 1 according to the eighth embodiment can realize HDR.

[0100] Furthermore, the outer surface of each photoelectric conversion unit PD has a taper, as shown in Figure 26. The taper angles may be equal or different. Preferably, the taper angle is between 2 and 8 degrees. Also, the eighth embodiment can be applied to any of the first to fourth embodiments. Thus, the eighth embodiment can obtain the effects of any of the first to fourth embodiments.

[0101] Furthermore, the element isolation unit TI1 in the eighth embodiment may be the FTI shown in Figures 3 and 4, or the DTI shown in Figures 5 and 6.

[0102] (Ninth Embodiment) Figure 28 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the ninth embodiment. In the ninth embodiment, the impurity concentration on the first surface F1 side of the photoelectric conversion unit PD has a gradient. For example, the impurity concentration of the photoelectric conversion unit PD decreases from the first surface F1 to the second surface F2. The impurity concentration of the photoelectric conversion unit PD changes in the range from the first surface F1 to the halfway point in the Z direction of the photoelectric conversion unit PD. The impurity concentration from the halfway point to the second surface F2 of the photoelectric conversion unit PD is substantially uniform, similar to that of the first embodiment. As a result, it is sufficient to inject impurities from the first surface F1 into the range from the first surface F1 to less than halfway point in the Z direction of the photoelectric conversion unit PD. Therefore, crystal defects on the second surface F2 side of the photoelectric conversion unit PD can be reduced.

[0103] The impurity concentration on the first surface F1 of the photoelectric conversion unit PD has a gradient such that it decreases from the first surface F1 to the second surface F2. As a result, the potential gradient on the first surface F1 of the photoelectric conversion unit PD is generated not only by the taper of the side surface of the photoelectric conversion unit PD, but also by the gradient of impurity concentration. This allows for efficient charge transfer toward the first surface F1 on the first surface F1 of the photoelectric conversion unit PD.

[0104] The other configurations of the ninth embodiment may be the same as those of the first embodiment. Therefore, the ninth embodiment can obtain the effects of the first embodiment. The ninth embodiment can also be adapted to any of the second to eighth embodiments. Thus, the ninth embodiment can obtain the effects of any of the second to eighth embodiments.

[0105] (Tenth embodiment) Figure 29 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the tenth embodiment. In the tenth embodiment, the impurity concentration on the first surface F1 side of the photoelectric conversion unit PD has a gradient, which is the same as in the ninth embodiment. Also, the side surface of the photoelectric conversion unit PD is the same as in the third embodiment in that it includes a side surface Fs1 as a first side surface extending in the Z direction and a side surface Fs2 as a second side surface inclined with respect to the Z direction. In other words, the tenth embodiment is a combination of the third and ninth embodiments.

[0106] Here, the impurity concentration of the photoelectric conversion unit PD gradually decreases from the first surface F1 to the second surface F2, up to the position of side surface Fs1 (the position indicated by the dashed line). Furthermore, the impurity concentration of the photoelectric conversion unit PD is approximately uniform from the position of side surface Fs1 (the position indicated by the dashed line) to the second surface F2.

[0107] As a result, the potential gradient on the second surface F2 side of the photoelectric conversion unit PD is generated by the taper of the side surface Fs2 of the photoelectric conversion unit PD. The potential gradient on the first surface F1 side of the photoelectric conversion unit PD is generated by the gradient of impurity concentration in the photoelectric conversion unit PD. This allows charge to be efficiently transferred toward the first surface F1 in the photoelectric conversion unit PD.

[0108] The other components of the tenth embodiment may be the same as those of the first embodiment. Therefore, the tenth embodiment can obtain the effects of the first embodiment.

[0109] Furthermore, the pinning layer PN may be a fixed charge film formed on the inner wall surface of the trench used for the device isolation section TI after the trench has been formed in the semiconductor layer EPI. Alternatively, the pinning layer PN may be formed by solid-phase diffusion via the trench for the device isolation section TI. In addition, the pinning layer PN may be formed by PLAD (Plasma Lateral Aligned Doping) via the trench for the device isolation section TI.

[0110] (11th embodiment) Figure 30 is a cross-sectional view showing an example of the configuration of one pixel 2 according to the 11th embodiment. In the 11th embodiment, the pinning layer PN is made of an insulating material such as a silicon oxide film. An electrode ER is provided in the element isolation section. The electrode ER is made of a conductive material such as polysilicon or tungsten. The electrode ER is electrically isolated from the photoelectric conversion section PD by the pinning layer PN made of an insulating material. A negative voltage is applied to the electrode ER to extinguish the charge generated at the interface between the photoelectric conversion section PD and the pinning layer PN. This suppresses the generation of dark current. Other configurations of the 11th embodiment may be the same as those of the first embodiment. Therefore, the 11th embodiment can obtain the same effects as the first embodiment. Furthermore, the 11th embodiment can be combined with any of the second to tenth embodiments. As a result, the 11th embodiment can also obtain the effects of any of the second to tenth embodiments.

[0111] (Examples of applications to mobile devices) The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0112] Figure 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0113] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 31, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0114] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0115] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0116] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0117] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0118] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0119] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0120] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0121] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0122] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 31, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0123] Figure 32 shows an example of the installation position of the imaging unit 12031.

[0124] In Figure 32, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0125] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0126] Figure 32 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0127] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0128] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0129] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0130] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0131] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031, among the configurations described above.

[0132] Furthermore, this technology can be configured as follows:

[0133] (1) Semiconductor layer, The semiconductor layer is provided with 2 × 10 15 / cm 3 ~1 × 10 16 / cm 3 Multiple photoelectric conversion units containing a first conductivity type impurity at a concentration of, It comprises element isolation units provided between the plurality of adjacent photoelectric conversion units or inside each photoelectric conversion unit, An imaging device in which, in a cross-section of the semiconductor layer cut parallel to a first direction in which light is incident, the plurality of photoelectric conversion units each have a taper on their side surface such that the width in a second direction perpendicular to the first direction narrows as you move from the first surface of the semiconductor layer on the side opposite to the side in which light is incident to the second surface of the semiconductor layer on the side in which light is incident.

[0134] (2) The imaging apparatus according to (1), wherein in a cross-section of the semiconductor layer cut parallel to the first direction, the element isolation portion has a taper on its side surface such that the width in the second direction increases from the first surface to the second surface.

[0135] (3) The imaging apparatus according to (1) or (2), wherein the plurality of photoelectric conversion units have substantially uniform impurity concentrations between the first surface and the second surface.

[0136] (4) The imaging apparatus according to any one of (1) to (3), wherein the first direction is the charge transfer direction in the plurality of photoelectric conversion units.

[0137] (5) The imaging device according to any one of (1) to (4), wherein the plurality of photoelectric conversion units have the shape of a frustum of a cone, a frustum of an ellipse, or a frustum of a polygon.

[0138] (6) The imaging apparatus according to any one of (1) to (5), wherein the sides of the plurality of photoelectric conversion units have a taper angle of 2 to 8 degrees from the first direction.

[0139] (7) The imaging apparatus according to any one of (1) to (6), wherein the taper angle of the side surfaces of the plurality of photoelectric conversion units changes midway along the side surface.

[0140] (8) The imaging apparatus according to (7), wherein the sides of the plurality of photoelectric conversion units are bent midway along the side so as to protrude toward the element isolation unit.

[0141] (9) The imaging apparatus according to (7) or (8), wherein the sides of the plurality of photoelectric conversion units include a first side portion extending in the first direction and a second side portion inclined with respect to the first direction.

[0142] (10) The imaging apparatus according to any one of (1) to (9), wherein, in the cross-section of the semiconductor layer cut parallel to the first direction, the taper angles of the sides on both sides of the plurality of photoelectric conversion units are different from each other.

[0143] (11) The semiconductor layer further comprises a first diffusion layer provided on the first surface side of the semiconductor layer, which contains a first conductivity type impurity at a higher concentration than the photoelectric conversion portion, The imaging apparatus according to (10), wherein the taper angle of the first side surface relatively far from the first diffusion layer is greater than the taper angle of the second side surface relatively close to the first diffusion layer.

[0144] (12) The element isolation unit is provided inside each of the plurality of photoelectric conversion units, The imaging apparatus according to (11), wherein, in a cross-section of the semiconductor layer cut parallel to the first direction, the element isolation portion located inside the plurality of photoelectric conversion portions has a taper on its side surface such that the width in the second direction increases from the first surface to the second surface.

[0145] (13) The imaging apparatus according to (1) or (2), wherein the impurity concentration of the plurality of photoelectric conversion units decreases from the first surface to the second surface.

[0146] (14) The sides of the plurality of photoelectric conversion units include a first side portion extending in the first direction and a second side portion inclined with respect to the first direction. The imaging apparatus according to (13), wherein the impurity concentration of the plurality of photoelectric conversion units gradually decreases from the first surface to the second surface up to the position of the first side surface, and is substantially uniform from the position of the first side surface to the second surface.

[0147] (15) The imaging apparatus according to any one of (1) to (14), further comprising a first semiconductor region containing a second conductivity type impurity, provided between the plurality of photoelectric conversion units and the element isolation unit.

[0148] (16) A first diffusion layer is provided on the first surface side of the semiconductor layer and contains a first conductivity type impurity at a higher concentration than the photoelectric conversion portion, A second semiconductor region is provided on the first surface side of the semiconductor layer and contains a second conductivity type impurity, The imaging apparatus according to any one of (1) to (15), further comprising a first transistor provided between the first diffusion layer and the second semiconductor region.

[0149] (17) The imaging apparatus according to any one of (1) to (16), wherein the element isolation portion penetrates between the first surface and the second surface of the semiconductor layer.

[0150] (18) The semiconductor layer is provided on the second surface side and further comprises a third semiconductor region containing a second conductivity type impurity, The imaging apparatus according to any one of (1) to (16), wherein the element isolation portion is provided from the first surface to the third semiconductor region of the semiconductor layer.

[0151] Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of this disclosure. Also, the effects described herein are merely illustrative and not limiting, and other effects may exist. [Explanation of symbols]

[0152] 1. Imaging device 2 pixels 3 pixel area 4. Vertical drive circuit 5-column signal processing circuit 6. Horizontal drive circuit 7 Output Circuit 8 Control circuits PD Photoelectric Conversion Unit TI, STI element isolation section FD floating layer Tr1~Tr3 Transistors PN pinning layer PW well layer CNPW

Claims

1. Semiconductor layer, The semiconductor layer is provided with 2 × 10 １５ / cm ３ ~1 x 10 １６ / cm ３ Multiple photoelectric conversion units containing a first conductivity type impurity at a concentration of, It comprises element isolation units provided between the plurality of adjacent photoelectric conversion units or inside each photoelectric conversion unit, An imaging device in which, in a cross-section of the semiconductor layer cut parallel to a first direction in which light is incident, the plurality of photoelectric conversion units each have a taper on their side surface such that the width in the second direction perpendicular to the first direction narrows as you move from the first surface of the semiconductor layer on the side opposite to the side in which light is incident to the second surface of the semiconductor layer on the side in which light is incident.

2. The imaging apparatus according to claim 1, wherein in a cross-section of the semiconductor layer cut parallel to the first direction, the element isolation portion has a taper on its side surface such that the width in the second direction increases from the first surface to the second surface.

3. The imaging apparatus according to claim 1, wherein the plurality of photoelectric conversion units have substantially uniform impurity concentrations between the first surface and the second surface.

4. The imaging apparatus according to claim 1, wherein the first direction is the charge transfer direction in the plurality of photoelectric conversion units.

5. The imaging device according to claim 1, wherein the plurality of photoelectric conversion units have the shape of a frustum of a cone, a frustum of an ellipse, or a frustum of a polygon.

6. The imaging apparatus according to claim 1, wherein the sides of the plurality of photoelectric conversion units have a taper angle of 2 to 8 degrees from the first direction.

7. The imaging apparatus according to claim 1, wherein the taper angle of the side surfaces of the plurality of photoelectric conversion units changes midway along the side surface.

8. The imaging apparatus according to claim 7, wherein the sides of the plurality of photoelectric conversion units are bent midway along the side so as to protrude toward the element isolation unit.

9. The imaging apparatus according to claim 7, wherein the sides of the plurality of photoelectric conversion units include a first side portion extending in the first direction and a second side portion inclined with respect to the first direction.

10. The imaging apparatus according to claim 1, wherein, in the cross-section of the semiconductor layer cut parallel to the first direction, the taper angles of the sides of the plurality of photoelectric conversion units are different from each other.

11. The semiconductor layer further comprises a first diffusion layer provided on the first surface side, which contains a first conductivity type impurity at a higher concentration than the photoelectric conversion portion, The imaging apparatus according to claim 10, wherein the taper angle of the first side surface relatively far from the first diffusion layer is greater than the taper angle of the second side surface relatively close to the first diffusion layer.

12. The element isolation unit is provided inside each of the plurality of photoelectric conversion units, The imaging apparatus according to claim 11, wherein, in a cross-section of the semiconductor layer cut parallel to the first direction, the element isolation portion located inside the plurality of photoelectric conversion portions has a taper on its side surface such that the width in the second direction increases from the first surface to the second surface.

13. The imaging apparatus according to claim 1, wherein the impurity concentration of the plurality of photoelectric conversion units decreases from the first surface to the second surface.

14. The sides of the plurality of photoelectric conversion units include a first side portion extending in the first direction and a second side portion inclined with respect to the first direction. The imaging apparatus according to claim 13, wherein the impurity concentration of the plurality of photoelectric conversion units gradually decreases from the first surface to the second surface up to the position of the first side surface, and is substantially uniform from the position of the first side surface to the second surface.

15. The imaging apparatus according to claim 1, further comprising a first semiconductor region containing a second conductivity type impurity, provided between the plurality of photoelectric conversion units and the element isolation unit.

16. A first diffusion layer is provided on the first surface side of the semiconductor layer and contains a first conductivity type impurity at a higher concentration than the photoelectric conversion portion, A second semiconductor region containing a second conductivity type impurity is provided on the first surface side of the semiconductor layer, The imaging apparatus according to claim 1, further comprising a first transistor provided between the first diffusion layer and the second semiconductor region.

17. The imaging apparatus according to claim 1, wherein the element isolation portion penetrates between the first surface and the second surface of the semiconductor layer.

18. The semiconductor layer is provided on the second surface side and further comprises a third semiconductor region containing a second conductivity type impurity, The imaging apparatus according to claim 1, wherein the element isolation portion is provided from the first surface to the third semiconductor region of the semiconductor layer.

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