Image sensing device

Abstract

To provide an image sensing device from which timing skew between clock signals used in distance measurement is suppressed.SOLUTION: An image sensing device comprises a phase controller that generates a plurality of output clock signals. The phase controller comprises: a first clock distributor (a first demodulation driver with first to third stages) for receiving a first input clock signal Vmixa through a first input terminal and outputting a plurality of first output clock signals Vmixa<0:X> through a plurality of first output terminals; and a first conductive line La1 coupled in common to output terminals of a plurality of first output drivers OD.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to semiconductor design technology, and more particularly, to an image sensing device.

Background Art

[0002] An image sensing device is an element that captures an image by utilizing the properties of a semiconductor that reacts to light. Image sensing devices can be broadly classified into image sensing devices using a CCD (Charge Coupled Device) and image sensing devices using a CMOS (Complementary Metal Oxide Semiconductor). In recent years, due to the advantage that analog and digital control circuits can be directly realized on a single integrated circuit (IC), image sensing devices using CMOS are widely used.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide an image sensing device in which timing skew between clock signals used during distance measurement is suppressed.

Means for Solving the Problems

[0004] According to one aspect of the present invention, an image sensing device can include a first clock distributor for receiving a first input clock signal via a first input terminal and outputting a plurality of first output clock signals via a plurality of first output terminals, and a first conductive line commonly connected to the plurality of first output terminals.

[0005] The first clock distributor may include a first clock tree connected between the first input terminal and a plurality of first distribution terminals, and a plurality of first output drivers connected between the plurality of first distribution terminals and a plurality of first output terminals.

[0006] The system may further include a second conductive line that is commonly connected to the plurality of first distribution terminals.

[0007] The image sensing device may further include a plurality of second conductive lines connected in groups to the plurality of first distribution terminals, and a plurality of first couplers for selectively connecting the plurality of second conductive lines based on a plurality of first control signals.

[0008] According to another aspect of the present invention, the image sensing device may include a first clock distributor for receiving a first input clock signal via a first input terminal and outputting a plurality of first output clock signals via a plurality of first output terminals, a plurality of first conductive lines connected in groups to the plurality of first output terminals, and a plurality of first couplers for selectively connecting the plurality of first conductive lines based on a plurality of control signals.

[0009] The first clock distributor may include a first clock tree connected between the first input terminal and a plurality of first distribution terminals, and a plurality of first output drivers connected between the plurality of first distribution terminals and a plurality of first output terminals.

[0010] The system may further include a second conductive line that is commonly connected to the plurality of first distribution terminals.

[0011] The image sensing device may further include a plurality of second conductive lines connected in groups to the plurality of first distribution terminals, and at least one second coupler for selectively connecting the plurality of second conductive lines based on a plurality of first control signals.

[0012] According to yet another aspect of the present invention, the image sensing device may include a first clock tree for receiving a first input clock signal via a first input terminal and outputting a plurality of first clock signals via a plurality of first distribution terminals; a first conductive line commonly connected to the plurality of first distribution terminals; and a plurality of first output drivers for receiving the plurality of first clock signals and outputting a plurality of first output clock signals via a plurality of first output terminals.

[0013] The image sensing device may further include a second clock tree for receiving a second input clock signal (which has a different phase from the first input clock signal) via a second input terminal and outputting a plurality of second clock signals via a plurality of second distribution terminals, a second conductive line commonly connected to the plurality of second distribution terminals, and a plurality of second output drivers for receiving the plurality of second clock signals and outputting a plurality of second output clock signals via a plurality of second output terminals.

[0014] According to yet another aspect of the present invention, the image sensing device comprises a clock distributor for generating an output clock signal having a phase based on an input clock signal and outputting the output clock signal through each of its output terminals; a pixel array for generating a charge corresponding to incident light from a subject in response to the corresponding output clock signal and generating a pixel signal based on the charge; and an image processor for generating depth map information for the subject based on the pixel signal, wherein the output terminals are divided into output groups, the output terminals of each output group are connected to conductive lines, and adjacent output terminals are selectively connected to each other. [Effects of the Invention]

[0015] Embodiments of the present invention have the effect of eliminating noise (e.g., column fixed pattern noise) generated in the depth map by suppressing timing skew between clock signals used during depth measurement. [Brief explanation of the drawing]

[0016] [Figure 1] This is a block diagram of an image sensing device according to an embodiment of the present invention. [Figure 2] Figure 1 is a circuit diagram showing a portion of the pixels in the pixel array. [Figure 3] Figure 1 is a block diagram showing an example of a phase controller. [Figure 4] Figure 3 is a block diagram of the first demodulation driver. [Figure 5] Figure 4 is a circuit diagram illustrating the conductive lines (etc.) along with the first to third stages and the first output driver shown. [Figure 6] This is a block diagram showing another example of the phase controller shown in Figure 1. [Figure 7] Figure 6 shows the block diagram of the first demodulation driver. [Figure 8] Figures 6 and 7 are circuit diagrams illustrating the conductive lines along with the first to third stages, the first output driver, and the first skew suppressor. [Modes for carrying out the invention]

[0017] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to explain in detail to the extent that a person with ordinary skill in the art to which the present invention pertains can easily implement the technical idea of ​​the present invention.

[0018] Throughout the specification, when a part is "connected" to another part, this includes not only cases where it is "directly connected", but also cases where it is "electrically connected" with other elements interposed therebetween. Also, when a part "includes" or "comprises" a certain component, this means that, unless otherwise stated to the contrary, it can further include or comprise other components, rather than excluding other components. Further, throughout the description in the specification, even if some components are described in the singular form, it will be understood that the present invention is not limited thereto and that the components can consist of a plurality of elements.

[0019] FIG. 1 shows a block diagram of an image sensing apparatus according to an embodiment of the present invention.

[0020] As shown in FIG. 1, the image sensing apparatus 100 can generate distance map information representing the distance (depth) from the subject 200 using the TOF (time of flight) method. For example, the image sensing apparatus 100 can generate (i.e., calculate) the distance map information by detecting the phase difference between the transmitted light MS radiated to the subject 200 and the incident light RS reflected from the subject 200. For example, the image sensing apparatus 100 can include a light transmitter 110, a row controller 130, a phase controller 140, a pixel array 150, a signal converter 170, and an image processor 180.

[0021] The light transmitter 110 can output the transmitted light MS to the subject 200. For example, the transmitted light MS can be a periodic signal that toggles periodically.

[0022] The row controller 130 can generate multiple row control signals CTRL<0:Y> for controlling the pixel array 150 row by row, where "Y" can correspond to the number of rows in the pixel array 150. For example, the row controller 130 can generate a first row control signal CTRL<0:Y> for controlling the pixels arranged in the first row of the pixel array 150. <0> It can generate a Y+1 row control signal CTRL to control the pixels arranged in the Y+1 row of the pixel array 150. <y>It can generate.

[0023] The phase controller 140 can generate multiple first output clock signals Vmixa<0:X> and multiple second output clock signals Vmixb<0:X>, where "X" corresponds to the number of columns in the pixel array 150. Multiple first output clock signals Vmixa<0:X> can have the same phase as each other, multiple second output clock signals Vmixb<0:X> can have the same phase as each other, and multiple first output clock signals Vmixa<0:X> and multiple second output clock signals Vmixb<0:X> can have different phases as each other. For example, multiple first output clock signals Vmixa<0:X> and multiple second output clock signals Vmixb<0:X> can have a phase difference of 180 degrees.

[0024] The pixel array 150 can generate multiple pixel signals VPXs based on incident light RS, multiple low control signals CTRL<0:Y>, multiple first output clock signals Vmixa<0:X>, and multiple second output clock signals Vmixb<0:X>. The pixel array 150 can include multiple unit pixels for measuring the distance to the subject 200. The multiple unit pixels can be arranged in the row and column directions. Each unit pixel can generate first and second pixel signals based on its respective low control signal CTRL<#>, its respective first output clock signal Vmixa<#>, its respective second output clock signal Vmixb<#>, and incident light RS (see Figure 2).

[0025] The signal converter 170 can generate multiple digital signals (DADCs) based on multiple pixel signals (VPXs). For example, the signal converter 170 may include an ADC (analog to digital converter).

[0026] The image processor 180 can generate distance map information representing the distance to the subject 200 based on a plurality of digital signals DADCs. For example, the image processor 180 can generate (i.e., calculate) the distance map information by subtracting the first and second digital signals corresponding to the first and second pixel signals generated from each unit pixel.

[0027] Figure 2 shows a circuit diagram of a portion of the pixel array 150 shown in Figure 1. In other words, it shows the circuit diagram of the unit pixel.

[0028] As shown in Figure 2, the unit pixel may include a pixel pair. For example, the pixel pair may include a first pixel TAPA and a second pixel TAPB.

[0029] The first pixel TAPA receives the reset signal RX, the transmission signal TX, the selection signal SX, and the first output clock signal Vmixa. <0> Based on this, a first pixel signal VPX1 can be generated. The reset signal RX, the transfer signal TX, and the selection signal SX can be signals included in any one of the low control signals CTRL<#> among the multiple low control signals CTRL<0:Y> described above. For example, the first pixel TAPA may include a first sensing circuit P1, a first reset circuit RT1, a first transfer circuit TT1, a first charge storage circuit C1, a first drive circuit DT1, and a first selection circuit ST1.

[0030] The first sensing circuit P1 can be connected between the first node N1 and the first low-voltage terminal. The first sensing circuit P1 receives the first output clock signal Vmixa <0> Based on this, a first charge corresponding to the incident light RS can be generated. The first sensing circuit P1 may include a photodiode.

[0031] A first reset circuit RT1 can be connected between a first high-voltage terminal and a first node N1. The first reset circuit RT1 can reset a first sensing circuit P1 and a first charge storage node C1 based on a reset signal RX.

[0032] The first transfer circuit TT1 can be connected between the first node N1 and the first floating diffusion node FD1. The first transfer circuit TT1 can reset the first charge storage circuit C1 based on the transfer signal TX and transfer the first charge generated from the first sensing circuit P1 to the first charge storage circuit C1.

[0033] The first charge storage circuit C1 can be connected between the first floating diffusion node FD1 and the first low-voltage terminal. The first charge storage circuit C1 can store the first charge. For example, the first charge storage circuit C1 can be a parasitic capacitor.

[0034] A first drive circuit DT1 can be connected between the first high-voltage terminal and the first selection circuit ST1. The first drive circuit DT1 can drive the first column line COL1 with a high voltage supplied through the first high-voltage terminal based on the voltage applied to the first floating diffusion node FD1.

[0035] The first selection circuit ST1 can be connected between the first drive circuit DT1 and the first column line COL1. The first selection circuit ST1 can selectively connect the first drive circuit DT1 and the first column line COL1 based on a selection signal SX. The first selection circuit ST1 can output a first pixel signal VPX1 via the first column line COL1.

[0036] The second pixel TAPB uses the reset signal RX, the transmission signal TX, the selection signal SX, and the second output clock signal Vmixb. <0> A second pixel signal VPX2 can be generated based on this. For example, the second pixel TAPB may include a second sensing circuit P2, a second reset circuit RT2, a second transmission circuit TT2, a second charge storage circuit C2, a second drive circuit DT2, and a second selection circuit ST2.

[0037] A second sensing circuit P2 can be connected between the second node N2 and the first low-voltage terminal. The second sensing circuit P2 receives the second output clock signal Vmixb <0> Based on this, a second charge corresponding to the incident light RS can be generated. The second sensing circuit P2 may include a photodiode.

[0038] A second reset circuit RT2 can be connected between the first high-voltage terminal and the second node N2. The second reset circuit RT2 can reset the second sensing circuit P2 and the second charge storage node C2 based on a reset signal RX.

[0039] A second transfer circuit TT2 can be connected between a second node N2 and a second floating diffusion node FD2. The second transfer circuit TT2 can reset a second charge storage circuit C2 based on a transfer signal TX and transfer the second charge generated from the second sensing circuit P2 to the second charge storage circuit C2.

[0040] A second charge storage circuit C2 can be connected between a second floating diffusion node FD2 and the first low-voltage terminal. The second charge storage circuit C2 can be a parasitic capacitor.

[0041] A second drive circuit DT2 can be connected between the first high-voltage terminal and the second selection circuit ST2. The second drive circuit DT2 can drive the second column line COL2 with a high voltage supplied through the first high-voltage terminal, based on the voltage applied to the second floating diffusion node FD2.

[0042] A second selection circuit ST2 can be connected between the second drive circuit DT2 and the second column line COL2. The second selection circuit ST2 can selectively connect the second drive circuit DT2 and the second column line COL2 based on a selection signal SX. The second selection circuit ST2 can output a second pixel signal VPX2 via the second column line COL2.

[0043] Figure 3 shows a block diagram of an example of the phase controller 140 shown in Figure 1.

[0044] As shown in Figure 3, the phase controller 140 may include a modulation controller 141, a first demodulation driver 143, and a second demodulation driver 145.

[0045] The modulation controller 141 can generate first and second input clock signals Vmixa and Vmixb having different phases from each other. For example, the first and second input clock signals Vmixa and Vmixb may have a phase difference of 180 degrees.

[0046] The first demodulation driver 143 can generate multiple first output clock signals Vmixa<0:X> based on a first input clock signal Vmixa. For example, the first demodulation driver 143 can act as a first clock distributor and generate multiple first output clock signals Vmixa<0:X> with the same phase as the first input clock signal Vmixa.

[0047] The second demodulation driver 145 can generate multiple second output clock signals Vmixb<0:X> based on the second input clock signal Vmixb. For example, the second demodulation driver 145 can act as a second clock distributor, generating multiple second output clock signals Vmixb<0:X> with the same phase as the second input clock signal Vmixb.

[0048] Since the first and second demodulation drivers 143 and 145 can be designed similarly, the first demodulation driver 143 will be described as representative below.

[0049] Figure 4 shows a block diagram of the first demodulation driver 143 shown in Figure 3.

[0050] As shown in Figure 4, the first demodulation driver 143 may include a first clock tree and a plurality of first output drivers.

[0051] The first clock tree can have multiple stages, from 1st Stage to Nth Stage (where "N" is an integer greater than 3). For example, the first stage, 1st Stage, receives a first input clock signal Vmixa and can generate at least one clock signal Vmixa<0:A> (where "A" is a non-negative integer); the second stage, 2nd Stage, receives multiple clock signals Vmixa<0:A> output from the first stage, 1st Stage, and can generate multiple clock signals Vmixa<0:B> (where "B" is an integer greater than "A"); and the Nth stage, Nth Stage, receives multiple clock signals output from the N-1th stage, N-1th Stage, and can generate multiple clock signals Vmixa<0:K> (where "K" is an integer greater than "B").

[0052] Multiple first output drivers can receive multiple clock signals Vmixa<0:K> output from the first clock tree CT and generate multiple first output clock signals Vmixa<0:X>.

[0053] Figure 5 shows a circuit diagram illustrating the first clock tree shown in Figure 4, along with several first output drivers and at least one conductive line. Note, for example, that Figure 5 shows the first clock tree comprising first to third stages (i.e., "N" is 3).

[0054] As shown in Figure 5, the first stage can be connected between one input terminal and one output terminal. The first stage may include a first inverter connected between the one input terminal and the one output terminal. That is, the first stage may be assigned one output terminal (i.e., distribution terminal) per input terminal. In such a case, the first stage can output a first clock signal. The first clock signal may correspond to at least one clock signal Vmixa<0:A> described above (i.e., "A" is 0).

[0055] The second stage (2nd Stage) can be connected between one input terminal (i.e., connected to the one output terminal of the first stage (1st Stage)) and two output terminals. The second stage (2nd Stage) may include first and second inverters connected in parallel between the one input terminal and the two output terminals. That is, the second stage (2nd Stage) may be assigned two output terminals for each input terminal. In such a case, the second stage (2nd Stage) can output first and second clock signals. The first and second clock signals can correspond to the aforementioned plurality of clock signals Vmixa<0:B> (i.e., "B" is 1).

[0056] The third stage (3rd Stage) can be connected between two input terminals (i.e., connected to each of the two output terminals of the second stage (2nd Stage)) and six output terminals. The third stage (3rd Stage) may include first to third inverters connected in parallel between one of the two input terminals and three of the six output terminals, and fourth to sixth inverters connected in parallel between the remaining input terminal and the remaining three of the six output terminals. In other words, the third stage (3rd Stage) may be assigned three output terminals per input terminal. In such a case, the third stage (3rd Stage) can output first to sixth clock signals. The first to sixth clock signals can correspond to the aforementioned multiple clock signals Vmixa<0:K> (i.e., "K" is 5).

[0057] In embodiments of the present invention, the first to third stages (1st Stage to 3td Stage) are equipped with one inverter for each branched path (i.e., branch), but are not necessarily limited to this, and may be equipped with two or more inverters depending on the design. For example, if two or more inverters are equipped, the two or more inverters can be connected in series. Furthermore, the number of paths branched from each of the first to third stages (1st Stage to 3td Stage) can be varied depending on the design.

[0058] Multiple first output driver ODs can be connected between the six input terminals (i.e., connected to each of the six output terminals of the third stage) and the 24 output terminals. Multiple first output driver ODs may be assigned four output terminals per input terminal. In such a case, multiple first output driver ODs can output first to 24th output clock signals Vmixa<0:23>. The first to 24th output clock signals Vmixa<0:23> can correspond to the aforementioned multiple first output clock signals Vmixa<0:X> (i.e., "X" is 23).

[0059] In embodiments of the present invention, each of the multiple first output driver ODs is equipped with two inverters connected in series for each branched path (i.e., branch), but is not necessarily limited to this, and may be equipped with one inverter or three or more inverters connected in series depending on the design. Furthermore, the number of paths branched from the multiple first output driver ODs can be varied depending on the design.

[0060] For example, the output terminals of multiple first output drivers OD, i.e., the 24 output terminals, can be commonly connected by a first conductive line La1. This allows the transition timings of the first to 24th output clock signals Vmixa<0:23> to be averaged (i.e., become almost identical) while suppressing timing skew that occurs between the first to 24th output clock signals Vmixa<0:23>.

[0061] For reference, multiple first output drivers OD may have different RC delays reflected in their respective branched paths, and the characteristics of the inverters provided in multiple output drivers OD may differ (e.g., process and voltage variations). Therefore, timing skew can occur between the first to 24th output clock signals Vmixa<0:23>. However, as in one example of the present invention, the 24 output terminals are commonly connected by a first conductive line La1, so the transition timings of the first to 24th output clock signals Vmixa<0:23> can be almost identical. For example, among the multiple first output drivers OD, the first output driver group that outputs an output clock signal with a relatively fast transition timing and the second output driver group that outputs an output clock signal with a relatively slow transition timing will collide with or interfere with each other during the interval in which the timing skew occurs. When the first output driver group and the second output driver group begin to collide with each other, the transition timing of the output clock signal output from the first output driver group becomes relatively slower, and the transition timing of the output signal output from the second output driver group becomes relatively faster. Therefore, the transition timings of the first to 24th output clock signals Vmixa<0:23> can become almost identical.

[0062] As in other examples, the output terminals of the third stage, i.e., the six output terminals, can be commonly connected by a second conductive line La2. This allows the transition timings of the first to sixth clock signals output from the third stage to be averaged (i.e., nearly identical) while suppressing timing skew between the first to sixth clock signals. Suppressing the timing skew between the first to sixth clock signals can help suppress timing skew between the first to 24th output clock signals Vmixa<0:23>.

[0063] In another example, the output terminals of the second stage, i.e., the two output terminals, can be commonly connected by a third conductive line La3. This allows the transition timing of the first and second clock signals output from the second stage to be averaged, while suppressing the timing skew between the first and second clock signals. Suppressing the timing skew between the first and second clock signals can help suppress the timing skew between the first to 24th output clock signals Vmixa<0:23>.

[0064] Furthermore, by other means, at least one output terminal among the output terminals of the second stage (2nd Stage), the third stage (3rd Stage), and the multiple output terminals of the first output drivers (OD) can be commonly connected by at least one conductive line among the first to third conductive lines La1 to La3. This suppresses the timing skew that occurs between the first and second clock signals, the timing skew that occurs between the first to sixth clock signals, and the timing skew that occurs between the first to 24th output clock signals Vmixa<0:23>.

[0065] Figure 6 shows a block diagram of another example of the phase controller 140 shown in Figure 1.

[0066] As shown in Figure 6, the phase controller 140 may include a modulation controller 141, a first demodulation driver 143, a first skew suppressor 145, a second demodulation driver 147, and a second skew suppressor 149.

[0067] The modulation controller 141 can generate first and second input clock signals Vmixa and Vmixb having different phases from each other. For example, the first and second input clock signals Vmixa and Vmixb may have a phase difference of 180 degrees. The modulation controller 141 can generate a plurality of first control signals ENa<0:E> for controlling the first skew suppressor 145 and a plurality of second control signals ENb<0:E> for controlling the second skew suppressor 149. Whether each of the plurality of first control signals ENa<0:E> can be activated can be determined by the degree of timing skew occurring between the plurality of first output clock signals Vmixa<0:X>, and whether each of the plurality of second control signals ENb<0:E> can be activated can be determined by the degree of timing skew occurring between the plurality of second output clock signals Vmixb<0:X>. The degree of timing skew occurring between multiple first output clock signals Vmixa<0:X> and the degree of timing skew occurring between multiple second output clock signals Vmixb<0:X> can be determined by testing or simulation. In other words, multiple first control signals ENa<0:E> and multiple second control signals ENb<0:E> can each be activated or deactivated based on the results of the aforementioned tests or simulations. In the embodiments of the present invention, it has been explained that multiple first control signals ENa<0:E> and multiple second control signals ENb<0:E> are generated from the modulation controller 141, but the invention is not necessarily limited to this. They can also be generated from a timing controller (not shown) provided in the image sensing device 100 for controlling the overall operation of the image sensing device 100, or from outside the image sensing device 100 (e.g., a control device).

[0068] The first demodulation driver 143 can generate multiple first output clock signals Vmixa<0:X> based on a first input clock signal Vmixa. For example, the first demodulation driver 143 can act as a first clock distributor and generate multiple first output clock signals Vmixa<0:X> with the same phase as the first input clock signal Vmixa.

[0069] The first skew suppressor 145 can be connected to the first demodulation driver 143. Based on a plurality of first control signals ENa<0:E>, the first skew suppressor 145 can suppress timing skew occurring between all of the plurality of first output clock signals Vmixa<0:X>, or suppress timing skew occurring between some of the plurality of first output clock signals Vmixa<0:X>.

[0070] The second demodulation driver 147 can generate multiple second output clock signals Vmixb<0:X> based on the second input clock signal Vmixb. For example, the second demodulation driver 147 can act as a second clock distributor, generating multiple second output clock signals Vmixb<0:X> with the same phase as the second input clock signal Vmixb.

[0071] A second skew suppressor 149 can be connected to a second demodulation driver 147. Based on a plurality of second control signals ENb<0:E>, the second skew suppressor 149 can suppress timing skew occurring between all of the plurality of second output clock signals Vmixb<0:X>, or suppress timing skew occurring between some of the plurality of second output clock signals Vmixb<0:X>.

[0072] The first and second demodulation drivers 143 and 147 can be designed similarly, and the first and second skew suppressors 145 and 149 can be designed similarly; therefore, the first demodulation driver 143 and the first skew suppressor 145 will be described as representative examples below.

[0073] Figure 7 shows a block diagram of the first demodulation driver 143 shown in Figure 6.

[0074] As shown in Figure 7, the first demodulation driver 143 may include a first clock tree and a plurality of first output drivers.

[0075] The first clock tree can have multiple stages, from 1st Stage to Nth Stage (where "N" is an integer greater than 3). For example, the first stage, 1st Stage, receives a first input clock signal Vmixa and can generate at least one clock signal Vmixa<0:A> (where "A" is a non-negative integer); the second stage, 2nd Stage, receives multiple clock signals Vmixa<0:A> output from the first stage, 1st Stage, and can generate multiple clock signals Vmixa<0:B> (where "B" is an integer greater than "A"); and the Nth stage, Nth Stage, receives multiple clock signals output from the N-1th stage, N-1th Stage, and can generate multiple clock signals Vmixa<0:K> (where "K" is an integer greater than "B").

[0076] Multiple first output drivers can receive multiple clock signals Vmixa<0:K> output from the first clock tree and generate multiple first output clock signals Vmixa<0:X>.

[0077] Figure 8 shows a circuit diagram illustrating at least one conductive line along with the first clock tree shown in Figure 6, a plurality of first output drivers OD, and the first skew suppressor 145 shown in Figure 5. Note, for example, that Figure 8 shows the first clock tree CT comprising first to third stages 1st Stage to 3td Stage (i.e., "N" is 3).

[0078] As shown in Figure 8, the first stage can be connected between one input terminal and one output terminal. The first stage can include a first inverter connected between the one input terminal and the one output terminal. That is, the first stage can be assigned one output terminal for each input terminal. In this case, the first stage can output a first clock signal. The first clock signal can correspond to at least one clock signal Vmixa<0:A> described above (i.e., "A" is 0).

[0079] The second stage (2nd Stage) can be connected between one input terminal (i.e., connected to the one output terminal of the first stage (1st Stage)) and two output terminals. The second stage (2nd Stage) may include first and second inverters connected in parallel between the one input terminal and the two output terminals. That is, the second stage (2nd Stage) may be assigned two output terminals for each input terminal. In such a case, the second stage (2nd Stage) can output first and second clock signals. The first and second clock signals can correspond to the aforementioned plurality of clock signals Vmixa<0:B> (i.e., "B" is 1).

[0080] The third stage (3rd Stage) can be connected between two input terminals (i.e., connected to each of the two output terminals of the second stage (2nd Stage)) and six output terminals. The third stage (3rd Stage) may include first to third inverters connected in parallel between one of the two input terminals and three of the six output terminals, and fourth to sixth inverters connected in parallel between the remaining input terminal and the remaining three of the six output terminals. In other words, the third stage (3rd Stage) may be assigned three output terminals per input terminal. In this case, the third stage (3rd Stage) can output first to sixth clock signals. The first to sixth clock signals can correspond to the aforementioned multiple clock signals Vmixa<0:K> (i.e., "K" is 5).

[0081] In embodiments of the present invention, the first to third stages (1st Stage to 3td Stage) are equipped with one inverter for each branched path (i.e., branch), but are not necessarily limited to this, and may be equipped with two or more inverters depending on the design. For example, if two or more inverters are equipped, the two or more inverters can be connected in series. Furthermore, the number of paths branched from each of the first to third stages (1st Stage to 3td Stage) can be varied depending on the design.

[0082] Multiple first output driver ODs can be connected between the six input terminals (i.e., connected to each of the six output terminals of the third stage) and the 24 output terminals. Multiple first output driver ODs may be assigned four output terminals per input terminal. In such a case, multiple first output driver ODs can output first to 24th output clock signals Vmixa<0:23>. The first to 24th output clock signals Vmixa<0:23> can correspond to the aforementioned multiple first output clock signals Vmixa<0:X> (i.e., "X" is 23).

[0083] In embodiments of the present invention, each of the multiple first output driver ODs is equipped with two inverters connected in series for each branched path (i.e., branch), but is not necessarily limited to this, and may be equipped with one inverter or three or more inverters connected in series depending on the design. Furthermore, the number of paths branched from the multiple first output driver ODs can be varied depending on the design.

[0084] For example, the output terminals of multiple first output drivers OD, i.e., the 24 output terminals, can be connected in groups by first to sixth conductive lines La1 to La6. That is, the 24 output terminals can be divided into six groups by the first to sixth conductive lines La1 to La6, and the output terminal of each of the six groups can be connected by each of the first to sixth conductive lines La1 to La6. The first to sixth conductive lines La1 to La6 can correspond to the six input terminals of multiple first output drivers OD. For example, the first conductive line La1 can be connected in common to four output terminals where the first to fourth output clock signals Vmixa<0:3> are output; the second conductive line La2 can be connected in common to four output terminals where the fifth to eighth output clock signals Vmixa<4:7> are output; the third conductive line La3 can be connected in common to four output terminals where the ninth to twelfth output clock signals Vmixa<8:11> are output; the fourth conductive line La4 can be connected in common to four output terminals where the thirteenth to sixteenth output clock signals Vmixa<12:15> are output; the fifth conductive line La5 can be connected in common to four output terminals where the seventeenth to twentyth output clock signals Vmixa<16:19> are output; and the sixth conductive line La6 can be connected in common to four output terminals where the twenty-first to twenty-fourth output clock signals Vmixa<20:23> are output.

[0085] The first skew suppressor 145 may include first to fifth couplers CPa1 to CPa5. The first to fifth couplers CPa1 to CPa5 can be connected between first to sixth conductive lines La1 to La6, respectively. The first to fifth couplers CPa1 to CPa5 can selectively connect the first to sixth conductive lines La1 to La6 based on first to fifth control signals ENa<0:4>. For example, the first coupler CPa1 may be connected to first control signal ENa <0> Based on this, the first and second conductive lines La1 and La2 can be selectively connected, and the second coupler CPa2 receives the second control signal ENa <1> Based on this, the second and third conductive lines La2 and La3 can be selectively connected, and the third coupler CPa3 receives the third control signal ENa <2> Based on this, the third and fourth conductive lines La3 and La4 can be selectively connected, and the fourth coupler CPa4 is connected to the fourth control signal ENa <3> Based on this, the fourth and fifth conductive lines La4 and La5 can be selectively connected, and the fifth coupler CPa5 connects to the fifth control signal ENa <5> Based on this, the fifth and sixth conductive lines La5 and La6 can be selectively connected. The first to fifth couplers CPa1 to CPa5 may each include a switch or a fuse.

[0086] If two or more conductive lines from the first to sixth conductive lines La1 to La6 are connected by at least one coupler from the first to fifth couplers CPa1 to CPa5, the transition timings of some or all of the first to twenty-fourth output clock signals Vmixa<0:23> can be averaged (i.e., become almost identical), while timing skew occurring between the first to twenty-fourth output clock signals Vmixa<0:23> can be suppressed.

[0087] For reference, multiple first output drivers OD may have different RC delays reflected in their respective branched paths, and the characteristics of the inverters provided in multiple output drivers OD may differ (e.g., process and voltage variations). Therefore, timing skew can occur between the first to 24th output clock signals Vmixa<0:23>. However, as in one example of the present invention, the 24 output terminals are connected by first to sixth conductive lines La1 to La6, and the first to sixth conductive lines La1 to La6 are selectively connected by first to fifth couplers CPa1 to CPa5. Therefore, the transition timings of the first to 24th output clock signals Vmixa<0:23> can be almost identical. For example, among the multiple first output drivers OD, the first output driver group that outputs an output clock signal with a relatively fast transition timing and the second output driver group that outputs an output clock signal with a relatively slow transition timing will collide with or interfere with each other during the interval in which the timing skew occurs. When the first output driver group and the second output driver group begin to conflict with each other, the transition timing of the output clock signal output from the first output driver group can be relatively delayed, and the transition timing of the output signal output from the second output driver group can be relatively accelerated. Therefore, the transition timings of the first to 24th output clock signals Vmixa<0:23> can be made almost identical.

[0088] As in other examples, the output terminals of the third stage, i.e., the six output terminals, can be connected in groups by the seventh and eighth conductive lines La7 and La8. That is, the six output terminals can be divided into two groups by the seventh and eighth conductive lines La7 and La8, and the output terminals of each of the two groups can be connected by the seventh and eighth conductive lines La7 and La8, respectively. The seventh and eighth conductive lines La7 and La8 can correspond to the two input terminals of the third stage. For example, the seventh conductive line La7 can be connected in common to three of the six output terminals, and the eighth conductive line La8 can be connected in common to the remaining three of the six output terminals.

[0089] The first skew suppressor 145 may further comprise a sixth coupler CPa6. The sixth coupler CPa6 may be connected between seventh and eighth conductive lines La7 and La8. The sixth coupler CPa6 is connected to a sixth control signal ENa <5> Based on this, the seventh and eighth conductive lines La7 and La8 can be selectively connected. The sixth coupler CPa6 may include a switch or fuse, etc.

[0090] If the seventh and eighth conductive lines La7 and La8 are connected by the sixth coupler CPa6, the transition timings of the first to sixth clock signals output from the third stage can be averaged (i.e., become almost identical), while timing skew occurring between the first to sixth clock signals can be suppressed. Suppressing the timing skew occurring between the first to sixth clock signals can help suppress the timing skew occurring between the first to 24th output clock signals Vmixa<0:23>.

[0091] Furthermore, by other examples, the output terminals of the second stage (2nd Stage) can be commonly connected by the ninth conductive line La9, the six output terminals of the third stage (3rd Stage) can be connected in groups by the seventh and eighth conductive lines La7 and La8, and the 24 output terminals of multiple first output drivers (OD) can be connected in groups by the first to sixth conductive lines La1 to La6. That is, the six output terminals can be divided into two groups by the seventh and eighth conductive lines La7 and La8, and the output terminals of each of the two groups can be connected by the seventh and eighth conductive lines La7 and La8, respectively. The 24 output terminals can be divided into six groups by the first to sixth conductive lines La1 to La6, and the output terminals of each of the six groups can be connected by the first to sixth conductive lines La1 to La6, respectively.

[0092] The first skew suppressor 145 may be equipped with first to sixth couplers CPa1 to CPa6. The first to fifth couplers CPa1 to CPa5 can be connected to the first to sixth conductive lines La1 to La6, respectively. The first to fifth couplers CPa1 to CPa5 can selectively connect the first to sixth conductive lines La1 to La6 based on the first to fifth control signals ENa<0:4>. For example, the first coupler CPa1 may be connected to the first control signal ENa <0> Based on this, the first and second conductive lines La1 and La2 can be selectively connected, and the second coupler CPa2 receives the second control signal ENa <1> Based on this, the second and third conductive lines La2 and La3 can be selectively connected, and the third coupler CPa3 receives the third control signal ENa <2> Based on this, the third and fourth conductive lines La3 and La4 can be selectively connected, and the fourth coupler CPa4 is connected to the fourth control signal ENa <3> Based on this, the fourth and fifth conductive lines La4 and La5 can be selectively connected, and the fifth coupler CPa5 connects to the fifth control signal ENa <5> Based on this, the fifth and sixth conductive lines La5 and La6 can be selectively connected. The sixth coupler CPa6 can be connected between the seventh and eighth conductive lines La7 and La8. The sixth coupler CPa6 is connected to the sixth control signal ENa <5> Based on this, the seventh and eighth conductive lines La7 and La8 can be selectively connected. The first to sixth couplers CPa1 to CPa6 may each include a switch or a fuse.

[0093] If two or more conductive lines from the first to sixth conductive lines La1 to La6 are connected by at least one coupler from the first to fifth couplers CPa1 to CPa5, the transition timings of some or all of the first to twenty-fourth output clock signals Vmixa<0:23> can be averaged (i.e., become almost identical), while timing skew occurring between the first to twenty-fourth output clock signals Vmixa<0:23> can be suppressed. If the seventh and eighth conductive lines La7 and La8 are connected by the sixth coupler CPa6, the transition timings of the first to sixth clock signals output from the third stage can be averaged (i.e., become almost identical), while timing skew occurring between the first to sixth clock signals can be suppressed. By suppressing the timing skew that occurs between the first to sixth clock signals, it is possible to help suppress the timing skew that occurs between the first to 24th output clock signals Vmixa<0:23>.

[0094] The operation of the image sensing device 100 having the above configuration is described as follows.

[0095] First, we will explain the operation of the image sensing device 100 when the phase controller 140 is configured as shown in Figures 3 to 5.

[0096] The phase controller 140 can generate a plurality of first output clock signals Vmixa<0:X> and a plurality of second output clock signals Vmixb<0:X>. The plurality of first output clock signals Vmixa<0:X> can have the same phase as each other, the plurality of second output clock signals Vmixb<0:X> can have the same phase as each other, and the plurality of first output clock signals Vmixa<0:X> and the plurality of second output clock signals Vmixb<0:X> can have different phases as each other. For example, the plurality of first output clock signals Vmixa<0:X> and the plurality of second output clock signals Vmixb<0:X> can have a phase difference of 180 degrees. In particular, the phase controller 140 can suppress a first timing skew occurring between the plurality of first output clock signals Vmixa<0:X> and can suppress a second timing skew occurring between the plurality of second output clock signals Vmixb<0:X>.

[0097] For example, the phase controller 140 can suppress the first timing skew by connecting the output terminals to which a plurality of first output clock signals Vmixa<0:X> are output and / or the distribution terminals associated with the plurality of first output clock signals Vmixa<0:X> to at least one conductive line (e.g., La1 to La3). The phase controller 140 can suppress the second timing skew by connecting the output terminals to which a plurality of second output clock signals Vmixb<0:X> are output and / or the distribution terminals associated with the plurality of second output clock signals Vmixb<0:X> to at least one conductive line (e.g., La1 to La3).

[0098] The pixel array 150 can generate multiple pixel signals VPXs based on incident light RS, multiple low control signals CTRL<0:Y>, multiple first output clock signals Vmixa<0:X>, and multiple second output clock signals Vmixb<0:X>.

[0099] The signal converter 170 can generate multiple digital signals DADCs based on multiple pixel signals VPXs, and the image processor 180 can generate distance map information representing the distance to the subject 200 based on the multiple digital signals DADCs.

[0100] Next, we will explain the operation of the image sensing device 100 when the phase controller 140 is configured as shown in Figures 6 to 8.

[0101] The phase controller 140 can determine whether to activate each of the multiple first control signals ENa<0:E> based on the degree of a first timing skew occurring between the multiple first output clock signals Vmixa<0:X>. The phase controller 140 can also determine whether to activate each of the multiple second control signals ENb<0:E> based on the degree of a second timing skew occurring between the multiple second output clock signals Vmixb<0:X>. The degree of the first timing skew and the degree of the second timing skew can be determined by testing or simulation.

[0102] The phase controller 140 can generate a plurality of first output clock signals Vmixa<0:X> and a plurality of second output clock signals Vmixb<0:X>. The plurality of first output clock signals Vmixa<0:X> can have the same phase as each other, the plurality of second output clock signals Vmixb<0:X> can have the same phase as each other, and the plurality of first output clock signals Vmixa<0:X> and the plurality of second output clock signals Vmixb<0:X> can have different phases as each other. For example, the plurality of first output clock signals Vmixa<0:X> and the plurality of second output clock signals Vmixb<0:X> can have a phase difference of 180 degrees. In particular, the phase controller 140 can suppress the first timing skew that occurs between the plurality of first output clock signals Vmixa<0:X> and can suppress the second timing skew that occurs between the plurality of second output clock signals Vmixb<0:X>.

[0103] For example, the phase controller 140 can suppress the first timing skew by connecting the output terminals where multiple first output clock signals Vmixa<0:X> are output and / or the distribution terminals associated with the multiple first output clock signals Vmixa<0:X> to at least one conductive line (e.g., La1~La9) and couplers CPa1~CPa6. The phase controller 140 can suppress the second timing skew by connecting the output terminals where multiple second output clock signals Vmixb<0:X> are output and / or the distribution terminals associated with the multiple second output clock signals Vmixb<0:X> to at least one conductive line (e.g., La1~La9) and couplers CPa1~CPa6.

[0104] The pixel array 150 can generate multiple pixel signals VPXs based on incident light RS, multiple low control signals CTRL<0:Y>, multiple first output clock signals Vmixa<0:X>, and multiple second output clock signals Vmixb<0:X>.

[0105] The signal converter 170 can generate multiple digital signals DADCs based on multiple pixel signals VPXs, and the image processor 180 can generate distance map information representing the distance to the subject 200 based on the multiple digital signals DADCs.

[0106] According to these embodiments of the present invention, there is an advantage in that timing skew between the clock signal generated by RC delay (RC delay) of the paths included in the clock tree and PV fluctuations (process and voltage variations) of the inverters provided in the clock tree can be suppressed. Furthermore, since a large timing skew occurs between the nodes (i.e., branching points or distribution points) of the clock tree, there is an advantage in that the timing skew can be fluidly adjusted and suppressed by selectively controlling the coupler.

[0107] While the technical concept of the present invention has been specifically described by the embodiments described above, it should be noted that the embodiments described above are for illustrative purposes only and not to limit them. Furthermore, a typical expert in the technical field of the present invention will understand that various embodiments are possible within the scope of the technical concept of the present invention through various substitutions, modifications, and changes. [Explanation of Symbols]

[0108] 100 Image Sensing Devices 110 Optical Transmitter 130 Low Controller 140 Phase Controller 150 pixel array 170 Signal Converter 180 Image Processors< / y>

Claims

1. A first clock tree is connected between a first input terminal and a plurality of first distribution terminals, and receives a first input clock signal via the first input terminal. A plurality of first output drivers are connected between the plurality of first distribution terminals and the plurality of first output terminals, and output a plurality of first output clock signals via the plurality of first output terminals. A first conductive line is connected in common to the plurality of first output terminals, A plurality of second conductive lines connected in groups to the plurality of first distribution terminals, A plurality of first couplers for selectively connecting the plurality of second conductive lines based on a plurality of first control signals, An image sensing device equipped with [a specific feature].

2. The image sensing device according to claim 1, further comprising a second conductive line commonly connected to the plurality of first distribution terminals.

3. A second clock distributor for receiving a second input clock signal having a different phase from the first input clock signal via a second input terminal, and outputting a plurality of second output clock signals via a plurality of second output terminals, A third conductive line is connected in common to the plurality of second output terminals, The image sensing device according to claim 1, further comprising the following:

4. The second clock distributor described above is: A second clock tree connected between the second input terminal and the plurality of second distribution terminals, A plurality of second output drivers connected between the plurality of second distribution terminals and the plurality of second output terminals, The image sensing device according to claim 3, comprising:

5. The image sensing device according to claim 4, further comprising a fourth conductive line commonly connected to the plurality of second distribution terminals.

6. A plurality of fourth conductive lines connected in groups to the plurality of second distribution terminals, A plurality of second couplers for selectively connecting the plurality of fourth conductive lines based on a plurality of second control signals, The image sensing device according to claim 4, further comprising the above.

7. The image sensing apparatus according to claim 1, further comprising a pixel array for generating pixel signals corresponding to depth map information based on a plurality of first output clock signals and light signals reflected from an object.

8. A first clock distributor for receiving a first input clock signal via a first input terminal and outputting a plurality of first output clock signals via a plurality of first output terminals, A plurality of first conductive lines connected in groups to the plurality of first output terminals, A plurality of first couplers for selectively connecting the plurality of first conductive lines based on a plurality of first control signals, An image sensing device equipped with [a specific feature].

9. The first clock distributor is, A first clock tree connected between the first input terminal and a plurality of first distribution terminals, A plurality of first output drivers connected between the plurality of first distribution terminals and the plurality of first output terminals, The image sensing device according to claim 8, comprising:

10. The image sensing device according to claim 9, further comprising a second conductive line commonly connected to the plurality of first distribution terminals.

11. A plurality of second conductive lines connected in groups to the plurality of first distribution terminals, A plurality of second couplers for selectively connecting the plurality of second conductive lines based on a plurality of second control signals, The image sensing device according to claim 9, further comprising the above.

12. A second clock distributor for receiving a second input clock signal via a second input terminal and outputting a plurality of second output clock signals via a plurality of second output terminals, A plurality of third conductive lines connected in groups to the plurality of second output terminals, A plurality of third couplers for selectively connecting the plurality of third conductive lines based on a plurality of third control signals, The image sensing device according to claim 8, further comprising the above.

13. The second clock distributor described above is: A second clock tree connected between the second input terminal and a plurality of second distribution terminals, and a plurality of second output drivers connected between the plurality of second distribution terminals and a plurality of second output terminals, The image sensing device according to claim 12, comprising:

14. The image sensing device according to claim 13, further comprising a fourth conductive line commonly connected to the plurality of second distribution terminals.

15. A plurality of fourth conductive lines connected in groups to the plurality of second distribution terminals, A plurality of fourth couplers for selectively connecting the plurality of fourth conductive lines based on a plurality of fourth control signals, The image sensing device according to claim 13, further comprising the above.

16. The image sensing apparatus according to claim 8, further comprising a pixel array for generating pixel signals corresponding to depth map information based on a plurality of first output clock signals and light signals reflected from an object.

17. A clock distributor for generating an output clock signal having a phase based on an input clock signal and outputting the output clock signal through each of its output terminals, A pixel array for generating a charge corresponding to incident light from an object in response to a corresponding output clock signal, and for generating a pixel signal based on the charge, An image processor for generating depth map information for the subject based on the aforementioned pixel signal, Equipped with, The aforementioned output terminals are divided into output groups, The output terminal of each output group is connected to a conductive line. An image sensing device in which adjacent output terminals are selectively connected to each other via corresponding couplers.

Images