Accelerating shared buses on a die for multi-channel communication

Abstract

A shared bus for inter-channel communication includes two or more channels, each having a signal processing element configured to receive and process a received channel-specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of the channels. An error checker is configured to check for errors in the received channel-specific signal. The shared bus connects to the two or more channels for transmitting the received channel-specific signal to the error checker and transmitting the test sequence to the signal processing elements of the channels. One or more pull-up and / or termination resistors connect to the shared bus. The bus includes a clock signal path and a data signal path. The test sequence is a pseudo-random bit sequence. The bus interface includes open-collector current mode logic drivers in a cascode arrangement.

Description

Technical Field

[0001] This invention relates to communication between channels, and more particularly to a shared bus for use during error checking and test signal generation.

Background Art

[0002] Functionality and complexity are continuously added to semiconductors. To increase test efficiency, end users require built-in diagnostic functions to quickly debug the end user's system without deploying or connecting complex and expensive test equipment. In a data center, this means that a low-performance link can be broken, a known data pattern such as a pseudo-random bit sequence (PRBS) generator can be introduced, and bit errors at various positions can be checked to properly debug the link.

Summary of the Invention

Problems to be Solved by the Invention

[0003] FIG. 1 shows a typical prior art of a multi-channel communication system integrating diagnostic elements together. This embodiment is an example in an optical communication system having channels 104A, 104B, 104C, and 104D shown in FIG. 1. Each channel may include a transmitter and a receiver for performing data transmission of transmission and reception. An electrical signal is supplied to the electrical elements of the receiver. For example, at input 108, an electrical signal from a photodetector and a transimpedance amplifier (not shown) is supplied to an AFE (Analog Front End) 112 that processes an analog signal and converts it into a digital signal. The digital signal is provided to a CDR (Clock Data Recovery) circuit 116 that regenerates the clock and data. Both the clock and the data are provided to a driver 120 configured to amplify the signal for downstream components.

[0004] The diagnostic elements are represented by sequence generators 124 and error checkers 128, each connected to the driver 120 via two paths 132 and 136. These paths 132 and 136 are high-speed paths and therefore must be dimensionally configured to handle high-speed operation. A sequence generator 124 and an error checker 128 are provided associated with each channel. Thus, the system in Figure 1 has four sequence generators 124 and four error checkers 128. While this system is acceptable as a conventional system with a channel pitch of 750 μm, this physical arrangement becomes impossible when the available area is limited due to the combined size of the signal paths and diagnostic elements. For example, the diagnostic system requires approximately two-thirds of the available area.

[0005] On the other hand, die size, and especially channel pitch, are not expected to increase. These factors must conform to industry standard components (optical channel pitch is only 250 μm). Even current-generation datacom chips, which integrate CDR functionality for electrical-to-optical (E to O) and vice versa (O to E) conversions, have a more stretched die size (2:1 ratio), leaving no room for a diagnostic block. The diagnostic block is an elaborate subsystem and therefore large, which is often overlooked but deserves more attention. As shown below in Figure 2, the diagnostic elements must be moved to the side. This creates a new problem of transmitting high-speed data back and forth.

[0006] Figure 2 shows an alternative prior art design when the allocated channel width per channel is 250 μm. In this layout, the diagnostic elements 204,208 are moved outside the channels, thereby requiring two communication paths per channel, resulting in a total of 16 pairs of controlled impedance traces (communication paths) (two for the NRZ stream), which must be of a size that allows for high-speed communication to reach each channel 104A, 104B, 104C, and 104D. These signal trace paths must travel a distance of millimeters that requires impedance-controlled transmission lines. Each channel has two different pairs connected to diagnostic elements 204,208 dedicated to that channel. Thus, each channel is provided with associated diagnostic elements 204,208. In a 4-channel system, four sets of diagnostic elements 204,208 are provided, such that each channel 104A, 104B, 104C, and 104D has associated diagnostic elements 204,208. This configuration may consume space, power resources, and the allocated space for the given narrow channel width, potentially making it impossible to mount on the die.

[0007] While it is known that it includes built-in diagnostic features, the transition to the new multilevel modulation scheme (from NRZ to PAM-4) significantly increases complexity and exacerbates the problem. On the chip, this requires multiple parallel high-speed paths that necessitate a significant amount of space. For example, at 30 Gb / s, each path would be 30 μm wide to avoid unwanted loss of signal quality. This path size is duplicated eightfold, resulting in a total path width that consumes unwanted space and would not fit within the allocated 250 μm channel width. [Means for solving the problem]

[0008] To overcome the shortcomings of prior art and provide additional benefits, a shared bus for inter-channel communication is disclosed.

[0009] In one embodiment, a shared bus for inter-channel communication includes two or more channels having signal processing elements. Each channel is configured to receive and process a received channel identification signal. A sequence generator is configured to generate an appropriate test sequence for testing the channel's signal processing elements. An error checker is provided and configured to perform error checking of the received channel identification signal. The shared bus is connected to two or more channels for transmitting the received channel identification signal to the error checker and for transmitting the test sequence to the channel's signal processing elements. This embodiment also includes one or more loads connected to the shared bus. The loads may be one or more resistors, one or more resistors and a peaking inductor, or other types of loads.

[0010] In one embodiment, the bus is formed by a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The size, location, and number of loads (such as pull-up resistors) are selected to optimize reflection and jitter. In one embodiment, an error checker is configured to compare a received channel identification signal with a known channel identification signal generated by a sequence generator in order to detect errors. In one embodiment, each channel has a bus interface that includes an open collector current-mode logic driver in a cascode array.

[0011] Furthermore, a method for inter-channel communication via a shared bus is disclosed. One embodiment of this method includes the step of initializing the error checking mode of a selected channel. Another embodiment of this method includes the step of enabling the transmission or reception of data via the shared bus for the selected channel and the step of disabling the transmission or reception of data via the shared bus for channels that are not selected. Another embodiment of this method includes the step of generating sequence data using a sequence generator and the step of transmitting the sequence data from the sequence generator to the selected channel via the shared bus. Another embodiment of this method subsequently includes the step of processing the sequence data using data selected to generate processed sequence data and the step of checking for errors in the processed sequence data by comparing the processed sequence data with the sequence data.

[0012] In one embodiment, the bus comprises a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The size, position, and number of loads are selected to optimize reflection and jitter. In the method of claim 7, the error checker is configured to compare a received channel identification signal with a known channel identification signal generated by a sequence generator in order to detect an error. In one configuration, each channel has a bus interface that includes an open-collector current-mode logic driver in a cascode array.

[0013] Furthermore, an inter-channel communication system including two or more data communication channels is disclosed, each data communication channel having a data processing unit. A bus driver is associated with each channel so that the bus driver is configured to occupy or release the bus, and to transmit or receive data over the shared bus. The shared bus is connected to the bus driver associated with each channel so that the shared bus is also connected to at least one error checker and a sequence generator configured to generate sequence data.

[0014] As discussed below, the shared bus is a two-conductor bus consisting of a clock signal path and a data signal path. A sequence generator is configured to generate a pseudo-random bit sequence, and transmission over the shared bus may occur using a bus driver associated with the sequence generator. The system may further include two or more pull-up resistors connected to the shared bus. In one configuration, an error checker is configured to process the sequence data generated by the sequence generator after it has been processed by the data processing unit in order to detect errors. The system may also include one or more termination resistors connected to the shared bus to reduce reflections and jitter.

[0015] Other systems, methods, features, and advantages of this invention will become apparent to those skilled in the art through consideration of the following drawings and detailed description. All such additional systems, methods, features, and advantages are included in this description, are within the scope of this invention, and are intended to be protected by the appended claims.

[0016] The configurations shown in the drawings do not need to be scaled; instead, the focus is on illustrating the principle of the invention. The same reference numerals in the drawings indicate corresponding parts in different drawings. [Brief explanation of the drawing]

[0017] [Figure 1]This diagram shows representative prior art for multi-channel communication systems that integrate diagnostic elements. [Figure 2] This figure shows an alternative prior art design when the allocated channel width per channel is 250 μm. [Figure 3] This figure shows typical usage environments. [Figure 4] This figure shows an example of a layout for high-speed communication between a diagnostic element and multiple communication channels. [Figure 5] Figure 4 shows a typical high-speed communication system. [Figure 6A] This diagram shows a typical driver circuit. [Figure 6B] This diagram shows a typical end-to-end driver circuit with an interconnection bus. [Figure 7] This figure shows the bus layout geometry of a die equipped with multiple optical modules. [Figure 8] This figure shows a typical signal plot obtained as a result of high-speed communication via a diagnostic signal bus. [Modes for carrying out the invention]

[0018] Figure 3 shows a typical usage environment. In this embodiment, the first host 304 generates or receives data to be transmitted to a remote location such as the second host 328. The first host 304 processes the data and prepares it for transmission before supplying it to the first optical module 312. The data from the first host 304 travels to the first optical module 312 as an electrical signal via the electrical channel 308.

[0019] The first optical module 312 converts an electrical signal indicating data into an optical signal that is transmitted to the second optical module 320 via an optical channel 316 such as an optical fiber cable. In the second optical module, the optical signal is converted into an electrical signal that is provided to the second host 328 via an electrical channel 324. The second host 328 regenerates and repairs the data after movement from the remote first host 304 and provides the data for use by subsequent processing elements. In this processing path, the data transmitted from the second host 328 to the first host 304 is processed in reverse order. Although shown in the form of an optical communication system, it is also contemplated that the innovative techniques disclosed below may be utilized in electrical or wireless communication environments.

[0020] FIG. 4 shows an example layout of high-speed communication between a diagnostic element and a plurality of communication channels. Other configurations per se other than this one example are possible within the scope not departing from the claims. In this example, only 250 μm is allocated as the width of each channel, and the layout thus shown solves the reasons made clear in the background art section. There are AFE 430, CDR 432, and driver 436 that consume die area within this width, leaving no room for the large pattern generator 412 and error detection module ́408. Therefore, the pattern generator 412 and error detection module 408 are shared among the plurality of channels 404. A two-path shared bus 424 having a data path 416 and a clock path 420 connects each of the channels 404A, 404B, 404C, 404D to the pattern generator 412 and the error detection module 408. Inside each of the channels 404A, 404B, 404C, 404D, the pattern generator 412, and the error detection module 408, drivers for transmitting and receiving data and being synchronized by a clock are provided.

[0021] This example has several advantages over the prior art shown in FIGS. 1 and 2. From the four sequence generators and four error checkers in FIG. 1, each channel Sequence generator 412 and error checkerArea savings are achieved by reducing the number of systems until sharing with 408. This is a significant reduction in area requirements. When reducing the allocated channel width to 250 μm, it becomes possible to fit the system on the die. Compared to the system of FIG. 2, only two conductive paths 416, 420 are required instead of eight large paths (two for each channel to the diagnostic element). This reduces the layout complexity, signal combinations, and size requirements (2 paths vs. 8 paths in FIG. 2).

[0022] FIG. 5 shows a representative high-speed communication system of FIG. 4. In relation to FIG. 4, 404A of channel 0, 404B of channel 1, 404C of channel 2, and 404D of channel 3 are shown. Channel drivers 508A, 508B, 508C, 508D connected to the shared bus 424 are associated with each channel. Although shown as a single line, bus 424 includes two conductive paths. Also, a diagnostic system driver 512 connected to the sequence generator 412 and the error checker 408 is connected to bus 424. The diagnostic system driver 512 interfaces the sequence generator 412 and the error checker 408 with the bus 424. Drivers 520, 508 have the function of supplying signals through the channels. The sequence generator 412 and the error checker 408 share driver 520, although it is also considered that the generator and the checker each have their own driver.

[0023] Each end of the bus 424 is provided with an adjustable termination element 504. The termination element 504 includes some kind of resistor or impedance configured to match the impedance of the bus 424. The impedance of the termination element 504 and its matching to the bus 424 may be selected to minimize reflection, minimize power loss, or mitigate jitter. Therefore, in some embodiments, the resistance or impedance of the termination element 504 is not precisely matched to the resistance or impedance of the bus 424. The termination element 504 may be adjustable and may consist of a resistor, a MOS switch, other elements, or a group of elements. Also, as shown in Figure 5, one or more loads 530 may be, for example, multiple pull-up resistors configured to reduce reflection and jitter. These loads 530 are selectively and strategically placed and sized based on testing to adapt to high-frequency operation, such as operation at 30 Gb / s. The number of loads 530 may be located at several positions along the bus 424. An optimized algorithm is used to derive the position, number, and value of load 530.

[0024] During operation, Sequence The generator 412, the error checker 408, or both may be operational. In error detection mode, received data is provided to a specific channel, such as 404B of channel 1. To determine if this received data has an error, the data is sent to the error checker 408 via bus 424 using the driver 508B of channel 1, and the error checker 408 checks for errors in the received data. If the sequence generator 412 is running, the sequence generator generates a sequence that is sent to bus 424 using the diagnostic system driver 520. From bus 424, the sequence is sent to the requested channel 404. Either channel can be selected via a resistor setting and a local switch. On a common channel, the sequence generator and the error checker cannot both be running simultaneously, nor can they be requested by the application.

[0025] Figure 6A shows a typical driver circuit. This is only one possible configuration for the driver circuit. In this embodiment, the driver circuit is a cascode array open collector current-mode logic (CML) driver using bipolar technology. Other technologies such as CMOS, BiCMOS, or HBT may be used without departing from the scope of the invention. The driver die 604 includes the circuit shown. A resistor 612 is connected between the voltage node 608 and the driver and is connected by a bus 616. The driver includes a first transistor 624 and a second transistor 628 arranged in a cascode configuration. Transistor 624 has a base connected to the voltage node 620 and a collector connected to the opposite terminal of resistor 612. Its emitter terminal is also connected to capacitor 636A, and capacitor 636A has an opposite terminal connected to a reference ground. Capacitor 636A is smaller in size than capacitor 636B. Capacitor 636A offers the benefit of reducing or eliminating discontinuities as its size decreases, but can become a source of unwanted reflections. The emitter of transistor 624 is connected to the collector terminal of transistor 628 as shown. The base of transistor 628 is connected to voltage node 620, while its emitter terminal is connected to ground via resistor 632. This configuration isolates the sensitive node (bus node 616) from node 640.

[0026] Figure 6B shows a typical die-to-die communication system using the associated driver. This embodiment shows a bus 616 interconnecting the first die 640 and the second die 644. The dies may include channels for processing elements, or they may be part of an error checker or sequence generator. A pull-up resistor 612 is also shown connected to the bus 616 and a voltage node 608. The second die 644 is configured to use a transmit start subcircuit 648 and a transmit stop subcircuit 652 in transmit mode. The signal 654 to be transmitted to the bus 616 is input 658The current source 660 is activated when power is supplied. During the transmit-stop mode, the current source 662 is shut off and input 664 is connected to ground.

[0027] During receive-start mode, the first die 640 receives signal 670 through bus 616 and supplies it to output 672. During receive-start mode, current source 674 is activated. During receive-off mode, current source 680 is turned off. Figure 6B shows one typical circuit of the driver and bus system, and it should be considered that other circuit configurations may be generated deviating from this exact circuit but will not deviate from the claims.

[0028] Figure 7 shows the bus layout geometry of a die using multiple optical subsystems. This is only one possible bus layout, and other embodiments themselves are possible without departing from the scope of the following claims. Elements described above or known in the prior art are not described in detail, but instead focus on new perspectives. The illustrated die 704 consists of four channels referred to as channel 0, channel 1, channel 2, and channel 3. This system may be configured as a transmitter or receiver, although this is a general definition. Optical fibers 716A, 716B, 716C, and 716D connect to or supply signals to die 704, sending optical signals to the optical subsystems 704A, 704B, 704C, and 704D of each channel. The optical subsystems 704A, 704B, 704C, and 704D convert the optical signals into electrical signals that are provided to the electrical subsystems 708A, 708B, 708C, and 708D when the system is configured as a receiver. An example of such an optical subsystem is a photodetector coupled with a transimpedance amplifier (TIA). Electrical subsystems 708A, 708B, 708C, and 708D process signals to regenerate clock and data signals provided from outputs 740A, 740B, 740C, and 740D to downstream elements. If configured as a transmitter, the electric subsystem 708 prepares data for transmission, supplies the data to the optical subsystem 704, and transmits the data through the optical fiber 716. Examples of such optical subsystems include, but are not limited to, modulator drivers using silicon photonic components or laser drivers using lasers. Other embodiments are possible.

[0029] The shared diagnostic subsystem 712 is illustrated in relation to each channel. A new bus routing method is shown such that the data path 730, utilized by the shared diagnostic subsystem 712, is located beneath the mains power pad ring 720 or the ground pad ring 724. Similarly, the clock path 734, utilized by the shared diagnostic subsystem 712, is located beneath the mains power pad ring 720 or the ground pad ring 724. As illustrated, the data path 730 and the clock path 734 connect to each illustrated channel.

[0030] The data path 730 and the clock path 734 are connected to the ground padding 724 and Main power supply Placing the ground padding ring 724 and power padding ring 720 below the padding ring 720 offers several advantages. The data path 730 and clock path 734 are high-speed communication paths that themselves require controlled impedance traces and occupy a large amount of space due to the wavelength of the signals traveling along these paths. One such advantage is that the space is currently unused and the ground padding ring 724 and power padding ring 720 have ideally low impedance for use as references for the transmit lines. Furthermore, this region generally has ample space for the size of the data path 730 and clock path 734 without signal interference.

[0031] Figure 8 shows typical signal plots obtained as a result of high-speed communication through the diagnostic signal bus. These plots show eye diagrams of recovered data, which are sent to an error checker or transmitted through the bus used by a diagnostic system communicating with each channel. Plot 800 is shown by ATLC electromagnetic analysis modeling software. As can be seen from these plots, the data signals, generated sequence signals, and clock signals are properly recovered after being transmitted through the bus.

[0032] Since various embodiments of this invention are described, it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of this invention. In addition, the various features, elements and embodiments described below may be described in the claims, or combined in several combinations or arrangements.

Claims

1. A shared bus for inter-channel communication, It comprises two or more channels having signal processing elements, Each channel is configured to receive and process a channel-specific signal. The shared bus for inter-channel communication is A sequence generator configured to generate a suitable test sequence for testing the signal processing elements of a channel, An error checker configured to perform error checking on the received channel identification signal, The system further comprises a shared bus connected to the two or more channels, The aforementioned shared bus, The receiving channel identification signal is transmitted to the error checker. The test sequence is transmitted to the signal processing element of the channel, The shared bus for inter-channel communication is A shared bus for inter-channel communication further comprising one or more electrical load circuits connected to the shared bus.

2. The shared bus for inter-channel communication according to claim 1, wherein the shared bus is formed by a clock signal path and a data signal path.

3. The shared bus for inter-channel communication according to claim 1, wherein the test sequence is a pseudo-random bit sequence.

4. The aforementioned electrical load circuit is selected to optimize reflection and jitter. The shared bus for inter-channel communication according to claim 1, wherein the electrical load circuit includes an active load comprising one or more resistors, a combination of one or more peaking inductors and resistors, or one or more active devices not limited to bipolar or HBT CMOS transistors.

5. The error checker compares the received channel identification signal with a known channel identification signal generated by the sequence generator in order to detect an error. A shared bus for inter-channel communication according to claim 1, configured as described above.

6. A shared bus for inter-channel communication according to claim 1, wherein each channel has a bus interface including an open-collector current-mode logic driver in a cascode array.

7. A method of communication between channels via a shared bus, A step to initialize the error checking mode for the selected channel, The steps include enabling the transmission or reception of data via the shared bus for the selected channel, The steps include disabling the transmission or reception of data via the shared bus for channels that are not selected, The steps include generating sequence data using a sequence generator, The steps include transmitting the sequence data via the shared bus to the channel selected from the sequence generator, A step of processing the sequence data using data via the shared bus for the channel selected to generate the processed sequence data, A communication method comprising the step of checking for errors in the processed sequence data by comparing the processed sequence data with the sequence data.

8. The communication method according to claim 7, wherein the shared bus is formed by a clock signal path and a data signal path.

9. The communication method according to claim 7, wherein the sequence data is a pseudo-random bit sequence.

10. The communication method according to claim 7, wherein the size, location, and number of pull-up resistors connected to the shared bus are selected to optimize the reflection and jitter of signals transmitted on the shared bus.

11. The communication method according to claim 7, wherein the error checker is configured to compare a received channel identification signal with a known channel identification signal generated by the sequence generator in order to detect an error.

12. The communication method according to claim 7, wherein each channel has a bus interface including an open-collector current-mode logic driver in a cascode array.

13. A communication system between channels, Two or more data communication channels, each having a data processing unit, Each channel is equipped with a bus driver associated with it, The aforementioned bus driver, Connect to or disconnect from the bus, Configured to send or receive data via a shared bus, The shared bus is connected to the bus driver associated with each channel, The shared bus also connects to at least one of an error checker and a sequence generator configured to generate sequence data, and is part of a communication system.

14. The communication system according to claim 13, wherein the shared bus is two conductive buses consisting of a clock signal path and a data signal path.

15. The communication system according to claim 13, wherein the sequence generator is configured to generate a pseudo-random bit sequence and to transmit the pseudo-random bit sequence via the shared bus using a bus driver associated with the sequence generator.

16. The communication system according to claim 13, further comprising two or more pull-up resistors connected to the shared bus.

17. The communication system according to claim 13, wherein the error checker is configured to process the sequence data generated by the sequence generator after it has been processed by the data processing unit in order to detect an error.

18. The communication system according to claim 13, wherein the bus driver includes an open-collector current-mode logic driver in a cascode array.

19. The communication system according to claim 13, wherein the communication system includes one or more termination resistors connected to a shared bus to reduce reflection and jitter.

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