Array substrate and display panel

Abstract

The array substrate includes a substrate and a first conductive layer, a second conductive layer, a first insulating layer, and an oxide active layer provided on the substrate. The first conductive layer includes a source and a light-shielding electrode provided at intervals, the second conductive layer includes a barrier electrode connected to the source, the first insulating layer includes a first via provided corresponding to the source, and the oxide active layer includes a channel portion and a source contact portion located on one side of the channel portion, a portion of which is provided within the first via and connected to the barrier electrode. The barrier electrode is connected between the source contact portion and the source and corresponds to the first via, avoiding direct contact between the source contact portion and the source, and the barrier electrode prevents the diffusion of metal elements from the source to the source contact portion. [Effect] This method prevents metal elements in the source from diffusing into the oxide active layer and forming impurities at deep energy levels, which can degrade the performance of the device and affect its performance and bias temperature stress characteristics.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate and a display panel.

Background Art

[0002] In the field of display technologies, a thin film transistor (TFT) array substrate is an important component of a display panel. On the other hand, the manufacture of a thin film transistor array substrate involves a plurality of photo masks. The more photo masks are used, the longer, more difficult, and more costly the overall process flow of the thin film transistor array substrate becomes. In order to reduce the number of photo masks used, the source of the thin film transistor is placed below the oxide active layer, and the oxide active layer is stacked and connected to the underlying source. However, this stacking connection method causes performance degradation of the elements of the thin film transistor and affects the element performance and bias temperature stress (BTS) characteristics.

Summary of the Invention

Problems to be Solved by the Invention

[0003] This application provides an array substrate and a display panel to mitigate the conventional technical problem of performance degradation of the elements of a thin film transistor due to the stacking connection method between the oxide active layer and the source.

Means for Solving the Problems

[0004] In order to solve the above-mentioned problems, the technical solution provided in this application is as follows.

[0005] An embodiment of this application provides an array substrate, and the array substrate includes a substrate, and a first conductive layer provided on one side of the substrate and including a source and a light-shielding electrode provided at intervals, A second conductive layer is provided on the side of the first conductive layer away from the substrate, and includes a barrier electrode, the barrier electrode being connected to the source, A first insulating layer provided on the side of the first conductive layer away from the substrate and including a first via provided corresponding to the source, An oxide active layer provided on the side of the first insulating layer away from the substrate, comprising a channel portion and a source contact portion located on one side of the channel portion, wherein in the thickness direction of the array substrate, the channel portion is provided corresponding to the light-shielding electrode, a portion of the source contact portion is provided within the first via and connected to the barrier electrode, the barrier electrode is connected between the source contact portion and the source and provided corresponding to the first via, and the barrier electrode is configured to prevent the diffusion of a metal element in the source to the source contact portion, A second insulating layer is provided on the side of the oxide active layer away from the substrate and corresponding to the channel portion, The material includes a third conductive layer provided on the side of the second insulating layer away from the substrate and including a gate provided corresponding to the channel portion.

[0006] In the array substrate provided in the embodiment of the present application, the barrier electrode covers the surface of the source away from the substrate, the first insulating layer covers a portion of the barrier electrode, and the first via is provided in the first insulating layer at a position corresponding to the barrier electrode, and the source contact portion is connected to the barrier electrode exposed by the first via.

[0007] In the array substrate provided in the embodiment of the present application, the orthographic projection of the barrier electrode on the substrate coincides with the orthographic projection of the source on the substrate.

[0008] In the array substrate provided in the embodiment of the present application, the second conductive layer further includes a sub-electrode provided corresponding to the light-shielding electrode, the sub-electrode covering the surface of the light-shielding electrode away from the substrate, and the first insulating layer covering the sub-electrode and the gap between the light-shielding electrode and the source.

[0009] In the array substrate provided in the embodiment of the present application, the first insulating layer covers a portion of the source, the light-shielding electrode, and the space between the light-shielding electrode and the source, the portion of the source is exposed by the first via, the barrier electrode is located within the first via and connected to the source exposed by the first via, and the source contact portion covers the barrier electrode within the first via.

[0010] In the array substrate provided in the embodiment of the present application, the barrier electrode extends from within the first via to the surface of the first insulating layer away from the substrate, and the source contact portion further covers the barrier electrode located outside the first via.

[0011] In the array substrate provided in the embodiment of the present application, the orthographic projection of the opening on the source side of the first via on the substrate is within the range of the orthographic projection of the barrier electrode on the substrate.

[0012] In the array substrate provided in the embodiment of the present application, the thickness range of the film layer of the second conductive layer is 100 angstroms to 800 angstroms.

[0013] In the array substrate provided in the embodiments of the present application, the material of the second conductive layer comprises one of molybdenum, titanium, a molybdenum-titanium alloy, and indium tin oxide.

[0014] In the array substrate provided in the embodiment of the present application, the first conductive layer comprises a bonding layer and a main conductive layer located on the side of the bonding layer away from the substrate, wherein the material of the bonding layer comprises one of molybdenum, titanium, or a molybdenum-titanium alloy, and the material of the main conductive layer comprises copper.

[0015] In the array substrate provided in the embodiment of the present application, the oxide active layer further includes a drain contact portion located away from the source contact portion of the channel portion, and the array substrate is A third insulating layer provided on the side of the third conductive layer away from the substrate, A planarization layer provided on the side of the third insulating layer away from the substrate, A common electrode provided on the side of the planarized layer away from the substrate, A fourth insulating layer is provided on the side of the common electrode away from the substrate and includes a second via provided corresponding to the drain contact portion, The fourth insulating layer further includes a pixel electrode provided on the side away from the substrate, a portion of which is located within the second via, and which is connected to the drain contact portion.

[0016] The embodiments of the present application further include a display panel, the display panel including an array substrate according to one embodiment of the embodiments described above. [Effects of the Invention]

[0017] In the array substrate and display panel provided in the present application, the array substrate includes a substrate, a first conductive layer, a second conductive layer, a first insulating layer, and an oxide active layer provided on the substrate. The first conductive layer includes a source, the second conductive layer includes a barrier electrode connected to the source, the first insulating layer includes a first via provided corresponding to the source, a part of the source contact portion of the oxide active layer is provided in the first via and is connected to the barrier electrode. The barrier electrode is connected between the source contact portion and the source and is provided corresponding to the first via to avoid direct contact between the source contact portion and the source. On the other hand, the barrier electrode can prevent the diffusion of the metal element in the source to the source contact portion, thereby avoiding the metal element in the source diffusing into the oxide active layer to form impurities at deep energy levels and causing performance degradation of the device, which affects the device performance and bias temperature stress characteristics, and ultimately improves the stability of the device.

Brief Description of the Drawings

[0018] To more clearly explain the technical solutions in the embodiments or the prior art, the necessary drawings in the description of the embodiments or the prior art will be briefly described below. Obviously, the drawings related to the following description are merely some embodiments of the invention, and it is clear that those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0019] [Figure 1] This is a preamble related to an embodiment of the present application, which provides an array substrate. [Figure 2] It is a schematic diagram showing a cross-sectional configuration of the array substrate provided in the embodiment of the present application. [Figure 3] It is a schematic diagram showing another cross-sectional configuration of the array substrate provided in the embodiment of the present application. [Figure 4] It is a schematic diagram showing another cross-sectional configuration of the array substrate provided in the embodiment of the present application. [Figure 5]It is a schematic diagram showing another cross-sectional configuration related to the array substrate provided in the embodiment of the present application.

Embodiments for Carrying Out the Invention

[0020] The following description of each embodiment is made with reference to the accompanying drawings to illustrate specific embodiments in which the present application can be implemented. Terms indicating directions referred to in the present application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side surface", etc., refer only to the directions related to the accompanying drawings. Therefore, the terms indicating the directions used are for explaining and understanding the present application and are not intended to limit the present application. In the drawings, parts with similar configurations are denoted by the same reference numerals. Also, in the drawings, the thicknesses of some layers and regions are exaggerated for the sake of clear understanding and ease of explanation. That is, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0021] Regarding the problem of performance degradation of the thin-film transistor element due to the overlapping method between the oxide active layer and the source, the inventor of the present application has found the following through research. Referring to FIG. 1, FIG. 1 is a prelude to the embodiment of the present application, which provides an array substrate. The array substrate includes a substrate 10', a first insulating layer 11' provided on the substrate 10', a source 21', and an oxide active layer 40'. A part of the oxide active layer 40' is located in the first via of the first insulating layer 11' and overlaps the source 21'. The material of the source 21' is copper. Compared with aluminum, copper has a lower resistivity. However, copper is easy to diffuse and is likely to cause copper contamination. At the position of direct contact between the oxide active layer 40' and the source 21', the copper metal element of the source 21' diffuses into the oxide active layer 40', forming impurities with deep energy levels in the oxide active layer 40', leading to performance degradation of the thin-film transistor element and affecting the characteristics and bias temperature stress (BTS) characteristics of the element.

[0022] Therefore, this application provides an array substrate and a display panel.

[0023] Referring to Figure 2, Figure 2 is a schematic diagram showing a cross-sectional configuration of an array substrate provided in an embodiment of the present application.

[0024] The array substrate 100 includes a substrate 10 and a first conductive layer 20, a second conductive layer 30, a first insulating layer 11, an oxide active layer 40, a second insulating layer 12, and a third conductive layer 50 provided on the substrate 10. The first conductive layer 20 is provided on one side of the substrate 10 and includes a spaced-apart source 21 and a light-shielding electrode 22. The second conductive layer 30 is provided on the side of the first conductive layer 20 away from the substrate 10 and includes a barrier electrode 31, the barrier electrode 31 being connected to the source 21. The first insulating layer 11 is provided on the side of the first conductive layer 20 away from the substrate 10 and includes a first via 111 provided corresponding to the source 21.

[0025] The oxide active layer 40 is provided on the side of the first insulating layer 11 away from the substrate 10 and includes a channel portion 41 and a source contact portion 42 located on one side of the channel portion 41. In the thickness direction of the array substrate 100, the channel portion 41 is provided corresponding to the light-shielding electrode 22. In this application, "provided correspondingly" refers to the correspondence between two components in the thickness direction of the array substrate 100. The material of the oxide active layer may be indium gallium zinc oxide IGZO, indium gallium zinc tin oxide IGZTO, indium gallium oxide IGO, indium zinc oxide IZO, lanthanide IZO, etc.

[0026] A portion of the source contact portion 42 is provided within the first via 111 and connected to the barrier electrode 31, which is connected between the source contact portion 42 and the source 21 and is provided corresponding to the first via 111, thereby electrically connecting the source contact portion 42 to the source 21 by the barrier electrode 31. The barrier electrode 31 is configured to prevent the diffusion of metal elements from the source 21 to the source contact portion 42.

[0027] It should be noted that the connection described in this application differs from an electrical connection. Here, the connection described refers to two components being in direct contact, while an electrical connection refers to two components being electrically connected by the other component. For example, the connection of the source contact portion 42 to the barrier electrode 31 means that the source contact portion 42 is in direct contact with the barrier electrode 31, while the electrical connection of the source contact portion 42 to the source 21 means that the source contact portion 42 is electrically connected to the source 21 by the barrier electrode 31, but the source contact portion 42 is not in direct contact with the source 21.

[0028] The second insulating layer 12 is provided on the side of the oxide active layer 40 away from the substrate 10 and is provided in the thickness direction of the array substrate 100 corresponding to the channel portion 41. The third conductive layer 50 is provided on the side of the second insulating layer 12 away from the substrate 10 and includes a gate 51 provided corresponding to the channel portion 41.

[0029] In this embodiment, the source contact portion 42 is electrically connected to the source 21 by the barrier electrode 31, thereby avoiding direct contact between the source contact portion 42 and the source 21. On the other hand, the barrier electrode 31 can prevent the diffusion of metal elements in the source 21 into the source contact portion 42. As a result, the metal elements in the source 21 can diffuse into the oxide active layer 40 and form impurities at deep energy levels, which would lead to a degradation of the device's performance and affect the device's performance and bias temperature stress characteristics. This prevents such degradation and ultimately improves the stability of the device.

[0030] Specifically, the array substrate 100 further includes a first transistor provided on the substrate 10. The first transistor may be a thin-film transistor. The first transistor includes a source 21, an oxide active layer 40, and a gate 51. The oxide active layer 40 is provided on the side of the source 21 away from the substrate 10, and the gate 51 is provided on the side of the oxide active layer 40 away from the substrate 10, that is, the oxide active layer 40 is provided on the side of the source 21 away from the substrate 10, and the gate 51 is provided on the side of the oxide active layer 40 away from the substrate 10. The oxide active layer 40 includes a channel portion 41 and a source contact portion 42 located on one side of the channel portion 41. Of course, the oxide active layer 40 further includes a drain contact portion 43 located on the side of the channel portion 41 away from the source contact portion 42. That is, the drain contact portion 43 and the source contact portion 42 are located on opposite sides of the channel portion 41. Here, the gate 51 is provided opposite the channel portion 41, and the orthographic projection of the gate 51 on the substrate 10 coincides with the orthographic projection of the channel portion 41 on the substrate 10.

[0031] Optionally, the substrate 10 may be a rigid substrate or a flexible substrate. If the substrate 10 is a rigid substrate, it may be a rigid substrate such as a glass substrate, a quartz substrate, or a silicon chip. If the substrate 10 is a flexible substrate, it may be a flexible substrate such as a polyimide (PI) thin film or an ultrathin glass thin film. If the substrate 10 is polyimide, moisture and oxygen penetrate the substrate 10 more easily than a glass substrate. To prevent this, a buffer layer having a single-layer or multilayer structure containing silicon oxide or silicon nitride may be provided on the substrate 10.

[0032] The first conductive layer 20 is provided on the substrate 10. The first conductive layer 20 includes a spaced-apart and insulating source 21 and a light-shielding electrode 22. The light-shielding electrode 22 is provided at least in correspondence with the channel portion 41 to shield the channel portion 41 from light and reduce the light-induced leakage current of the first transistor. The first conductive layer 20 includes a coupling layer 201 and a main conductive layer 202 located on the side of the coupling layer 201 away from the substrate 10, that is, both the source 21 and the light-shielding electrode 22 include the coupling layer 201 and the main conductive layer 202.

[0033] The thickness of the main conductive layer 202 is greater than the thickness of the bonding layer 201. The material of the bonding layer 201 includes one of molybdenum, titanium, or a molybdenum-titanium alloy, and the material of the main conductive layer 202 includes copper. Since copper has low tackiness and is difficult to bond directly to the glass substrate or silicon oxide group, by providing the bonding layer 201 in the first conductive layer 20, the bonding layer 201 can increase the tackiness between the main conductive layer 202 and the substrate 10, and the bonding layer 201 can prevent the diffusion of copper metal elements in the main conductive layer 202 into the substrate 10, thereby avoiding contamination of the substrate 10.

[0034] The second conductive layer 30 is provided on the side of the first conductive layer 20 away from the substrate 10. A barrier electrode 31 is formed on the second conductive layer 30, corresponding to the source 21. The barrier electrode 31 covers the surface of the source 21 on the side away from the substrate 10.

[0035] For ease of explanation, this application defines the surface of each component away from the substrate 10 as the upper surface, the surface opposite the upper surface as the lower surface, and the material connecting the upper surface and the lower surface as the side wall. For example, the surface of the source 21 away from the substrate 10 is the upper surface of the source 21, the surface opposite the upper surface of the source 21 is the lower surface of the source 21, the lower surface of the source 21 is in contact with the substrate 10, and the material connecting the upper and lower surfaces of the source 21 is the side wall of the source 21. For example, the surface of the barrier electrode 31 away from the substrate 10 is the upper surface of the barrier electrode 31, the surface opposite the upper surface of the barrier electrode 31 is the lower surface of the barrier electrode 31, the lower surface of the barrier electrode 31 is in contact with the source 21, and the material connecting the upper and lower surfaces of the barrier electrode 31 is the side wall of the barrier electrode 31. The orthographic projection of the barrier electrode 31 on the substrate 10 overlaps with the orthographic projection of the source 21 on the substrate 10. As a result, the same photomask can be used when forming the barrier electrode 31 and the source 21 by patterning, thereby reducing the number of photomasks and lowering costs.

[0036] The material of the second conductive layer 30 has properties such as having weaker diffusion performance than copper and being conductive. For example, the material of the second conductive layer 30 is one of molybdenum, titanium, molybdenum-titanium alloy, indium tin oxide, etc. The thickness of the film layer of the second conductive layer 30 is smaller than the thickness of the film layer of the first conductive layer 20 and also smaller than the thickness of the film layer of the main conductive layer 202. The thickness of the film layer of the second conductive layer 30 is in the range of 100 angstroms to 800 angstroms, and may be, for example, 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, etc. If the thickness of the second conductive layer 30 is less than 100 angstroms, the barrier electrode 31 formed by the second conductive layer 30 will not effectively block the diffusion of metal elements in the source 21. If the thickness of the second conductive layer 30 is greater than 800 angstroms, it will affect the conductivity of the source 21, resulting in the formation of a topography with significant undulations.

[0037] Optionally, the second conductive layer 30 is provided with a sub-electrode 32 at a position corresponding to the light-shielding electrode 22. The sub-electrode 32 covers the surface of the light-shielding electrode 22 away from the substrate 10, preventing the diffusion of metallic elements from the light-shielding electrode 22 into the first insulating layer 11. The orthographic projection of the sub-electrode 32 on the substrate 10 overlaps with the orthographic projection of the light-shielding electrode 22 on the substrate 10, thereby allowing the same photomask to be used when patterning and forming the sub-electrode 32 and the light-shielding electrode 22, thereby reducing the number of photomasks and lowering costs.

[0038] The first insulating layer 11 covers the second conductive layer 30 and the substrate 10. Specifically, the first insulating layer 11 covers the upper surface and sidewall of the barrier electrode 31, the sidewall of the source 21, the upper surface and sidewall of the sub-electrode 32, the sidewall of the light-shielding electrode 22, the gap between the light-shielding electrode 22 and the source 21, and the substrate 10. Here, the first insulating layer 11 covering the upper surface of the barrier electrode 31 has the first via 111 formed at a position corresponding to the source 21, and the first via 111 exposes a part of the barrier electrode 31, that is, the first insulating layer 11 covers a part of the barrier electrode 31. The first via 111 penetrates the first insulating layer 11 and exposes at least a part of the barrier electrode 31. The hole diameter of the first via 111 is greater than 2 microns.

[0039] The orthographic projection of the opening of the first via 111 on the side closer to the source 21 on the substrate 10 is within the range of the orthographic projection of the barrier electrode 31 on the substrate 10, where the opening of the first via 111 on the side closer to the source 21 refers to an opening formed on the lower surface of the first insulating layer 11, and correspondingly, the opening formed on the upper surface of the first insulating layer 11 is away from the source 21. The thickness range of the film layer of the first insulating layer 11 is 3000 angstroms to 5000 angstroms, and the depth of the first via 111 is equal to the thickness of the film layer of the first insulating layer 11, that is, the depth of the first via 111 is in the range of 3000 angstroms to 5000 angstroms, for example, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, etc. The material of the first insulating layer 11 includes an inorganic material, and for example, the first insulating layer 11 may be a multilayer or monolayer containing at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0040] The oxide active layer 40 is provided on the side of the first insulating layer 11 away from the substrate 10. The source contact portion 42 and drain contact portion 43 of the oxide active layer 40 are both formed by making the oxide active layer 40 conductive so as to form a conductive region. The source contact portion 42 is located on a part of the first insulating layer 11 and within the first via 111, and the source contact portion 42 located within the first via 111 covers the hole wall of the first via 111 and the barrier electrode 31 exposed by the first via 111, and is connected to the barrier electrode 31.

[0041] Since the orthographic projection of the opening of the first via 111 on the substrate 10 that is closer to the source 21 is within the range of the orthographic projection of the barrier electrode 31 on the substrate 10, the source contact portion 42 located within the first via 111 is separated from the source 21 by the barrier electrode 31, and thereby the source contact portion 42 located within the first via 111 does not directly contact the source 21. The thickness of the oxide active layer 40 film is in the range of 100 angstroms to 500 angstroms, and may be, for example, 100 angstroms, 200 angstroms, 220 angstroms, 250 angstroms, 280 angstroms, 300 angstroms, 350 angstroms, 380 angstroms, 400 angstroms, 500 angstroms, etc.

[0042] The second insulating layer 12 is provided on the side of the oxide active layer 40 away from the substrate 10 and is provided corresponding to the channel portion 41. The material of the second insulating layer 12 includes an inorganic material, and for example, the second insulating layer 12 may be a multilayer or monolayer containing at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0043] The third conductive layer 50 is provided on the side of the second insulating layer 12 away from the substrate 10 and includes the gate 51 of the first transistor, the gate 51 being provided in correspondence with the second insulating layer 12. The third conductive layer 50 may be formed as a multilayer or monolayer having a low-resistance material, such as Al, Ti, Mo, Cu, Ni or an alloy thereof, or a material with high corrosion resistance. For example, the third conductive layer 50 may be a three-layer stack of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo.

[0044] Continuing with reference to Figure 2, the array substrate 100 further includes a third insulating layer 13, a planarization layer 14, a common electrode 60, a fourth insulating layer 15, and a pixel electrode 70. The third insulating layer 13 is provided on the side of the third conductive layer 50 away from the substrate 10, and for example, the third insulating layer 13 covers the upper surface and sidewall of the gate 51, the sidewall of the second insulating layer 12, the upper surface and sidewall of the source contact portion 42, the upper surface and sidewall of the drain contact portion 43, and a portion of the first insulating layer 11. The material of the third insulating layer 13 includes an inorganic material, and for example, the third insulating layer 13 may be a multilayer or monolayer containing at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0045] The planarization layer 14 is provided on the side of the third insulating layer 13 away from the substrate 10. The material of the planarization layer 14 includes an organic material, and for example, the planarization layer 14 may include a resin and be formed as, for example, polyacrylate or polyimide, or a silica-based organic material.

[0046] The common electrode 60 is provided on the side of the planarization layer 14 away from the substrate 10. The common electrode 60 may be formed from a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0047] The fourth insulating layer 15 is provided on the side of the common electrode 60 away from the substrate 10. The fourth insulating layer 15 includes a second via 141 provided corresponding to the drain contact portion 43, the second via 141 penetrating the fourth insulating layer 15, the planarization layer 14, and the third insulating layer 13, exposing a portion of the drain contact portion 43. The material of the fourth insulating layer 15 includes an inorganic material, and for example, the fourth insulating layer 15 may be a multilayer or monolayer containing at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0048] The pixel electrode 70 is provided in a layer of the fourth insulating layer 15 away from the substrate 10, with a portion of the pixel electrode 70 located within the second via 141 and connected to the drain contact portion 43 exposed by the second via 141. The pixel electrode 70 is provided opposite the common electrode 60, and the material of the pixel electrode 70 may be the same as that of the common electrode 60. For example, the pixel electrode 7 may be formed from a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0049] In one embodiment, with reference to Figures 1 to 3, Figure 3 is a schematic diagram showing another cross-sectional configuration of the array substrate 100 provided in an embodiment of the present application. Referring to Figure 3, the difference from the embodiment corresponding to Figure 2 is that the barrier electrode 31 is located within the first via 111, and the source contact portion 42 covers the barrier electrode 31 within the first via 111.

[0050] Specifically, the first insulating layer 11 has a first via 111 provided at a position corresponding to the source 21, and the first via 111 exposes a portion of the source 21. The barrier electrode 31 is provided within the first via 111 and is exposed by the first via 111. The barrier electrode 31 covers the hole wall of the first via 111 and the source 21 exposed by the first via 111, and is connected to the source 21. A portion of the source contact portion 42 is provided in the first via 111 and covers the barrier electrode 31 within the first via 111.

[0051] The orthographic projection of the opening of the first via 111 on the side closer to the source 21 on the substrate 10 is within the range of the orthographic projection of the barrier electrode 31 on the substrate 10. This separates the source contact portion 42 located within the first via 111 from the source 21 and the barrier electrode 31, thereby preventing the source contact portion 42 from directly contacting the source 21. Furthermore, by providing the barrier electrode 31 within the first via 111 and ensuring that the source contact portion 42 covers the barrier electrode 31 located within the first via 111, the contact area between the source contact portion 42 and the barrier electrode 31 is increased, improving the reliability of the electrical connection between the source contact portion 42 and the source 21. By providing the first via 111 with a relatively small hole diameter, a highly reliable electrical connection between the source contact portion 42 and the source 21 can be achieved, and consequently, the area occupied by the first transistor element can be reduced.

[0052] The thickness of the first insulating layer 11 is relatively large, and the thickness of the oxide active layer 40 is relatively small, with the thickness of the oxide active layer 40 being far smaller than the thickness of the first insulating layer 11. When the pore diameter of the first via 111 is relatively small, the thickness of the first insulating layer 11 is relatively large, and the taper angle of the first via 111 is relatively large. As a result, the oxide active layer 40, which has a relatively thin pore, is prone to problems such as disconnection when ascending through the first via 111, which in turn affects the reliability of the electrical connection between the source contact portion 42 and the source 21. To prevent problems such as disconnection when the oxide active layer 40 ascends through the first via 111, the first via 111 may be provided with a relatively large pore diameter. For example, the pore diameter of the first via 111 may be made larger than 2 microns. However, this configuration increases the area occupied by the first transistor element.

[0053] On the other hand, in this embodiment, by providing the barrier electrode 31 within the first via 111 and ensuring that the source contact portion 42 covers the barrier electrode 31 located within the first via 111, the contact area between the source contact portion 42 and the barrier electrode 31 can be increased. Even if a disconnection occurs when the source contact portion 42 ascends within the first via 111, the barrier electrode 31 can compensate for the disconnection in the source contact portion 42. This improves the reliability of the electrical connection between the source contact portion 42 and the source 21. By providing the first via 111 with a relatively small hole diameter, a highly reliable electrical connection between the source contact portion 42 and the source 21 can be achieved, and consequently, the area occupied by the first transistor element can be reduced.

[0054] Optionally, the end of the barrier electrode 31 away from the source 21 is flush with the upper surface of the first insulating layer 11, that is, the boundary of the barrier electrode 31 away from the source 21 is flush with the upper surface of the first insulating layer 11, in other words, the barrier electrode 31 is located within the first via 111 but does not extend beyond the first via 111. This does not affect the flatness of the upper surface of the first insulating layer 11 and is advantageous for the manufacture of the oxide active layer 40. Further details are omitted here, as they are based on the examples described above.

[0055] In one embodiment, with reference to Figures 1 to 4, Figure 4 is a schematic diagram showing another cross-sectional configuration of the array substrate 100 provided in an embodiment of the present application. Referring to Figure 4, the difference from the embodiment corresponding to Figure 3 is that the barrier electrode 31 extends from within the first via 111 to the surface of the first insulating layer 11 away from the substrate 10, and the source contact portion 42 further covers the barrier electrode 31 located outside the first via 111. That is, the barrier electrode 31 is further provided on a portion of the upper surface of the first insulating layer 11, thereby further increasing the contact area between the source contact portion 42 and the barrier electrode 31, and consequently further improving the reliability of the electrical connection between the source contact portion 42 and the source 21. Further descriptions are omitted here, as they refer to the embodiments described above.

[0056] In one embodiment, referring to Figures 1 to 5, Figure 5 is a schematic diagram showing another cross-sectional configuration of the array substrate 100 provided in an embodiment of the present application. Referring to Figure 5, the difference from the embodiment corresponding to Figure 2 is that the array substrate 100 is partitioned into a pixel region PA and a bonding region BA located on one side of the pixel region PA. The first transistor, the common electrode 60, and the pixel electrode 70 are all located within the pixel region PA. The array substrate 100 further includes a bonding terminal 80 located in the bonding region BA, the bonding terminal 80 being used to bond an external drive circuit to supply a signal to the pixel region PA. The first insulating layer 11 is provided with a third via at a position corresponding to the bonding terminal 80, the third via exposing the bonding terminal 80.

[0057] The bonding terminal 80 includes a first sub-bonding portion 23 and a second sub-bonding portion 33, the second sub-bonding portion 33 being located on the side of the first sub-bonding portion 23 away from the substrate 10. The first sub-bonding portion 23 is formed by the first conductive layer 20, and the second sub-bonding portion 33 is formed by the second conductive layer 30, that is, the first conductive layer 20 further includes the first sub-bonding portion 23 located in the bonding region BA, and the second conductive layer 30 further includes the second sub-bonding portion 33 located in the bonding region BA. The first sub-bonding portion 23 is provided in the same layer as the source 21, and the second sub-bonding portion 33 is provided in the same layer as the barrier electrode 31.

[0058] The material of the second conductive layer 30 is indium tin oxide. Since indium tin oxide is an oxide, its resistance does not increase due to subsequent processes such as oxygen ashing and high temperatures. On the other hand, molybdenum, titanium, and molybdenum-titanium alloys are susceptible to the effects of subsequent processes such as oxygen ashing and high temperatures, resulting in increased resistance. Therefore, when the first conductive layer 20 and the second conductive layer 30 are further used to form the bonding terminal 80 of the bonding region BA, indium tin oxide is selected as the material for the second conductive layer 30 so as not to affect the overall impedance of the bonding terminal 80. Further details are omitted here, as they are based on the examples described above.

[0059] Based on the same inventive concept, the present application further provides a display panel comprising an array substrate 100 according to one embodiment of the embodiments described above. The display panel may be a liquid crystal display panel, an organic light-emitting diode display panel, or another type of display panel.

[0060] As can be seen from the embodiments described above, the array substrate and display panel provided in the present application include, the array substrate, a substrate, and a first conductive layer, a second conductive layer, a first insulating layer, an oxide active layer, a second insulating layer, and a third conductive layer provided on the substrate, wherein the first conductive layer includes a spaced source and a light-shielding electrode, the second conductive layer includes a barrier electrode connected to the source, the first insulating layer includes a first via provided corresponding to the source, the first via exposing at least a portion of the barrier electrode, and the oxide active layer includes a channel portion and a source contact portion located on one side of the channel portion, the channel portion is provided corresponding to the light-shielding electrode, and the source contact A portion of the part is provided within the first via and connected to the barrier electrode, and the barrier electrode is connected between the source contact portion and the source and provided corresponding to the first via. This electrically connects the source contact portion to the source via the barrier electrode, avoiding direct contact between the source contact portion and the source. On the other hand, the barrier electrode can prevent the diffusion of metal elements from the source to the source contact portion. This prevents metal elements from diffusing into the oxide active layer and forming impurities at deep energy levels, which would degrade the performance of the device and affect the device performance and bias temperature stress characteristics, thereby improving the stability of the device.

[0061] In the embodiments described above, each embodiment has its own focus, and for parts of the embodiments that are not described in detail, you can refer to the relevant descriptions in other embodiments.

[0062] The embodiments of the present application have been described in detail above. While this specification has described the principles and embodiments of the present application using specific examples, the descriptions of the embodiments are merely intended to aid in understanding the technical proposal and its core concept. Those skilled in the art may modify the technical proposals described in the above-described embodiments or substitute some of their technical features with equivalent ones, but it should be understood that these modifications or substitutions do not cause the essence of the corresponding technical proposal to deviate from the scope of the technical proposals of the various embodiments of the present application.

Claims

1. An array substrate, Substrate and, A first conductive layer is provided on one side of the substrate, and includes a source and a light-shielding electrode, spaced apart from each other. A second conductive layer is provided on the side of the first conductive layer away from the substrate, and includes a barrier electrode, the barrier electrode being connected to the source, A first insulating layer is provided on the side of the first conductive layer away from the substrate and includes a first via provided in correspondence with the source, An oxide active layer provided on the side of the first insulating layer away from the substrate, comprising a channel portion and a source contact portion located on one side of the channel portion, wherein in the thickness direction of the array substrate, the channel portion is provided corresponding to the light-shielding electrode, a part of the source contact portion is provided in the first via and connected to the barrier electrode, the barrier electrode is connected between the source contact portion and the source and provided corresponding to the first via, and the barrier electrode is configured to prevent the diffusion of a metal element in the source to the source contact portion, A second insulating layer is provided on the side of the oxide active layer away from the substrate and corresponding to the channel portion, The second insulating layer includes a third conductive layer provided on the side of the second insulating layer away from the substrate and including a gate provided corresponding to the channel portion, The barrier electrode covers the surface of the source away from the substrate, the first insulating layer covers a portion of the barrier electrode, and the first via is provided at a position on the first insulating layer corresponding to the barrier electrode, and the source contact portion is connected to the barrier electrode exposed by the first via. The second conductive layer further includes a sub-electrode provided corresponding to the light-shielding electrode, the sub-electrode covering the surface of the light-shielding electrode away from the substrate, and the first insulating layer covering the sub-electrode and the space between the light-shielding electrode and the source. Array substrate.

2. The orthographic projection of the barrier electrode on the substrate coincides with the orthographic projection of the source on the substrate. The array substrate according to claim 1.

3. An array substrate, Substrate and, A first conductive layer is provided on one side of the substrate, and includes a source and a light-shielding electrode, spaced apart from each other. A second conductive layer is provided on the side of the first conductive layer away from the substrate, and includes a barrier electrode, the barrier electrode being connected to the source, A first insulating layer is provided on the side of the first conductive layer away from the substrate and includes a first via provided in correspondence with the source, An oxide active layer provided on the side of the first insulating layer away from the substrate, comprising a channel portion and a source contact portion located on one side of the channel portion, wherein in the thickness direction of the array substrate, the channel portion is provided corresponding to the light-shielding electrode, a part of the source contact portion is provided in the first via and connected to the barrier electrode, the barrier electrode is connected between the source contact portion and the source and provided corresponding to the first via, and the barrier electrode is configured to prevent the diffusion of a metal element in the source to the source contact portion, A second insulating layer is provided on the side of the oxide active layer away from the substrate and corresponding to the channel portion, The second insulating layer includes a third conductive layer provided on the side of the second insulating layer away from the substrate and including a gate provided corresponding to the channel portion, The first insulating layer covers a portion of the source, the light-shielding electrode, and the gap between the light-shielding electrode and the source, the portion of the source is exposed by the first via, the barrier electrode is located within the first via and connected to the source exposed by the first via, and the source contact portion covers the barrier electrode within the first via. Array substrate.

4. The barrier electrode extends from within the first via to the surface of the first insulating layer away from the substrate, and the source contact portion further covers the barrier electrode located outside the first via. The array substrate according to claim 3.

5. The orthographic projection of the opening of the first via on the side closer to the source on the substrate is within the range of the orthographic projection of the barrier electrode on the substrate. The array substrate according to any one of claims 1 to 4.

6. The thickness of the second conductive layer is in the range of 100 angstroms to 800 angstroms. The array substrate according to claim 5.

7. The material of the second conductive layer includes one of molybdenum, titanium, molybdenum-titanium alloy, and indium tin oxide. The array substrate according to claim 5.

8. The first conductive layer comprises a bonding layer and a main conductive layer located on the side of the bonding layer away from the substrate, wherein the material of the bonding layer comprises one of molybdenum, titanium, or a molybdenum-titanium alloy, and the material of the main conductive layer comprises copper. The array substrate according to claim 5.

9. The oxide active layer further includes a drain contact portion located on the side of the channel portion away from the source contact portion, The aforementioned array substrate is A third insulating layer provided on the side of the third conductive layer away from the substrate, A planarization layer provided on the side of the third insulating layer away from the substrate, A common electrode provided on the side of the planarized layer away from the substrate, A fourth insulating layer is provided on the side of the common electrode away from the substrate and includes a second via provided corresponding to the drain contact portion, The fourth insulating layer is provided on the side away from the substrate, a portion of which is located within the second via, and which is connected to the drain contact portion, further comprising: The array substrate according to claim 5.

10. Includes an array substrate according to any one of claims 1 to 4, Display panel.

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