Amplifier module and system where the ground terminal is adjacent to the power amplifier die

Abstract

To provide a sufficient ground reference to a power transistor die.SOLUTION: An amplifier module 200 includes a module substrate 210. A thermal dissipation structure 316 extends through the module substrate. A ground contact 434 of a power transistor die 233 is coupled to a surface of the thermal dissipation structure. An encapsulant material 380 covers a mounting surface 209 of the module substrate and the power transistor die. A surface of the encapsulant material defines a contact surface 382 of the amplifier module. A ground terminal 244 is embedded within the encapsulant material and has a proximal end coupled to a ground terminal pad 344 and a distal end exposed at the contact surface. The ground terminal pad is electrically coupled to an RF ground layer 302 through a via 444. The RF ground layer is also electrically coupled to the thermal dissipation structure.SELECTED DRAWING: Figure 4A

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to amplifier modules, and more particularly, to amplifier modules comprising a power transistor die.

Background Art

[0002] Wireless communication systems utilize power amplifier modules to increase the power of radio frequency (RF) signals. A power amplifier module includes a module substrate and an amplifier circuit coupled to the mounting surface of the module substrate. A typical module substrate includes input and output (I / O) terminals on the bottom surface of the module (i.e., the surface opposite the mounting surface of the module), and may include a conductor signal routing structure extending between the I / O terminals and bond pads through and across the module substrate. Further, one or more ground / thermal dissipation structures may extend through the module substrate between the mounting surface and the bottom surface.

[0003] The amplifier circuit often includes a power transistor die having one or more integrated power transistors with a bottom-side conductor ground layer. The bottom-side conductor ground layer of the power transistor die is directly connected to the surface of a ground / thermal dissipation structure exposed at the mounting surface of the module substrate. Along with the function of removing heat from the power transistor die, the ground / thermal dissipation structure may function to provide a ground reference to the power transistor die.

[0004] An electrical connection is established between the bond pad on the module's mounting surface and the I / O bond pad on the power transistor die to transmit RF signals between the module substrate and the power transistor die. When the integrated power transistor is a field-effect transistor (FET), the input bond pad of the die is connected to the gate terminal of the FET, and the output bond pad of the die is connected to the drain terminal of the FET. The source terminal of the FET is coupled through the die to the bottom-side conductor ground layer, and this conductor ground layer is similarly connected to the ground / heat dissipation structure of the module substrate, as described above.

[0005] To integrate the above-mentioned power amplifier module into a communication system, the module is typically coupled to the mounting surface of a printed circuit board (PCB). More specifically, the bottom surface of the module board is connected to the top surface of the system PCB so that the bottom-side module signal I / O terminals are aligned with the corresponding signal I / O pads on the PCB mounting surface. In addition, the module board is connected to the system PCB so that the module's ground / heat dissipation structure contacts a PCB heat spreader extending through the system PCB. Thus, the combination of the module's ground / heat dissipation structure and the system PCB heat spreader may serve a dual function: providing a thermal path to remove heat generated by the power transistor die and providing a ground reference for the power transistor die.

[0006] During operation, the power transistor amplifies the input RF signal received through the input bond pad of the transistor die and transmits the amplified RF signal to the output bond pad of the transistor die. Meanwhile, the heat generated by the power transistor die is dissipated through a ground / heat dissipation structure embedded in the module board and through the system PCB heat spreader, and the ground reference is also provided through the ground / heat dissipation structure and the system PCB heat spreader.

[0007] The above configuration works well for many applications. However, other applications require a different configuration in which the thermal path for the heat generated by the power transistor die extends away from the system PCB rather than through it. However, such different structures introduce new challenges, including difficulties related to providing a sufficient ground reference to the power transistor die.

[0008] A more complete understanding of the subject matter, when considered in conjunction with the following drawings, can be obtained by referring to the detailed description and claims. Similar reference numbers refer to similar elements throughout the drawings. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] U.S. Patent No. 7755186 [Brief explanation of the drawing]

[0010] [Figure 1] Schematic diagram of a Doherty power amplifier in a power amplifier module. [Figure 2] A top view of a power amplification module embodying the Doherty power amplifier of Figure 1, according to an exemplary embodiment. [Figure 3] Figure 2 shows a side view of the power amplifier module along line 3-3. [Figure 4A] A cross-sectional side view along line 4-4 of an exemplary embodiment of the power amplifier module in Figure 2. [Figure 4B] A cross-sectional side view along line 4-4 of an exemplary embodiment of the power amplifier module in Figure 2. [Figure 5A] A cross-sectional side view along line 5-5 of an exemplary embodiment of a power amplifier module in Figure 2. [Figure 5B] A cross-sectional side view along line 5-5 of an exemplary embodiment of a power amplifier module in Figure 2. [Figure 5C]A cross-sectional side view along line 5-5 of an exemplary embodiment of a power amplifier module in Figure 2. [Figure 6] A cross-sectional side view of an amplifier system comprising the power amplifier module shown in Figure 2, coupled to a system board and a heatsink, according to an exemplary embodiment. [Figure 7] A flowchart of a method for fabricating a power amplifier module and an amplifier system according to an exemplary embodiment. [Modes for carrying out the invention]

[0011] Embodiments of the subject matter of the invention described herein include an amplifier system comprising a system substrate (e.g., a printed circuit board (PCB)) and a power amplifier module coupled to the system substrate. The power amplifier module comprises a module substrate having an embedded heat dissipation structure and a power amplifier die connected to the embedded heat dissipation structure. In contrast to conventional systems in which the embedded heat dissipation structure is coupled to a heat spreader on the system substrate, the power amplifier module is mounted on the system substrate in a "flipped orientation" such that the embedded heat dissipation structure faces away from the system substrate. Thus, in one embodiment, a heat sink may be directly connected to the exposed surface of the embedded heat dissipation structure of the power amplifier module.

[0012] In such systems, proper grounding of the power amplifier die relative to the system board is crucial for achieving superior performance. It is known that current (DC or RF) must proceed in a closed loop. "Return current" is defined as the current that flows back to its source through the ground plane. Current always takes a path with the least "obstacle." For pure DC current, for example, the obstacle is resistance. In contrast, RF current tends to take a path with the least inductance. At higher frequencies, RF return current path optimization plays a significant role in power amplifier performance. More specifically, the return current path for the power amplifier die is relatively short (in electrical length) to avoid a significant decrease in efficiency, gain, or other performance metrics. Various embodiments of a power amplifier module having a grounding structure that provides a proper ground / return current path to the power amplifier die of a power amplifier module mounted relative to a system PCB in a flipped orientation, as described above, are disclosed herein, as detailed below.

[0013] The embodiments of the power amplifier modules described herein may be used to implement any of several different types of power amplifiers. An example of a Doherty power amplifier module is used herein to provide a concrete example that helps to convey the details of the subject matter of the invention. However, those skilled in the art will understand, based on the description herein, that the subject matter of the invention may also be used in power amplifier modules to implement other types of amplifiers. Therefore, because the subject matter of the invention may also be used in other types of power amplifier modules, the Doherty power amplifiers in the following exemplary embodiments are not intended to limit the use of the subject matter of the invention.

[0014] Before describing the various physical implementations of the power amplifier module, refer to Figure 1. Figure 1 is a schematic diagram of a Doherty power amplifier 110 implemented in the power amplifier module 100. The power amplifier module 100 essentially comprises a Doherty amplifier 110 implemented on a module substrate (e.g., module substrate 210, Figure 2). In one embodiment, the Doherty amplifier 110 comprises an RF input node 112, an RF output node 114, a power splitter 120, a carrier amplifier path 130 having one or more carrier amplifier dies (e.g., dies 233, 234, Figure 2), a peak amplifier path 150 having one or more peak amplifiers (e.g., dies 253, 254, Figure 2), a phase delay and impedance inverting element 170, and a combining node 172. In addition, as will be discussed in more detail below, the power amplifier module 100 also includes one or more ground terminals 141, 145 configured to provide an external ground reference to the power amplifier die of the carrier and peak amplifier paths 130, 150, according to various embodiments. As will be described in more detail below, the ground terminals 141, 145 are positioned very close to the power amplifier die to optimize the ground return loop for the die, according to various embodiments.

[0015] When integrated into a larger RF system, the RF input node 112 is coupled to an RF signal source, and the RF output load 114 is coupled to a load 190 (e.g., an antenna or other load). The RF signal source provides an input RF signal, which is typically an analog signal containing spectral energy centered around one or more carrier frequencies. Fundamentally, the Doherty amplifier 110 is configured to amplify the input RF signal and to generate the amplified RF signal at the RF output node 114.

[0016] In one embodiment, the power splitter 120 has one input 122 and two outputs 124, 126. The power splitter input 122 is coupled to an RF input node 112 to receive an input RF signal. The power splitter 120 is configured to split the RF input signal received at input 122 into first and second RF signals (or carrier and peak signals) which are provided to carrier and peak amplifier paths 130, 150 through outputs 124, 126. According to one embodiment, the power splitter 120 includes a first phase shift element configured to give a first phase shift (e.g., a phase shift of about 90 degrees) to the peak signal before the peak signal is provided to output 126. Thus, at outputs 124 and 126, the carrier and peak signals are out of phase by about 90 degrees from each other.

[0017] When the Doherty amplifier 110 has a symmetrical configuration (i.e., a configuration in which the carrier and peak amplifier power transistors are substantially identical in dimensions), the power splitter 120 may, in some embodiments, split or divide the input RF signal received at input 122 into two very similar signals having equal power. In contrast, when the Doherty amplifier 110 has an asymmetrical configuration (i.e., a configuration in which one of the amplifier power transistors, typically the peak amplifier transistor, is much larger), the power splitter 120 may output carrier and peak signals having unequal power.

[0018] The outputs 124, 126 of the power splitter 120 are respectively connected to the carrier and peak amplifier paths 130, 150. The carrier amplifier path 130 is configured to amplify the carrier signal from the splitter 120 and to provide the amplified carrier signal to the power combining node 172. Similarly, the peak amplifier path 150 is configured to amplify the peak signal from the power splitter 120 and to provide the amplified peak signal to the power combining node 172, and the paths 130, 150 are designed such that the amplified carrier and peak signals reach the power combining node 172 in phase with each other.

[0019] According to one embodiment, the carrier amplifier path 130 includes an input circuit 131 (e.g., including an impedance matching circuit), a carrier amplifier 132 implemented using one or more carrier amplifier dies (e.g., dies 233, 234, FIG. 2), and a phase shift and impedance inversion element 170.

[0020] In various embodiments, the carrier amplifier 132 includes an RF input terminal 134, an RF output terminal 138, and one or more amplification stages coupled between the input and output terminals 134, 138. The RF input terminal 134 is coupled to the first output 124 of the power splitter 120 through the input circuit 170, and thus the RF input terminal 134 receives the carrier signal generated by the power splitter 120.

[0021] Each amplification stage of the carrier amplifier 132 includes a power transistor. In a single-stage carrier amplifier 132, a single power transistor may be implemented on a single power amplifier die. In a two-stage carrier amplifier 132, two power transistors may be implemented on a single power amplifier die, or, as illustrated in the power amplifier module shown in FIG. 2, each power amplifier may be implemented on a separate die (e.g., dies 233, 234, FIG. 2).

[0022] In any case, each power transistor has a control terminal (e.g., a gate terminal) and first and second current carrier terminals (e.g., a drain terminal and a source terminal). In a single-stage device with a single power transistor, the control terminal is electrically connected to the RF input terminal 134, the current carrier terminal (e.g., the drain terminal) is electrically connected to the RF output terminal 138, and the other current carrier terminal (e.g., the source terminal) is electrically connected to a ground reference (or another voltage reference). In contrast, a two-stage amplifier has two power transistors coupled in series, with the first transistor acting as a driver amplifier transistor with relatively low gain and the second transistor acting as a final-stage amplifier transistor with relatively high gain. In such embodiments, the control terminal of the driver amplifier transistor is electrically connected to the RF input terminal 134, one of the current carrier terminals of the driver amplifier transistor (e.g., the drain terminal) may be electrically connected to the control terminal of the final stage amplifier transistor, and the other current carrier terminal of the driver amplifier transistor (e.g., the source terminal) may be electrically connected to a ground reference (or another voltage reference) through one embodiment of a specialized ground terminal 141. In addition, one of the current carrier terminals of the final stage amplifier transistor (e.g., the drain terminal) is electrically connected to the RF output terminal 138, and the other current carrier terminal of the final stage amplifier transistor (e.g., the source terminal) may be electrically connected to a ground reference (or another voltage reference) through one embodiment of a specialized ground terminal 141. As will be described in more detail with Figures 2 to 4, the electrical connection of the carrier amplifier driver and / or final stage amplifier transistor to the ground reference may be made using a specialized ground terminal placed very close to the carrier amplifier transistor to provide a relatively short ground return path to the carrier amplifier.

[0023] In addition to the power transistors, input and output impedance matching networks and a bias circuit (not shown in Figure 1) may be included within the carrier amplifier 132 and / or electrically coupled to the carrier amplifier 132. Furthermore, in one embodiment where the carrier amplifier 132 is a two-stage device, an interstage matching network (not shown in Figure 1) may be included within the carrier amplifier 132 between the driver amplifier transistor and the final stage amplifier transistor.

[0024] In one embodiment, the RF output terminal 138 of the carrier amplifier 132 is coupled to a power combining node 172 via a phase shift and impedance inverting element 170. According to one embodiment, the impedance inverting element is a lambda / 4 (λ / 4) transmission line phase shift element that imparts a relative phase shift of approximately 90 degrees to the carrier signal after amplification by the carrier amplifier 132. The first end of the impedance inverting element 170 is coupled to the RF output terminal 138 of the carrier amplifier 132, and the second end of the phase shift element 170 is coupled to the power combining node 172.

[0025] The following refers to the peak amplifier path 150, which in one embodiment comprises a peak amplifier 152 and an input circuit 151 (e.g., an impedance matching circuit). In various embodiments, the peak amplifier 152 comprises an RF input terminal 154, an RF output terminal 158, and one or more amplification stages coupled between the input and output terminals 154, 158. The RF input terminal 154 is coupled to the second output 126 of the power splitter 120, and therefore the RF input terminal 154 receives the peak signal generated by the power splitter 120.

[0026] Together with the carrier amplifier 132, each amplification stage of the peak amplifier 152 comprises a power transistor having a control terminal and first and second current carrier terminals. The power transistors of the peak amplifier 152 may be electrically coupled between the RF input and output terminals 154, 158, in the same manner as described above with respect to the carrier amplifier 132. Additional details discussed with respect to the carrier amplifier 132 also apply to the peak amplifier 152, and those additional details will not be repeated here for the sake of brevity. However, one important point to reiterate is that the current carrier terminal of each peak amplifier transistor (e.g., the source terminal of the driver and / or final stage peak amplifier transistor) may be electrically connected to a ground reference (or another voltage reference) through one embodiment of a specialized ground terminal 145, as described above with respect to the carrier amplifier 132. As will be described in more detail with respect to Figures 2-4, the electrical connection of the peak amplifier driver and / or final stage amplifier transistor to the ground reference may be made using a specialized ground terminal placed very close to the peak amplifier transistor to provide a relatively short ground return path to the peak amplifier.

[0027] The RF output terminal 158 of the peak amplifier 152 is coupled to a power combining node 172. In one embodiment, the RF output terminal 158 of the peak amplifier 152 and the power combining node 172 are implemented by a common element. More specifically, in one embodiment, the RF output terminal 158 of the peak amplifier 152 is configured to function as both the combining node 172 and the output terminal 158 of the peak amplifier 152. To facilitate the combining of the amplified carrier and peak signals, the RF output terminal 158 (and therefore the combining node 172) is connected to the second end of the phase shift and impedance inverting element 170. In other embodiments, the combining node 172 may be a separate element from the RF output terminal 158.

[0028] In any case, the amplified carrier and peak RF signals are combined in phase at the combining node 172. The combining node 172 is electrically coupled to the RF output node 114 to provide the amplified and combined RF output signal to the RF output node 114. In one embodiment, an output impedance matching network 174 between the combining node 172 and the RF output node 114 functions to provide appropriate load impedances to the carrier and peak amplifiers 132, 152, respectively. The resulting amplified RF output signal is generated at the RF output node 114, to which an output load 190 (e.g., an antenna) is connected.

[0029] Amplifier 110 is configured such that the carrier amplifier path 130 provides amplification for relatively low-level input signals, and both amplification paths 130 and 150 operate in combination to provide amplification for relatively high-level input signals. This may be achieved, for example, by biasing the carrier amplifier 132 so that it operates in class AB mode, and by biasing the peak amplifier 152 so that it operates in class C mode.

[0030] In the embodiment shown in Figure 1 and described above, the first phase shift element in the splitter 120 imparts a phase shift of approximately 90 degrees to the peak signal before amplification, and the phase shift and impedance inverter element 170 similarly imparts a phase shift of approximately 90 degrees to the amplified carrier signal, so that the amplified carrier and peak signals are combined in phase at the synthesis node 172. Such an architecture is called a non-inverting Doherty amplifier architecture. In an alternative embodiment, the first phase shift element in the splitter 120 may impart a phase shift of approximately 90 degrees to the carrier signal rather than the peak signal before amplification, and the phase shift and impedance inverter element 170 may instead be provided at the output of the peak amplifier. Such an alternative architecture is called an inverting Doherty amplifier architecture. In further alternative embodiments, other combinations of phase-shifting elements may be implemented in the carrier and / or peak paths 130, 150 before amplification to achieve a phase difference of approximately 90 degrees between the carrier signal and the peak signal before amplification, and the phase shifts applied to the amplified carrier and peak signals may be selected accordingly to ensure that the signals are combined in phase at the synthesis node 172.

[0031] Figure 2 is a top view of a power amplifier module 200 embodying the Doherty amplifiable circuit of Figure 1, according to an exemplary embodiment. For improved understanding, Figure 2 should be referenced together with Figure 3, a cross-sectional side view of module 200 of Figure 2 along line 3-3. Essentially, the power amplifier module 200 comprises a Doherty power amplifier (e.g., power amplifier 110, Figure 1) mounted on a multilayer module board 210, a number of power transistor dies 233, 234, 253, 254, and other electrical components. Note that the various components of the power amplifier module 200 correspond to the components shown in Figure 1, and that corresponding components between Figure 1 and Figures 2-3 have the same last two digits (e.g., components 120 and 220 are corresponding components).

[0032] The power amplifier module 200 comprises a module substrate 210 in the form of a multilayer printed circuit board (PCB) or other suitable substrate. The module substrate 210 has a top surface 209 (also called the “mounting surface”) and a bottom surface 211 (also called the “heat sink mounting surface”). As described in more detail below, several components and terminals 212, 214, 241-248, 261, 262, 265, 266 are coupled to the mounting surface 209 of the module substrate 210, and a non-conductive encapsulant material 380 (e.g., a plastic encapsulant) is placed on the top surface 382 (also called the “contact surface”) of the module 200, on the mounting surface 209, and above the components and terminals 212, 214, 241-248, 261, 262, 265, 266. As shown in Figure 3, the encapsulation material 380 has a thickness 384 that is greater than the maximum height of the components covered by the encapsulation material 380 (e.g., the splitter 220 and the power transistor dies 233, 234, 253, 254).

[0033] As will be described in more detail below, the lower or base end faces of terminals 212, 214, 241-248, 261, 262, 265, and 266 are coupled to conductor features on the mounting surface 209 of the module substrate 210, and the upper or tip faces of terminals 212, 214, 241-248, 261, 262, 265, and 266 are exposed at the contact surface 382 of the encapsulation material 380. Conductor mounting material 383 (e.g., solder balls, solder paste, or conductor adhesive) is placed on the exposed tip faces of terminals 212, 214, 241-248, 261, 262, 265, and 266 to facilitate the electrical and mechanical mounting of the module 200 to the system substrate (e.g., system substrate 610, Figure 6), which will be described in more detail later. Various features and embodiments of terminals 212, 214, 241-248, 261, 262, 265, and 266 will be discussed in more detail later.

[0034] As shown in Figure 3, the module substrate 210 comprises multiple dielectric layers 305, 306, 307 (formed from, for example, FR-4, ceramic, or other PCB dielectric material) arranged alternately with multiple conductive layers 301, 302, 303, 304, the top surface 209 of the module substrate 210 is formed by the patterned conductive layer 301, and the bottom surface 211 of the module substrate 210 is formed by the conductive layer 304. Although the module substrate 210 is shown to comprise three dielectric layers 305-307 and four conductive layers 301-304, it should be noted that other embodiments of the module substrate may comprise more or fewer dielectric and / or conductive layers.

[0035] Each of the different conductor layers 301-304 may have a primary purpose and may also have conductor features for signal and / or voltage / ground routing between other layers. The following description outlines the primary purpose of each of the conductor layers 301-304, but it should be understood that the layers (or their functions) may be arranged differently from the specific arrangement best shown in Figure 3 and discussed below.

[0036] For example, in one embodiment, a patterned conductor layer 301 on the mounting surface 209 of the module substrate 210 may function primarily as a signal transmission layer. More specifically, the layer 301 comprises a plurality of conductor features (e.g., conductor pads or traces) which serve as mounting points for dies 233, 234, 253, 254 and other discrete components, and further provide electrical connectivity between dies 233, 234, 253, 254 and other discrete components. In addition, as discussed below, the layer 301 may comprise a plurality of conductor pads (e.g., signal terminal pad 312 and ground terminal pads 342, 344, 366) specifically designated for mounting conductive signal and / or ground terminals 212, 214, 241-248, 261, 262, 265, 266, as described in more detail with Figures 4 and 5.

[0037] The second patterned conductor layer 302 functions as an RF ground layer. The RF ground layer 302 also includes several conductor features (e.g., conductor traces) that can be electrically coupled to the conductor features of the signal transmission layer 301 and to the system ground layer 304 (described below) via conductor vias 311, 313, 315 extending through the dielectric layers 305-307. For example, the conductor ground terminal pads 342, 344, 366 are electrically coupled to the RF ground layer 302 via via 311, and the RF ground layer 302 is similarly electrically coupled to the system ground layer 304 via vias 313, 315 (and routing features of the conductor layer 303).

[0038] The third patterned conductor layer 303 functions to transmit the bias voltage to the power transistors 236, 237, 256, and 257 in the dies 233, 234, 253, and 254, and may also function as a routing layer as described above. Finally, the fourth conductor layer 304 functions as a system ground layer and a heat sink mounting layer, as will be described in more detail with Figure 6.

[0039] According to one embodiment, the module substrate 210 may include one or more heat dissipation structures 316 extending between the top and bottom surfaces 209, 211 of the module substrate 210. The dies 233, 234, 253, 254 are physically and electrically coupled to the surface 317 of the heat dissipation structure 316 exposed at the top surface 209 of the module substrate 210. The bottom surface 318 of the heat dissipation structure 316 may be exposed at the bottom surface 211 of the module substrate 210, or the bottom surface 318 of the heat dissipation structure 316 may be covered by a bottom conductive layer 304, as shown in Figure 3. In any case, the heat dissipation structure 316 is configured to provide a heat path between the dies 233, 234, 253, 254 and the bottom surface 318 of the heat dissipation structure 316 (and therefore the bottom surface of the module substrate 210). In various embodiments, the heat dissipation structure 316 may comprise conductive metal coins that are press-fitted and / or mounted into through-holes extending between the surfaces 209, 211 of the module substrate 210. In alternative embodiments, each of the heat dissipation structures 316 may comprise a plurality (or a set) of conductive thermal vias (e.g., circular or rod-shaped vias) extending between the surfaces 209, 211 of the module substrate 210. As described in more detail with Figure 6, the surfaces 318 of the heat dissipation structures 316 (or portions of the conductive layer 304 overlapping their surfaces 318) are physically and thermally coupled to a heat sink (e.g., a heat sink, Figure 6) when the module 200 is integrated into a larger electrical system.

[0040] The power amplifier module 200 further comprises an RF signal input terminal 212 (e.g., RF input node 112, Figure 1), a two-stage carrier amplifier 232 (e.g., amplifier 132, Figure 1), a two-stage peak amplifier 252 (e.g., amplifier 152, Figure 1), various phase shift and impedance inverting elements, a combining node 272 (e.g., combining node 172, Figure 1), an output impedance matching network 274 (e.g., network 174, Figure 1), and an RF signal output terminal 214 (e.g., RF output node 114, Figure 1).

[0041] Terminal 212 functions as an RF signal input terminal for module 200 and is coupled to the RF signal input pad 312 at the top surface 209 of module board 210. Through one or more conductive structures (e.g., vias, traces, and / or wire bonds as shown), the RF signal input pad 312 is electrically coupled to the input 222 to power splitter 220.

[0042] Although discrete dies and / or components are shown as single elements in Figure 2, the power splitter 220 connected to the mounting surface 209 of the system board 210 may comprise one or more discrete dies and / or components. The power splitter 220 comprises one input 222 and two output terminals (not numbered, but corresponding to terminals 124 and 126 in Figure 1). The input terminal 222 is electrically coupled to the RF signal input pad 312 and to the RF signal input terminal 212 through one or more conductive structures (e.g., vias, traces, and / or wire bonds as shown) and is therefore configured to receive input RF signals. The output terminals of the power splitter 220 are electrically coupled to inputs 235, 255 for carrier and peak amplifiers 232, 252 through one or more conductive structures (e.g., vias, traces, and / or wire bonds) and input circuits 231, 251.

[0043] The power splitter 220 splits the power of the input RF signal received through the RF input terminal 212 into first and second RF signals generated at the output terminal of the power splitter 220. In addition, the power splitter 220 may include one or more phase shift elements configured to give a phase difference of about 90 degrees between the RF signals provided to the splitter output terminal. The first and second RF signals generated at the output of the power splitter 220 may have equal or unequal power, as described above.

[0044] The first output of the power splitter is electrically coupled to the carrier amplifier path 130 (i.e., the carrier amplifier 232), and the second output of the power splitter is electrically coupled to the peak amplifier path (i.e., to the peak amplifier 252). The RF signal generated at the second power splitter output may be delayed by approximately 90 degrees from the RF signal generated at the first power splitter output. In other words, the RF signal provided to the peak amplifier path may be delayed by approximately 90 degrees from the RF signal provided to the carrier amplifier path. In any case, the first RF signal generated by the power splitter 220 is amplified through the carrier amplifier path 232, and the second RF signal generated by the power splitter 220 is amplified through the peak amplifier path 252.

[0045] In a particular embodiment of Figure 2, each of the carrier and peak amplifier paths comprises two-stage power amplifiers 232,252, where driver amplifier transistors 236,256 are mounted on driver amplifier dies 233,253, and final-stage amplifier transistors 237,257 are mounted on separate final-stage amplifier dies 234,254. For example, each of the transistors 236,237,256,257 may be a field-effect transistor (FET), such as a lateral diffusion metal oxide semiconductor (LDMOS) FET or a high electron mobility transistor (HEMT). The specification and claims may refer to each transistor having a control terminal and two current-conducting terminals. For example, using FET-related terminology, “control terminal” refers to the gate terminal of the transistor, and the first and second current-conducting terminals refer to the drain and source terminals (or source and drain terminals) of the transistor. The following description may use terminology commonly used with FET devices, but the various embodiments are not limited to implementations using FET devices, and are intended to apply to implementations using bipolar junction transistor (BJT) devices or other suitable types of transistors instead.

[0046] More specifically, the carrier amplifier 232 comprises a silicon driver stage die 233 and a gallium nitride (GaN) final stage die 234, according to an exemplary embodiment, and the peak amplifier 252 also comprises a silicon driver stage die 253 and a GaN final stage die 254. In other embodiments, each of the carrier and peak amplifiers 232,252 may comprise a two-stage power amplifier mounted on a single die, or each of the carrier and peak amplifiers 232,252 may comprise a single-stage power amplifier mounted on a single die. In yet another embodiment, each of the carrier and peak amplifiers may comprise a two-stage power amplifier mounted on separate driver and final stage dies, wherein the driver and final stage dies may be formed using the same semiconductor technology (e.g., both the driver and final stage dies are silicon dies or GaN dies), or the driver and / or final stage dies may be formed using semiconductor technology different from the above technology (e.g., the driver and / or final stage dies are silicon germanium (SiGe) and / or gallium arsenide (GaAs) dies).

[0047] The carrier amplifier path comprises the driver stage die 233 described above, the final stage die 234, and a phase shift and impedance inversion element 270 (e.g., element 170, Figure 1). The driver stage die 233 and the final stage die 234 of the carrier amplifier path 232 are electrically coupled together in a cascaded configuration between the input terminal 235 of the driver stage die 233 (corresponding to the carrier amplifier input) and the output terminal 238 of the final stage die 234 (corresponding to the carrier amplifier output).

[0048] The driver stage die 233 comprises a plurality of integrated circuits. In one embodiment, the integrated circuit of die 233 comprises, in one embodiment, a series-coupled arrangement of input terminals 235 (e.g., input terminal 135, Figure 1), an input impedance matching circuit (unnumbered), a silicon power transistor 236, an integrated portion of an interstage impedance matching circuit (unnumbered), and an unnumbered output terminal. More specifically, the gate of transistor 236 is electrically coupled to input terminal 235 through the impedance matching circuit, and the drain of transistor 236 is electrically coupled to the output terminal of die 233 through the output impedance matching circuit. The source of transistor 236 is electrically coupled to a conductor layer (or source terminal 434 such as source contact 434, Figures 4A, 4B) at the bottom surface of die 233, and the bottom conductor layer is physically, electrically and thermally coupled to the exposed top surface 317 of the heat dissipation structure 316.

[0049] The output terminals of the driver stage die 233 are electrically connected to the input terminals of the final stage die 234 by a wire bond array (unnumbered) or another type of electrical connection. The final stage die 234 may also comprise multiple integrated circuits. In one embodiment, the integrated circuit of die 234 comprises a series-coupled arrangement of input terminals (unnumbered), a GaN power transistor 237, and an output terminal 238 (e.g., output terminal 138, Figure 1). More specifically, the gate of transistor 237 is electrically coupled to the input terminal of die 234, and the drain of transistor 237 is electrically coupled to the output terminal of die 234. The source of transistor 237 is electrically coupled to a conductor layer at the bottom surface of die 234, and the bottom conductor layer is physically, electrically, and thermally coupled to the exposed top surface 317 of the heat dissipation structure 316.

[0050] The peak amplifier path comprises the driver stage die 253 and the final stage die 254 described above. The driver stage die 253 and the final stage die 254 of the peak amplifier path 252 are electrically coupled together in a cascaded configuration between the input terminal 255 of the driver stage die 253 (corresponding to the peak amplifier input) and the output terminal 258 of the final stage die 254 (corresponding to the peak amplifier output).

[0051] The driver stage die 253 comprises a plurality of integrated circuits. In one embodiment, the integrated circuit of die 253 comprises a series-coupled arrangement of input terminals 255 (e.g., input terminal 155, Figure 1), an input impedance matching circuit (unnumbered), a silicon power transistor 256, an integrated portion of an interstage impedance matching circuit (unnumbered), and, in one embodiment, an unnumbered output terminal. More specifically, the gate of transistor 256 is electrically coupled to input terminal 255 through the impedance matching circuit, and the drain of transistor 256 is electrically coupled to the output terminal of die 253 through the output impedance matching circuit. The source of transistor 256 is electrically coupled to a conductor layer at the bottom surface of die 253, and the bottom conductor layer is physically, electrically, and thermally coupled to the exposed top surface of a heat dissipation structure (e.g., similar to or identical to heat dissipation structure 316).

[0052] The output terminals of the driver stage die 253 are electrically connected to the input terminals of the final stage die 254 by a wire bond array (unnumbered) or another type of electrical connection. The final stage die 254 may also comprise multiple integrated circuits. In one embodiment, the integrated circuit of die 254 comprises a series-coupled arrangement of input terminals (unnumbered), a GaN power transistor 257, and an output terminal 258 (e.g., output terminal 158, Figure 1). More specifically, the gate of transistor 257 is electrically coupled to the input terminal of die 254, and the drain of transistor 257 is electrically coupled to the output terminal 258 of die 254. The source of transistor 257 is electrically coupled to a conductor layer at the bottom surface of die 254, and the bottom conductor layer is physically, electrically, and thermally coupled to the exposed top surface of a heat dissipation structure.

[0053] The amplified carrier signal is generated at the output terminal 238 of the final stage die 234, and the amplified peak signal is generated at the output terminal 258 of the final stage die 254, the final stage die 254 also functions as a synthesis node 272 for the amplifier (e.g., node 172, Figure 1). According to one embodiment, the output terminal 238 of the carrier final stage die 234 is electrically coupled to the first end of the phase shift and impedance inverting element 270 (e.g., by a wire bond (unnumbered) or another type of electrical connection), and the output terminal 258 of the peak final stage die 254 is electrically coupled to the second end of the phase shift and impedance inverting element 270 (e.g., by a wire bond (unnumbered) or another type of electrical connection).

[0054] According to one embodiment, the phase-shift and impedance-inverting element 270 may be implemented by a quarter-wavelength or lambda / 4 (λ / 4) or shorter transmission line (e.g., a microstrip transmission line with an electrical length of up to about 90 degrees) formed from a portion of the conductor layer 301. As used herein, lambda is the wavelength of the RF signal at the fundamental frequency of the amplifier's operation (e.g., a frequency in the range of about 600 megahertz (Mz) to about 10 gigahertz (GHz) or higher). The combination of the phase-shift and impedance-inverting element 270 and wire-bonded (or other) connections to the output terminals 238,258 of the dies 234,254 may provide a relative phase shift of about 90 degrees with respect to the amplified carrier signal as the signal travels from output terminal 238 to output terminal 258 / combination node 272. When the various phase shifts applied separately to the carrier and peak RF signals through the carrier and peak paths are approximately equal, the amplified carrier and peak RF signals are combined in approximately in-phase at output terminal 258 / combining node 272.

[0055] The output terminal 258 / combination node 272 is electrically coupled to the RF output terminal 214 (e.g., node 114, Figure 1) through an output impedance matching network 274 (e.g., network 174, Figure 1) (e.g., by wire bonding or other types of electrical connections). The output impedance matching network 274 functions to present appropriate load impedances to the carrier and peak final stage dies 234, 254, respectively. As shown in a highly simplified form in Figure 2, the output impedance matching network 274 may include various conductor traces and additional discrete components (e.g., capacitors, inductors, and / or resistors) between the output terminal 258 / combination node 272 and the RF output terminal 214 to provide the desired impedance matching.

[0056] As previously discussed, several terminals 212, 214, 241-248, 261, 262, 265, and 266 are coupled to the mounting surface 209 of the module substrate 210, and a non-conductive encapsulation material 380 is placed on the mounting surface 209 and around the terminals 212, 214, 241-248, 261, 262, 265, and 266 to form the contact surface 382 of the module 200. Certain of terminals 212 and 214 correspond to signal I / O terminals, and the others of terminals 241-248, 261, 262, 265, and 266 correspond to embodiments of ground terminals. Although not shown in Figure 2, additional terminals providing bias voltages (e.g., gate and / or drain bias voltages) for transistors 236, 237, 246, and 247 may be coupled to the mounting surface 209.

[0057] A first embodiment of terminals 212, 214, 241-248, 261, 262, 265, and 266 is shown in more detail in Figures 3, 4A, and 5. Similar to Figure 3, Figures 4A and 5A are cross-sectional side views of the power amplifier module 200 of Figure 2 along lines 4-4 and 5-5, respectively.

[0058] More specifically, the cross-sections in Figures 3, 4A, and 5A are cut through terminals 212, 214, 242-244, 265, and 266, where terminals 212 and 214 are signal terminals and terminals 242-244, 265, and 266 are ground terminals. Regardless of their type, each terminal 212, 214, 242-244, 265, and 266 is connected to a terminal pad (e.g., terminal pads 312, 314, 342, 343, 344, 365, and 366) on the mounting surface 209 of the module substrate 210, and each terminal pad is formed from a portion of the patterned conductor layer 301. The signal terminals 212 and 214 are configured to transmit RF signals, and therefore the signal terminals 212 and 214 and their associated signal pads 312 and 314 are electrically coupled to conductor traces formed from portions of the signal transmission layer 301. In contrast, the ground terminals 241-248, 261, 262, 265, and 266 are configured to provide a connection between the RF ground layer 302 and the external ground (e.g., the ground layer 602 of the system board 610, Figure 6). Thus, their ground terminals and their associated ground terminal pads (e.g., pads 342, 343, 344, 365, and 366) are electrically coupled to the RF ground layer 302 through conductive vias (e.g., vias 442, 443, 444, 465, and 466). As best shown in Figure 4A, the RF ground layer 302 is also electrically coupled to the heat dissipation structure (e.g., structure 316) to which the dies 233, 234, 253, 254 are connected. Thus, the combination of the heat dissipation structure 316, the RF ground layer 302, the vias 442, 443, 444, 465, 466, the ground terminal pads 342, 343, 344, 365, 366, and the ground terminals 241-248, 261, 262, 265, 266 provides a conductive path between the power transistor dies 233, 234, 253, 254 and the contact surface 382 of the module 200.

[0059] According to certain embodiments, as best shown in Figures 3 and 4A, at least some of the ground terminals 241-248 are located adjacent to, and "in very close proximity to," one or more sides of the power transistor dies 233, 234, 253, and 254. As used herein, the expression "in very close proximity" in the above context means that the physical distance (e.g., distance 485, Figure 4A) between the side of the power transistor die (e.g., die 234) (e.g., side 334, Figure 4A) and the side of the ground terminal (e.g., ground terminal 244) is less than the width of the die adjacent to the ground terminal (e.g., width 486, which is the dimension of the die parallel to distance 485). In addition to or instead of this, the expression “very close” means, in the above context, that the electrical length of the conductive path (e.g., dashed path 487) between the heights of the ground contact for the die (e.g., bottom source contact 434), the RF ground layer (e.g., layer 302), any intervening vias (e.g., via 444), the ground terminal pad (e.g., pad 344), and the ground terminal (e.g., terminal 244) through the heat dissipation structure (e.g., structure 316) is less than about lambda / 5 (λ / 5) in some embodiments, or less than about lambda / 16 (λ / 16) in other embodiments. Figure 2 shows ground terminals 241-248 located at specific positions on the mounting surface 209 of the module substrate 210, although ground terminals 241-248 may also be located at additional and / or different positions. More specifically, it is desirable to have a ground terminal so that the final effect of the ground terminal can be minimized, or to nearly eliminate the RF return current that extends across the module substrate 210, which may have a peak current area similar to that of a standing wave.

[0060] As will be explained in more detail with Figure 6, positioning the ground terminals 241-248 in close proximity to the power transistor dies 233, 234, 253, and 254 facilitates a relatively short return current loop for the dies 233, 234, 253, and 253 when the module 200 is mounted on a system board (e.g., system board 610, Figure 6) and put into operation. This configuration avoids potential detrimental performance problems that can occur in systems with relatively long return current loops.

[0061] According to another specific embodiment, as best shown in Figures 3 and 5A, at least several other ground terminals 261, 262, 265, 266 are positioned on both sides of terminals 212, 214 and "very close" to both sides, so as to provide GSG (ground-signal-ground) terminal structures 260, 264 to the RF input and RF output of module 200. As used herein, the expression "very close" in the above context means that the physical distance (e.g., distance 585, Figure 5A) between the side of a ground terminal (e.g., ground terminal 265 or 266) and the nearest side of a signal terminal (e.g., signal terminal 214) is less than twice the width of the signal terminals 212, 214. By implementing the GSG terminal structure at the RF input and RF output of module 200, the length of the return current loop associated with the terminal structure may be very short. In addition, the radiated electromagnetic energy from signal terminals 212 and 214 may be terminated to ground by the adjacent ground terminals 261, 262, 265, and 266, thereby avoiding potential performance problems that may arise when the radiated electromagnetic energy can reach other parts of the module.

[0062] In the embodiments shown in Figures 3, 4A, and 5, each signal and ground terminal 214, 215, 241-248, 261, 262, 264, 265 is provided with a rigid conductor terminal pillar or post, the base end of which is directly connected to the respective terminal pad (e.g., terminal pads 312, 314, 342, 343, 344, 365, 366), and the tip end is exposed at the contact surface 382 of module 200. According to one embodiment, the pillars for the signal and ground terminals 214, 216, 241-248, 261, 262, 264, 265 are formed from a highly conductive material such as copper or another suitable conductive metal. The pillars may be pre-formed and attached to the signal and ground terminals 214, 216, 241-248, 261, 262, 265 using solder, conductive adhesive, sintering, brazing, or other suitable materials and methods. In other embodiments, pillars may be pre-formed in-situ with respect to signal and ground terminals 214, 216, 241-248, 261, 262, 264, and 265.

[0063] As shown in Figure 2, in some embodiments, each terminal pillar may have a square or rectangular cross-section, but alternatively, in other embodiments, the terminal pillar may have a circular or rod-shaped cross-section. For example, when the terminal pillar has a square or circular cross-section, the terminal pillar may have a width 386 (or diameter) in the range of about 300 micrometers to about 800 micrometers (e.g., about 500 micrometers), but the width 386 may be smaller or larger. The height 385 of the terminal pillar may be in the range of about 500 micrometers to about 1500 micrometers (e.g., about 1000 micrometers), but for example, the terminal pillar may be shorter or taller. According to one embodiment, the height 385 of the terminal pillar may be approximately equal to the thickness 384 of the encapsulating material 380, such that the tip of the terminal pillar is substantially coplanar with the contact surface 382 of the module 200. In other embodiments, the tips of the signal and ground terminal pillars may be recessed below or extend above the contact surface 382 of the module 200. In any case, the tips of the signal and ground terminal pillars are exposed at the contact surface 382, ​​and the conductor mounting material at the tips allows the module 200 to be physically and electrically connected to the system board (e.g., system board 610, Figure 6).

[0064] Figures 3, 4A, and 5A show signal and ground terminals 214, 216, 241-248, 261, 262, 264, and 265 having conductive pillars embedded in the encapsulation material of module 200. In an alternative embodiment, as shown in Figures 4B, 5B, and 5C, the signal and ground terminals 214, 216, 241-248, 261, 262, 264, and 265 may instead be implemented in the form of a small interposer structure attached to the signal and ground terminal pads (e.g., terminal pads 312, 314, 342, 343, 344, 365, and 366) before overmolding the module substrate 210 and components with the encapsulation material 380.

[0065] For example, Figure 4B is a cross-sectional side view along line 4-4 of a modified version 200' of the power amplifier module 200 of Figure 2, and includes interposer ground terminals 243', 244' located on both sides of a power transistor die 234 according to another exemplary embodiment. Similarly, Figure 5B is a cross-sectional side view along line 5-5 of a modified version 200'' of the power amplifier module 200 of Figure 2, and includes interposer ground terminals 265', 266' located on both sides of an interposer signal terminal 214' according to another exemplary embodiment.

[0066] On the right side of Figure 4B are two cross-sectional views of a “typical” interposer terminal 491 (i.e., an interposer terminal that may be used for any or all of the signal and ground terminals of module 200). On that side, i.e., as shown in the cross-sectional view (upper view on the right side of Figure 4B), the interposer terminal 491 comprises a dielectric 492 (formed from, for example, FR-4, ceramic, or other suitable dielectric material) having top and bottom surfaces 493,494, and a conductor via 495 extending through the dielectric 492 between the top and bottom surfaces 493,494 of the dielectric 492. In addition, conductor pads 496,497 are placed on the top and bottom surfaces 493,494, in contact with the first and second ends of the conductor via 495, respectively. A top-down cross-sectional view (lower view on the right side of Figure 4B) shows that the conductor via 495 may have a circular cross-sectional shape. However, in other embodiments, the conductive via 495 may instead have a square, rectangular, or rod shape. In any case, the interposer terminal 491 provides a conductive path between the pads 496, 497 through the via 495.

[0067] When the via 495 has a square or circular cross-section, the via 495 may have a width 486 (or diameter) in the range of about 300 micrometers to about 800 micrometers (e.g., about 500 micrometers), although the width 486 may be smaller or larger. The height 485 of the interposer terminal 491 may be in the range of about 500 micrometers to about 1500 micrometers (e.g., about 1000 micrometers), although the interposer terminal may be shorter or taller, for example. According to one embodiment, the height 485 of the interposer terminal 491 may be approximately equal to the thickness 384 of the encapsulating material 380, such that the top conductor pad 496 of each interposer terminal may be substantially coplanar with the contact surface 382 of the module 200'. In other embodiments, the top conductor pad 496 of each interposer terminal, with the tips of the signal and ground terminal pillars, may be recessed below or extend above the contact surface 382 of the module 200'. In any case, the conductor pads 496 of each interposer terminal are exposed at the contact surface 382, ​​and the conductor mounting material 383 on the top conductor pads allows the module 200' to be physically and electrically connected to the system board (e.g., system board 610, Figure 6).

[0068] The signal and ground terminals 214, 216, 241-248, 261, 262, 264, and 265 in Figures 2 and 3 may be replaced with interposer terminals such as the interposer terminal 491 shown in Figure 4. For example, as described above, Figure 4B shows a modified module 200' having interposer ground terminals 243', 244' located on both sides of a power transistor die 234 according to an exemplary embodiment. Similar to the embodiment shown in Figure 4, the interposer ground terminals 243', 244' (each having the structure of a typical interposer terminal 491) are positioned close to the die 234, and the electrical length of the conductive path (e.g., dashed path 487') between the height of the ground contact for the die (e.g., bottom source contact 434), the RF ground layer (e.g., layer 302), an optional intervening via (e.g., via 444), the ground terminal pad (e.g., pad 344), and the interposer ground terminal (e.g., terminal 244') through the heat dissipation structure is less than about lambda / 5 (λ / 5) in some embodiments and less than about lambda / 16 (λ / 16) in other embodiments.

[0069] As described above, Figure 5B shows a modified module 200" in which interposer ground terminals 265' and 266', located on both sides of the interposer signal terminal 214', provide a GSG (ground-signal-ground) terminal structure 264' to the RF output of module 200". A similar structure may be implemented at the RF input of module 200".

[0070] Another embodiment is shown in Figure 5C, a cross-sectional side view of another modified version 200'' along line 5-5 of the power amplifier module 200 in Figure 2, and Figure 5C again shows a GSG terminal 264'' with interposer ground terminals 265'', 266'' arranged on both sides of the interposer signal terminal 214'' according to another exemplary embodiment. The main difference between the embodiments in Figure 5B and Figure 5C is that the multiple interposer terminals 265'', 266'', 214'' that generate the GSG terminal structure 264'' in Figure 5B are replaced in Figure 5C by a single, multi-terminal interposer 591. More specifically, the multi-terminal interposer 591 comprises a dielectric 592 (e.g., formed from FR-4, ceramic, or other suitable dielectric material) having top and bottom surfaces 593, 594, and multiple conductor vias 595-1, 595-2, 595-3 are dielectric 59 2 extends between the top and bottom surfaces 593, 594 of the dielectric 592. In addition, the conductor pads 596-1, 596-2, 596-3, 597-1, 597-2, 597-3 are placed on the top and bottom surfaces 593, 594, respectively, in contact with the first and second ends of each of the multiple conductor vias 595-1, 595-2, 595-3. Again, each of the conductor vias 595-1, 595-2, 595-3 is circular, square, The cross-sectional shape may be rectangular or bar-shaped. In any case, pad 596-1, via 595-1, and pad 597-1 correspond to the first ground interposer terminal 265”, the combination of pad 596-2, via 595-2, and pad 597-2 corresponds to the signal interposer terminal 214”, and the combination of pad 596-3, via 595-3, and pad 597-3 corresponds to the second ground interposer terminal 266”. The first and second ground interposer terminals 265”, 266”, and the signal interposer terminal 214”, generate yet another embodiment of the GSG terminal structure 264”.

[0071] As previously shown, to integrate an embodiment of the power amplifier module 200 into a larger electrical system (e.g., a first-stage amplifier in a cellular base station), one side of the power amplifier module 200 is physically and electrically coupled to a system board, and a heatsink is attached to the opposite side of the power amplifier module 200. To illustrate the integration of the power amplifier module 200 into such a system, refer to Figure 6. Figure 6 is a cross-sectional side view of an amplifier system 600 comprising the power amplifier module 200 of Figure 2, coupled to a system board 610 and a heatsink 616 according to an exemplary embodiment.

[0072] The RF system 600 comprises a system substrate 610, a power amplifier module 200 (or modules 200', 200", 200'''), and a heat sink. According to one embodiment, the system substrate 610 comprises a multilayer printed circuit board (PCB) or other suitable substrate. The system substrate 610 has a top surface 609 (also called the "mounting surface") and an opposite bottom surface 611. As shown in Figure 6, the system substrate 610 comprises a plurality of dielectric layers 605, 606, 607 (e.g., FR-4, ceramic, or other PCB dielectric material) arranged alternately with a plurality of conductive layers 601, 602, 603, and the top surface 609 of the system substrate 610 is formed by the patterned conductive layer 601. While the system substrate 610 is shown to comprise three dielectric layers 605-607 and three conductive layers 601-603, it should be noted that other embodiments of the system substrate may comprise more or fewer dielectric and / or conductive layers.

[0073] Each of the different conductor layers 601-604 may have a primary purpose and may also have conductor features for signaling and / or voltage / ground routing between other layers. The following description outlines the primary purposes of each of the conductor layers 601-603, but it should be understood that the layers (or their functions) may be arranged differently from the specific arrangement best shown in Figure 6 and discussed below.

[0074] For example, in one embodiment, a patterned conductor layer 601 on the mounting surface 609 of the system board 610 may function primarily as a signal transmission layer. More specifically, the layer 601 comprises a plurality of conductor features (e.g., conductor pads or traces), which function as a module 200, an input RF connector 691, and an output RF connector 692. Each of the RF connectors 691, 692 may be a coaxial connector having, for example, a central signal conductor 693 and an outer ground shield 694. According to one embodiment, the signal conductor 693 of the RF input connector 691 is electrically coupled to a first conductor trace 612 of layer 601 and similarly coupled to an input terminal 212 of module 200, as described in more detail below. In addition, the signal conductor 693 of the RF output connector 692 is electrically coupled to a second conductor trace 614 of layer 601 and similarly coupled to an output terminal (e.g., terminal 214, Figure 2) of module 200. The ground shield 694 of connectors 691 and 692 is electrically coupled to additional (unnumbered) traces and is similarly electrically coupled to the system ground layer 602 of the system board 610 through a conductive via 695 extending between layers 601 and 602.

[0075] As just shown, the conductor layer 602 functions as the system ground layer. In addition to being electrically coupled to the ground shield 694 of connectors 691 and 692, and to additional traces (unnumbered), the system ground layer 602 is also electrically coupled to an additional ground pad 641 on the mounting surface 609 via an additional conductor via 696. As will be described in more detail below, the additional ground pad 641 is physically and electrically coupled to various ground terminals of module 200 (e.g., terminals 241-248, 261, 262, 265, 266).

[0076] Module 200 (or any of modules 200', 200, 200"') is coupled to the mounting surface 609 of the system board 610 in an orientation reversed (or "flipped") from the orientation shown in Figures 3 to 5. More specifically, module 200 is coupled to the system board 610 such that the contact surface 382 of module 200 and the mounting surface 609 of the system board 610 face each other. To connect module 200 to the system board 610, each of the terminals of module 200 (e.g., terminals 212, 214, 241-248, 261, 262, 265, 266, Figure 2) is aligned and in contact with the corresponding pads on the mounting surface 609 of the system board 610. In embodiments where the conductor mounting material 383 is placed on the exposed ends of the module terminals, the conductor mounting material 383 is reflowed or cured to physically connect the module terminals to the corresponding pads on the mounting surface 609 of the module substrate 610. In other embodiments, the conductor mounting material may also be placed on conductor pads of the system substrate 610 (e.g., pads 612, 614, 641) and subjected to appropriate reflow or curing treatment to connect the module 200 to the system substrate 610.

[0077] In one embodiment, the heatsink 616 of the power amplifier module 200 is physically and thermally coupled to the heatsink mounting surface 211, and more specifically, to the conductive layer 304 and / or the surface 318 of the embedded heat dissipation structure 316 of the module 200. The heatsink 616 is formed from a thermal conductive material which may also be conductive. For example, the heatsink 616 may be formed from copper or another bulk conductive material. A thermal conductive material 698 (e.g., thermal grease) is dispensed onto the heatsink mounting surface 211 (and / or the surface 318 of the heat dissipation structure 316) and / or onto the heatsink to couple the heatsink 616 to the power amplifier module 200, so that the heatsink 616 may come into contact with the heatsink mounting surface 211. The heatsink 616 is then clamped, screwed, or fixed in place.

[0078] During operation of the RF system 600, the input RF signal is supplied to the RF input terminal 212 on the contact surface 382 of the power amplifier module 200 via the RF input terminal 691 and the trace / pad 612. The input RF signal is transmitted through terminal 212 and additional components (e.g., power splitter 220, Figure 2) to the power transistor dies 233, 234, 253, 254 that amplify the input RF signal as discussed earlier. The amplified output RF signal is generated at output terminal 214, which is coupled to the trace / pad 614 and to the RF output terminal 692.

[0079] According to one embodiment, a ground path is provided between each of the power transistor dies 233, 234, 253, 254 and the system ground layer 602. For example, in the dies 233, 234 shown in Figure 6, the ground path for each die 233, 234 comprises a first conductor ground path (e.g., ground paths 487, 487', Figures 4A, 4B) extending from the ground contact for the die through a portion of the heat dissipation structure 316, the RF ground layer 302 of the module 200, optional intervening vias (e.g., vias 442, 444), ground terminal pads (e.g., pads 342, 344, Figures 3, 4A, 4B), and one or more ground terminals (e.g., terminals 241-244, Figures 2, 3, 4A, 4B). As shown by the dashed line path 687 in Figure 6, the ground path extends to the system ground layer 602 through one or more ground pads 641 and one or more ground vias 696 on the mounting surface 609 of the system board 610.

[0080] As previously discussed in detail, the ground terminals 241-244 of module 200 are placed in close proximity to the power transistor dies 233, 234, 253, and 254, resulting in a relatively short ground return path for module 200. Preferably, the total electrical length of the ground path between the ground contacts for each die 233, 234, 253, and 254 and the system ground layer 602 is less than approximately lambda / 5 (λ / 5) in some embodiments and less than approximately lambda / 16 (λ / 16) in other embodiments.

[0081] During operation, a considerable amount of thermal energy (heat) can be generated by the power transistors within the power transistor dies 233, 234, 253, and 254. As indicated by arrow 699, the thermal energy generated by the power transistors is transferred to the heat sink 616 through a heat dissipation structure 316 that effectively dissipates the heat into the surrounding environment. Thus, the heat dissipation structure 316 provides two functions: 1) to transfer the heat generated by the power transistor dies 233, 234, 253, and 254 to the heat sink 616, and 2) to electrically connect the ground contacts of the dies 233, 234, 253, and 254 to the system ground.

[0082] Figure 7 is a flowchart of a method for fabricating a power amplifier module (e.g., power amplifier module 200, Figure 2) and assembling the power amplifier module into an RF system (e.g., RF system 600, Figure 6) according to an exemplary embodiment. The method may begin in block 702 by fabricating a multilayer module substrate (e.g., module substrate 210, Figures 2 and 3) using known techniques. As previously discussed, a plurality of pads and traces are formed from portions of a patterned conductive layer (e.g., layer 301, Figure 3) on the mounting surface of the module substrate. In block 704, various terminals (e.g., terminals 212, 214, 241-248, 262, 263, 265, 266, Figure 2), power transistor dies (e.g., dies 233, 234, 253, 254, Figure 2), and other components (e.g., power splitter 220, Figure 2) are connected to the mounting surface of the module board, and additional connections (e.g., wire bonds) are made between the power transistor dies and the components. In block 706, the module board, terminals, dies, and other components are encapsulated (e.g., by encapsulation material 380 in Figure 3) to form contact surfaces 382 (where the tips of the terminals are exposed).

[0083] In block 708, module 200 is inverted so that the module terminals are aligned and in contact with the corresponding pads (e.g., pads 612, 614, 641, Figure 6) on the mounting surface of the system board (e.g., system board, Figure 6). Conductive mounting material (e.g., solder or conductive adhesive material 383) is reflowed, cured, or treated to create mechanical and electrical connections between the module terminals and the system board pads. This establishes the signal and ground paths between the module and the system board.

[0084] Finally, in block 710, a heatsink (e.g., heatsink 616, Figure 6) is attached to the heatsink mounting surface (e.g., surface 211, Figures 3 and 6) of the module board. For example, the heatsink may be attached to the module board using a thermal conductive material (e.g., material 698 such as thermal grease), clamps, screws, and / or other mounting means. The method is then completed.

[0085] One embodiment of an amplifier module comprises a module substrate having a mounting surface, a signal transmission layer, a ground layer, and a first ground terminal pad on the mounting surface. A heat dissipation structure extends through the module substrate. The ground contacts of the power transistor die are coupled to the first surface of the heat dissipation structure. An encapsulation material covers the mounting surface and the power transistor die of the module substrate, and the surface of the encapsulation material forms the contact surface of the amplifier module. The first ground terminal is embedded within the encapsulation material. The first ground terminal has a base end coupled to the first ground terminal pad and a tip exposed at the contact surface. The first ground terminal is electrically coupled to the ground contacts of the power transistor die through the first ground terminal pad, the ground layer of the module substrate, and the heat dissipation structure.

[0086] One embodiment of an amplifier system comprises a system board and an amplifier module. The system board has a first mounting surface, a first signal transmission layer, a first ground layer, and a ground pad on the first mounting surface, the ground pad being electrically coupled to the first ground layer. The amplifier module has a contact surface and a heat sink mounting surface. The amplifier module is coupled to the system board such that the mounting surface of the system board faces the contact surface of the amplifier module. The amplifier module comprises a module board having a second mounting surface, a second signal transmission layer, a second ground layer, and a ground terminal pad on the second mounting surface. In addition, the amplifier module comprises a heat dissipation structure extending through the module board. The heat dissipation structure has a first surface and a second surface, the first surface being exposed on the second mounting surface of the module board. In addition, the amplifier module comprises a power transistor die having a ground contact, the ground contact being coupled to the first surface of the heat dissipation structure. The encapsulation material covers the second mounting surface of the module substrate and the power transistor die, and the surface of the encapsulation material forms the contact surface of the amplifier module. The amplifier module further includes a ground terminal embedded in the encapsulation material, the ground terminal having a base end coupled to the ground terminal pad and a tip exposed at the contact surface, and is electrically coupled to the ground contact of the power transistor through the ground terminal pad, the second ground layer of the module substrate, and the heat dissipation structure.

[0087] One embodiment of a method for manufacturing a power amplifier comprises the step of coupling a power transistor die to a heat dissipation structure extending through a module substrate, the module substrate having a first mounting surface, a first signal transmission layer, a first ground layer, and a first ground terminal pad on the first mounting surface. The first surface of the heat dissipation structure is exposed on the first mounting surface of the module substrate. The power transistor die has a ground contact coupled to the first surface of the heat dissipation structure. The method comprises the steps of coupling the base end of the first ground terminal to the first ground terminal of the module substrate, and covering the first mounting surface of the module substrate and the power transistor die with an encapsulation material to form an amplifier module. The surface of the encapsulation material forms a contact surface of the amplifier module, the tip of the first ground terminal is exposed on the contact surface, and the first ground terminal is electrically coupled to the ground contact of the power transistor die through the first ground terminal pad, the ground layer of the module substrate, and the heat dissipation structure.

[0088] The detailed descriptions provided herein are essentially illustrative and are not intended to limit the embodiments of this subject matter or the application and use of such embodiments. As used herein, the term “exemplary” means “to serve as an example, a demonstration or illustration.” Any implementation described herein as an example is not necessarily construed as preferable or advantageous to other implementations. Furthermore, there is no intention to be bound by any expressed or given theories presented in the aforementioned technical field, background, or detailed descriptions.

[0089] The connecting lines shown in the various drawings contained herein are intended to represent exemplary functional relationships and / or physical connections between various elements. It should be noted that many alternative or additional functional relationships or physical connections may be presented in one embodiment of this subject matter. In addition, certain technical terms may be used herein solely for reference purposes and are therefore not intended to be limiting; terms such as “first,” “second,” and other such terms referring to structures do not give a sequence or order unless explicitly indicated by the context.

[0090] As used herein, “node” means any internal or external reference point, connection point, link, signal line, conductor element, etc., to which a given signal, logic level, voltage, data pattern, current, or quantity is presented. Furthermore, three or more nodes may be realized by a single physical element (and three or more signals may be multiplexed, modulated, or distinguished even if they are received or output at a common node).

[0091] The aforementioned descriptions both refer to elements, nodes, or features that are “connected” or “joined.” As used herein, unless otherwise specified, “connected” means that one element is directly linked to (or communicates directly with) another element, not necessarily mechanically. Similarly, unless otherwise specified, “joined” means that one element is directly or indirectly linked to (or communicates directly or indirectly with) another element, not necessarily mechanically. Thus, while the schematics shown in the drawings represent one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in one embodiment of the subject matter shown.

[0092] While one or more exemplary embodiments are presented in the above detailed description, it is recognized that many variations exist. It is also recognized that one or more exemplary embodiments described herein are not intended to limit in any way the scope, availability, or configuration of the claimed subject matter. Rather, the above detailed description provides a convenient roadmap for those skilled in the art to implement one or more embodiments described herein. It is understood that various modifications are made in the function and arrangement of elements without departing from the scope defined by the claims, including known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. It is an amplifier module, A module substrate having a mounting surface, a signal transmission layer, a ground layer, and a first ground terminal pad on the mounting surface, A heat dissipation structure extending through the module substrate, having a first surface and a second surface, wherein the first surface is exposed on the mounting surface of the module substrate, A power transistor die having a ground contact, wherein the ground contact is coupled to the first surface of the heat dissipation structure, An encapsulation material that covers the mounting surface of the module substrate and the power transistor die, wherein the surface of the encapsulation material forms the contact surface of the amplifier module, An amplifier module comprising: a first ground terminal embedded in the encapsulating material, having a base end coupled to the first ground terminal pad and a tip exposed on the contact surface, and electrically coupled to the ground contact of the power transistor die through the first ground terminal pad, the ground layer of the module substrate, and the heat dissipation structure.

2. The amplifier module according to claim 1, wherein the heat dissipation structure comprises a conductive structure selected from a metal coin and a set of thermal vias.

3. The amplifier module according to claim 1, wherein the ground layer of the module substrate is in contact with the heat dissipation structure.

4. The amplifier module according to claim 1, wherein the first ground terminal is provided with a conductor pillar.

5. The first ground terminal is, The amplifier module according to claim 1, comprising an interposer terminal having a dielectric having a top surface and a bottom surface, and a conductive via extending between the top surface and the bottom surface of the dielectric.

6. The first ground terminal is, A first conductor pad located on the top surface of the dielectric and connected to the first end of the conductor via, the first conductor pad corresponding to the tip of the first ground terminal, The amplifier module according to claim 5, further comprising: a second conductor pad located on the bottom surface of the dielectric and connected to the second end of the conductor via, the second conductor pad corresponding to the base end of the first ground terminal.

7. The module board further comprises a signal terminal pad, a second ground terminal pad, and a third ground terminal pad on the mounting surface, wherein the signal terminal pad is electrically connected to either the input or output of the power transistor die through the signal transmission layer, and the second ground terminal pad and the third ground terminal pad are adjacent to the signal terminal pad. The aforementioned amplifier module is A signal terminal embedded within the aforementioned encapsulating material, having a base end coupled to the signal terminal pad and a tip exposed at the contact surface, A second ground terminal embedded within the aforementioned sealing material, having a base end coupled to the second ground terminal pad and a tip end exposed at the contact surface, A third ground terminal embedded within the aforementioned sealing material, further comprising a base end coupled to the third ground terminal pad and a tip end exposed at the contact surface, The amplifier module according to claim 1, wherein the signal terminal, the second ground terminal, and the third ground terminal form a ground-signal-ground terminal structure.

8. It is an amplifier system, A system substrate having a first mounting surface, a first signal transmission layer, a first ground layer, and a ground pad on the first mounting surface, wherein the ground pad is electrically coupled to the first ground layer, An amplifier module having a contact surface and a heat sink mounting surface, wherein the amplifier module is coupled to the system board such that the first mounting surface of the system board faces the contact surface of the amplifier module, and the amplifier module is A module substrate having a second mounting surface, a second signal transmission layer, a second ground layer, and a first ground terminal pad on the second mounting surface, A heat dissipation structure extending through the module substrate, having a first surface and a second surface, wherein the first surface is exposed on the second mounting surface of the module substrate, A power transistor die having a ground contact, wherein the ground contact is coupled to the first surface of the heat dissipation structure, An encapsulation material that covers the second mounting surface of the module substrate and the power transistor die, wherein the surface of the encapsulation material forms the contact surface of the amplifier module, An amplifier system further comprising: a first ground terminal embedded in the encapsulating material, having a base end coupled to the first ground terminal pad and a tip exposed on the contact surface, and electrically coupled to the ground contact of the power transistor die through the first ground terminal pad, the second ground layer of the module substrate, and the heat dissipation structure.

9. The amplifier system according to claim 8, wherein the tip of the first ground terminal is coupled to the ground pad of the system board.

10. The module board further comprises a signal terminal pad, a second ground terminal pad, and a third ground terminal pad on the second mounting surface, wherein the signal terminal pad is electrically connected to either the input or output of the power transistor die through the second signal transmission layer, and the second ground terminal pad and the third ground terminal pad are adjacent to the signal terminal pad. The aforementioned amplifier module is A signal terminal embedded within the encapsulating material, having a base end coupled to the signal terminal pad and a tip exposed at the contact surface and electrically coupled to the first signal transmission layer of the system substrate, A second ground terminal embedded within the encapsulating material, having a base end coupled to the second ground terminal pad and a tip end exposed at the contact surface and electrically coupled to the first ground layer of the system substrate, A third ground terminal embedded in the encapsulating material, further comprising a base end coupled to the third ground terminal pad and a tip end exposed at the contact surface and electrically coupled to the first ground layer of the system substrate, The amplifier system according to claim 8, wherein the signal terminal, the second ground terminal, and the third ground terminal form a ground-signal-ground terminal structure.

11. The amplifier system according to claim 8, further comprising a heat sink bonded to the heat sink mounting surface.

12. A method for fabricating a power amplifier, A process for coupling a power transistor die to a heat dissipation structure extending through a module substrate, The module substrate has a first mounting surface, a first signal transmission layer, a first ground layer, and a first ground terminal pad on the first mounting surface. The first surface of the heat dissipation structure is exposed on the first mounting surface of the module substrate. The power transistor die has a ground contact coupled to the first surface of the heat dissipation structure, and the process is as follows: A step of connecting the base end of the first ground terminal to the first ground terminal pad of the module substrate, A method comprising the steps of covering the first mounting surface of the module substrate and the power transistor die with an encapsulation material to form an amplifier module, wherein the surface of the encapsulation material forms a contact surface of the amplifier module, the tip of the first ground terminal is exposed at the contact surface, and the first ground terminal is electrically coupled to the ground contact of the power transistor die through the first ground terminal pad, the first ground layer of the module substrate, and the heat dissipation structure.

13. The method according to claim 12, further comprising the step of coupling the amplifier module to a system board such that the second mounting surface of the system board faces the contact surface of the amplifier module, wherein the system board further comprises a second signal transmission layer, a second ground layer, and a ground pad on the second mounting surface, the ground pad being electrically coupled to the second ground layer, and the tip of the first ground terminal being coupled to the ground pad.

14. The amplifier module has a heat sink mounting surface opposite to the contact surface, and the method is The method according to claim 13, further comprising the step of coupling the heatsink to the heatsink mounting surface of the amplifier module.

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