Semiconductor unit

Abstract

To equalize apportionment of a current at switching time among semiconductor modules connected in parallel to one another.SOLUTION: A laminated wiring 13 includes: a first conductor 13a which connects terminals 11a1-11d1 of capacitors 11a to 11d and each positive terminal 12a1-12f1 of a plurality of semiconductor modules 12a-12f; a second conductor 13b which connects terminals 11a2-11d2 of the capacitors 11a-11d and each negative terminal 12a2-12f2; and an insulator 13c. Slits 13a1-13a5, 13b1-13b5 are formed at least one of the first conductor 13a and the second conductor 13b (in both of them in the example of FIG. 1), and thereby among the semiconductor modules 12a-12f, a variation in a total of respective inductance values between the respective terminals 11a1-11d1 and one positive terminal 12a1-12f1 closest to the respective terminals and respective inductance values between the respective negative terminals 12a2-12f2 and one terminal 11a2-11d2 closest to the respective negative terminals is smaller than or equal to 10 nH.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor unit having a plurality of semiconductor modules connected in parallel.

Background Art

[0002] There is a semiconductor unit in which a plurality of semiconductor modules including switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are connected in parallel in order to improve the conduction current capacity.

[0003] Also, there is a technique of connecting a plurality of semiconductor modules in parallel using laminated wiring including a first conductor and a second conductor. For example, the positive terminals of each semiconductor module are connected to a first conductor connected to one of the two terminals of a capacitor functioning as a DC power supply, and the negative terminals of each semiconductor module are connected to a second conductor connected to the other of the two terminals of the capacitor. The output terminals of the plurality of semiconductor modules are electrically connected to the output terminals of the semiconductor unit.

[0004] Conventionally, in an inverter unit including a plurality of semiconductor switches connected in parallel, there is a technique of arranging output wiring at a position facing the input wiring and making the current paths uniform in the longest path so that current imbalance does not occur (see, for example, Patent Document 1). However, in the case of this structure, since the current path becomes long, the wiring inductance becomes large and the surge voltage at the time of switching becomes large. Also, since the path through which the high-frequency current flows at the time of switching also becomes long, EMI (Electro-Magnetic Interference) problems such as radiation noise occur.

[0005] It has been proposed to provide slits in busbars to resolve current imbalances in semiconductor modules connected in parallel (see, for example, Patent Documents 2 and 3). Furthermore, it is known that in multiple semiconductor chips connected in parallel, the emitter electrodes of each chip are connected to the same conductive material via individually positioned terminals (see, for example, Patent Document 4).

[0006] Furthermore, regarding the arrangement of multiple semiconductor modules, there is a method in which a capacitor module is provided around a rotating axis, and multiple semiconductor modules are arranged in a circumferential direction on the outer surface of the capacitor module (see, for example, Patent Document 5). Another method is to arrange multiple semiconductor modules concentrically around a cylindrical case in which a hole for passing a motor shaft or the like is formed (see, for example, Patent Document 6).

[0007] Furthermore, there is a technique that detects the circulating current flowing through the wiring connected to the emitters of parallel-connected switching elements and controls the on / off state of each switching element using a gate drive circuit based on the result (see, for example, Patent Document 7). [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2016-174503 [Patent Document 2] Japanese Patent Publication No. 2017-139915 [Patent Document 3] Japanese Patent Publication No. 2006-203974 [Patent Document 4] Japanese Patent Publication No. 2020-156310 [Patent Document 5] Japanese Patent Publication No. 2021-19383 [Patent Document 6] International Publication No. 2016-125673 [Patent Document 7] Japanese Patent Publication No. 2015-149828 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] In a technique for connecting multiple semiconductor modules in parallel by using laminated wiring to connect the positive and negative terminals of capacitors and each semiconductor module, the wiring inductance becomes uneven between the capacitor and the positive and negative terminals of each semiconductor module. Furthermore, the wiring inductance becomes uneven between the output terminals of each semiconductor module and the output terminals of the semiconductor unit. This leads to a problem of uneven current distribution during switching.

[0010] The present invention has been made in view of these points, and aims to provide a semiconductor unit that can equalize the current distribution during switching between semiconductor modules connected in parallel. [Means for solving the problem]

[0011] According to one aspect of the present invention, a semiconductor unit is provided comprising: one or more capacitors having a first terminal and a second terminal; a plurality of semiconductor modules, each having a positive terminal, a negative terminal and a first output terminal; a laminate wiring having a first conductor connecting the first terminal to each of the positive terminals; a second conductor connecting the second terminal to each of the negative terminals; an insulator disposed between the first conductor and the second conductor to insulate the first conductor and the second conductor, wherein a slit is provided in at least one of the first conductor and the second conductor so that the variation in the sum of the inductance values ​​from the first terminal to the nearest positive terminal and the inductance values ​​from the negative terminal to the nearest second terminal is 10 nH or less among the plurality of semiconductor modules; and an output wiring having each connection portion connected to each of the first output terminals; a second output terminal; and an intermediate portion electrically connecting each connection portion to the second output terminal. [Effects of the Invention]

[0012] According to the disclosed technology, it is possible to equalize the current sharing during switching between semiconductor modules connected in parallel.

Brief Description of the Drawings

[0013] [Figure 1] It is a plan view showing a semiconductor unit of the first embodiment. [Figure 2] It is a perspective view showing an example of a slit provided in the first conductor and the second conductor. [Figure 3] It is a diagram showing an example of an equivalent circuit of a semiconductor unit of the first embodiment. [Figure 4] It is a plan view showing a semiconductor unit of a comparative example. [Figure 5] It is a diagram showing an equivalent circuit of a semiconductor unit of a comparative example. [Figure 6] It is a plan view showing a modified example of a semiconductor unit of the first embodiment. [Figure 7] It is a plan view showing a semiconductor unit of the second embodiment. [Figure 8] It is a cross-sectional view taken along line VIII-VIII of FIG. 7. [Figure 9] It is a plan view showing the connection relationship between a capacitor and a laminated wiring. [Figure 10] It is a perspective view showing an example of a coaxial wiring portion. [Figure 11] It is a plan view showing a modified example of a semiconductor unit of the second embodiment. [Figure 12] It is a cross-sectional view taken along line XII-XII of FIG. 11.

Modes for Carrying Out the Invention

[0014] The embodiments for carrying out the invention will be described below with reference to the drawings. In the following description, "top," "bottom," "front side," and "back side" are merely convenient expressions to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "top" and "bottom" are not limited to the direction of gravity.

[0015] (First Embodiment) Figure 1 is a plan view showing a semiconductor unit according to the first embodiment. The semiconductor unit 10 has one or more capacitors (in the example of Figure 1, there are four capacitors 11a, 11b, 11c, and 11d) having first terminals and second terminals. Capacitors 11a to 11d function as DC power supplies. Hereinafter, the first terminals will be denoted as terminals 11a1, 11b1, 11c1, and 11d1. The second terminals will be denoted as terminals 11a2, 11b2, 11c2, and 11d2.

[0016] Furthermore, the semiconductor unit 10 has multiple semiconductor modules (in the example in Figure 1, there are six semiconductor modules 12a, 12b, 12c, 12d, 12e, and 12f), each having a positive terminal, a negative terminal, and a first output terminal. In Figure 1, the positive terminals of semiconductor modules 12a to 12f are positive terminals 12a1, 12b1, 12c1, 12d1, 12e1, and 12f1, and the negative terminals of semiconductor modules 12a to 12f are negative terminals 12a2, 12b2, 12c2, 12d2, 12e2, and 12f2.

[0017] Furthermore, in the example shown in Figure 1, each of the semiconductor modules 12a to 12f has two first output terminals. The first output terminals of semiconductor module 12a are first output terminals 12a3 and 12a4, the first output terminals of semiconductor module 12b are first output terminals 12b3 and 12b4, and the first output terminals of semiconductor module 12c are first output terminals 12c3 and 12c4. In addition, the first output terminals of semiconductor module 12d are first output terminals 12d3 and 12d4, the first output terminals of semiconductor module 12e are first output terminals 12e3 and 12e4, and the first output terminals of semiconductor module 12f are first output terminals 12f3 and 12f4.

[0018] Each of the semiconductor modules 12a to 12f has a configuration in which, as explained in Figure 3 below, for example, IGBTs, which are an example of switching elements, are connected in series, and a diode is connected in antiparallel to each switching element. Note that the number of semiconductor modules is not limited to six, but can be two or more.

[0019] Furthermore, the semiconductor unit 10 has laminate wiring 13. The laminate wiring 13 has a first conductor 13a on its back surface, a second conductor 13b on its front surface, and an insulator 13c between the first conductor 13a and the second conductor 13b, with a larger area in the XY plane than the first conductor 13a and the second conductor 13b. The laminate wiring 13 is positioned above the capacitors 11a to 11d. The first conductor 13a connects the terminals 11a1 to 11d1 of the capacitors 11a to 11d to the positive terminals 12a1 to 12f1, respectively. The second conductor 13b connects the terminals 11a2 to 11d2 of the capacitors 11a to 11d to the negative terminals 12a2 to 12f2, respectively. The insulator 13c is placed between the first conductor 13a and the second conductor 13b, and insulates the first conductor 13a from the second conductor 13b.

[0020] For example, copper or aluminum can be used as the material for the first conductor 13a and the second conductor 13b. For example, a resin material such as PET (Poly Ethylene Terephthalate) film or glass epoxy resin can be used as the material for the insulator 13c.

[0021] A slit is provided in at least one of the first conductor 13a and the second conductor 13b such that the variation in the sum of the inductance values ​​from terminals 11a1 to 11d1 to the nearest positive terminals 12a1 to 12f1 and the inductance values ​​from negative terminals 12a2 to 12f2 to the nearest terminals 11a2 to 11d2 is 10 nH or less between semiconductor modules 12a to 12f.

[0022] Figure 2 is a perspective view showing an example of slits provided in the first and second conductors. In the examples of Figures 1 and 2, the slits are provided in both the first conductor 13a and the second conductor 13b and are positioned to overlap in a plan view. As shown in Figure 2, the first conductor 13a is provided with slits 13a1, 13a2, 13a3, 13a4, and 13a5, and the second conductor 13b is provided with slits 13b1, 13b2, 13b3, 13b4, and 13b5.

[0023] In the example shown in Figure 1, the slits 13a1-13a5 and 13b1-13b5 are located between the positive and negative terminals of adjacent semiconductor modules in the X direction in a plan view.

[0024] Furthermore, the semiconductor unit 10 has an output wiring 14. The output wiring 14 has connection parts 14a1, 14a2, 14a3, 14a4, 14a5, and 14a6 that are connected to the first output terminals 12a3 to 12f3 and 12a4 to 12f4 of the semiconductor modules 12a to 12f, an intermediate part 14b, and a second output terminal 14c.

[0025] For example, the first output terminals 12a3 and 12a4 of semiconductor module 12a are connected to connection part 14a1, and the first output terminals 12b3 and 12b4 of semiconductor module 12b are connected to connection part 14a2. The intermediate part 14b electrically connects each of the connection parts 14a1 to 14a6 to the second output terminal 14c. The second output terminal 14c corresponds to the output terminal of the semiconductor unit 10.

[0026] Figure 3 shows an example of an equivalent circuit of the semiconductor unit according to the first embodiment. Each of the semiconductor modules 12a to 12f shown in Figure 1 has an upper arm and a lower arm made of IGBTs and diodes.

[0027] Semiconductor module 12a has IGBTs 20a and 22a and diodes 21a and 23a, semiconductor module 12b has IGBTs 20b and 22b and diodes 21b and 23b. Semiconductor module 12c has IGBTs 20c and 22c and diodes 21c and 23c, semiconductor module 12d has IGBTs 20d and 22d and diodes 21d and 23d, semiconductor module 12e has IGBTs 20e and 22e and diodes 21e and 23e, and semiconductor module 12f has IGBTs 20f and 22f and diodes 21f and 23f.

[0028] In semiconductor module 12a, the collector of IGBT20a and the cathode of diode 21a are connected to the positive terminal 12a1. The emitter of IGBT20a and the anode of diode 21a are connected to the first output terminals 12a3 and 12a4, and the collector of IGBT22a and the cathode of diode 23a. The emitter of IGBT22a and the anode of diode 23a are connected to the negative terminal 12a2. The other semiconductor modules 12b to 12f have a similar circuit configuration.

[0029] A gate control circuit (not shown) is connected to the gates of IGBTs 20a to 20f on the upper arm, and IGBTs 20a to 20f are turned on or off at the same timing. A gate control circuit (not shown) is also connected to the gates of IGBTs 22a to 22f on the lower arm, and IGBTs 22a to 22f are turned on or off at a timing opposite to that of IGBTs 20a to 20f.

[0030] The equivalent circuit in Figure 3 shows the wiring inductance of each part. As shown in Figures 1 and 2, by providing slits 13a1 to 13a5, the wiring inductance between capacitors 11a to 11d and positive terminals 12a1 to 12f1 is divided into wiring inductances 30, 31a, 31b, 31c, 31d, 31e, and 31f. Wiring inductance 30 is the wiring inductance of the wide wiring portion in the first conductor 13a where no slits are provided. Wiring inductances 31a to 31f are the wiring inductances of the narrow wiring portion separated by slits 13a1 to 13a5.

[0031] For example, the wiring inductance 31a is the wiring inductance in the portion between the left end of the first conductor 13a and the slit 13a1. The wiring inductance 31b is the wiring inductance in the portion of the first conductor 13a between the slits 13a1 and 13a2.

[0032] Similarly, as shown in Figures 1 and 2, by providing slits 13b1 to 13b5, the wiring inductance between capacitors 11a to 11d and negative terminals 12a2 to 12f2 is divided into wiring inductances 32, 33a, 33b, 33c, 33d, 33e, and 33f. Wiring inductance 32 is the wiring inductance of the wide wiring portion in the second conductor 13b where no slits are provided. Wiring inductances 33a to 33f are the wiring inductances of the narrow wiring portions separated by slits 13b1 to 13b5.

[0033] For example, the wiring inductance 33a is the wiring inductance in the portion between the left end of the second conductor 13b and the slit 13b1. The wiring inductance 33b is the wiring inductance in the portion of the second conductor 13b between the slits 13b1 and 13b2.

[0034] Furthermore, the wiring inductance between the first output terminals 12a3, 12a4~12f3, 12f4 and the second output terminal 14c is divided into wiring inductances 34a, 34b, 34c, 34d, 34e, 34f, and 35. Wiring inductances 34a~34f are the wiring inductances at the connection points 14a1~14a6 of the output wiring 14, and wiring inductance 35 is the wiring inductance at the intermediate section 14b of the output wiring 14.

[0035] Figure 3 also illustrates the wiring inductances within semiconductor modules 12a to 12f. Wiring inductances 36a, 36b, 36c, 36d, 36e, and 36f represent the wiring inductances between the upper arms of semiconductor modules 12a to 12f and the positive terminals 12a1 to 12f1, respectively. Wiring inductances 37a, 37b, 37c, 37d, 37e, and 37f represent the wiring inductances between the lower arms of semiconductor modules 12a to 12f and the negative terminals 12a2 to 12f2, respectively. Wiring inductances 38a, 38b, 38c, 38d, 38e, and 38f represent the wiring inductances between the upper and lower arms of semiconductor modules 12a to 12f and the first output terminals 12a3, 12a4 to 12f3, and 12f4, respectively.

[0036] As shown in Figures 1 and 2, by providing slits 13a1 to 13a5 and 13b1 to 13b5, the wiring inductance between capacitors 11a to 11d and semiconductor modules 12a to 12f becomes equivalent inductance value. The reason for this is explained below.

[0037] The wiring inductance of the laminate wiring 13 is inversely proportional to the wiring width and the distance between the first conductor 13a and the second conductor 13b. Therefore, the inductance values ​​of the wiring inductances 31a~31f and 33a~33f in the narrow wiring width section separated by the slits are larger than the inductance values ​​of the wiring inductances 30 and 32 in the wide wiring width section where no slits are provided. If the difference in wiring width between the wide wiring width section and the narrow wiring width section is large, the inductance value of the wiring inductance between the capacitors 11a~11d and the semiconductor modules 12a~12f will be approximately equal to the inductance values ​​of the wiring inductances 31a~31f and 33a~33f. By providing slits so that the wiring widths separated by the slits are the same, the inductance values ​​of the wiring inductances 31a~31f and 33a~33f can be made equal, and as a result, the wiring inductance between capacitors 11a~11d and semiconductor modules 12a~12f can be made to have the same inductance value. In this way, the variation in the total inductance value from terminals 11a1~11d1 to the nearest positive terminal 12a1~12f1 and from negative terminals 12a2~12f2 to the nearest terminal 11a2~11d2 can be kept below 10nH between semiconductor modules 12a~12f.

[0038] Furthermore, in each of the semiconductor modules 12a to 12f, the sum of the inductance values ​​of the wiring inductances 36a to 36f and the inductance values ​​of the wiring inductances 37a to 37f is approximately 10 nH, thus limiting the variation to 10 nH or less.

[0039] The positions and shapes of the slits 13a1-13a5 and 13b1-13b5 are not particularly limited to the above configuration, as long as the variation is 10 nH or less.

[0040] Furthermore, in the semiconductor unit 10 of the first embodiment, by providing the connection sections 14a1 to 14a6 and the intermediate section 14b as described above, the wiring inductance between the second output terminal 14c and the semiconductor modules 12a to 12f can be made to have equivalent inductance values. Since the wiring width of the connection sections 14a1 to 14a6 is narrower than that of the intermediate section 14b, the inductance values ​​of the wiring inductances 34a to 34f are larger than the inductance value of the wiring inductance 35. If the difference in wiring width between the connection sections 14a1 to 14a6 and the intermediate section 14b is large, the inductance value of the wiring inductance between the second output terminal 14c and the semiconductor modules 12a to 12f will be approximately the inductance value of the wiring inductances 34a to 34f. By providing connection points 14a1 to 14a6 with the same wiring width, the inductance values ​​of the wiring inductances 34a to 34f can be made equal, and as a result, the wiring inductance between the second output terminal 14c and the semiconductor modules 12a to 12f can be made to the same inductance value. In this way, on the output side as well, the variation in inductance values ​​from each of the connection points 14a1 to 14a6 to the second output terminal 14c can be kept to 10nH or less between the semiconductor modules 12a to 12f.

[0041] An example of the operation of the semiconductor unit 10 will be explained. When the IGBTs 20a to 20f on the upper arms of semiconductor modules 12a to 12f are turned on, current flows from capacitors 11a to 11d through semiconductor modules 12a to 12f and the second output terminal 14c. At this time, current flows through wiring inductances 30, 31a to 31f, 36a to 36f, 38a to 38f, 34a to 34f, and 35.

[0042] On the other hand, when the IGBTs 22a to 22f on the lower arms of semiconductor modules 12a to 12f are turned on, current flows from the second output terminal 14c through the semiconductor modules 12a to 12f and capacitors 11a to 11d. At this time, current flows through wiring inductances 35, 34a to 34f, 37a to 37f, 33a to 33f, and 32.

[0043] During switching, the change in current generates a voltage V = L·di / dt across the inductance of each wiring.

[0044] A single-phase inverter can be realized by using two such semiconductor units 10, and a three-phase inverter can be realized by using three semiconductor units 10.

[0045] As described above, in the semiconductor unit 10 of the first embodiment, the wiring inductance between capacitors 11a to 11d and semiconductor modules 12a to 12f, and between semiconductor modules 12a to 12f and the second output terminal 14c are evenly distributed. Therefore, the current distribution during switching can be equalized among semiconductor modules 12a to 12f.

[0046] (Comparative example) Figure 4 is a plan view showing a comparative semiconductor unit. In Figure 4, the same elements as those shown in Figure 1 are denoted by the same reference numerals.

[0047] The comparative semiconductor unit 40, like the semiconductor unit 10 of the first embodiment, has laminate wiring 41 having a first conductor 41a on the back surface, a second conductor 41b on the front surface, and an insulator 41c between the first conductor 41a and the second conductor 41b, with a larger area in the XY plane than the first conductor 41a and the second conductor 41b. However, the first conductor 41a and the second conductor 41b do not have slits.

[0048] Furthermore, the output wiring 42 of the comparative example semiconductor unit 40 has a common wiring 42a to which the first output terminals 12a3, 12a4~12f3, 12f4 are connected, and a second output terminal 42b connected to the central part of the common wiring 42a. The output wiring 42 does not have connection parts 14a1~14a6 like the semiconductor unit 10 of the first embodiment.

[0049] Figure 5 shows the equivalent circuit of a comparative semiconductor unit. In Figure 5, elements identical to those shown in Figure 3 are denoted by the same reference numerals.

[0050] Wiring inductances 45a, 45b, 45c, and 45d are the wiring inductances between capacitors 11a to 11d and positive terminals 12a1 to 12f1. Wiring inductances 46a, 46b, 46c, and 46d are the wiring inductances between capacitors 11a to 11d and negative terminals 12a2 to 12f2.

[0051] Wiring inductance 47a is the wiring inductance between the first output terminals 12a3,12a4 and the first output terminals 12b3,12b4. Wiring inductance 47b is the wiring inductance between the first output terminals 12b3,12b4 and the first output terminals 12c3,12c4. Wiring inductance 47c is the wiring inductance between the first output terminals 12c3,12c4 and the second output terminal 42b. Wiring inductance 47d is the wiring inductance between the second output terminal 42b and the first output terminals 12d3,12d4. Wiring inductance 47e is the wiring inductance between the first output terminals 12d3,12d4 and the first output terminals 12e3,12e4. Wiring inductance 47f is the wiring inductance between the first output terminals 12e3,12e4 and the first output terminals 12f3,12f4.

[0052] In such a semiconductor unit 40, the inductance values ​​of the wiring inductances 45a to 45d are uneven, and the inductance values ​​of the wiring inductances 46a to 46d are also uneven. This is because the distances from the capacitors 11a to 11d to the positive terminals 12a1 to 12f1 and the negative terminals 12a2 to 12f2 are uneven.

[0053] Furthermore, the inductance values ​​of the output wiring inductances are also uneven, as shown below. For example, the wiring inductances between the first output terminals 12a3 and 12a4 and the second output terminal 42b of semiconductor module 12a are 47a, 47b, and 47c. In contrast, the wiring inductance between the first output terminals 12c3 and 12c4 and the second output terminal 42b of semiconductor module 12c is only 47c. As a result, a larger current flows through semiconductor module 12c than through semiconductor module 12a, resulting in an uneven current distribution during switching.

[0054] In contrast to the semiconductor unit 40 of the comparative example, in the semiconductor unit 10 of the first embodiment, the wiring inductance is equalized as described above, so that the current distribution during switching can be equalized among the semiconductor modules 12a to 12f. Furthermore, this reduces the current derating (current reduction considering heat generation due to current imbalance) of the semiconductor modules 12a to 12f. For this reason, the current rating of the semiconductor unit 10 can be increased when using semiconductor modules of the same rating.

[0055] (modified version) Figure 6 is a plan view showing a modified example of the semiconductor unit of the first embodiment. In Figure 6, the same reference numerals are used for the same elements as those shown in Figure 1.

[0056] In the modified semiconductor unit 50, slits are provided such that at least one of the wiring widths of the path of the first conductor 13a connecting terminals 11a1 to 11d1 and positive terminals 12a1 to 12f1, or the wiring width of the path of the second conductor 13b connecting terminals 11a2 to 11d2 and negative terminals 12a2 to 12f2, becomes narrower as the distance to capacitors 11a to 11d decreases. For this reason, the shape of the slits differs from the slits in the semiconductor unit 10 of the first embodiment.

[0057] In the example shown in Figure 6, the positive terminals 12c1 and 12d1 are closer to the capacitors 11a to 11d than the positive terminals 12a1 and 12f1. Therefore, slits 51a1, 51a2, and 51a3 are provided such that the wiring width of the path of the first conductor 13a connecting the positive terminals 12c1 and 12d1 to terminals 11a1 to 11d1 is narrower than the wiring width of the path of the first conductor 13a connecting the positive terminals 12a1 and 12f1 to terminals 11a1 to 11d1. Slits 13a1 and 13a5 are I-shaped, while slits 51a1 to 51a3 are T-shaped.

[0058] Similarly, in the example in Figure 6, the negative terminals 12c2 and 12d2 are closer to the capacitors 11a to 11d than the negative terminals 12a2 and 12f2. For this reason, slits 51b1, 51b2, and 51b3 are provided such that the wiring width of the path of the second conductor 13b connecting the negative terminals 12c2 and 12d2 to terminals 11a2 to 11d2 is narrower than the wiring width of the path of the second conductor 13b connecting the negative terminals 12a2 and 12f2 to terminals 11a2 to 11d2. Slits 13b1 and 13b5 are I-shaped, while slits 51b1 to 51b3 are T-shaped.

[0059] As described above, by providing slits, the wiring width can be adjusted to take into account the distance to capacitors 11a to 11d, thereby further equalizing the wiring inductance.

[0060] Furthermore, in the modified semiconductor unit 50, the intermediate portion 52a of the output wiring 52 is formed such that the wiring width increases as it moves further away from the second output terminal 14c. This allows the intermediate portion 52a to be connected to the connection portions 14a1 to 14a6 with a wiring width that takes into account the distance from the second output terminal 14c. As a result, the wiring inductance can be made more uniform.

[0061] (Second Embodiment) Figure 7 is a plan view showing a semiconductor unit of the second embodiment. Figure 8 is a cross-sectional view taken along line VIII-VIII in Figure 7. Figure 9 is a plan view showing the connection relationship between the capacitor and the laminated wiring. Figure 10 is a perspective view showing an example of a coaxial wiring section. In Figures 7 to 9, the same reference numerals are used for the same elements as those shown in Figure 1.

[0062] In the semiconductor unit 60 of the second embodiment, as shown in Figure 7, the semiconductor modules 12a to 12f are arranged in a ring shape in plan view. As shown in Figures 7 and 8, the laminate wiring 61, which includes the first conductor 61a, the second conductor 61b, and the insulator 61c, is located in the central part of the ring.

[0063] Furthermore, cooling fins (for example, cooling fins 63a and 63d in Figure 8) are provided on the underside of the semiconductor modules 12a to 12d.

[0064] As shown in Figures 8 and 9, the positive terminals 12a1 to 12f1 of semiconductor modules 12a to 12f are electrically connected to the terminals 11a1 to 11d1 of capacitors 11a to 11d via a first conductor 61a located in the center of the ring. In addition, the negative terminals 12a2 to 12f2 of semiconductor modules 12a to 12f are electrically connected to the terminals 11a2 to 11d2 of capacitors 11a to 11d via a second conductor 61b located in the center of the ring.

[0065] Furthermore, as shown in Figure 9, slits are provided between the positive and negative terminals of adjacent semiconductor modules in the first conductor 61a and the second conductor 61b. Slits 61a1, 61a2, 61a3, 61a4, 61a5, and 61a6 are slits provided in the first conductor 61a, and slits 61b1, 61b2, 61b3, 61b4, 61b5, and 61b6 are slits provided in the second conductor 61b. Slits 61a1 to 61a6 and slits 61b1 to 61b6 are positioned to overlap in a plan view.

[0066] In the example shown in Figure 9, capacitors 11a to 11d are located in the central part of the circular laminate wiring 61. Therefore, the wiring distance from capacitors 11a to 11d to the positive terminals 12a1 to 12f1 or the negative terminals 12a2 to 12f2 can be approximately the same length. As a result, the variation in the inductance values ​​of the wiring inductance between semiconductor modules 12a to 12f is small, and slits do not necessarily need to be provided. However, providing slits can further reduce this variation.

[0067] Furthermore, the laminated wiring 61 has coaxial wiring sections 61d and 61e. The coaxial wiring section 61d is connected to a circular first conductor 61a, and the coaxial wiring section 61e is connected to a circular second conductor 61b. The coaxial wiring section 61e is located on the inner circumference side of the coaxial wiring section 61d. An insulator may be provided between the coaxial wiring sections 61d and 61e.

[0068] Furthermore, the output wiring 62 includes wiring sections 62a1, 62a2, 62a3, 62a4, 62a5, 62a6, coaxial wiring section 62b, and wiring section 62c that are connected to the first output terminals 12a3, 12a4, 12f3, and 12f4 of the semiconductor modules 12a to 12f.

[0069] The wiring sections 62a1 to 62a6 are formed to extend in the direction of the central axis of the ring from the first output terminals 12a3, 12a4 to 12f3 and 12f4 of the semiconductor modules 12a to 12f, and are connected to the coaxial wiring section 62b.

[0070] As shown in Figure 10, the coaxial wiring section 62b and the coaxial wiring sections 61d and 61e are coaxial with the central axis of the ring. The coaxial wiring section 62b is located on the outer circumference side of the coaxial wiring sections 61d and 61e, which are made of laminate wiring 61.

[0071] Wiring section 62c electrically connects wiring sections 62a1 to 62a6. Note that wiring section 62c is optional.

[0072] In this output wiring 62, the wiring sections 62a1 to 62a6 have the same function as the connection sections 14a1 to 14a6 shown in Figure 1. The coaxial wiring section 62b functions as the intermediate section 14b shown in Figure 1. The configuration corresponding to the second output terminal 14c in Figure 1 is not shown, but it is located above the coaxial wiring section 62b and is connected, for example, to an external power supply that charges the capacitors 11a to 11d.

[0073] The equivalent circuit of the semiconductor unit 60 is almost the same as the equivalent circuit shown in Figure 3, but if the wiring section 62c is provided, the first output terminals 12a3, 12a4 to 12f3, and 12f4 in Figure 3 will be connected.

[0074] By providing the output wiring 62 as described above, the wiring distance to the second output terminal can be made uniform between semiconductor modules 12a to 12f, thereby suppressing variations in the inductance value of the wiring inductance.

[0075] Furthermore, in the semiconductor unit 60 of the second embodiment, the laminate wiring 61 and output wiring 62 have coaxial wiring sections 61d, 61e, and 62b, so that electromagnetic field vibrations caused by high-frequency currents during switching can be shielded by the coaxial wiring section 62b. As a result, EMI noise can also be reduced.

[0076] (modified version) Figure 11 is a plan view showing a modified example of the semiconductor unit according to the second embodiment. Figure 12 is a cross-sectional view taken along line XII-XII in Figure 11. In Figures 11 and 12, the same reference numerals are used for the same elements as those shown in Figure 1.

[0077] In the modified semiconductor unit 70, similar to semiconductor unit 60, the semiconductor modules 12a to 12f are arranged in a ring shape in plan view, but the longest of the three sides representing height, length, or width is positioned parallel to the central axis of the ring. Figure 12 shows a schematic diagram of the dimensions of semiconductor module 12a. In the example in Figure 12, of the height H, length L, and width W, L is the longest, so the side L is positioned parallel to the central axis of the ring.

[0078] Furthermore, cooling fins 63a, 63b, 63c, 63d, 63e, and 63f are arranged on the outer periphery of each of the semiconductor modules 12a to 12f.

[0079] The laminated wiring 71 has a hexagonal shape in plan view and comprises a first conductor 71a, a second conductor 71b, and an insulator 71c. The connection relationships between the first conductor 71a and the second conductor 71b and the respective terminals of the capacitors 11a to 11d and the respective positive and negative terminals of the semiconductor modules 12a to 12f are the same as in Figure 9. The first conductor 71a and the second conductor 71b may be provided with slits as shown in Figure 9.

[0080] Furthermore, the laminated wiring 71 has hexagonal coaxial wiring sections 71d and 71e in plan view. The coaxial wiring section 71d is connected to the first conductor 71a, and the coaxial wiring section 71e is connected to the second conductor 71b. The coaxial wiring section 71e is located on the inner circumference side of the coaxial wiring section 71d. An insulator may be provided between the coaxial wiring sections 71d and 71e.

[0081] Furthermore, the output wiring includes wiring sections 72a1, 72a2, 72a3, 72a4, 72a5, and 72a6 connected to the first output terminals 12a3, 12a4, 12f3, and 12f4 of the semiconductor modules 12a to 12f (not shown in Figure 12), and a hexagonal coaxial wiring section 72b in plan view.

[0082] The wiring sections 72a1 to 72a6 are formed to extend in the direction of the central axis of the ring from the first output terminals 12a3, 12a4 to 12f3 and 12f4 of the semiconductor modules 12a to 12f, and are connected to the coaxial wiring section 72b.

[0083] As shown in Figures 11 and 12, the coaxial wiring section 72b and the coaxial wiring sections 71d and 71e are coaxial with the central axis of the ring. The coaxial wiring section 72b is located on the outer circumference side of the coaxial wiring sections 71d and 71e made of laminate wiring 71.

[0084] The same effects as those of semiconductor unit 60 can be obtained in the modified semiconductor unit 70 as described above. Furthermore, in semiconductor unit 70, the semiconductor modules 12a to 12f are arranged such that the longest of the three sides representing height, length, or width is parallel to the central axis of the ring, thus reducing the size of semiconductor unit 70 in the X and Y directions. In addition, in the examples of Figures 11 and 12, the first output terminals 12a3, 12a4 to 12f3, and 12f4 of semiconductor modules 12a to 12f can be brought closer together, thus shortening the wiring length of the output wiring.

[0085] The above describes one aspect of the semiconductor unit of the present invention based on embodiments, but these are merely examples and the invention is not limited to those described above. [Explanation of Symbols]

[0086] 10 Semiconductor Units 11a~11d Capacitors 11a1~11d1,11a2~11d2 terminal 12a~12f Semiconductor Modules 12a1~12f1 Positive terminal 12a2~12f2 Negative terminal 12a3, 12a4~12f3, 12f4 First output terminal 13. Laminated wiring 13a First Conductor 13a1~13a5, 13b1~13b5 Slit 13b Second conductor 13c insulator 14 Output Wiring 14a1~14a6 Connection section 14b Middle part 14c Second output terminal

Claims

1. One or more capacitors having a first terminal and a second terminal, Multiple semiconductor modules, each having a positive terminal, a negative terminal, and a first output terminal, A laminate wiring comprising a first conductor connecting the first terminal to each of the positive terminals, a second conductor connecting the second terminal to each of the negative terminals, and an insulator disposed between the first conductor and the second conductor to insulate the first conductor and the second conductor, wherein a slit is provided in at least one of the first conductor and the second conductor, so that the variation in the sum of the inductance values ​​from the first terminal to the nearest positive terminal and the inductance values ​​from the negative terminal to the nearest second terminal is 10 nH or less among the plurality of semiconductor modules, Output wiring having each connection part connected to each of the first output terminals, a second output terminal, and an intermediate part that electrically connects each of the connection parts and the second output terminal, A semiconductor unit equipped with the following features.

2. The semiconductor unit according to claim 1, wherein the slits are provided in both the first conductor and the second conductor and are positioned to overlap in a plan view.

3. The semiconductor unit according to claim 1, wherein the slit is provided such that at least one of the wiring widths of the path of the first conductor connecting the first terminal and the positive terminal, or the wiring width of the path of the second conductor connecting the second terminal and the negative terminal, becomes narrower as the distance to the one or more capacitors decreases.

4. The semiconductor unit according to any one of claims 1 to 3, wherein the output wiring has a variation in inductance value of 10 nH or less from each connection to the second output terminal.

5. The semiconductor unit according to claim 1, wherein the intermediate portion is formed such that the wiring width increases with respect to the portion further away from the second output terminal.

6. The semiconductor unit according to claim 1, wherein the plurality of semiconductor modules are arranged in a ring, the positive terminal of each of the plurality of semiconductor modules is electrically connected to the first terminal via the first conductor located in the central part of the ring, and the negative terminal of each of the plurality of semiconductor modules is electrically connected to the second terminal via the second conductor located in the central part.

7. The semiconductor unit according to claim 6, wherein the plurality of semiconductor modules arranged in a ring are arranged such that the longest of the three sides representing height, length, or width is parallel to the central axis of the ring.

8. The semiconductor unit according to claim 6, wherein each connection portion of the output wiring is formed to extend in the direction of the central axis of the ring from the first output terminal of each of the plurality of semiconductor modules arranged in a ring.

9. The semiconductor unit according to claim 6, wherein each of the output wiring and the laminate wiring includes a coaxial wiring portion with the central axis of the ring being coaxial.

Images