Low inductance components
By using leads with a specific length-to-width ratio and series capacitors, the inductance of multilayer ceramic devices is reduced, addressing the issue of self-inductance in lead wires and enabling compact, efficient electronic components with integrated filtering and protection.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KYOCERA AVX COMPONENTS CORP
- Filing Date
- 2026-02-20
- Publication Date
- 2026-05-19
AI Technical Summary
Lead wires in multilayer ceramic devices exhibit self-inductance, increasing the overall inductance of the component, which is undesirable in miniaturized electronic components.
Designing a low-inductance component with leads having a length-to-width ratio less than about 20, and incorporating capacitors in a series configuration, optionally with a discrete varistor, to reduce inductance.
The design achieves reduced inductance, making it suitable for space-constrained applications like automotive motor start-stop systems, while providing filtering and EMI/ESD protection in a single package.
Smart Images
Figure 2026083051000001_ABST
Abstract
Description
Technical Field
[0001] Cross - reference to Related Applications
[0001] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62 / 838,421, filed on April 25, 2019, which is incorporated herein by reference in its entirety. filed on April 25, 2019, which is incorporated herein by reference in its entirety.
Background Art
[0002]
[0002] For some time, the design of various electronic components has been driven by the general industry trend towards not only improving functionality but also miniaturization. Multilayer ceramic devices, such as multilayer ceramic capacitors and varistors, may be composed of multiple dielectric electrode layers. During manufacturing, the layers can be pressed and formed into a vertically stacked structure. Multilayer ceramic devices can include a single capacitor or multiple capacitors. Such devices can be provided with lead wires for connecting to other electrical components. However, lead wires exhibit self - inductance that undesirably increases the overall inductance of the component. However, lead wires exhibit self - inductance that undesirably increases the overall inductance of the component.
Summary of the Invention
Means for Solving the Problems
[0003]
[0003] According to one embodiment of the present invention, a low - inductance component can include a multilayer monolithic device including a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. Leads can be coupled to the first active terminal, the second active terminal, and / or the at least one ground terminal. The leads can have respective lengths and maximum widths. The ratio of the length to the maximum width of each lead can be less than about 20. Leads can be coupled to the first active terminal, the second active terminal, and / or the at least one ground terminal. The leads can have respective lengths and maximum widths. The ratio of the length to the maximum width of each lead can be less than about 20.
[0004]
[0004] According to another embodiment of the present invention, a method for forming a low inductance component The Act may include providing a multilayer monolithic device body including electrodes forming a pair of capacitors, forming a first active terminal, a second active terminal, and at least one ground terminal outside the multilayer monolithic device body such that the pair of capacitors are connected in series between a first active terminal and a second active terminal, and connecting at least one lead to at least one of the terminals of the first active terminal, the second active terminal, or the at least one ground terminal, wherein the at least one lead has a length and a maximum width, and the ratio of the length to the width of the at least one lead is less than about 20.
[0005]
[0005] Other features and aspects of the present invention will be discussed in more detail below.
[0006] A complete and effective representation of the subject matter of this disclosure, including its best mode, directed towards those skilled in the art. The disclosure is described herein with reference to the following attached drawings. [Brief explanation of the drawing]
[0006] [Figure 1A]
[0007] This is an external perspective view of an exemplary embodiment of a low-inductance component including a lead, as described in the subject matter of this disclosure. [Figure 1B]
[0008] This figure shows another embodiment of the lead of the device shown in Figure 1A, according to an aspect of the present disclosure. [Figure 2]
[0009] This is an external perspective view of another embodiment of a low-inductance component, including a discrete varistor, according to the subject matter of this disclosure. [Figure 3A]
[0010] This figure shows the first electrode layer of the component shown in Figure 1A, according to an aspect of the subject matter of this disclosure. [Figure 3B] This figure shows the second electrode layer of the component shown in Figure 1A, according to an aspect of the subject matter of this disclosure. [Figure 3C]
[0011] This figure shows the stack-up of electrodes, including the first electrode layer in Figure 3A and the second electrode layer in Figure 3B. [Figure 3D]
[0012] Figure 1A is a schematic diagram of the device. [Figure 3E]
[0013] Figure 2 is a schematic diagram of the device. [Figure 4A]
[0014] This figure shows a first electrode layer of an electrode configuration in another embodiment of a low-inductance component according to an aspect of the present disclosure. [Figure 4B] This figure shows a second electrode layer of the electrode configuration of another embodiment of a low-inductance component according to an aspect of the present disclosure. [Figure 4C]
[0015] This figure shows the stacking of electrodes, including the first electrode layer in Figure 4A and the second electrode layer in Figure 4B. [Figure 5A]
[0016] Figures 3A to 4C show an additional electrode configuration, including an additional capacitor, compared to the electrode configuration described above. [Figure 5B]
[0017] Figures 3A to 4C show another additional electrode configuration, including an additional capacitor, compared to the electrode configuration described above. [Figure 6]
[0018] Figure 6A is a schematic diagram of the device shown in Figure 5A.
[0019] Figure 6B is a schematic diagram of the device shown in Figure 5B. [Figure 7]
[0020] This is a flowchart of a method for forming a low-inductance component according to the subject matter of this disclosure. [Modes for carrying out the invention]
[0007]
[0021] The repeated use of reference numerals throughout this specification and the accompanying drawings is intended to represent the same or similar features, elements, or steps thereof.
[0022] Here, various embodiments of the present invention are referred to in detail, and one or more examples thereof are shown below. Each example is provided as an illustration of the present invention, not a limitation thereof. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention. For example, features illustrated or described as part of one embodiment can be used in another embodiment and can result in yet another embodiment. Accordingly, the present invention is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.
[0008]
[0023] Generally speaking, the present invention relates to low-inductance components. A low-inductance component can include one or more capacitors. Without intending to be limited by theory, a capacitor is an electrical component that stores electrical energy in an electric field. In some embodiments, the component can also include a discrete varistor connected to one or more capacitors. Without intending to be limited by theory, a varistor is an electrical component having an electrical resistance that can change depending on the applied voltage, thereby becoming a voltage-dependent resistor.
[0009]
[0024] The component can include one or more leads configured to exhibit low inductance. In certain applications, low inductance may be highly desirable. For example, aspects of the present disclosure can be particularly useful in automotive applications such as motor start-stop applications.
[0010]
[0025] The low-inductance leads can be coupled to a first active terminal, a second active terminal, and / or a ground terminal of the component. The leads can have respective lengths and maximum widths. The ratio of the length to the maximum width of each lead is less than about 50, in some embodiments less than about 30, in some embodiments less than about 20, in some embodiments less than about 15, in some embodiments less than about 10, in some embodiments less than about 8, In some embodiments, it can be less than about 5, in some embodiments less than about 4, and in some embodiments less than about 2.
[0011]
[0026] The leads can have various suitable cross-sectional shapes. For example, one or more leads can have a substantially rectangular cross-section. A substantially rectangular cross-section can have a maximum width in a first direction and a minimum width in a second direction perpendicular to the first direction. The ratio of the maximum width to the minimum width can be greater than about 2, and in some embodiments greater than about 3, in some embodiments greater than about 4, in some embodiments greater than about 5, in some embodiments greater than about 8, in some embodiments greater than about 10, in some embodiments greater than about 20, in some embodiments greater than 50, and in some embodiments greater than 100. However, in other embodiments, the leads can have a cross-sectional shape that is circular, oval, polygonal, or any other suitable shape.
[0012]
[0027] In some embodiments, one or more leads can comprise a plurality of elongated conductive members that are woven, braided, or otherwise configured together to form the lead.
[0013]
[0028] The above features can result in a low inductance component that can include one or more capacitors. For example, a first capacitor and a second capacitor can be configured in a split feedthrough type construction with respect to a first active terminal, a second active terminal, and at least one ground terminal. The first and second capacitors can be formed by internal electrodes separated by a dielectric layer. configured. The first and second capacitors can be formed by internal electrodes separated by a dielectric layer.
[0014]
[0029] ]>In some embodiments, a discrete varistor is coupled to a multilayer monolithic device to form a low-inductance integrated component with both capacitor and varistor functions. The discrete varistor may include a first external varistor terminal connected to a first active terminal of a multilayer capacitor and a second external varistor terminal connected to a second active terminal. For example, a discrete varistor and a multilayer capacitor can be stacked to form a single monolithic component. Combining capacitors and varistors provides low-inductance filtering and EMI and / or EMI / ESD circuit protection in a single package, which can be particularly useful in space-constrained situations. Furthermore, integrating capacitor and varistor functions into a single component reduces inductance compared to two separate components, each exhibiting its own parasitic inductance (e.g., caused by their respective leads).
[0015]
[0030] In some embodiments, leads can be connected to external terminals and / or components can be overmolded. Thus, the overmolded layer can encapsulate discrete varistors and multilayer monolithic capacitor devices. The overmolded layer can protect components from damage, for example, shock or moisture.
[0016]
[0031] As described above, the first and second capacitors may be configured in a split feedthrough type configuration. For example, the first plurality of electrode layers may be located within the body and connected to the first active terminal. The second plurality of electrode layers may be located within the body and connected to the second active terminal. The third plurality of electrode layers may be connected to the ground terminal and capacitively coupled to each of the first plurality of electrode layers and the second plurality of electrode layers (for example, in a split feedthrough type configuration). The first capacitor may be formed in a first overlap region between the first plurality of electrode layers and the third plurality of electrode layers. The second capacitor may be formed in a second overlap region between the second plurality of electrode layers and the third plurality of electrode layers. It is possible.
[0017]
[0032] In one embodiment, the first capacitor may have a first capacitance, and the second capacitor may have a second capacitance. In some embodiments, the first and second overlapping regions may be approximately equal such that the second capacitance may be approximately equal to the first capacitance. However, in other embodiments, the first and second overlapping regions may be different such that the first capacitance may be greater than or less than the second capacitance.
[0018]
[0033] For example, at least one of the first capacitances of the second capacitance may be in the range of about 10 nF to about 3 μF, in some embodiments, in the range of about 200 nF to about 2 μF, and in some embodiments, in the range of about 400 nF to about 1.5 μF. The second capacitance may be in the range of about 5% to about 500% of the first capacitance, in some embodiments, in the range of about 10% to about 300%, in some embodiments, in the range of about 25% to about 200%, and in some embodiments, in the range of about 50% to about 150%.
[0019]
[0034] In some embodiments, the third electrode layers can be cruciate in shape overall and can be connected to a pair of opposing grounding terminals. For example, each of the third electrode layers may include a pair of opposing edges. One of the opposing edges can be connected to a first grounding terminal, and the other of the opposing edges can be connected to a second grounding terminal.
[0020]
[0035] A multilayer monolithic capacitor device does not necessarily have to include any additional capacitors formed within the monolithic body. For example, the first, second, and third electrodes may consist of stacks of electrodes extending through most of the thickness of the monolithic body. For example, the ratio of the thickness of the electrode stack to the thickness of the monolithic body may range from about 0.5 to about 0.97, in some embodiments from about 0.6 to about 0.95, and in some embodiments from about 0.7 to about 0.9.
[0021]
[0036] Generally, the dielectric layers of multilayer monolithic devices can be made from any material commonly applied in the art. For example, the dielectric layer can be made from a ceramic material containing a titanate as its main component. The titanate may include, but is not limited to, barium titanate (BaTiO3). The ceramic material may also contain oxides of rare earth metals and / or compounds of acceptor-type elements such as Mn, V, Cr, Mo, Fe, Ni, Cu, Co, etc. The titanate may also include MgO, CaO, Mn3O4, Y2O3, V2O5, ZnO, ZrO2, Nb2O5, Cr2O3, Fe2O3, P2O5, SrO, Na2O, K2O, Li2O, SiO2, WO3, etc. In addition to ceramic powder, the ceramic material may also contain other additives, organic solvents, plasticizers, binders, dispersants, etc.
[0022]
[0037] In general, the internal electrodes of a multilayer monolithic device can be made of any material commonly applied in the art. For example, the internal electrodes can be formed by sintering a conductive paste in which the main component is a noble metal material. These materials may include, but are not limited to, palladium, palladium-silver alloys, nickel, and copper. For example, in one embodiment, the electrodes may be made of nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95% by weight or more. The Ni or Ni alloy may contain various trace components in amounts of 0.1% by weight or less, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc.
[0023]
[0038] The ceramic body of a multilayer monolithic device can be formed using any method commonly known in the art. For example, the ceramic body can be formed by creating a laminate in which ceramic sheets and patterned internal electrodes are alternately stacked, removing the binder from the laminate, sintering the binder-free laminate at a high temperature in the range of 1200°C to 1300°C in a non-oxidizing atmosphere, and then re-oxidizing the sintered laminate in an oxidizing atmosphere.
[0024]
[0039] Generally, varistors can be configured to divert electrical surges to ground. For example, a varistor may have a clamping voltage ranging from about 3 volts to about 150 volts, in some embodiments from about 5 volts to about 100 volts, in some embodiments from about 10 volts to about 50 volts, and in some embodiments from about 15 volts to about 30 volts.
[0025]
[0040] A varistor may include a ceramic body with external electrodes. The ceramic body is manufactured by sintering a laminate in which ceramic layers and internal electrodes are alternately stacked. Each pair of adjacent internal electrodes faces each other with a ceramic layer in between, and each can be electrically coupled to a different external electrode.
[0026]
[0041] Generally, the dielectric layer may include any suitable dielectric material, such as barium titanate, zinc oxide, or any other suitable dielectric material. For example, various additives that generate or increase the voltage-dependent resistance of the dielectric material may be included in the dielectric material. For example, in some embodiments, the additives may include oxides of cobalt, bismuth, manganese, or combinations thereof. In some embodiments, the additives may include oxides of gallium, aluminum, antimony, chromium, boron, titanium, lead, barium, nickel, vanadium, tin, or combinations thereof. The dielectric material may be doped with additives in the range of about 0.5 mol percent to about 3 mol percent, and in some embodiments, in the range of about 1 mol percent to about 2 mol percent. The average grain size of the dielectric material may contribute to the nonlinear properties of the dielectric material. In some embodiments, the average grain size may be in the range of about 10 microns to 100 microns, and in some embodiments, in the range of about 20 microns to 80 microns. The varistor may also include two terminals, and each electrode may be connected to its respective terminal. The electrode may provide resistance along its length and / or at the connection between the electrode and the terminal.
[0027]
[0042] In general, internal electrodes can be made from any material commonly used in the art. For example, internal electrodes can be formed by sintering a conductive paste in which the main component is a noble metal material. These materials may include, but are not limited to, palladium, palladium-silver alloys, silver, nickel, and copper. For example, in one embodiment, the electrodes may be made from nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95% by weight or more. Ni or Ni alloys may contain various trace components in amounts of 0.1% by weight or less, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, and S.
[0028]
[0043] Components can have various sizes. For example, components can have case sizes ranging from EIA0504 or lower to EIA2920 or higher. Examples of case sizes include 0805, 1206, 1806, 2020, etc.
[0029]
[0044] Next, exemplary embodiments will be described with reference to the drawings. Figure 1A shows an external perspective view of an exemplary embodiment of a low-inductance component 100, generally according to the subject matter of this disclosure. As illustrated, the component 100 may include a body 102 such as a hexahedron. The component 100 includes a first active terminal 104, a second active terminal 106, and a first terminal It may include a ground terminal 108 and a second grounding terminal 110.
[0030]
[0045] The first active lead 112 and the second active lead 114 may be connected to the first active terminal 104 and the second active terminal 106, respectively. The first ground lead 116 and the second ground lead 118 may be connected to the first ground terminal 108 and the second ground terminal 110, respectively.
[0031]
[0046] One or more of the leads 112, 114, 116, and 118 may have a length and a maximum width. The ratio of the length to the maximum width of at least one lead may be less than about 20. For example, the first active lead 112 may have a length 120 in the Z direction 122, a maximum width 124 in the X direction 126, and a minimum width 127 in the Y direction 128. The ratio of the maximum width 124 to the minimum width 127 may be greater than about 2. The first active lead 112 may have a substantially rectangular cross-sectional shape; for example, the first active lead 112 may be flattened overall, i.e., ribbon-shaped. In some embodiments, the ratio of the length to the maximum width of one or more leads 112, 114, 116, and 118 may be less than about 20. In some embodiments, each lead may have its respective length and width, each having a ratio of less than about 20.
[0032]
[0047] Figure 1B shows another embodiment of the lead 132 according to an aspect of the present disclosure. The lead 132 may have an overall circular or oval cross-sectional shape. The lead 132 may have a maximum width 134 and a minimum width 136. In other embodiments, the lead may comprise a plurality of elongated braided conductive members.
[0033]
[0048] Figure 2 shows an external perspective view of another embodiment of component 200 according to the subject matter of the present disclosure. Component 200 may include a multilayer monolithic device 201, which may include a body 202 such as a hexahedron, a first active terminal 204, a second active terminal 206, a first ground terminal 208, and a second ground terminal 210, as described above with reference to Figure 1A, for example.
[0034]
[0049] Component 200 may include a discrete varistor 240 having a first external varistor terminal 242 and a second external varistor terminal 244. Component 200 may include a first active lead 246 coupled to each of the first active terminal 204 and the first external varistor terminal 242 of the multilayer monolithic capacitor device 201. Component 200 may include a second active lead 248 coupled to each of the second active terminal 206 and the second external varistor terminal 244 of the multilayer monolithic capacitor device 201.
[0035]
[0050] One or more of the leads 246, 248, 250, and 251 may have the lengths and maximum widths described above, for example with reference to Figure 1A. The ratio of the length to the maximum width of one or more of the leads 246, 248, 250, and 251 may be less than about 20. For example, as shown with reference to Figure 2, the first active lead 248 may have a length 252 in the Z direction 122, a maximum width 254 in the X direction 126, and a minimum width 256 in the Y direction 128. The ratio of the maximum width 254 to the minimum width 256 may be greater than about 2. The first active lead 248 may have a substantially rectangular cross-sectional shape. For example, the first active lead 248 may be flattened overall (for example, like a ribbon shape). In some embodiments, each of the leads 246, 248, 250, and 251 may have a length that is at least 20 times greater than the maximum width of each of the leads 246, 248, 250, and 251.
[0036]
[0051] Low inductance component 100 in Figure 1A and / or multilayer monolayer in Figure 2 The thick capacitor device 201 may include two capacitors formed in series between a first terminal and a second terminal, as described herein, for example. As will be understood by those skilled in the art relating to all embodiments described herein, the coordinating layer in the multilayer structure in question comprises an electrode layer, which then forms an integrated capacitive structure.
[0037]
[0052] Figure 3A shows the first electrode layer 320. The first electrode layer 320 is described with reference to component 100 in Figure 1A. However, it should be understood that the multilayer monolithic capacitor device 201 in Figure 2 can be configured similarly. The first electrode layer 320 may include a cross-shaped electrode 322 having a pair of opposing edges 324, 326 connected to the first and second ground terminals 108, 110 of component 100 in Figure 1A, respectively. Figure 3B shows the second electrode layer 328, which includes a first electrode 330 connected to the first active terminal 104 (Figure 1A) and a second electrode 332 connected to the second active terminal 106 (Figure 1A). Figure 3C shows the stacking of the alternating first and second electrode layers 320, 328.
[0038]
[0053] Figure 3D shows a schematic diagram 300 of device 100 of Figure 1A. Device 100 can provide a single device solution for housing series and parallel capacitors. Device 100 may include a first capacitor 338 and a second capacitor 340. As shown again with reference to Figures 3A and 3B, the first capacitor 338 may be formed in a first overlap region 334 between the cross-shaped electrode 322 and the first electrode 330. The second capacitor 356 may be formed in a second overlap region 336 between the cross-shaped electrode 322 and the second electrode 332. The first overlap region 334 may be approximately equal to the second overlap region 336 such that the first and second capacitors exhibit approximately equal capacitance. However, in other embodiments, the first overlap region 334 may be larger or smaller than the second overlap region 336, and as a result, the first capacitance may be larger or smaller than the second capacitance. One or both of the first and second capacitances may be in the range of about 10 nF to about 3 μF.
[0039]
[0054] The first active lead 112 may be connected to the first capacitor 338 (for example, via the first active terminal 104 shown in Figure 1). The second active lead 114 may be connected to the second capacitor 340 (for example, via the second active terminal 106 shown in Figure 1). The first and second ground leads 116, 118 may be connected in a split feedthrough configuration at a position between the first and second capacitors 338, 340. For example, the first and second ground leads 116, 118 may be connected to ground terminals 180, 110, respectively (Figure 1A).
[0040]
[0055] Figure 3E shows a schematic diagram of device 200 in Figure 2. A varistor 352 may be electrically connected between the active leads 112 and 114.
[0056] Figures 4A and 4B show electrode configurations of other embodiments of multilayer capacitors according to aspects of the present disclosure. As shown with reference to Figure 4A, the first electrode layer 420 may include a cross-shaped electrode 222 having a pair of opposing edges 424, 426 that can be connected to the first and second ground terminals 108, 110 (Figure 1A), respectively. Figure 4B shows a second electrode layer 428 including a first electrode 430 connected to the first active terminal 104 and a second electrode 432 connected to the second active terminal 106. Figure 4C shows a stack of alternating first and second electrode layers 420, 428. As shown again with reference to Figure 4A, the cross-shaped electrode 422 may overlap with the first electrode 430 along the first overlap region 434 to form a first capacitor 438, and may overlap with the second electrode 432 along the second overlap region 436 to form a second capacitor 440.
[0041]
[0057] Figures 5A and 5B show, with reference to Figures 3A to 4C, each additional electrode configuration including an additional capacitor with respect to the electrode configuration described above. The electrode configurations of Figures 5A and 5B are described with reference to component 100 of Figure 1A. However, it should be understood that the multilayer monolithic capacitor device 201 of Figure 2 can be configured similarly. As shown with reference to Figure 5A, the first electrode configuration 500 may include a first region 501 and a second region 508. The first region may include, for example, a cross-shaped electrode 502, a first electrode 504, and a second electrode 506, as described above with reference to Figures 3A to 3C.
[0042]
[0058] The second region 508 may include a third capacitor formed by a plurality of interleaved third electrodes 510 with a plurality of fourth electrodes 512. The third electrodes 510 may be connected to a first active terminal 104 (Figure 1A), and the fourth electrodes 512 may be connected to a second active terminal 106 (Figure 1A).
[0043]
[0059] Figure 5B shows a second electrode configuration 550 including a first region 552, a second region 554, and a third region 556. The first region 552 may include an electrode stack including one or more cross-shaped electrodes 558, one or more first electrodes 560, and one or more second electrodes 562, for example, as described above with reference to Figures 3A to 3C.
[0044]
[0060] The second region 554 may include a plurality of third electrodes 564 interleaved with a plurality of fourth electrodes 566. The third electrodes 564 may be connected to a first active terminal 104 (Figure 1A), and the fourth electrodes 556 may be connected to a second active terminal 106 (Figure 1A).
[0045]
[0061] The third region 556 may include, for example, a stack of electrodes including a cross-shaped electrode 568, a first electrode 570, and a second electrode 572, as described above with reference to Figures 3A to 3C.
[0046]
[0062] Figure 6A shows a schematic diagram of device 500 of Figure 5A. More specifically, device 500 may include active leads 602, 603. The first capacitor 604 and the second capacitor 606 may be formed in the first region 607, for example, as described above with reference to Figure 5A. The ground lead 610 may be connected at a location between the first capacitor 604 and the second capacitor 606 (for example, connected to the cross-shaped electrode 502 as described above with reference to Figure 5A). The third capacitor 608 may be electrically connected in parallel with the first and second capacitors 604, 606 in the second region 609, between the active leads 602, 603, as described above with reference to Figure 5A.
[0047]
[0063] Figure 6B shows a schematic diagram of device 550 in Figure 5B. Device 550 can generally be configured similarly to device 500 in Figure 5A. In addition, varistor 660 may be connected in parallel with capacitors 654, 656, and 658 between active leads 648 and 652.
[0048]
[0064] Figure 7 is a flowchart of Method 700 for forming a low-inductance component. Generally, Method 700 is described herein with reference to components 100, 200 in Figures 1A and 2. However, it should be understood that the disclosed Method 700 can be carried out using any suitable component. In addition, although Figure 7 shows the steps performed in a particular order for illustrative and explanatory purposes, the method described herein is not limited to a particular order or arrangement. A person skilled in the art using the disclosure provided herein will be able to describe various steps of the method disclosed herein without departing from the scope of this disclosure. You will come to understand that the 'P' can be omitted, rearranged, combined, and / or adapted in various ways.
[0049]
[0065] Method 700 may include, in (702), providing a multilayer capacitor body including electrodes that form a pair of capacitors, as described above with reference to Figures 1A to 6B, for example.
[0050]
[0066] Method 700 may include, for example, as described above with reference to Figures 1A to 6B, forming a first active terminal, a second active terminal, and at least one ground terminal outside the multilayer capacitor body such that a pair of capacitors are connected in series between the first active terminal and the second active terminal in (704).
[0051]
[0067] Method 700 may include, in (706), connecting at least one lead to at least one of the first active terminal, the second active terminal, or at least one ground terminal. The leads may have their respective lengths and maximum widths. (If there are multiple leads) the ratio of the length to the width of each of the at least one lead may be less than about 20.
[0052]
[0068] It should be understood that the individual steps in achieving the disclosed configuration are intended only as representative examples and do not represent the necessary use of other aspects beyond the general nature of the otherwise disclosed information. For example, a person skilled in the art will recognize that the selected steps may be performed to produce a particular design selected for a given use of the subject matter of this disclosure.
[0053]
[0069] While such subject matter of this disclosure is described in detail with respect to its particular embodiments, those skilled in the art will understand that, once they reach the aforementioned understanding, modifications, variations, and equivalents to such embodiments will readily be generated. Therefore, the scope of this disclosure is by example and not by limitation, and the disclosure of subject matter does not preclude the inclusion of such modifications, variations, and / or additions to the subject matter of this disclosure, as will readily apparent to those skilled in the art.
Claims
1. A multilayer monolithic device comprising a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal, A low-inductance component comprising at least one lead coupled to the first active terminal, the second active terminal, or at least one of the at least one ground terminal, wherein the at least one lead has a length and a maximum width, and the ratio of the length of the at least one lead to the maximum width is less than about 20.
2. The low-inductance component according to claim 1, wherein at least one lead has a substantially rectangular cross-section, the substantially rectangular cross-section having the maximum width in a first direction and the minimum width in a second direction perpendicular to the first direction.
3. The low-inductance component according to claim 2, wherein the ratio of the maximum width to the minimum width is greater than approximately 2.
4. The low-inductance component according to claim 1, wherein the at least one lead comprises a first active lead, a second active lead, and at least one ground lead, each connected to the first active terminal, the second active terminal, and the at least one ground terminal, respectively.
5. The low-inductance component according to claim 1, further comprising a discrete varistor having a first external varistor terminal and a second external varistor terminal, wherein at least one lead comprises a first lead coupled to the first active terminal and the first external varistor terminal, respectively.
6. The low-inductance component according to claim 1, wherein the at least one lead comprises a plurality of woven elongated conductive members.
7. The aforementioned multilayer monolithic device further, A main body comprising multiple dielectric layers, A plurality of first electrode layers are arranged within the main body and connected to the first active terminal, A plurality of second electrode layers are arranged within the main body and connected to the second active terminal, The component according to claim 1, comprising a third plurality of electrode layers connected to at least one grounding terminal, the third plurality of electrode layers capacitively coupled to each of the first plurality of electrode layers and the second plurality of electrode layers, forming the first capacitor between the first plurality of electrode layers and the third plurality of electrode layers, and the second capacitor between the second plurality of electrode layers and the third plurality of electrode layers.
8. The component according to claim 7, wherein the third plurality of electrode layers are generally cross-shaped.
9. The component according to claim 7, wherein the at least one grounding terminal comprises a first grounding terminal and a second grounding terminal.
10. The component according to claim 9, wherein each of the third plurality of electrode layers comprises a pair of opposing edges, one of the opposing edges being connected to the first grounding terminal and the other of the opposing edges being connected to the second grounding terminal.
11. The component according to claim 9, wherein the first grounding terminal is located on the opposite side of the second grounding terminal.
12. The component according to claim 1, wherein the first capacitor has a first capacitance, and the second capacitor has a second capacitance that is substantially equal to the first capacitance.
13. The component according to claim 1, wherein at least one of the first capacitance or the second capacitance is in the range of about 10 nF to about 3 μF.
14. The third plurality of electrode layers overlap with the first plurality of electrode layers along the first overlap region, The component according to claim 1, wherein the third plurality of electrode layers overlap with the second plurality of electrode layers along a second overlap region substantially equal to the first overlap region.
15. The discrete varistor is stacked on top of the multilayer monolithic device, as per claim 1.
16. The component according to claim 1, further comprising an overmolded layer that encapsulates the discrete varistor and the multilayer monolithic device.
17. The component according to claim 1, wherein the ratio of the thickness of the stacked electrodes to the thickness of the monolithic body is greater than about 0.
4.
18. The component according to claim 1, further comprising a fourth plurality of electrodes connected to the first external terminal, and a fifth plurality of electrodes connected to the second external terminal and interleaved with the fourth plurality of electrodes to form a third capacitor.
19. A method for forming a low-inductance component, The steps include providing a multilayer monolithic device body including electrodes that form a pair of capacitors, The steps include forming the first active terminal, the second active terminal, and at least one ground terminal outside the multilayer monolithic device body such that the pair of capacitors are connected in series between the first active terminal and the second active terminal, A method comprising the step of connecting at least one lead to at least one of the first active terminal, the second active terminal, or the at least one ground terminal, wherein the at least one lead has a length and a maximum width, and the ratio of the length to the width of the at least one lead is less than about 20.