Power semiconductor elements and power semiconductor modules

Abstract

To provide a power semiconductor element and a power semiconductor module with good heat dissipation efficiency even in a power semiconductor chip with a termination structure such as a guard ring, a field plate, and a RESURF.SOLUTION: A power semiconductor element 1 has a power semiconductor chip 10 with a first electrode 11 and a second electrode 12 on a first side and a third electrode 13 on a second side, the opposite side of the first side, where the first electrode 11 is provided in the main cell area, and a fourth electrode 31 provided on the first side of the power semiconductor chip 10 so that it can conduct with the first electrode 11 and has an overhang extending outward from the outer periphery of the power semiconductor chip 10.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a power semiconductor device and a power semiconductor module.

Background Art

[0002] A power semiconductor device is a semiconductor device that has a large voltage and current to be handled and has a switching function, and is used for power control and power conversion in power transmission and distribution systems, trains, hybrid vehicles, electric vehicles, various production facilities, home appliances, industrial machines, and the like. As a modularized form of such a power semiconductor device, Patent Document 1 discloses a power module having a double-sided heat dissipation structure provided with heat dissipation plates on the upper side and the lower side, respectively.

[0003] When modularizing a power semiconductor device, it is necessary to wire the power semiconductor chip constituting the power semiconductor device and an external terminal with a wire or a lead frame and then seal it with resin. A power semiconductor chip is obtained by fabricating a switching element in a wafer made of a power semiconductor material such as Si or SiC in a previous process and then dicing it, and is also called a die. Such a power semiconductor chip has a terminal structure portion provided so as to surround its periphery on the first surface side where a main cell region (for example, a source region) is provided. Such a terminal structure portion has, for example, a guard ring, a field plate, a RESURF, and a structure combining these, and alleviates the electric field concentration on the first surface side.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When modularizing power semiconductor elements in this way, one end of the wire and one end of the lead frame must be routed with an upward distance from the termination structure. Although the lead frame has a larger cross-sectional area than the wire, the area in contact with the main cell region of the power semiconductor chip by one end of the lead frame is small, making it difficult to connect the lead frame to the main cell region. As the size of the power semiconductor chip becomes even smaller, the area for attaching wires and lead frames becomes even smaller, making miniaturization and improvement of heat dissipation efficiency difficult.

[0006] Therefore, one of the objectives of the present invention is to provide a power semiconductor element and a power semiconductor module that have good heat dissipation efficiency even in power semiconductor chips having termination structures such as guard rings, field plates, and resurfs. [Means for solving the problem]

[0007] The concept of this invention is as follows: One concept of this invention is, A power semiconductor chip comprising a first electrode and a second electrode on a first surface, and a third electrode on the second surface opposite to the first surface, wherein the first electrode is located in the main cell region, A fourth electrode is provided on the first surface side of the power semiconductor chip so as to be able to conduct electricity with the first electrode, and has a protruding portion that extends outward from the outer peripheral edge of the power semiconductor chip, It is a power semiconductor device equipped with [a specific feature / ability]. One concept of this invention is, A plurality of power semiconductor chips, each having a first electrode and a second electrode on a first surface, and a third electrode on the second surface opposite to the first surface, with the first electrode located in the main cell region. A fourth electrode is provided so as to be able to conduct electricity with each of the first electrodes of the plurality of power semiconductor chips, and has a protruding portion that extends outward from the outer edge of the power semiconductor chip, This relates to a power semiconductor device equipped with the following features. One concept of this invention is, The present invention relates to a power semiconductor module comprising one or more of the power semiconductor elements, wherein a metal layer is provided on the outer side in the thickness direction of the power semiconductor chip as part of the fourth electrode so as to be conductive to an external terminal. One concept of this invention is, Multiple power semiconductor devices belonging to the first group, Multiple power semiconductor devices belonging to the second group, Equipped with, Each of the plurality of power semiconductor elements in the first group and the second group is, A power semiconductor chip comprising a first electrode and a second electrode on a first surface, and a third electrode on the second surface opposite to the first surface, wherein the first electrode is located in the main cell region, A fourth electrode is provided so as to be electrically connected to the first electrode of the corresponding power semiconductor chip, and has a protruding portion that extends outward from the outer peripheral edge of the corresponding power semiconductor chip, A fifth electrode provided to be electrically connected to the third electrode of the corresponding power semiconductor chip, A sixth electrode provided to be electrically connected to the second electrode of the corresponding power semiconductor chip, It is equipped with, The fourth and sixth electrodes of each of the power semiconductor elements in the first group are arranged in the same direction as the fifth electrode of each of the power semiconductor elements in the second group. The fourth electrode of each power semiconductor element in the first group, the fifth electrode of each power semiconductor element in the first group, the sixth electrode of each power semiconductor element in the first group, the fourth electrode of each power semiconductor element in the second group, the fifth electrode of each power semiconductor element in the second group, and the sixth electrode of each power semiconductor element in the second group are provided to be electrically connected to the corresponding external terminals of the fourth electrode, the fifth electrode, and the sixth electrode for each group. Regarding power semiconductor modules. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide power semiconductor elements and power semiconductor modules that have good heat dissipation efficiency even in power semiconductor chips having termination structures such as guard rings, field plates, and resurfs. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic cross-sectional view showing a power semiconductor device according to the first embodiment of the present invention. [Figure 2] Figure 2 is a schematic diagram showing a top view of a power semiconductor device according to the first embodiment of the present invention. [Figure 3] Figure 3 is a schematic cross-sectional view of a power semiconductor device according to a second embodiment of the present invention. [Figure 4] Figure 4 is a schematic diagram showing a top view of a power semiconductor device according to a second embodiment of the present invention. [Figure 5] Figure 5 is a schematic diagram showing a top view of a power semiconductor device according to a second embodiment of the present invention, which differs from Figure 4. [Figure 6] Figure 6 is a schematic diagram showing a top view of a power semiconductor device according to a second embodiment of the present invention, which differs from Figures 4 and 5. [Figure 7]FIG. 7 is a diagram schematically showing a top view of a power semiconductor device according to a second embodiment of the present invention, which is different from FIGS. 4 to 6. [Figure 8] FIG. 8 is a cross-sectional view schematically showing the outline of a power semiconductor device according to a third embodiment of the present invention. [Figure 9] FIG. 9 is a diagram schematically showing the positional relationship in a top view of a power semiconductor chip, an enclosure portion, a first electrode, and a third electrode among the power semiconductor devices according to the third embodiment of the present invention. [Figure 10] FIG. 10 is a diagram schematically showing a top view of a power semiconductor chip. [Figure 11] FIG. 11 is a cross-sectional view schematically showing the outline of a power semiconductor device according to a fourth embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view schematically showing the outline of a power semiconductor module according to a fifth embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view schematically showing the outline of a power semiconductor module according to a sixth embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view schematically showing the outline of a power semiconductor module according to a seventh embodiment of the present invention. [Figure 15] FIG. 15 is a cross-sectional view schematically showing the outline of a power semiconductor module according to an eighth embodiment of the present invention. [Figure 16A] FIG. 16A is a cross-sectional view schematically showing a starting state of a method for manufacturing a power semiconductor module according to a ninth embodiment of the present invention. [Figure 16B] FIG. 16B is a cross-sectional view schematically showing the next state of FIG. 16A for a method for manufacturing a power semiconductor module according to a ninth embodiment of the present invention. [Figure 16C] FIG. 16C is a cross-sectional view schematically showing the next state of FIG. 16B for a method for manufacturing a power semiconductor module according to a ninth embodiment of the present invention. [Figure 16D] FIG. 16D is a cross-sectional view schematically showing the next state of FIG. 16C for a method for manufacturing a power semiconductor module according to a ninth embodiment of the present invention. [Figure 16E]Figure 16E is a schematic cross-sectional view showing the next state in Figure 16D regarding a method for manufacturing a power semiconductor module according to the ninth embodiment of the present invention. [Figure 16F] Figure 16F is a schematic cross-sectional view showing the next state in Figure 16E regarding a method for manufacturing a power semiconductor module according to the ninth embodiment of the present invention. [Figure 16G] Figure 16G is a schematic cross-sectional view showing the next state in Figure 16F regarding a method for manufacturing a power semiconductor module according to the ninth embodiment of the present invention. [Figure 17A] Figure 17A is a schematic cross-sectional view showing the starting state of a method for manufacturing a power semiconductor module according to the 10th embodiment of the present invention. [Figure 17B] Figure 17B is a schematic cross-sectional view showing the next state in Figure 17A regarding the manufacturing method of a power semiconductor module according to the tenth embodiment of the present invention. [Figure 17C] Figure 17C is a schematic cross-sectional view showing the next state in Figure 17B regarding a method for manufacturing a power semiconductor module according to the tenth embodiment of the present invention. [Figure 17D] Figure 17D is a schematic cross-sectional view showing the next state in Figure 17C regarding a method for manufacturing a power semiconductor module according to the tenth embodiment of the present invention. [Figure 17E] Figure 17E is a schematic cross-sectional view showing the next state in Figure 17D regarding a method for manufacturing a power semiconductor module according to the tenth embodiment of the present invention. [Figure 17F] Figure 17F is a schematic cross-sectional view showing the next state of Figure 17E regarding a method for manufacturing a power semiconductor module according to the tenth embodiment of the present invention. [Figure 18] Figure 18 is a cross-sectional view showing an example of a power semiconductor chip. [Figure 19A] Figure 19A is a perspective view of a power module according to the 11th embodiment of the present invention. [Figure 19B] Figure 19B is a partially exploded view of a power module according to the 11th embodiment of the present invention. [Figure 20A]Figure 20A is a plan view of the first ceramic plate and the metal plate provided thereon. [Figure 20B] Figure 20B is a bottom view of the first ceramic plate and the metal plate provided thereon. [Figure 21A] Figure 21A is a plan view of the second ceramic plate and the metal plate provided thereon. [Figure 21B] Figure 21B is a bottom view of the second ceramic plate and the metal plate provided thereon. [Figure 22] Figure 22 shows the power semiconductor module shown in Figure 19A, in a hypothetical assembly configuration sandwiched between two ceramic plates, illustrating the arrangement of each component. [Figure 23] Figure 23 shows the equivalent circuit of the power semiconductor module shown in Figure 19A. [Figure 24A] Figure 24A shows the pattern of the fourth electrode in a power semiconductor device. [Figure 24B] Figure 24B shows the pattern of the fourth electrode in a power semiconductor device different from that shown in Figure 24A. [Figure 25] Figure 25 shows a microscopic image of the prototype sample, with the upper left being the first surface and the upper right being the second surface. The lower left and lower right show line diagrams of the main elements appearing in the microscopic image. [Figure 26] Figure 26 shows the measurement results of the thermal transient characteristics of the sample. [Figure 27A] Figure 27A shows the drain current characteristics with respect to drain voltage, with the gate voltage as a parameter, as part of the measurement results of the electrical characteristics of the sample. [Figure 27B] Figure 27B shows the breakdown voltage measurement results among the electrical characteristics measurement results of the sample. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described in detail below with reference to the drawings. The matters described in the embodiments of the present invention can be modified as appropriate within the scope of the present invention.

[0011] [First Embodiment] Figure 1 is a schematic cross-sectional view of a power semiconductor device according to the first embodiment of the present invention, and Figure 2 is a schematic top view of the power semiconductor device according to the first embodiment of the present invention. The cross-sectional view in Figure 1 corresponds to the cross-section along line II in Figure 2. In Figure 1, the horizontal direction of the paper is the y direction, the vertical direction is the z direction, and the direction perpendicular to both of these is the x direction.

[0012] The power semiconductor element 1 according to the first embodiment of the present invention comprises a power semiconductor chip 10, a surrounding portion (also called a holding portion) 20 that surrounds and holds the side surface of the power semiconductor chip 10 in a circumferential manner, and a multilayer wiring portion 30 provided on the first surface side of the power semiconductor chip 10. The power semiconductor chip 10 has a first electrode 11 and a second electrode 12 on the first surface side, and a third electrode 13 on the surface opposite to the first surface ("second surface"). Here, the first surface means either the top or bottom surface of the power semiconductor chip 10, and the second surface means the surface provided on the opposite side of the first surface. Top view refers to the state of the first surface of the power semiconductor chip having the first electrode 11 and the second electrode 12, viewed from the first surface toward the second surface. This definition is the same in other embodiments. Here, "surface" may also be called "main surface".

[0013] The power semiconductor chip 10 is composed of a part of a vertical power semiconductor element. A vertical power semiconductor element is a power semiconductor element that switches a large current ON / OFF between the first electrode 12 and the third electrode 13 by electrical control of the second electrode 12, for example, by applying a voltage. A vertical structure is adopted in order to obtain a sufficiently low on-resistance even when a large current flows in the ON state, and to maintain the applied voltage inside the element. That is, in the ON state, electrons pass through the inversion channel and spread throughout the drift layer to take up the area of ​​the current path, thereby achieving low on-resistance, and in the OFF state, the voltage is maintained by the depletion layer extending from the first surface into the drift layer. Here, the semiconductor element may be either a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The first electrode 11, the second electrode 12, and the third electrode 13 correspond to the source electrode, gate electrode, and drain electrode in the case of a MOSFET, and to the emitter electrode, base electrode, and collector electrode in the case of an IGBT. Here, the power semiconductor element 1, taking a MOSFET as an example, may be a trench type in which the gate insulating layer is provided in a trench groove and a part of the gate electrode is embedded, or a planar type in which the gate insulating layer and the gate electrode are stacked.

[0014] The power semiconductor chip 10 is formed by creating MOSFETs and IGBTs on a wafer made of power semiconductor material such as Si, SiC, and GaN through semiconductor process processing, and then cutting them into chips (also called dies) by dicing. Therefore, before dicing, a termination structure 14 is formed on the outer periphery that will become the chip. Here, the termination structure has, for example, a guard ring, a field plate, a resurface, or a structure combining these, and mitigates electric field concentration on the first surface side.

[0015] As shown in Figure 2, the power semiconductor chip 10 is divided into three areas on the first surface visible from above: a main cell area 16A on which a first electrode 11 (e.g., source electrode or emitter electrode) corresponding to the type of transistor is provided; a termination area 14A between the main cell area 16A and the outer edge 15 of the chip, on which a termination structure 14 is provided; and a second electrode 12A between the main cell area 16A and the termination area 14A, with the second electrode 12 provided between the termination area 14A and the main cell area 16A, with a portion of the main cell area 16A cut out. In Figure 2, the area 12A on which the second electrode 12 is provided is located approximately in the middle of the main cell area 16A in the x-direction, but it is not limited to this, and may be biased towards the corner of the main cell area 16A or in the center of the main cell area 16A.

[0016] As shown in Figures 1 and 2, the surrounding portion 20 is an insulating member that surrounds and holds the power semiconductor chip 10 from the side, and is made of a high heat-resistant resin such as epoxy resin or maleimide resin that can withstand the operation of the power semiconductor at temperatures of 175°C or higher. A first insulating layer 21 is provided on almost the entire surface of the first surface of the surrounding portion 20, excluding the through hole 21a of the power semiconductor chip 10, and the first insulating layer 21 covers the termination structure portion 14 of the power semiconductor chip 10 from above.

[0017] A multilayer wiring section 30 is formed on the first side of the power semiconductor chip 10 and the surrounding section 20, and a fourth electrode 31 and a sixth electrode 33 are formed by this multilayer wiring section 30. On the other hand, a fifth electrode 32 is formed on the second side of the power semiconductor chip 10.

[0018] The fourth electrode 31 is provided on the first surface side of the power semiconductor chip 10 and is capable of conducting electricity with the first electrode 11. As shown in Figure 1, the fourth electrode 31 has a protruding portion 31a that extends outward from the outer edge of the power semiconductor chip 10 parallel to the first surface (in both the x and y directions in the figure). The protruding portion 31a is a part that does not overlap with the power semiconductor chip 10 when viewed from above. The fourth electrode 31 conducts electricity with the first electrode 11 through the portion that overlaps with the power semiconductor chip 10 when viewed from above, and also transfers heat generated in the junction portion within the power semiconductor chip 10 to the protruding portion 31a. Therefore, heat generated within the power semiconductor chip 10 can be efficiently transferred to the outside. Instead of using wires or lead frames as in the conventional method, a layer of metal (including alloys) is used to make the cross-sectional area of ​​the current-carrying portion and the cross-sectional area of ​​the heat-conducting portion larger than that of the first electrode 11, making it possible to transfer the current to the outside of the power semiconductor element 1.

[0019] The fourth electrode 31 is provided on the first side of the power semiconductor chip 10 not only in the main cell region but also partially on the insulating layer 21 on the termination structure 14 by the protruding portion 31a. Since the fourth electrode 31 can be provided straddling the termination structure 14 via the insulating layer 21, the degree of design freedom regarding the shape and dimensions of the fourth electrode 31 in top view is increased.

[0020] The fifth electrode 32 is provided on the second surface side of the power semiconductor chip 10 so as to be electrically connected to the third electrode 13. When viewed from above, the fifth electrode 32 overlaps most or almost completely with the power semiconductor chip 10, and therefore is electrically connected to the third electrode 13, and heat generated in the junction portion within the power semiconductor chip 10 is transferred from the third electrode 13 to the fifth electrode 32. Thus, heat generated within the power semiconductor chip 10 can be efficiently transferred to the outside both above and below by using not only the fourth electrode 31 but also the fifth electrode 32.

[0021] The sixth electrode 33 is provided on the first surface side of the power semiconductor chip 10 and is capable of electrical contact with the second electrode 12. As shown in Figure 1, the sixth electrode 33 has a protruding portion 33a that extends outward from the outer peripheral edge of the power semiconductor chip 10 parallel to the first surface (in both the x and y directions in the figure). The protruding portion 33a is a part that does not overlap with the power semiconductor chip 10 when viewed from above. The sixth electrode 33 is electrically connected to the second electrode 12 by the portion that overlaps with the power semiconductor chip 10 when viewed from above. On the first surface side of the power semiconductor chip 10, the sixth electrode 33 is provided not only in the main cell region but also partially on the insulating layer 21 on the termination structure 14 by the protruding portion 33a. Since the sixth electrode 33 can be provided straddling the termination structure 14 via the insulating layer 21, the degree of design freedom regarding the arrangement, shape, and dimensions of the exposed portion of the sixth electrode 33 is increased. This exposed portion is part of the protruding section 33a.

[0022] In the first embodiment of the present invention, since the fourth electrode 31 is provided on the first insulating layer 21 on the first surface side of the power semiconductor chip 10 and the surrounding portion 20, it can have a larger area than the main cell region 16A of the power semiconductor chip 10. As a result, the heat generated inside the power semiconductor chip 10 due to conductivity between the fourth electrode 31 and the fifth electrode 32 can be efficiently released to the outside through the fourth electrode 31 on the first surface side close to the junction portion of the power semiconductor chip 10.

[0023] In particular, when the size of the power semiconductor chip 10 becomes small, such as a few millimeters square (for example, 3 mm x 3 mm) in plan view, the area available for fixing one end of a wire or lead frame to the first surface of the power semiconductor chip 10 becomes smaller. In contrast, as in the first embodiment of the present invention, even if the size of the power semiconductor chip 10 becomes small, the power semiconductor element 1 is provided with a surrounding portion 20 that surrounds the power semiconductor chip 10 from the side, and the protruding portion 34a of the fourth electrode 34 can be provided on the first insulating layer 21 provided on the surrounding portion 20. Therefore, in the power semiconductor element 1 according to the first embodiment of the present invention, the size limitation of the power semiconductor chip 10 in top view is extremely small.

[0024] Of the fourth electrode 31, when viewed from above, the area ratio of the area outside the power semiconductor chip 10 to the main cell area 16A of the power semiconductor chip 10 is preferably 20% or more, and in particular, if it is 50% or more, the heat dissipation efficiency will be extremely good. The thickness between the fourth electrode 31 and the fifth electrode 32 is preferably at most about 500 μm. This is because the thickness of the power semiconductor chip 10 can be sufficiently increased, resulting in a higher breakdown voltage.

[0025] [Second Embodiment] A power semiconductor element according to a second embodiment of the present invention will now be described. Figure 3 is a schematic cross-sectional view of a power semiconductor element 1 according to a second embodiment of the present invention. In the first embodiment, the power semiconductor element 1 has one power semiconductor chip 10, but in the second embodiment, the power semiconductor element 1 has multiple power semiconductor chips 10, which is the difference.

[0026] The power semiconductor element 1 according to the second embodiment comprises two power semiconductor chips 10 (10A, 10B) arranged at the same height, and each power semiconductor chip 10 is provided with a first electrode 11 and a second electrode 12 on the first surface side, and a third electrode 13 on the second surface side.

[0027] The fourth electrode 31 is provided on the first surface side so as to be able to conduct electricity with the first electrode 11 of the power semiconductor chip 10A and also with the first electrode 11 of the power semiconductor chip 10B. The fourth electrode 31 has a protruding portion 31a that extends outward (at least in the y-direction in the illustrated case) parallel to the first surface from the outer peripheral edge of each of the power semiconductor chips 10 (10A, 10B). The protruding portion 31a is a part that does not overlap with the power semiconductor chip 10 when viewed from above. The fourth electrode 31 conducts electricity with the first electrode 11 through the portion that overlaps with the power semiconductor chip 10 when viewed from above, and also transfers heat generated in the junction portion within the power semiconductor chip 10 (10A, 10B) to the protruding portion 31a. Therefore, heat generated within the power semiconductor chip 10 can be efficiently transferred to the outside. Instead of using wires or lead frames as in the conventional method, a layer of metal (including alloys) allows the cross-sectional area of ​​the current-carrying portion and the cross-sectional area of ​​the portion involved in heat conduction to be larger than that of the first electrode 11, making it possible to pass the current outside the power semiconductor element 1.

[0028] The fourth electrode 31 is provided on the first side of the power semiconductor chip 10 (10A, 10B) not only in the main cell region but also partially on the insulating layer 21 on the termination structure 14 by the protruding portion 31a. Since the fourth electrode 31 can be provided straddling the termination structure 14 via the insulating layer 21, the design freedom regarding the shape and dimensions of the fourth electrode 31 in top view is increased.

[0029] The fourth electrode 31 is preferably provided in common to the power semiconductor chips 10 (10A, 10B). In other words, it may be provided separately for each power semiconductor chip 10A and 10B, but it is preferable that there be a single fourth electrode 31.

[0030] The fifth electrode 32 is provided on the second surface side of the power semiconductor chip 10 (10A, 10B) so as to be electrically connected to the third electrode 13. The fifth electrode 32 may be provided separately for each power semiconductor chip 10A and 10B, but as shown in Figure 3, it is preferable to have a single fifth electrode 32. That is, the fifth electrode 32 has a portion 32d that can be electrically connected to each of the third electrodes 13 of the power semiconductor chip 10 (10A, 10B), and a portion 32e that connects these portions 32d to each other. The electrical connection and heat conduction between the fifth electrode 32 and the third electrode 13 are the same as described in the first embodiment.

[0031] The sixth electrode 33 is provided on the first surface side of the power semiconductor chip 10 (10A, 10B) and is capable of electrical contact with the second electrode 12. The sixth electrode 33 may be provided separately for each power semiconductor chip 10A and 10B, but it is preferable that there be a single sixth electrode 33, as shown in Figure 3. That is, the sixth electrode 33 has a protruding portion 33a that extends outward from the outer peripheral edge of each power semiconductor chip 10 (10A, 10B) parallel to the first surface (at least in the y-direction in the illustrated case) without overlapping with the power semiconductor chip 10 (10A, 10B) when viewed from above, and the two are integrated and connected by this protruding portion 33a. The electrical contact between the sixth electrode 33 and the second electrode 12 is the same as described in the first embodiment. The sixth electrode 33 is provided on the first side of the power semiconductor chip 10 (10A, 10B) not only in the main cell region but also on the insulating layer 21 on the termination structure 14 by the protruding portion 33a. Since the sixth electrode 33 can be provided straddling the termination structure 14 via the insulating layer 21, the degree of design freedom regarding the arrangement, shape, and dimensions of the exposed portion of the sixth electrode 33 is increased. In a top view, the sixth electrode 33 overlaps with a part of the enclosure portion 20 that exists between it and the power semiconductor chip 10 (10A, 10B).

[0032] Figures 4 and 5 schematically show a top view of the power semiconductor element 1 according to the second embodiment, showing the case where the power semiconductor element has two power semiconductor chips 10. As shown in Figure 4, in a top view, the sixth electrodes 33 on each power semiconductor chip 10 (10A, 10B) are adjacent and integrated, and the exposed portion in the top view is rectangular. In this case, the fourth electrode 31, for example, forms an endless loop shape, i.e., an annular shape, along the outer circumference of the power semiconductor element 1 in a top view. Here, the fourth electrode 31 may have an ended shape instead of an endless loop shape in a top view, and the rectangular sixth electrode 33 can be removed to the outside. As shown in Figure 5, in a top view, the fourth electrodes 31 on each power semiconductor chip 10 (10A, 10B) are adjacent and integrated, and the exposed portion in the top view is rectangular. In this case, the sixth electrode 33 is provided, for example, in a top view, parallel to the fourth electrode 31 on the opposite side, along the outer circumference of the power semiconductor element 1, with region 12A in between.

[0033] Figures 6 and 7 schematically show a top view of a power semiconductor element 1 according to a second embodiment, which differs from Figures 4 and 5, and show the case in which the power semiconductor element 1 has four power semiconductor chips 10. As shown in Figure 6, in a top view of the power semiconductor element 1, the sixth electrodes 33 of each power semiconductor chip 10 (10A, 10B, 10C, 10D) are adjacent to each other and form a single unit, and the exposed portion in the top view is rectangular. In this case, the fourth electrode 31, for example, has a terminal shape along the outer circumference of the power semiconductor element 10 in a top view. The reason for the terminal shape is to allow the rectangular sixth electrode 33 to be removed. As shown in Figure 7, in a top view of the power semiconductor element 1, the fourth electrodes 31 of each power semiconductor chip 10 (10A, 10B, 10C, 10D) are adjacent to each other and form a single unit, and the exposed portion in the top view is rectangular. In this case, the sixth electrode 33 has an ended shape, for example, when viewed from above, along the outer circumference of the power semiconductor element 10. The loop shape is used to allow the rectangular fourth electrode 31 to be brought out. Note that even if the sixth electrode 33 has an endless loop shape, a stacked structure can be used.

[0034] In the power semiconductor element 1 according to the second embodiment, multiple power semiconductor chips 10 of the same shape and rating are provided, and by the fourth electrode 31, fifth electrode 32, and sixth electrode 33 of each power semiconductor device 10, they are connected in parallel, making it possible to output, for example, a natural number multiple of the rated current. This eliminates the need to individually design and manufacture power semiconductor chips according to the current and voltage ratings.

[0035] As shown in Figures 4 to 7, the fourth electrode 31 and the sixth electrode 33 may be rectangular (including square), ended, or endless loop (annular) on either the upper or lower surface of the multiple power semiconductor chips 10, and may also have notches or through holes in a portion of each electrode. This is to prevent the metal layers constituting each electrode from peeling off the power semiconductor chip 10 due to the difference in thermal expansion coefficients between each electrode, including the fourth electrode 31 and the sixth electrode 33, and the power semiconductor chip 10, as the power semiconductor element 1 generates heat during operation. In addition to the ended shape, the fourth electrode 31 and the sixth electrode 33 may also be endless by stacking them so that they cross over at different heights.

[0036] The embodiments of the present invention will be described in more detail below.

[0037] [Third Embodiment] Figure 8 is a schematic cross-sectional view of a power semiconductor element according to the third embodiment. Figure 9 is a schematic diagram showing the top view positional relationship of the power semiconductor chip 10, the surrounding portion 20, the fourth electrode 31, and the sixth electrode 33 in the power semiconductor element according to the third embodiment of the present invention. The cross-sectional view in Figure 8 corresponds to the cross-section along the line VIII-VIII in Figure 9.

[0038] The power semiconductor element 1 according to the third embodiment of the present invention comprises a power semiconductor chip 10, a surrounding portion (also called a holding portion) 20 that surrounds and holds the side surface of the power semiconductor chip 10 in a circumferential manner, a fourth electrode 31 and a sixth electrode 33 provided on the first surface side of the power semiconductor chip 10, and a fifth electrode 32 provided on the second surface side of the power semiconductor chip 10. The fourth electrode 31 and the sixth electrode 33 constitute a multilayer wiring portion 30. The power semiconductor chip 10 has a first electrode 11 and a second electrode 12 on the first surface side, and a third electrode 13 on the second surface side.

[0039] Figure 10 is a schematic diagram showing a top view of the power semiconductor chip 10. The power semiconductor chip 10 is composed of a part of a vertical power semiconductor element, similar to the first embodiment. The power semiconductor chip 10 is divided on its first surface into a main cell region 16A, where a source electrode or emitter electrode is provided as a first electrode 11 depending on the type of transistor; a termination region 14A, which is the region between the main cell region 16A and the outer edge 15 of the chip and where a termination structure 14 is provided; and a region 12A, between the main cell region 16A and the termination region 14A, where a second electrode 12 is provided, cutting out a part of the main cell region 16A. In Figure 10, the region 12A where the second electrode 12 is provided is located approximately in the middle of the main cell region 16A in the x-direction, but it is not limited to this, and may be biased towards the corner of the main cell region 16A or in the center of the main cell region 16A.

[0040] The surrounding portion 20 is the same as in the first embodiment. A multilayer wiring portion 30 is formed on the first side of the power semiconductor chip 10 and the surrounding portion 20, and the fourth electrode 31 and the sixth electrode 33 are formed by the multilayer wiring portion 30. On the other hand, a fifth electrode 32 is formed on the second side of the power semiconductor chip 10.

[0041] The fourth electrode 31 is provided on the first side of the power semiconductor chip 10 and is composed of a stack of one or more metal layers. As shown in Figure 8, the fourth electrode 31 is composed of a stack of a first metal layer 34, a second metal layer 35, and a third metal layer 36. A portion of the first metal layer 34 is provided in the through-hole 21a (see Figure 9) of the first insulating layer 21 and is configured to be electrically connected to the first electrode 11, and is provided to cover a portion of the first insulating layer 21. The second metal layer 35 is in contact with the first metal layer 34 on the side opposite to the power semiconductor chip 10. The third metal layer 36 is in contact with the second metal layer 35 on the side opposite to the power semiconductor chip 10. The number of stacked metal layers can be two, three, or four, but fewer is preferable to reduce the number of process steps. Since the first metal layer 34 to the third metal layer 36 are identical in shape when viewed from above, the heat dissipation efficiency is improved, as will be described later.

[0042] As shown in Figure 9, the first metal layer 34 of the fourth electrode 31 is provided in the through-hole 21a of the first insulating layer 21, and is provided not only above the through-hole 21a, but also on the termination structure 14 of the power semiconductor chip 10 and on a part of the surrounding portion 20. That is, as shown in Figure 8, the first electrode 31 is composed of an embedded portion 34a provided in the through-hole 21a of the first insulating layer 21 and configured so that its lower surface can conduct electricity with the first electrode 11, and an extended portion 34b extending in a planar manner from the upper end of the embedded portion 34a. The extended portion 34b is composed of a portion 34c that overlaps with the main cell region 16A in a top view, a portion 34d that overlaps with the region from the termination region 14A to the outer edge 15 of the chip in a top view, and a portion 34e that protrudes from the outer edge 15 of the power semiconductor chip 10 and overlaps with the surrounding portion 20 (in particular, referred to as the protruding portion). Here, the buried portion 34a is made of the first metal layer 34, and the extended portion 34b is made of the first metal layer 34, the second metal layer 35, and the third metal layer 36.

[0043] Here, the first metal layer 34 is composed of a metallic material with good thermal conductivity, such as a Cu layer, an Al layer, or an alloy layer containing Cu or Al. The thickness L2 of the protruding portion 34b of the first metal layer 34 is determined by its lower limit based on electrical conductivity and its upper limit so as not to cause stress due to the difference in thermal expansion coefficients between the power semiconductor chip 10 and the first metal layer 34. It is preferable that L2 has a thickness of 10 μm or more and 150 μm or less. The depth L1 of the through-hole 21a (embedded portion 34a) of the insulating layer 21 is determined in relation to the insulating layer 21, and is preferably, for example, 5 μm or more and 20 μm or less.

[0044] The second metal layer 35 is made of a metallic material such as a Ni layer, and the third metal layer 36 is made of a metallic material such as Au. Here, the second metal layer 35 is approximately 6 μm thick, and the third metal layer 36 is approximately 50 μm thick. The second metal layer 35 is provided to prevent the bonding layer that contacts the upper surface of the third metal layer 36 on the opposite side from the second metal layer 35 from becoming brittle due to diffusion of components of the first metal layer 34. The third metal layer 36 is provided to prevent oxidation of the second metal layer 35.

[0045] As shown in Figure 8, the fifth electrode 32 is provided on the second side of the power semiconductor chip 10 and is composed of one or more stacked metal layers. The fifth electrode 32 has the following stacked structure: The first metal layer 32a is provided on the third electrode 13 of the power semiconductor chip 10 and is flush with the second surface of the enclosure 20. The second metal layer 32b is provided on the side opposite to the power semiconductor chip 10 of the first metal layer 32a, and the third metal layer 32c is provided on the side opposite to the power semiconductor chip 10 of the second metal layer 32b. The second metal layer 32b and the third metal layer 32c are provided in this order from top to bottom (towards the -z direction) so as to protrude from the enclosure 20 in the back direction (-z). The number of metal layers constituting the second electrode 32 may be 3, 2, 4, or any other number of layers as shown in the figure. As shown in the figure, the first metal layer 32a, the second metal layer 32b, and the third metal layer 32c are determined to the size of the power semiconductor chip 10, and all of the metal layers have the same dimensions except for the thickness direction.

[0046] Here, the first metal layer 32a is composed of a metallic material with good thermal conductivity, such as a Cu layer, an Al layer, or an alloy layer containing Cu or Al, and it is preferable that the first metal layer 32a has a thickness of 5 μm or more, and particularly 10 μm or more. This is because sufficient heat is dissipated within this thickness range. In this case, the thickness of the first metal layer 32a is set so that stress does not concentrate due to the difference in thermal expansion coefficients between the power semiconductor chip 10 and the first metal layer 32a.

[0047] The second metal layer 32b is composed of a metallic material such as a Ni layer, and the third metal layer 32c is composed of a metallic material such as Au. Here, the second metal layer 32b is approximately 6 μm thick, and the third metal layer 32c is approximately 50 μm thick. The second metal layer 32b is provided to prevent the bonding layer that contacts the third metal layer 32c on the opposite side of the second metal layer 32b from becoming brittle due to diffusion of components from the first metal layer 32a. The third metal layer 32c is provided to prevent oxidation of the second metal layer 32b.

[0048] The sixth electrode 33 is formed as part of the multilayer wiring section 30 on the first surface side of the power semiconductor chip 10 and the surrounding section 20, in a region that does not overlap with the fourth electrode 31 when viewed from above. The sixth electrode 33 is provided on the first surface side of the power semiconductor chip 10 and is composed of a stack of one or more metal layers. As shown in Figure 8, the sixth electrode 33 is composed of a stack of a first metal layer 37, a second metal layer 38, and a third metal layer 39. A portion of the first metal layer 37 is provided in the through-hole 21b (see Figure 9) of the first insulating layer 21 and is configured to be electrically connected to the second electrode 12, and is provided to cover a portion of the first insulating layer 21. The second metal layer 38 is in contact with the first metal layer 37 on the side opposite to the power semiconductor chip 10. The third metal layer 39 is in contact with the second metal layer 38 on the side opposite to the power semiconductor chip 10. The number of metal layers can be two, three, or four, but fewer layers are preferable to reduce the number of process steps.

[0049] As shown in Figure 9, the first metal layer 37 of the sixth electrode 33 is provided in the through-hole 21b of the first insulating layer 21, and is provided not only above the through-hole 21b, but also on the termination structure 14 of the power semiconductor chip 10 and on a part of the surrounding portion 20. In other words, as shown in Figure 8, the sixth electrode 33 is composed of an embedded portion 37a embedded in the through-hole 21b of the first insulating layer 21 so that its lower surface can conduct electricity with the second electrode 12, an extended portion 37b extending planarly from the upper end of the embedded portion 37a, and a connecting portion 37f connected to the extended portion 37b, separated from the fourth electrode 31 and stacked in the opposite direction to the embedded portion 37a. The extended portion 37b is composed of a portion 37c that overlaps with the region 12A where the gate electrode is provided in a top view, a portion 37d that overlaps with the region from the termination region 14A to the outer edge 15 of the chip in a top view, and a portion 37e that protrudes from the outer edge 15 of the power semiconductor chip 10 and overlaps with the surrounding portion 20 (in particular, referred to as the protruding portion). Here, the buried portion 37a and the extended portion 37b are formed of the first metal layer 37, and the connecting portion 37f is formed of the second metal layer 35 and the third metal layer 36.

[0050] Here, it is preferable that the first metal layer 37, the second metal layer 38, and the third metal layer 39 constituting the sixth electrode 33 are made of the same thickness and material as the first metal layer 34, the second metal layer 35, and the third metal layer 36 constituting the fourth electrode 31.

[0051] On the first side of the power semiconductor chip 10, a first insulating layer 21, a second insulating layer 22, and a third insulating layer 23 are provided in this order. The first insulating layer 21 has dimensions from the upper surface of the enclosure portion 20 to the lower surface of the extended portion 34b of the first metal layer 34 on the fourth electrode 31, that is, from the upper surface of the enclosure portion 20 to the lower surface of the extended portion 37b of the first metal layer 37 on the sixth electrode 33. The second insulating layer 22 has the same thickness as the extended portion 34b of the first metal layer 34 on the fourth electrode 31 and the extended portion 37b of the first metal layer 37 on the sixth electrode 33. The third insulating layer 23 has the same thickness as the sum of the thicknesses of the second metal layer 35 and the third metal layer 36 on the fourth electrode 31, that is, the sum of the thicknesses of the second metal layer 38 and the third metal layer 39 on the sixth electrode 33. Therefore, the third metal layer 36 as the outermost layer on the fourth electrode 31 and the third metal layer 39 as the outermost layer on the sixth electrode 33 are flush with the surface due to the lamination of the first insulating layer 21, the second insulating layer 22, and the third insulating layer 23. This makes it possible to make the fourth electrode 31 and the sixth electrode 33, which are provided on the first surface side of the power semiconductor chip 10, non-contact.

[0052] A fourth insulating layer 24 is provided on the second surface of the enclosure portion 20 so as to surround the second metal layer 32b and the third metal layer 32c.

[0053] In the third embodiment of the present invention, the fourth electrode 31 is provided on the first insulating layer 21 on the first surface side of the power semiconductor chip 10 and the surrounding portion 20, so that it can have a larger area than the main cell region 16A of the power semiconductor chip 10. As a result, the heat generated inside the power semiconductor chip 10 due to conductivity between the fourth electrode 31 and the fifth electrode 32 can be efficiently released to the outside through the fourth electrode 31 on the first surface side close to the junction portion of the power semiconductor chip 10.

[0054] In conventional technology, when connecting an external terminal to a power semiconductor chip with a wire, the area where one end of the wire is fixed to the semiconductor chip cannot utilize most of the main cell area 16A, but only a portion of it (area A1 in Figure 10), resulting in a high current density in the wire. Also, when connecting an external terminal to a power semiconductor chip with a lead frame, it is necessary to separate it upwards to avoid contact with the termination structure of the power semiconductor chip. This narrows the area where one end of the lead frame on the power semiconductor chip side can be fixed, making it impossible to provide a heat conduction material above that part of the lead frame. As a result, the current density depends on the size of the cross-section of the lead frame that crosses the current direction, leading to a high current density in the lead frame.

[0055] In contrast to these prior arts, in the third embodiment of the present invention, the first electrode 31 has an overhang 34e extending outward from the power semiconductor chip 10, thereby increasing the top-view area of ​​the overhang 34b of the first electrode 31. As described later, a metal plate (reference numeral 41 in Figure 13, 135b in Figure 20A) is provided above the overhang 34b to dissipate heat to the outside via the second metal layer 35 and the third metal layer 36. Furthermore, the area of ​​the cross-section intersecting the thickness direction of the first electrode 16 can be increased, thus reducing the current density of the first electrode 31.

[0056] Furthermore, in the third embodiment of the present invention, the sixth electrode 33 has an overhang 37e on the outside of the power semiconductor chip 10, and a connection portion 37f is provided at one end of the overhang 37e above the surrounding portion 20. Therefore, as shown in Figure 10, it is not necessary to connect one end of the wire within the region 12A where the gate electrode of the power semiconductor chip 10 is provided. In other words, in the third embodiment of the present invention, as shown in Figure 9, the overhang 37e can be made wide on the outside of the power semiconductor chip 10 so as to overlap the surrounding portion 20 in a top view, and in a direction that intersects with the direction in which the extension portion 37b extends from the embedded portion 34a in the through hole 21b, thereby increasing the degree of design freedom.

[0057] [Fourth Embodiment] Figure 11 is a schematic cross-sectional view of a power semiconductor element 1 according to a fourth embodiment of the present invention. In the fourth embodiment, the fourth electrode 31, fifth electrode 32, and sixth electrode 33 of the second embodiment are made more concrete. Parts that are the same as or corresponding to those in Figure 3 are denoted by the same reference numerals and their descriptions are omitted.

[0058] The fourth electrode 31 has a multilayer structure, and is composed of a stack of a first metal layer 34, a second metal layer 35, and a third metal layer 36, as shown in Figure 11, for example. The configurations of the first metal layer 34, the second metal layer 35, and the third metal layer 36 are the same as in the third embodiment.

[0059] The fifth electrode 32 has a multilayer structure, and is composed of a stack of a first metal layer 32a, a second metal layer 32b, and a third metal layer 32c, as shown in Figure 11, for example. The configurations of the first metal layer 32a, the second metal layer 32b, and the third metal layer 32c are the same as in the third embodiment.

[0060] The sixth electrode 33 has a multilayer structure, and is composed of a stack of a first metal layer 37, a second metal layer 38, and a third metal layer 39, as shown in Figure 11, for example. The configurations of the first metal layer 37, the second metal layer 38, and the third metal layer 39 are the same as in the third embodiment.

[0061] [Fifth Embodiment] Figure 12 is a schematic cross-sectional view of a power semiconductor element 1 according to a fifth embodiment of the present invention. The same reference numerals are used for the same or corresponding components and parts as those shown in Figure 8 of the power semiconductor element 1.

[0062] The power semiconductor element 1 according to the fifth embodiment of the present invention differs from the fourth embodiment in the following respects. In the power semiconductor element 1 according to the fifth embodiment, the upper surface of the first insulating layer 25 does not reach the upper surface of the power semiconductor chip 10 and is thinner than the first insulating layer 21 in Figure 8. As a result, the fourth insulating layer 26 is provided between the first insulating layer 25 and the second insulating layer 22, and overlaps with the peripheral edge of the power semiconductor chip 10 in a top view. In this overlapping portion 34a, the first metal layer 34 of the first electrode 31 is thinner compared to other portions. Also, the first metal layer 37 of the third electrode 33 is thinner in this overlapping portion 37a compared to other portions.

[0063] With this configuration, the power semiconductor element 1 according to the fifth embodiment of the present invention is thinner than the power semiconductor element 1 according to the fourth embodiment.

[0064] [Sixth Embodiment] A sixth embodiment of the present invention relates to a power semiconductor element 1 according to the first to fifth embodiments, and further comprises a plurality of metal plates 40 having external terminals. Furthermore, it optionally comprises a cooling unit 55, such as a cooling unit.

[0065] Figure 13 is a cross-sectional view of a power semiconductor module 2 according to the sixth embodiment of the present invention. Figure 13 shows a case in which both a plurality of metal plates 40 and a cooling section 55 are provided for the power semiconductor element 1 of the third embodiment. The same applies to the power semiconductor elements according to the other embodiments described above.

[0066] In the power semiconductor element 1 according to the first to fifth embodiments, a metal plate 40 is in contact with the power semiconductor chip 10 and each electrode provided above and below it, from above or below, corresponding to each electrode. Since the power semiconductor element 1 has at least three electrodes, three metal plates 41, 42, and 43 are used. The first metal plate 41 is provided on the outermost metal layer of the fourth electrode 31 (the third metal layer 36 in Figure 13) from above, with solder or bonding material 47 interposed as necessary. The second metal plate 42 is provided on the outermost metal layer of the fifth electrode 32 (the third metal layer 32c in Figure 13) from below, with solder or bonding material 48 interposed as necessary. The third metal plate 43 is provided on the outermost metal layer of the sixth electrode 33 (the third metal layer 39 in Figure 13) from above, with solder or bonding material 49 interposed as necessary. The metal plates 40 (41, 42, 43) are made of metals with good thermal conductivity, such as copper plates. Each of these metal plates 40 has the shape of an external terminal and is electrically connected to the outside.

[0067] The first metal plate 41 and the third metal plate 43 are held on the lower surface of the ceramic plate 53, and the second metal plate 42 is held on the upper surface of the ceramic plate 54. A cooling section 56 is provided on the upper surface of the ceramic plate 53 with grease interposed therebetween, and a cooling section 57 is provided on the lower surface of the ceramic plate 54 with grease interposed therebetween. Cooling water is configured to flow through the upper and lower cooling sections 55 (56, 57) via water channels (not shown). Here, the ceramic plates 53 and 54 are made of materials such as silicon nitride (SiN) and aluminum nitride (AlN).

[0068] [Seventh Embodiment] Figure 14 is a schematic cross-sectional view of a power semiconductor module 2 according to the seventh embodiment of the present invention. The same reference numerals are used for members and parts that are the same as or correspond to the power semiconductor element 1 shown in Figure 8. The power semiconductor module 2 according to the seventh embodiment of the present invention is a module comprising a power semiconductor chip 10 and a drive chip 60 for driving the power semiconductor chip 10 by applying a voltage to the second electrode 12 of the power semiconductor chip 10.

[0069] The driver chip 60, like the power semiconductor chip 10, has a first electrode 61 and a second electrode 62 on its first side and a third electrode 63 on its second side. It is a vertical semiconductor element that switches current ON / OFF between the first electrode 61 and the third electrode 63 by applying a voltage to the second electrode 62. The first side of the driver chip 60 is flush with the first side of the power semiconductor chip 10, and the manufacturing process on the first side of the power semiconductor module 2 is configured to be carried out simultaneously on the power semiconductor chip 10 and the driver chip 60. On the lower surface (-z direction surface) of the third electrode 63 of the driver chip 60, a second electrode 72 is provided, which consists of a stacked structure of a first metal layer 72a, a second metal layer 72b, and a third metal layer 72c, similar to the power semiconductor chip 10. Here, the laminated structure of the first metal layer 72a, the second metal layer 72b, and the third metal layer 72c is made of the same material and thickness as the first metal layer 32a, the second metal layer 32b, and the third metal layer 32c that constitute the second electrode 32 of the power semiconductor chip 10.

[0070] A connecting electrode 71 is provided on the first surface side of the power semiconductor chip 10, the drive chip 60, and the surrounding portion 20 in order to connect the second electrode 12 of the power semiconductor chip 10 and the first electrode 61 of the drive chip 60. The connecting electrode 71 is composed of a first metal layer 74 consisting of an embedded portion 74a, an embedded portion 74b, and an extended portion 74c, a second metal layer 75 provided so as to be in contact with a part of the extended portion 74c of the first metal layer 74, and a third metal layer 76 provided on the second metal layer 75. The embedded portions 74a and 74b are provided in the through holes of the first insulating layer 21 provided on the second electrode 12 of the power semiconductor chip 10 and the first electrode 61 of the drive chip 60. Therefore, since the termination structure portion 14 of the power semiconductor chip 10 and the termination structure portion 64 of the driver chip 60 are covered with the first insulating layer 21, the degree of freedom of wiring can be increased, similar to the protruding portion 37e in the third embodiment. The extension portion 74c is provided at the upper end of the buried portion 74a and the buried portion 74b, extending at least in the direction in which the power semiconductor chip 10 and the driver chip 60 are arranged. The second metal layer 75 and the third metal layer 76 are provided at approximately the midpoint between the buried portion 74a and the buried portion 74b, and do not overlap with the buried portions 74a and 74b in a top view.

[0071] A fifth electrode 73 is provided on the first surface side of the drive chip 60 and the surrounding portion 20, connected to the second electrode 62. As shown in Figure 14, the fifth electrode 73 is composed of a laminate of a first metal layer 77, a second metal layer 78, and a third metal layer 79. A portion of the first metal layer 77 is provided in a through-hole of the first insulating layer 21 and is configured to be electrically connected to the second electrode 62, and is provided to cover a portion of the first insulating layer 21. The second metal layer 78 is in contact with the first metal layer 77 on the side opposite to the drive chip 60. The third metal layer 79 is in contact with the second metal layer 78 on the side opposite to the drive chip 60.

[0072] The first metal layer 74 on the connecting electrode 71 and the first metal layer 77 on the fifth electrode 73 on the driving chip 60 have the same material and thickness as the first metal layer 34 on the fourth electrode 31 on the power semiconductor chip 10. The second metal layer 75 on the connecting electrode 71 and the second metal layer 78 on the fifth electrode 73 on the driving chip 60 have the same material and thickness as the second metal layer 35 on the fourth electrode 31 on the power semiconductor chip 10. The third metal layer 76 on the connecting electrode 71 and the third metal layer 79 on the fifth electrode 73 on the driving chip 60 have the same material and thickness as the third metal layer 36 on the fourth electrode 31 on the power semiconductor chip 10.

[0073] In the seventh embodiment, the metal plate 40 is composed of a first metal plate 41 connected to the fourth electrode 31 on the first side of the power semiconductor chip 10 via solder or bonding material 47 as necessary, a second metal plate 42 connected to the second electrode 32 on the second side of the power semiconductor chip 1 via solder or bonding material 48 as necessary, a third metal plate 44 connected to the connecting electrode 71 via solder or bonding material 50 as necessary, a fifth metal plate 45 connected to the fifth electrode 73 on the first side of the drive chip 60 via solder or bonding material 51 as necessary, and a fourth metal plate 46 connected to the second electrode 72 on the second side of the drive chip 60 via solder or bonding material 52.

[0074] As shown in Figure 14, the power semiconductor module 2 according to the seventh embodiment can be efficiently modularized by making the thickness of the power semiconductor chip 10 and the driver chip 60 substantially the same, and by making the upper and lower wiring structures of the same thickness and material. Since the power semiconductor module 2 adopts the structure of the power semiconductor element 1 according to the first, third, and other embodiments, it provides similar effects and advantages.

[0075] [Eighth Embodiment] Figure 15 is a schematic cross-sectional view of a power semiconductor module 2 according to the eighth embodiment of the present invention. The same reference numerals are used for the same or corresponding components and parts as those shown in Figure 12 (power semiconductor element 1) and Figure 14 (power semiconductor module 2). The power semiconductor module 2 according to the fifteenth embodiment of the present invention is a module comprising a power semiconductor chip 10 and a drive chip 60 for energizing and driving the second electrode 12 of the power semiconductor chip 10.

[0076] In the eighth embodiment, instead of the first insulating layer 21 as in the seventh embodiment, a first insulating layer 25 and a fourth insulating layer 26 are provided, and the shapes of the first metal layer 34 on the fourth electrode of the power semiconductor chip 10, the first metal layer 74 on the connecting electrode 71, and the first metal layer 77 on the fifth electrode 73 of the driving chip 60 are different.

[0077] The power semiconductor module 2 according to the eighth embodiment employs the same configuration as the power semiconductor element 1 according to the fifth embodiment, and also employs the same configuration as the power semiconductor module 2 according to the seventh embodiment. Therefore, it provides the same effects and advantages as these.

[0078] [Ninth Embodiment] Next, as a ninth embodiment of the present invention, a method for manufacturing a power semiconductor element 1 and a method for manufacturing a power semiconductor module 2 will be described. In the following description, the method for manufacturing the power semiconductor element 1 shown in Figures 2 and 11 will be described. This method can also be applied to cases where the power semiconductor element 1 has a single power semiconductor chip 10, with necessary modifications.

[0079] Figures 16A to 16G are schematic cross-sectional views illustrating, in order, the manufacturing method of the power semiconductor module 2 according to the ninth embodiment of the present invention. Note that Figures 16A to 16G are not diagrams for each process, but rather some are shown together.

[0080] First, multiple power semiconductor chips 10 are prepared. On the second side of each power semiconductor chip 10, a metal layer 101 made of metal is formed, which is thicker than the first metal layer 32a of the fifth electrode 32.

[0081] Next, as shown in Figure 16A, an adhesive sheet 103 is placed on the carrier substrate 102, and power semiconductor chips 10 are arranged at predetermined intervals. At this time, the second surface of the power semiconductor chip 10 faces upward, and the first electrode and second electrode on the first surface face the adhesive sheet 103. In addition, among the multiple power semiconductor chips 10, pairs or sets that will become a single power semiconductor element 1 during manufacturing are arranged such that, for example, the first electrodes are adjacent to each other, and the second electrodes are adjacent to each other.

[0082] Next, the device is molded with resin in the state shown in Figure 16A. The thickness of the molded resin layer 104 is set to the thickness required to mold each metal layer 101 on the power semiconductor chip 10. Then, the carrier substrate 102 and adhesive sheet 103 are removed.

[0083] Next, as shown in Figure 16B, an insulating layer 105, which will become the first insulating layer 21, is provided to form through holes (contact holes) 105a for the first electrode 11 and the second electrode 12 of the power semiconductor chip 10.

[0084] Next, as shown in Figure 16C, the first metal layer 34 of the fourth electrode 31 and the first metal layer 37 of the sixth electrode 33 are formed. At this time, the corresponding metal layers may be formed, patterned, and the unnecessary metal layers may be removed.

[0085] Next, the molded resin layer 104 and the metal layer 101 are ground to a predetermined thickness and polished using CPM or similar methods. This forms a portion 32d of the first metal layer 32a on the fifth electrode 32. Around the same time, an insulating layer 106, which will become the second insulating layer 22, and an insulating layer 107, which will become the third insulating layer 23, are provided, and through holes (contact holes) are formed so that the first metal layer 34 of the fourth electrode 31 and the first metal layer 37 of the sixth electrode 33 are exposed. This state is shown in Figure 16D.

[0086] Next, as shown in Figure 16E, the second metal layer 35 of the fourth electrode 31 and the second metal layer 38 of the sixth electrode 33 are formed in the through-holes of the insulating layer 107, and then the third metal layer 36 of the fourth electrode 31 and the third electrode 39 of the sixth electrode 33 are formed on top of them.

[0087] Around the same time, an insulating layer 24 is formed on the back side, and a through hole is provided so that a portion 32d of the first metal layer 32a of the fifth electrode 32 is exposed. Then, a portion 32e of the remaining first metal layer 32a is formed on top of the portion 32d of the first metal layer 32a of the fifth electrode 32. This connects the power semiconductor chips 10 together at the first metal layer 32a of the fifth electrode 32. Then, a second metal layer 32b of the fifth electrode 32 is formed, and on top of that, a third metal layer 32c of the fifth electrode 32 is formed. Note that if it is desired to connect the power semiconductor chips 10 together at the second metal layer 32b of the fifth electrode 32, the formation of the portion 32e of the remaining first metal layer 32a should be omitted.

[0088] Next, as shown in Figure 16G, each power semiconductor element 1 is cut. This completes the production of the power semiconductor elements 1. The metal plates 40 mounted on ceramic plates 53 and 54 are sandwiched between the power semiconductor elements 1 produced in this way, an outer frame to prevent leakage is attached, and grease is applied to create a cooling section 55 (see Figure 13).

[0089] As described above, in the manufacturing method of the power semiconductor element 1 according to the ninth embodiment of the present invention, when forming the eighth electrode 32, a metal layer 101 such as Cu is provided on the third electrode 13 of the power semiconductor chip 10 to a thickness of, for example, 10 μm or more by plating, vapor deposition, or sputtering, the entire chip is molded with resin, and the molded portion is removed by processes such as grinding and polishing, the metal layer 101 is thinned to, for example, 5 μm, and other metal layers can be provided thereon.

[0090] [Tenth Embodiment] Next, a method for manufacturing a power semiconductor module 2 will be described as a tenth embodiment of the present invention. A method for manufacturing a power semiconductor module 2 according to the fifth embodiment will be described.

[0091] Figures 17A to 17F are schematic cross-sectional views illustrating, in order, the manufacturing method of the power semiconductor module 2 according to the tenth embodiment of the present invention. Note that Figures 17A to 17F are not diagrams for each process, but rather some are shown together.

[0092] First, multiple power semiconductor chips 10 and driver chips 60 are prepared. On the second side of the power semiconductor chip 10 and driver chip 60, a metal layer 101 made of metal is formed, which is thicker than the first metal layer 32a of the fifth electrode 32 and the second metal layer 72a of the fifth electrode 72, respectively.

[0093] Next, as shown in Figure 17A, an adhesive sheet 103 is placed on the carrier substrate 102, and the power semiconductor chip 10 and the driver chip 60 are arranged at predetermined intervals. At this time, the second surfaces of the power semiconductor chip 10 and the driver chip 60 are positioned facing upwards, with the first electrode and second electrode on the first surface facing the adhesive sheet 103.

[0094] Next, the components are molded with resin in the state shown in Figure 17A. The thickness of the molded resin layer 104 is such that the metal layers 101 on the power semiconductor chip 10 and the driver chip 60 are molded. Then, the carrier substrate 102 and the adhesive sheet 103 are removed.

[0095] Next, as shown in Figure 17B, an insulating layer 105, which will become the first insulating layer 21, is provided to form through holes (contact holes) 105a to the first electrode 11 and second electrode 12 of the power semiconductor chip 10 and the first electrode 61 and second electrode 62 of the drive chip 60.

[0096] Next, as shown in Figure 17C, the first metal layer 34 of the fourth electrode 31, the first metal layer 74 of the connecting electrode 71, and the first metal layer 77 of the sixth electrode 73 are formed. At this time, the metal layers may be formed, patterned, and any unnecessary metal layers may be removed.

[0097] Next, the molded resin layer 104 and the metal layer 101 are ground to a predetermined thickness and polished with CPM or the like. Around the same time, an insulating layer 106 which will become the second insulating layer 22 and an insulating layer 107 which will become the third insulating layer 23 are provided, and through holes (contact holes) are formed so that the first metal layer 34 of the fourth electrode 31, the first metal layer 74 of the connecting electrode 71, and the first metal layer 77 of the sixth electrode 73 are exposed. This state is shown in Figure 17D.

[0098] Next, as shown in Figure 17E, the second metal layer 35 of the fourth electrode 31, the second metal layer 75 of the connecting electrode 71, and the second metal layer 78 of the sixth electrode 73 are formed in the through-holes of the insulating layer 107 which will become the third insulating layer 23. Then, the third metal layer 36 of the fourth electrode 31, the third electrode 76 of the connecting electrode 71, and the third metal layer 79 of the sixth electrode 73 are formed on top of that.

[0099] Around the same time, an insulating layer 108, which will become the insulating layer 24, is formed on the back side, and through holes are provided so that the first metal layer 32a of the fifth electrode 32 and the first metal layer 72a of the fifth electrode 72 are exposed. Then, the second metal layer 32b of the fifth electrode 32 and the second metal layer 72b of the fifth electrode 72 are formed, and on top of that, the third metal layer 32c of the fifth electrode 32 and the third metal layer 72c of the fifth electrode 72 are formed.

[0100] Next, as shown in Figure 17F, each power semiconductor module 2 is cut. This completes the production of the power semiconductor modules 2. The metal plates 40 mounted on the ceramic plates 53 and 54 are sandwiched between the power semiconductor modules 2 produced in this manner from above and below, an outer frame to prevent leakage is attached, and grease is applied to create a cooling section 55 (see Figure 14).

[0101] Thus, in the manufacturing method of the power semiconductor module 2 according to the tenth embodiment of the present invention, when forming the fifth electrode 32 and the fifth electrode 72, a metal layer 101 such as Cu is provided on the second electrodes 13 and 63 of the power semiconductor chip 10 and the driving chip 60 to a thickness of, for example, 10 μm or more using plating, vapor deposition, and sputtering, the entire chip is molded with resin, and the molded portion is removed by processes such as grinding and polishing, the metal layer 101 is thinned to, for example, 5 μm, and other metal layers can be provided on top of it.

[0102] The manufacturing methods for the power semiconductor element 1 and power semiconductor module 2 according to the ninth and tenth embodiments of the present invention have the following configuration. First, one or more power semiconductor chips 10 and drive chips 60, each having a metal layer 101 made of a Cu layer, an Al layer, or an alloy layer containing Cu or Al formed on the back surface of a third electrode 13, 63, are arranged on the same surface, for example, on an adhesive sheet 103 (Figures 16A and 17A). Next, the outer peripheral surface of the power semiconductor chip 10, including the metal layer 101, is surrounded by a resin layer (e.g., a molded resin layer 104), and in doing so, the resin layer (e.g., a molded resin layer 104) is provided so that the metal layer 101 is not exposed. Then, the metal layer 101 and the resin layer (e.g., mold resin layer 104) are ground and polished to partially remove at least the metal layer 101. This allows the surrounding portion 20 to surround the power semiconductor chip 10, and the first metal layer 32a of the fifth electrode 32 (and the first metal layer 72a of the fifth electrode 72) to be provided on the second surface side of the power semiconductor chip 10.

[0103] Furthermore, an insulating layer 105 is formed on the first surface side of one or more power semiconductor chips 10, and through holes 105a are provided at predetermined locations, and the first metal layer 34 of the fourth electrode 31 is formed in the through holes 105a. Also, an insulating layer 106 is formed on the first surface side, and through holes 106a are provided at predetermined locations, and the second metal layer 35 of the fourth electrode 31 is formed in the through holes 106a. Similarly, the third metal layer 36 of the fourth electrode 31 is formed. By repeating this process, a redistribution layer is formed on the first surface side of the power semiconductor chip 10 by multiple metal layers, and the fourth electrode 31 can be formed in an area wider than the first electrode 11 (main cell area 16A in Figure 10) of the power semiconductor chip 10. The same applies to the connecting electrode 71 and the sixth electrode 73, in that a redistribution layer is formed on the first surface side of the power semiconductor chip 10 by multiple metal layers.

[0104] Here, an example of a power semiconductor chip 10 will be described. Figure 18 is a cross-sectional view showing an example of a power semiconductor chip 10. The left side of Figure 18 is a cross-sectional view of a part of the main cell region 16A, and the right side of Figure 18 is a cross-sectional view of the termination region 14A of the power semiconductor chip 10. The power semiconductor chip 10 has, for example, the following planar MOS structure. The drain region 110 is made of a power semiconductor substrate, and a drain electrode 111 is formed on the drain region 110 as a back electrode (also called a "bottom electrode"), and a drift region 112 is provided on the drain region 111. This drain region 112 is made up of one column 112a and the other column 112b (for example, an N column and a P column). The N column is an N-type drift region, and the P column is a P-type drift region. A body region 113 is formed on the surface region of the drift region 112, and a source region 114 and a body contact region 115 are formed within the body region 113. A gate electrode 117 is formed on the semiconductor surface of the source region 114, with a gate insulating layer 116 interposed between them. An interlayer insulating layer 118 is formed on the gate electrode 117, and a source electrode 119 is formed on the interlayer insulating layer 118. Although a planar type is shown in the figure, a trench type may also be used. Furthermore, an IGBT may be used instead of a MOS.

[0105] As shown on the right side of Figure 18, the structure of the terminal region 14A is such that a GR (guard ring) layer 121 is formed on the surface area of ​​the drift region 112, and a guard ring metal layer 122 is formed thereon. The structure of the terminal region 14A may also be a resurf structure, a field plate structure, or a combination thereof.

[0106] In a single power semiconductor module, a pair of power semiconductor chips 10 may be connected to each other to form an upper arm and a lower arm, respectively. Furthermore, the number of pairs may be one, two, or three.

[0107] [Twelfth Embodiment] A power semiconductor module according to the twelfth embodiment of the present invention comprises one or more power semiconductor elements 1 as described above, wherein a metal layer (for example, a third metal layer 31) exposed on the outer side in the thickness direction of the power semiconductor chip 1 as part of the fourth electrode 31 is provided to be electrically connected to an external terminal.

[0108] Figure 19A is a perspective view of the power module 3 according to the 11th embodiment of the present invention, and Figure 19B is a partially exploded view of the power module 3 according to the 11th embodiment of the present invention. A power semiconductor module 3 according to the 11th embodiment of the present invention includes a first ceramic plate 131, a second ceramic plate 132, a metal plate 133 provided on the non-facing side of the first ceramic plate 131, a metal plate 134 provided on the non-facing side of the second ceramic plate 132, a plurality of metal plates 135a, 135b, 135c provided on the facing side of the first ceramic plate 131, and a plurality of metal plates 136a, 136b provided on the facing side of the second ceramic plate 132, with one or more power semiconductor elements 1 sandwiched between them, and the corresponding fourth electrode 31, fifth electrode 32, and sixth electrode 33 of the power semiconductor element 1 being electrically connected via solder or a conductive bonding material by the metal plates 135a, 135b, 135c and the metal plates 136a, 136b.

[0109] In the illustrated configuration, four power semiconductor elements 1 are arranged. An insulating frame material 137 is sandwiched between the opposing surfaces of the first ceramic plate 131 and the second ceramic plate 132. The frame material 137 has four openings 137a, and each opening 137a is provided with a power semiconductor element 1. As shown in the illustration, in pairs of adjacent openings 137a, the fourth electrode 31 and the sixth electrode 33 of the power semiconductor element 1 are positioned facing the first ceramic plate 131, and in the remaining pair of openings 137a, the fifth electrode 32 of the power semiconductor element 1 is positioned facing the first ceramic plate 131.

[0110] Figure 20A is a plan view of the first ceramic plate 131 and the metal plate provided thereon, and Figure 20B is a bottom view of the first ceramic plate 131 and the metal plate provided thereon. As shown in Figure 20B, a metal plate 133 is provided on the non-facing side of the first ceramic plate 131, except for the peripheral edge, and a plurality of metal plates 135a, 135b, and 135c are provided on the facing side of the first ceramic plate 131. Patterns are formed on the insulating layers 138a, 138b, and 138c of the metal plates 135a, 135b, and 135c so that they can be electrically connected to the fourth electrode 34, fifth electrode 35, and sixth electrode 36 of the power semiconductor element 1, respectively. As shown in Figure 20A, the insulating layer 138a is open so that the sixth electrode 33 of the power semiconductor element 1 can connect to the metal plate 135a. An insulating layer 138b is opened so that the fourth electrode 31 of the power semiconductor element 1 connects to the metal plate 135b. An insulating layer 138c is opened so that the fifth electrode 32 of the power semiconductor element 1 connects to the metal plate 135c. Each metal plate 135a, 135b, and 135c protrudes outward from the outer edge of the first ceramic plate 131, and external terminals 135d, 135e, 135f, and 135g are formed by these protruding portions so as to be connected to the outside. Here, external terminals 135e and 135f are formed from the same metal plate 135b, with one serving as, for example, the source electrode terminal and the other as the auxiliary source electrode terminal. By providing the auxiliary source terminal, the potential reference point of the control signal from the control electrode, for example, the gate signal, can be placed on the chip electrode of the power semiconductor chip 10, and a voltage drop due to parasitic inductance in the wiring to the chip inside the package, which occurs when the potential reference point of the gate signal is outside the package, is prevented.

[0111] Figure 21A is a plan view of the second ceramic plate 132 and the metal plate provided thereon, and Figure 21B is a bottom view of the second ceramic plate 132 and the metal plate provided thereon. As shown in Figure 21B, a metal plate 134 is provided on the non-opposing side of the second ceramic plate 132, except for the peripheral edge, and a plurality of metal plates 136a, 136b are provided on the opposing side of the second ceramic plate 132. Patterns are formed on the insulating layers 139a, 139b of the metal plates 136a, 136b so that they can be electrically connected to the fourth electrode 31, fifth electrode 32, and sixth electrode 33 of the power semiconductor element 1, respectively. As shown in Figure 21A, the insulating layer 139a is open so that the sixth electrode 33 of the power semiconductor element 1 can connect to the metal plate 136a. The insulating layer 139b has openings so that the fourth electrode 31 and the fifth electrode 32 of the power semiconductor element 1 are connected to the metal plate 136b. Each metal plate 136a and 136b protrudes outward from the outer circumference of the second ceramic plate 132, and external terminals 136d, 136e, 136f, and 136g are formed by these protruding portions so as to be connected to the outside. Here, one of the external terminals 136e and 136f becomes the source electrode terminal, and the other becomes the auxiliary source electrode terminal.

[0112] Preferably, the metal plates 135b and 135c of the first ceramic plate 131 have openings in their corresponding insulating layers 138b and 138c, respectively, and a snubber capacitor 140 (see Figure 22) is provided between the metal plates 135b and 135c through these openings.

[0113] Figure 22 is a plan view of the power semiconductor module 3 shown in Figure 19A, when it is temporarily assembled in a direction sandwiched between two ceramic plates, so that the arrangement of each component can be seen. As shown in the upper left of Figure 22, the first ceramic plate 131 is placed with the metal plates 135a, 135b, and 135c on its upper surface. The insulating layers 137a, 137b, and 137c are not shown in Figure 22. On top of that, as shown in the left center of Figure 22, the frame 137 is placed. As shown in the lower left of Figure 22, the power semiconductor elements 1 are placed in the openings 137a of the frame 137. At that time, the sixth electrode 33, the fourth electrode 31, and the fifth electrode 32 of the power semiconductor element 1 are positioned so that they can be connected to the lower metal plates 135a, 135b, and 135c. If necessary, a snubber capacitor 140 is placed in the central opening 137b of the frame 137 so that its electrodes face downward. Then, as shown on the right in Figure 22, the second ceramic plate 132 is positioned with the metal plates 136a and 136b facing downwards. At this time, the sixth electrode 33 of the power semiconductor element 1 is positioned so that it can be connected to the upper metal plate 136a. In Figure 22, the insulating layers 139a, 139b, 134 and the metal plate 134 are not shown, and the lower members are indicated by dotted lines to the extent necessary to show the relationship with the lower members. Note that each of the metal plates 135a, 135b, 135c, 136a, and 136b is connected to the corresponding fourth electrode 31, fifth electrode 32, and sixth electrode 33 of the power semiconductor element 1 using solder or a conductive bonding material.

[0114] Figure 23 shows the equivalent circuit of the power semiconductor module 3 shown in Figure 19A. The power semiconductor element 1 is configured by connecting a power transistor and a diode in parallel. A snubber capacitor C and a resistor R are provided between P and N. G1 and G2 are the external terminals of the gate, S1 and S2 are the external terminals of the auxiliary source, and Out(U) is the external terminal of the output. This constitutes the upper arm and the lower arm.

[0115] As described above, the power semiconductor module 3 according to the twelfth embodiment of the present invention comprises a plurality of power semiconductor elements 1 belonging to the first group 3A and a plurality of power semiconductor elements 1 belonging to the second group 3B, and each of the plurality of power semiconductor elements 1 of the first group 3A and the second group 3B has the configuration according to the first embodiment. That is, the power semiconductor element 1 comprises a power semiconductor chip 10 having a first electrode 11 and a second electrode 12 on the first surface side and a third electrode 13 on the second surface side opposite to the first surface, with the first electrode 11 provided in the main cell region, a fourth electrode 31 provided so as to be able to conduct with the first electrode 11 of the corresponding power semiconductor chip 1 and having a protruding portion that extends outward from the outer peripheral edge of the corresponding power semiconductor chip 1, a fifth electrode 32 provided so as to be able to conduct with the third electrode 13 of the corresponding power semiconductor chip 1, and a sixth electrode 33 provided so as to be able to conduct with the second electrode 12 of the corresponding power semiconductor chip 1. In the first group 3A, the fourth electrode 31 and the sixth electrode 33 of each power semiconductor element 1 are positioned in the same direction as the fifth electrode 32 of each power semiconductor element 1 in the second group 3B. That is, the fourth electrode 31 and the sixth electrode 33 of each power semiconductor element 1 in the second group 3B are positioned in the same direction as the fifth electrode 32 of each power semiconductor element 1 in the first group 3A. The fourth electrode 31 of each power semiconductor element 1 in the first group 3A, the fifth electrode 32 of each power semiconductor element 1 in the first group 3A, the sixth electrode 33 of each power semiconductor element 1 in the first group 3A, the fourth electrode 31 of each power semiconductor element 1 in the second group 3B, the fifth electrode 32 of each power semiconductor element 1 in the second group 3B, and the sixth electrode 33 of each power semiconductor element 1 in the second group 3B are provided to be electrically connected to the external terminals by metal plates 135a, 135b, 135c, 136a, and 136b that constitute the corresponding external terminals for each of the fourth electrode 31, fifth electrode 32, and sixth electrode 33 in each group.In Figures 20A, 20B, 21A, and 21B, the metal plates 135a, 135b, 135c, 136a, and 136b are held by the corresponding first ceramic plate 131 and second ceramic plate 132, respectively, so they can be thin and may be layers made of metal (including alloys). For this reason, the metal plates 135a, 135b, 135c, 136a, and 136b can be called external connection electrodes, including the meaning of layers made of metal (including alloys).

[0116] In the power semiconductor element 1 according to the embodiment of the present invention, one or more power semiconductor chips are rewired using a multilayer wiring layer, resulting in a wireless, lead-frameless structure that allows for smaller inductance compared to cases using wires and lead frames. Furthermore, the multilayer wiring structure enables heat dissipation not only through current conduction but also through thermal conduction. By packaging multiple power semiconductor chips into one, it becomes easy to obtain an output that is a natural number multiple of the output of a single power semiconductor chip. The power semiconductor elements 1 and power semiconductor modules 2, 3 according to each embodiment of the present invention can be water-cooled by immersion. Depending on the number of power semiconductor chips 10 in the power semiconductor element 1, it can be applied to small robots such as drones, data centers, trains, electric vehicles, and the like.

[0117] Even power semiconductor chips that have only low output due to the semiconductor material used, such as GaN, can have their source, gate, and drain connected by multilayer wiring layers.

[0118] Conventionally, due to the small size of power semiconductor chips, it has been difficult to connect wires and lead frames to the chips, making mass production impossible. Furthermore, if wires and lead frames cannot be connected to each chip individually, it is difficult to pass large currents through them. In addition, it is difficult to transfer heat from the junction (heat-generating part) inside the chip to the outside. In the technology of power semiconductor devices with low output and small chips, redistribution layers have not been used conventionally because they lead to increased costs. However, as in the embodiment of the present invention, by connecting the first electrode, second electrode, and third electrode of one or more power semiconductor chips to external terminals using redistribution layers, electrodes with protruding portions can be provided, thereby enabling the passage of large currents and heat dissipation.

[0119] In any embodiment of the present invention, each electrode constituting the redistribution layer has a laminated structure including a layer made of a material with good thermal conductivity. The layer made of the material with good thermal conductivity (for example, the first metal layer) has a thickness of 100 μm to 300 μm (at least 75 μm, preferably 100 μm). This allows heat generated within the power semiconductor chip to be transferred to the outside via the first metal layer, and also allows current to flow. In particular, since the cross-sectional area of ​​the first metal layer increases in the direction of thickness, the current density can also be gradually reduced.

[0120] [others] The following describes various variations applicable to the embodiments of the present invention described above. Figures 24A and 24B show the pattern of the fourth electrode in the power semiconductor device 1. The same reference numerals are used as for the components shown in Figures 2 and 9. As shown in Figure 24A, the fourth electrode 31 has a portion 34c that overlaps with the main cell region 16A, a portion 34d that overlaps with the region from the terminal region to the outer edge of the chip, and a portion 34e that overlaps with the surrounding portion 20. Here, portion 34d is a bridging portion between portion 34c and portion 34e, and is composed of three parts: a portion that protrudes only in the +x direction and the -x direction, and a portion that protrudes in the +y direction. As a result, there is a region between portion 34c and portion 34e where the metal layer that will become the fourth electrode 31 is not provided. This allows for stress distribution.

[0121] As shown in Figure 24B, the fourth electrode 31 has a portion 34c that overlaps with the main cell region 16A, a portion 34d that overlaps with the region from the terminal region to the outer edge of the chip, and a portion 34e that overlaps with the surrounding portion 20. Unlike Figure 24A, the fourth electrode 31 shown in Figure 24B is provided such that portion 34g is sandwiched in the x-axis direction by portion 37c that overlaps with the region of the main cell region 16A where the gate electrode is provided.

[0122] [Prototype example] Next, a prototype example will be described. Figure 25 is a microscopic image of the prototype sample, with the upper left being the first surface and the upper right being the second surface, and the lower left and lower right being diagrams of the microscopic image, respectively. The lower part shows an image of the microscopic image. As shown in Figure 25, most of the first surface of the power semiconductor chip is the main cell region (source electrode), and a fourth electrode 31 is provided to conduct electricity to half of the main cell region. The fourth electrode 31 has an overhanging electrode that extends outward from the power semiconductor chip 10 in the x and y directions by an extension portion 34b. A sixth electrode (gate electrode) 32 is provided in a part of the remaining half of the first surface of the power semiconductor chip 10, and an overhanging electrode in the y direction is provided on an insulating layer provided on the terminal region along the y direction from the sixth electrode. On the other hand, a third electrode (drain electrode) is provided over the entire surface of the second surface of the power semiconductor chip 10, and a fifth electrode 32 is provided on that surface.

[0123] Figure 26 shows the measurement results of thermal transient characteristics. As samples, measurements were taken using a diode-type power switch element in two cases: Case 1, where it was cooled from a first side, and Case 2, where it was cooled from a second side. In both cases, measurements were taken with and without grease between the water cooling unit and the switch. A T3Ster was used for the measurements. The horizontal axis in Figure 26 represents the thermal resistance (cumulative thermal resistance) R of the heat transfer path. th [K / W] is shown, with the vertical axis representing heat capacity (cumulative heat capacity) C. th The graph shows [Ws / K]. The left end of the graph represents the heat source (chip), and as you move to the right, you move further away from the heat source and the heat dissipates into the atmosphere (ambient temperature). The curves in the middle represent the thermal characteristics of the heat transfer path in the mounting structure; a steep slope indicates a structure with low thermal resistance, and a gentle slope indicates a structure with high thermal resistance. It can be seen that cooling from the first side is more efficient than cooling from the second side.

[0124] Figure 26 shows that in both Case 1, where the unit is cooled from the first side, and Case 2, where it is cooled from the second side, applying grease to the water cooling unit improves thermal conductivity. When grease is applied, in Case 1, where the unit is cooled from the first side, heat is dissipated from the upper electrode, and compared to Case 2, where the unit is cooled from the second side, the thermal resistance R th That has decreased by about 60% to about 40%.

[0125] Figures 27A and 27B show the measurement results of the electrical characteristics of the sample. As shown in Figure 27A, it shows the drain current characteristics with respect to source-drain voltage when the gate voltage is a parameter. These are the drain currents with respect to source-drain voltage when the gate voltage is 7V, 9V, 11V, 13V, and 15V. It was confirmed that a power semiconductor device with a source-drain voltage of 2V and a drain current of 20A was fabricated. The gate-source was short-circuited using a curve tracer, and a voltage was applied between the source and drain to measure the current flowing between the source and drain. From Figure 27B, which shows the results, the breakdown voltage was determined to be 900V, and it was confirmed to be a high breakdown voltage.

[0126] It goes without saying that each embodiment of the invention may incorporate parts of other embodiments or be modified as appropriate. [Explanation of Symbols]

[0127] 1: Power semiconductor element 2,3: Power semiconductor modules 10: Power semiconductor chips 11: First electrode 12: Second electrode 12A: Region where the second electrode is provided 13: Third electrode 14:Terminal structure part 14A: Termination area 15: Chip outer edge (outer edge) 16A: Main cell area 20: Enclosed section 21: First insulating layer 21a, 21b: Through hole 22: Second insulating layer 23: Third insulating layer 24: The fourth insulating layer 25: First insulating layer 26: The fourth insulating layer 30: Multilayer wiring section 31: Fourth electrode 32: Fifth electrode 32a: First metal layer 32b: Second metal layer 32c: Third metallic layer 33: Third electrode 34: First metal layer 34a: Buried section 34b: Extension part 34c: Area overlapping with the main cell region 34d: The area overlapping with the region from the terminal region to the outer edge of the chip. 34e: The part that overlaps with the enclosed area (the protruding part) 35: Second metal layer 36: The third metallic layer 37: First metal layer 37a: Buried part 37b: Extension part 37f: Connection part 37c: The area that overlaps with the region where the gate electrode is located. 37d: The area overlapping with the region from the terminal region to the outer edge of the chip. 37e: The part that overlaps with the enclosed area (the protruding part) 38: Second Metal Layer 39: The third metallic layer 40,41,42,43: Metal plate 44,45: Ceramic plate 50,51,52: Cooling section 60: Drive chip 61: First electrode 62: Second electrode 63: Third electrode 64:Terminal structure part 71: Connecting electrodes 72: Fifth electrode 72a: First metal layer 72b: Second metal layer 72c: Third metallic layer 73: The sixth electrode 74: First metal layer 74a, 74b: Buried part 74c: Extension part 75: Second metal layer 76: Second Metal Layer 77: First Metal Layer 78: Second Metal Layer 79: The third metallic layer 101: Metal layer 102: Carrier substrate 103: Adhesive sheet 104: Mold resin layer 105,106: Insulating layer 105a, 106a: Through holes (contact holes)

Claims

1. A power semiconductor chip comprising a first electrode and a second electrode on a first surface, a third electrode on the second surface opposite to the first surface, and the first electrode located in the main cell region, A fourth electrode is provided on the first surface side of the power semiconductor chip so as to be able to conduct electricity with the first electrode, and has a protruding portion that extends outward from the outer edge of the power semiconductor chip, A fifth electrode is provided on the second surface side of the power semiconductor chip so as to be able to conduct electricity with the third electrode, A sixth electrode is provided on the first surface side of the power semiconductor chip so as to be able to conduct electricity with the second electrode, and has a protruding portion that extends outward from the outer peripheral edge of the power semiconductor chip, A first metal plate is provided on the fourth electrode from either the upper or lower direction, A second metal plate is provided on the fifth electrode from either the upper or lower direction, A third metal plate is provided on the sixth electrode from either the upper or lower direction, The first metal plate and the first ceramic plate that holds the third metal plate, A second ceramic plate that holds the second metal plate, A cooling section that sandwiches the first ceramic plate and the second ceramic plate from above and below, It is equipped with, The first metal plate, the second metal plate, and the third metal plate each have the shape of an external terminal, forming a power semiconductor module.

2. The power semiconductor chips are a plurality of, The power semiconductor module according to claim 1, wherein the fourth electrode is provided so as to be electrically connected to the first electrode of each of the plurality of power semiconductor chips.

3. The fifth electrode is configured to include a first metal layer provided on the side of the third electrode opposite to the first electrode, and a second metal layer provided on the side of the first metal layer opposite to the first electrode. The first metal layer is a Cu layer, an Al layer, or an alloy layer containing Cu or Al. The power semiconductor module according to claim 1.

4. On the first side of the power semiconductor chip, a termination structure is provided between the outer edge of the power semiconductor chip and the main cell region. An insulating layer is provided on at least the terminal structure, The fourth electrode is configured such that a portion of it is provided within a through-hole in the insulating layer and can conduct electricity with the first electrode, and has a first metal layer provided such that, in a top view, it at least partially overlaps with the first electrode and at least partially overlaps with the insulating layer on the terminal structure. The power semiconductor module according to claim 1 or 2.

5. The fourth electrode is composed of a second metal layer provided on the first metal layer opposite to the insulating layer, The protruding portion is composed of at least a part of the second metal layer. The power semiconductor module according to claim 4.

6. The first metal layer is a Cu layer, an Al layer, or an alloy layer containing Cu or Al. The power semiconductor module according to claim 4 or 5.

7. Of the fourth electrodes, when viewed from above, the area ratio of the area outside the power semiconductor chip to the main cell area of ​​one power semiconductor chip is 20% or more per power semiconductor chip. A power semiconductor module according to any one of claims 1 to 6.

8. On the first side of the power semiconductor chip, a termination structure is provided between the outer edge of the power semiconductor chip and the main cell region. An insulating layer is provided on at least the terminal structure, The sixth electrode is configured such that a portion of it is provided within a through-hole in the insulating layer and can conduct electricity with the second electrode, and includes a first metal layer provided such that, in a top view, it at least partially overlaps with the second electrode and at least partially overlaps with the insulating layer on the terminal structure, and a second metal layer provided on the first metal layer on the opposite side of the insulating layer, separated from the second electrode so as not to overlap with the second electrode in a top view. The power semiconductor module according to claim 1 or 2.

9. The protruding portion of the sixth electrode is composed of the second metal layer. The power semiconductor module according to claim 8.

10. The power semiconductor module according to any one of claims 1 to 9, further comprising an insulating enclosure surrounding the outer peripheral side surface of the power semiconductor chip, wherein the protruding portion of the fourth electrode is provided on the enclosure.

11. The power semiconductor module according to claim 10, wherein the surface of the enclosed portion opposite to the fourth electrode is flush with a first metal layer provided on the opposite side of the first electrode as part of the fifth electrode, and the first metal layer does not protrude from the outside in the thickness direction of the enclosed portion.

12. Multiple power semiconductor devices belonging to the first group, Multiple power semiconductor devices belonging to the second group, Equipped with, Each of the plurality of power semiconductor elements in the first group and the second group is, A power semiconductor chip comprising a first electrode and a second electrode on a first surface, a third electrode on the second surface opposite to the first surface, and the first electrode located in the main cell region, A fourth electrode is provided so as to be electrically connected to the first electrode of the corresponding power semiconductor chip, and has a protruding portion that extends outward from the outer peripheral edge of the corresponding power semiconductor chip, A fifth electrode provided to be electrically connected to the third electrode of the corresponding power semiconductor chip, A sixth electrode provided to be electrically connected to the second electrode of the corresponding power semiconductor chip, It is equipped with, The fourth electrode and the sixth electrode of each of the power semiconductor elements in the first group are arranged in the same direction as the fifth electrode of each of the power semiconductor elements in the second group. The fourth electrode of each power semiconductor element in the first group, the fifth electrode of each power semiconductor element in the first group, the sixth electrode of each power semiconductor element in the first group, the fourth electrode of each power semiconductor element in the second group, the fifth electrode of each power semiconductor element in the second group, and the sixth electrode of each power semiconductor element in the second group are provided to be electrically connected to the corresponding external terminals for each of the fourth, fifth, and sixth electrodes in each group. Power semiconductor module.

13. The power semiconductor module according to claim 12, wherein at least one of the power semiconductor elements in the first group and at least one of the power semiconductor elements in the second group has a plurality of power semiconductor chips.

14. The power semiconductor module according to claim 12 or 13, wherein a capacitor is provided between the fourth electrode of each of the power semiconductor elements in the first group and the fifth electrode of each of the power semiconductor elements in the second group.

15. A power semiconductor chip comprising a first electrode and a second electrode on a first surface, a third electrode on the second surface opposite to the first surface, and the first electrode being provided in the main cell region, An insulating layer having through holes is provided on the first surface of the power semiconductor chip, A fourth electrode is provided on the first surface side of the power semiconductor chip so as to be able to conduct electricity with the first electrode, and has a protruding portion that extends outward from the outer edge of the power semiconductor chip, A sixth electrode comprising: an embedded portion provided in the through-hole on the first surface side of the power semiconductor chip so as to be able to conduct electricity with the second electrode; a connecting portion provided away from the fourth electrode and in the opposite direction to the embedded portion; and an extension portion provided between the embedded portion and the connecting portion; It is equipped with, On the first surface side of the power semiconductor chip, a termination structure is provided between the outer peripheral edge of the power semiconductor chip and the main cell region, and the insulating layer is provided at least on the termination structure. The sixth electrode is configured to include a first metal layer that constitutes the embedded portion and the extended portion by being provided such that, in a top view, it at least partially overlaps with the second electrode and at least partially overlaps with the insulating layer on the terminal structure portion, and a second metal layer that constitutes the connection portion by being provided on the first metal layer on the opposite side of the insulating layer, spaced apart from the second electrode so as not to overlap with the second electrode in a top view. The connecting portion extends in a direction intersecting the direction in which the extended portion extends from the buried portion. Power semiconductor device.

16. The power semiconductor element according to claim 15, wherein a plurality of power semiconductor chips are provided, and each of the second electrodes is connected to the sixth electrode.

17. Furthermore, the power semiconductor element according to claim 15 or 16, further comprising a fifth electrode provided on the second surface side of the power semiconductor chip so as to be electrically connected to the third electrode.

18. The fifth electrode is configured to include a first metal layer provided on the side of the third electrode opposite to the first electrode, and a second metal layer provided on the side of the first metal layer opposite to the first electrode. The first metal layer of the fifth electrode is a Cu layer, an Al layer, or an alloy layer containing Cu or Al. The power semiconductor device according to claim 17.

19. The fourth electrode is configured such that a portion of it is provided within a through-hole in the insulating layer and can conduct electricity with the first electrode, and has a first metal layer provided such that, in a top view, it at least partially overlaps with the first electrode and at least partially overlaps with the insulating layer on the terminal structure. A power semiconductor device according to any one of claims 15 to 18.

20. The fourth electrode is composed of a second metal layer provided on the first metal layer opposite to the insulating layer, The protruding portion of the fourth electrode is composed of at least a part of the second metal layer. The power semiconductor device according to claim 19.

21. The first metal layer of the fourth electrode is a Cu layer, an Al layer, or an alloy layer containing Cu or Al. The power semiconductor device according to claim 19 or 20.

22. Of the fourth electrodes, when viewed from above, the area ratio of the area outside the power semiconductor chip to the main cell area of ​​one power semiconductor chip is 20% or more per power semiconductor chip. A power semiconductor device according to any one of claims 15 to 21.

23. The power semiconductor element according to any one of claims 15 to 22, further comprising an insulating enclosure surrounding the outer peripheral side surface of the power semiconductor chip, wherein the protruding portion of the fourth electrode is provided on the enclosure.

24. A fifth electrode provided on the second surface side of the power semiconductor chip so as to be electrically connected to the third electrode, An insulating enclosure surrounding the outer peripheral side of the power semiconductor chip, It also has the following features: The protruding portion of the fourth electrode is provided on the enclosed portion, The power semiconductor element according to claim 15 or 16, wherein the surface of the enclosed portion opposite to the fourth electrode is flush with a first metal layer provided on the opposite side of the first electrode as part of the fifth electrode, and the first metal layer does not protrude from the outside in the thickness direction of the enclosed portion.

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