Optical module

Abstract

In an optical module having an electrical integrated circuit and an optical integrated circuit, the heat dissipation performance of the optical integrated circuit is improved. [Solution] The optical module comprises a wiring board having a core layer, a first laminate stacked on the upper surface of the core layer, recesses opening on the upper and side surfaces of the first laminate, and a first metal layer disposed on the upper surface of the core layer with its upper surface exposed at the bottom of the recess; an optical integrated circuit disposed on the upper surface of the first metal layer; and an electrical integrated circuit disposed on the upper surface of the first laminate, capable of transmitting and receiving signals with the optical integrated circuit, wherein the first metal layer extends from a region overlapping with the optical integrated circuit in a plan view to a region not overlapping with the optical integrated circuit in a plan view.

Description

Technical Field

[0001] The present invention relates to an optical module.

Background Art

[0002] There is known an optoelectronic conversion device including a circuit board having a first recess, a first metal wiring formed from the bottom surface of the first recess to the surface on which the first recess is formed in the circuit board, an optical element disposed in the first recess and flip-chip bonded to the first metal wiring on the bottom surface of the first recess, and a circuit chip flip-chip bonded to the first metal wiring on the surface on which the first recess is formed (Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a device, it is preferable to consider heat dissipation of the circuit chip as well as heat dissipation of the optical element.

[0005] The present invention has been made in view of the above points, and an object thereof is to improve heat dissipation of an optical integrated circuit in an optical module having an electrical integrated circuit and an optical integrated circuit.

Means for Solving the Problems

[0006] The present optical module includes a wiring board having a core layer, a first laminate laminated on the upper surface of the core layer, a recess opening to the upper surface and side surface of the first laminate, and a first metal layer disposed on the upper surface of the core layer and having an upper surface exposed at the bottom of the recess. It has a pad,The first laminate comprises an optical integrated circuit disposed on the upper surface of the first metal layer and an electrical integrated circuit disposed on the upper surface of the first laminate capable of transmitting and receiving signals with the optical integrated circuit. The optical integrated circuit is positioned with the side opposite to the side on which the pad is provided facing the side of the first metal layer, The first metal layer extends from a region that overlaps with the optical integrated circuit in a plan view to a region that does not overlap with the optical integrated circuit in a plan view. [Effects of the Invention]

[0007] According to the disclosed technology, in an optical module having an electrical integrated circuit and an optical integrated circuit, the heat dissipation of the optical integrated circuit can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view illustrating an optical module according to the first embodiment. [Figure 2] This is a partial plan view illustrating an optical module according to the first embodiment. [Figure 3] This is a partial cross-sectional view illustrating an optical module according to the first embodiment. [Figure 4] This is a diagram (part 1) illustrating the manufacturing process of an optical module according to the first embodiment. [Figure 5] This is a diagram (part 2) illustrating the manufacturing process of an optical module according to the first embodiment. [Figure 6] This is a partial plan view illustrating an optical module according to a modified example 1 of the first embodiment. [Figure 7] This is a partial cross-sectional view illustrating an optical module according to a modified example 1 of the first embodiment. [Figure 8] This is a partial cross-sectional view illustrating an optical module according to a modified example 2 of the first embodiment. [Figure 9] This is a plan view illustrating an optical module according to a modified example 3 of the first embodiment. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0010] <First Embodiment> [Structure of the optical module] Figure 1 is a plan view illustrating an optical module according to the first embodiment. Figure 2 is a partial plan view illustrating an optical module according to the first embodiment, showing an enlarged view of the R portion of Figure 1. Figure 3 is a partial cross-sectional view illustrating an optical module according to the first embodiment, showing a cross-section along line AA in Figure 2.

[0011] Referring to Figures 1 to 3, the optical module 1 includes a wiring board 2, a photonic integrated circuit (PIC) 60, an electronic integrated circuit (EIC) 70, an electronic integrated circuit 80, and an optical fiber array 90.

[0012] The electrical integrated circuit 80 can be placed, for example, near the center of the wiring board 2 in a plan view. The optical integrated circuit 60, the electrical integrated circuit 70, and the optical fiber array 90 can each be placed one or more times. If the wiring board 2 is rectangular in a plan view, the optical integrated circuit 60, the electrical integrated circuit 70, and the optical fiber array 90 can be placed in multiple sets, for example, along each side of the rectangle. In this case, the electrical integrated circuit 80 and each of the electrical integrated circuits 70 can be placed close together, enabling high-speed transmission and reception of electrical signals between the electrical integrated circuit 80 and each of the electrical integrated circuits 70.

[0013] (Wiring board 2) The wiring board 2 has a core layer 10 having an upper surface 10a and a lower surface 10b which is the opposite surface of the upper surface 10a; a first laminate 51 including wiring layers and insulating layers alternately stacked on the upper surface 10a of the core layer 10; a second laminate 52 including wiring layers and insulating layers alternately stacked on the lower surface 10b of the core layer 10; and recesses 51x that open on the upper surface and side surface of the first laminate 51.

[0014] The first laminate 51 has a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, an insulating layer 17, a wiring layer 18, an insulating layer 19, a wiring layer 20, an insulating layer 21, a wiring layer 22, an insulating layer 23, a wiring layer 24, and a solder resist layer 25, which are sequentially laminated on the upper surface 10a of the core layer 10. The second laminate 52 has a wiring layer 32, an insulating layer 33, a wiring layer 34, an insulating layer 35, a wiring layer 36, an insulating layer 37, a wiring layer 38, an insulating layer 39, a wiring layer 40, an insulating layer 41, a wiring layer 42, an insulating layer 43, a wiring layer 44, and a solder resist layer 45, which are sequentially laminated on the lower surface 10b of the core layer 10.

[0015] In the first embodiment, for the sake of convenience, in the optical module 1, the side of the solder resist layer 25 of the wiring board 2 is taken as the upper side or one side, and the side of the solder resist layer 45 is taken as the lower side or the other side. Also, the surface on the solder resist layer 25 side of each part is taken as one surface or the upper surface, and the surface on the solder resist layer 45 side is taken as the other surface or the lower surface. However, the optical module 1 can be used in an upside-down state or arranged at an arbitrary angle. Also, the plan view means viewing the object from the normal direction of the upper surface 10a of the core layer 10, and the planar shape means the shape of the object viewed from the normal direction of the upper surface 10a of the core layer 10.

[0016] The core layer 10 can be formed, for example, in a rectangular shape in plan view. The thickness of the core layer 10 is, for example, about 100 to 1000 μm. The core layer 10 is provided with a through-wiring 11 that penetrates the core layer 10 in the thickness direction. The planar shape of the through-wiring 11 is, for example, circular.

[0017] The core layer 10 is preferably made of glass. When the main body 61 of the optical integrated circuit 60 described later is made of silicon, by using the glass-made core layer 10, the difference in the coefficient of thermal expansion from the main body 61 of the optical integrated circuit 60 can be reduced. Thereby, the stress on the optical waveguide 63 of the optical integrated circuit 60 can be relaxed. The type of glass constituting the core layer 10 is not limited, and for example, alkali-free glass, fused quartz glass, borosilicate glass, etc. can be used. <000,0097>

[0018] A substrate containing an insulating resin such as epoxy resin may be used as the core layer 10. Similarly, if the main body 61 of the optical integrated circuit 60 described later is made of silicon, it is preferable to select a core layer 10 containing an insulating resin that has a thermal expansion coefficient close to that of silicon. The thermal expansion coefficient of the core layer 10 containing the insulating resin can be adjusted, for example, by including glass cloth or fillers in the core layer 10. The thermal expansion coefficient of silicon is 2.6 × 10⁻⁶ at room temperature. -6 It's around / K.

[0019] The wiring layer 12 is located on the upper surface 10a of the core layer 10. The wiring layer 12 may include a metal layer 12M. The wiring layer 32 is located on the lower surface 10b of the core layer 10. The wiring layer 32 may include a metal layer 32M. The wiring layer 12 containing the metal layer 12M and the wiring layer 32 containing the metal layer 32M are electrically connected by through-wiring 11. The wiring layers 12 and 32 are each patterned into a predetermined planar shape. The metal layers 12M and 32M can be formed, for example, as solid blocks. For the materials of the wiring layers 12 and 32, and the through-wiring 11, for example, copper (Cu) can be used. The thickness of the wiring layers 12 and 32 is, for example, about 10 to 40 μm. Note that the wiring layer 12, the wiring layer 32, and the through-wiring 11 may be formed integrally.

[0020] The insulating layer 13 is formed on the upper surface 10a of the core layer 10 so as to cover the wiring layer 12. As the material for the insulating layer 13, for example, an insulating resin mainly composed of epoxy resin or polyimide resin can be used. The thickness of the insulating layer 13 can be, for example, about 30 to 40 μm. The insulating layer 13 may contain fillers such as silica (SiO2).

[0021] The wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 comprises via wiring that penetrates the insulating layer 13 and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern is electrically connected to the wiring layer 12 via the via wiring. The material of the wiring layer 14 and the thickness of the wiring pattern can be the same as, for example, the same as the wiring layer 12. The wiring layer 14 may include pads.

[0022] The insulating layer 15 is formed so as to cover the wiring layer 14 on the upper surface of the insulating layer 13. The material and thickness of the insulating layer 15 can be the same as, for example, the insulating layer 13. The insulating layer 15 may contain fillers such as silica (SiO2).

[0023] The wiring layer 16 is formed on one side of the insulating layer 15. The wiring layer 16 comprises via wiring that penetrates the insulating layer 15 and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern is electrically connected to the wiring layer 14 via the via wiring. The material of the wiring layer 16 and the thickness of the wiring pattern can be the same as, for example, the same as the wiring layer 12. The wiring layer 16 may include pads.

[0024] The insulating layer 17 is formed so as to cover the wiring layer 16 on the upper surface of the insulating layer 15. The material and thickness of the insulating layer 17 can be the same as, for example, the insulating layer 13. The insulating layer 17 may contain fillers such as silica (SiO2).

[0025] The wiring layer 18 is formed on one side of the insulating layer 17. The wiring layer 18 comprises via wiring that penetrates the insulating layer 17 and a wiring pattern formed on the upper surface of the insulating layer 17. The wiring pattern is electrically connected to the wiring layer 16 via the via wiring. The material of the wiring layer 18 and the thickness of the wiring pattern can be the same as, for example, the same as the wiring layer 12. The wiring layer 18 may include pads.

[0026] The insulating layer 19 is formed so as to cover the wiring layer 18 on the upper surface of the insulating layer 17. The material and thickness of the insulating layer 19 can be the same as, for example, the insulating layer 13. The insulating layer 19 may contain fillers such as silica (SiO2).

[0027] The wiring layer 20 is formed on one side of the insulating layer 19. The wiring layer 20 comprises via wiring that penetrates the insulating layer 19 and a wiring pattern formed on the upper surface of the insulating layer 19. The wiring pattern is electrically connected to the wiring layer 18 via the via wiring. The material of the wiring layer 20 and the thickness of the wiring pattern can be the same as, for example, the same as the wiring layer 12. The wiring layer 20 may include pads.

[0028] The insulating layer 21 is formed so as to cover the wiring layer 20 on the upper surface of the insulating layer 19. The material and thickness of the insulating layer 21 can be the same as, for example, the insulating layer 13. The insulating layer 21 may contain fillers such as silica (SiO2).

[0029] The wiring layer 22 is formed on one side of the insulating layer 21. The wiring layer 22 comprises via wiring that penetrates the insulating layer 21 and a wiring pattern formed on the upper surface of the insulating layer 21. The wiring pattern is electrically connected to the wiring layer 20 via the via wiring. The material of the wiring layer 22 and the thickness of the wiring pattern can be the same as, for example, the same as the wiring layer 12. The wiring layer 22 may include pads.

[0030] The insulating layer 23 is formed so as to cover the wiring layer 22 on the upper surface of the insulating layer 21. The material and thickness of the insulating layer 23 can be the same as, for example, the insulating layer 13. The insulating layer 23 may contain fillers such as silica (SiO2).

[0031] The wiring layer 24 is formed on one side of the insulating layer 23. The wiring layer 24 comprises via wiring that penetrates the insulating layer 23 and a pad formed on the upper surface of the insulating layer 23. The pad is electrically connected to the wiring layer 22 via the via wiring. The material of the wiring layer 24 and the thickness of the pad can be the same as, for example, the same as that of the wiring layer 12. The wiring layer 24 may include a wiring pattern.

[0032] The solder resist layer 25 is a protective insulating layer located on the outermost side of the wiring substrate 2, and is formed to cover the wiring layer 24 on the upper surface of the insulating layer 23. The solder resist layer 25 has an opening, and a portion of the upper surface of the wiring layer 24 is exposed within the opening. The planar shape of the opening can be, for example, circular. The solder resist layer 25 can be formed from, for example, a photosensitive epoxy insulating resin or an acrylic insulating resin. The thickness of the solder resist layer 25 is, for example, about 15 to 35 μm.

[0033] Furthermore, a metal layer may be formed on the surface of the wiring layer 24 exposed within the openings of the solder resist layer 25, or an organic film may be formed by applying an anti-oxidation treatment such as OSP (Organic Solderability Preservative) treatment. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer formed by stacking a Ni layer and an Au layer in that order), a Ni / Pd / Au layer (a metal layer formed by stacking a Ni layer, a Pd layer and an Au layer in that order), and an Sn layer.

[0034] The insulating layer 33 is formed to cover the wiring layer 32 on the lower surface 10b of the core layer 10. The material and thickness of the insulating layer 33 can be the same as, for example, the insulating layer 13. The insulating layer 33 may contain fillers such as silica (SiO2).

[0035] The wiring layer 34 is formed on the other side of the insulating layer 33. The wiring layer 34 comprises via wiring that penetrates the insulating layer 33 and a wiring pattern formed on the lower surface of the insulating layer 33. The wiring pattern is electrically connected to the wiring layer 32 via the via wiring. The material and thickness of the wiring layer 34 can be the same as, for example, the wiring layer 12. The wiring layer 34 may include pads. The wiring layer 34 may include a metal layer 34M. The metal layer 34M can be formed, for example, as a solid.

[0036] The insulating layer 35 is formed on the lower surface of the insulating layer 33 so as to cover the wiring layer 34. The material and thickness of the insulating layer 35 can be the same as, for example, the insulating layer 13. The insulating layer 35 may contain fillers such as silica (SiO2).

[0037] The wiring layer 36 is formed on the other side of the insulating layer 35. The wiring layer 36 comprises via wiring that penetrates the insulating layer 35 and a wiring pattern formed on the underside of the insulating layer 35. The wiring pattern is electrically connected to the wiring layer 34 via the via wiring. The material and thickness of the wiring layer 36 can be the same as, for example, the wiring layer 12. The wiring layer 36 may include pads. The wiring layer 36 may include a metal layer 36M. The metal layer 36M can be formed, for example, as a solid.

[0038] The insulating layer 37 is formed on the lower surface of the insulating layer 35 so as to cover the wiring layer 36. The material and thickness of the insulating layer 37 can be the same as, for example, the insulating layer 13. The insulating layer 37 may contain fillers such as silica (SiO2).

[0039] The wiring layer 38 is formed on the other side of the insulating layer 37. The wiring layer 38 comprises via wiring that penetrates the insulating layer 37 and a wiring pattern formed on the underside of the insulating layer 37. The wiring pattern is electrically connected to the wiring layer 36 via the via wiring. The material and thickness of the wiring layer 38 can be the same as, for example, the wiring layer 12. The wiring layer 38 may include pads. The wiring layer 38 may include a metal layer 38M. The metal layer 38M can be formed, for example, as a solid.

[0040] The insulating layer 39 is formed to cover the wiring layer 38 on the lower surface of the insulating layer 37. The material and thickness of the insulating layer 39 can be the same as, for example, the insulating layer 13. The insulating layer 39 may contain fillers such as silica (SiO2).

[0041] The wiring layer 40 is formed on the other side of the insulating layer 39. The wiring layer 40 comprises via wiring that penetrates the insulating layer 39 and a wiring pattern formed on the underside of the insulating layer 39. The wiring pattern is electrically connected to the wiring layer 38 via the via wiring. The material and thickness of the wiring layer 40 can be the same as, for example, the wiring layer 12. The wiring layer 40 may include pads. The wiring layer 40 may include a metal layer 40M. The metal layer 40M can be formed, for example, as a solid.

[0042] The insulating layer 41 is formed on the lower surface of the insulating layer 39 so as to cover the wiring layer 40. The material and thickness of the insulating layer 41 can be the same as, for example, the insulating layer 13. The insulating layer 41 may contain fillers such as silica (SiO2).

[0043] The wiring layer 42 is formed on the other side of the insulating layer 41. The wiring layer 42 comprises via wiring that penetrates the insulating layer 41 and a wiring pattern formed on the underside of the insulating layer 41. The wiring pattern is electrically connected to the wiring layer 40 via the via wiring. The material and thickness of the wiring layer 42 can be the same as, for example, the wiring layer 12. The wiring layer 42 may include pads. The wiring layer 42 may include a metal layer 42M. The metal layer 42M can be formed, for example, as a solid.

[0044] The insulating layer 43 is formed on the underside of the insulating layer 41 so as to cover the wiring layer 42. The material and thickness of the insulating layer 43 can be the same as, for example, the insulating layer 13. The insulating layer 43 may contain fillers such as silica (SiO2).

[0045] The wiring layer 44 is formed on the other side of the insulating layer 43. The wiring layer 44 comprises via wiring that penetrates the insulating layer 43 and a pad formed on the lower surface of the insulating layer 43. The pad is electrically connected to the wiring layer 42 via the via wiring. The material of the wiring layer 44 and the thickness of the pad can be the same as, for example, the same as the wiring layer 12. The wiring layer 44 may include a wiring pattern. In the wiring layer 44, the portion connected to the metal layer 42M via the via wiring may be formed as a solid.

[0046] The metal layers 34M, 36M, 38M, 40M, 42M, and a portion of the wiring layer 44 are arranged alternately beneath the metal layer 32M, with an insulating layer in between, and are electrically connected to the metal layer 32M via via wiring that penetrates the insulating layer.

[0047] The solder resist layer 45 is a protective insulating layer located on the outermost side of the wiring board 2, and is formed to cover the wiring layer 44 on the underside of the insulating layer 43. The material and thickness of the solder resist layer 45 can be the same as, for example, the solder resist layer 25. The solder resist layer 45 has an opening, in which a portion of the underside of the wiring layer 44 is exposed. The planar shape of the opening can be, for example, circular. The wiring layer 44 exposed in the opening can be used, for example, as a pad for electrically connecting to a mounting board such as a motherboard. If necessary, the aforementioned metal layer may be formed on the underside of the wiring layer 44 exposed in the opening, or an anti-oxidation treatment such as OSP treatment may be applied.

[0048] The recess 51x penetrates the solder resist layer 25 and the insulating layers 23, 21, 19, 17, and 15, and is formed to a depth of a portion of the insulating layer 13. The top surface of the metal layer 12M, which is located on the top surface 10a of the core layer 10, is exposed at the bottom of the recess 51x. The top surface of the insulating layer 13, which is located on the top surface 10a of the core layer 10, is also exposed at the bottom of the recess 51x. The side surface of the metal layer 12M exposed at the bottom of the recess 51x is covered by the insulating layer 13, which is also exposed at the bottom of the recess 51x.

[0049] The upper surface of the insulating layer 13 exposed at the bottom of the recess 51x is lower than the upper surface of the insulating layer 13 constituting the first laminate 51. The upper surface of the insulating layer 13 exposed at the bottom of the recess 51x is flush with, for example, the upper surface of the metal layer 12M. The side surface of the insulating layer 13 exposed at the bottom of the recess 51x is exposed on the side surface of the core layer 10. The side surface of the insulating layer 13 exposed at the bottom of the recess 51x is flush with, for example, the side surface of the core layer 10.

[0050] The recess 51x is, for example, rectangular in shape when viewed from above. The inner wall surface of the recess 51x is, for example, perpendicular to the upper surface 10a of the core layer 10. The upper surface of the metal layer 12M and the upper surface of the insulating layer 13 that constitute the bottom surface of the recess 51x are, for example, parallel to the upper surface 10a of the core layer 10. In this application, perpendicular and parallel include deviations of up to ±10 degrees from strictly perpendicular and parallel.

[0051] (Optical integrated circuit 60, electrical integrated circuit 70, electrical integrated circuit 80, optical fiber array 90) The optical integrated circuit 60 has a main body 61, pads 62 provided on the main body 61, and one or more optical waveguides 63. The main body 61 can be made of, for example, silicon. The pads 62 can be made of, for example, copper or aluminum. The optical waveguide 63 is, for example, a silicon optical waveguide. The optical integrated circuit 60 further has one or more optical elements, which are not shown. The optical elements are, for example, light-emitting elements or light-receiving elements. The optical integrated circuit 60 can convert electrical signals from the electrical integrated circuit 70 into optical signals and transmit them to the optical fiber array 90, or convert optical signals from the optical fiber array 90 into electrical signals and transmit them to the electrical integrated circuit 70. The thickness of the optical integrated circuit 60 can be, for example, 200 μm or more and 400 μm or less. If the optical integrated circuit 60 has a thickness of this magnitude, stress on the optical waveguide 63 due to warping of the core layer 10, etc., can be alleviated, optical axis misalignment between adjacent devices can be suppressed, and good optical connection can be obtained.

[0052] The optical integrated circuit 60 is positioned on the upper surface of the metal layer 12M exposed within the recess 51x of the wiring substrate 2 via a bonding material 110, such that the optical waveguide 63 is located on the side closer to the electrical integrated circuit 70. For example, a thermal interface material (TIM) can be used as the bonding material 110. For example, soft metals such as indium (In) and silver can be used as the thermal interface material. Alternatively, an organic resin binder containing metal fillers or graphite may be used as the thermal interface material. The optical integrated circuit 60 does not need to be electrically connected to the metal layer 12M.

[0053] The metal layer 12M extends from a region that overlaps with the optical integrated circuit 60 in a plan view to a region that does not overlap with the optical integrated circuit 60 in a plan view. The area of ​​the metal layer 12M located in the region that does not overlap with the optical integrated circuit 60 in a plan view is preferably 1.5 times or more, preferably 2 times or more, and more preferably 2.5 times or more, the total area of ​​the upper surfaces of the optical integrated circuits 60 arranged on the upper surface of the same metal layer 12M.

[0054] The electrical integrated circuit 70 has a main body 71 and pads 72 provided on the main body 71. The main body 71 can be made of, for example, silicon. The pads 72 can be made of, for example, copper or aluminum. The electrical integrated circuit 70 is capable of transmitting and receiving signals with the optical integrated circuit 60. The electrical integrated circuit 70 is, for example, an IC chip such as a driver that drives the optical elements of the optical integrated circuit 60. Specifically, the electrical integrated circuit 70 may be, for example, an IC chip incorporating a DSP (Digital Signal Processor) or amplifier that processes the output signal from the optical integrated circuit 60.

[0055] The electrical integrated circuit 70 is located on the upper surface of the first stack 51 of the wiring board 2. The electrical integrated circuit 70 can be flip-chip mounted on the upper surface of the first stack 51, for example. Specifically, the pads 72 of the electrical integrated circuit 70 are electrically connected to a portion of the wiring layer 24 that constitutes the wiring board 2 via a bonding material 120. A portion of the electrical integrated circuit 70 extends from the first stack 51 onto the optical integrated circuit 60, and a portion of the pads 72 is electrically connected to the pads 62 via the bonding material 120. The bonding material 120 is, for example, a solder bump. As the material for the solder bump, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used.

[0056] The optical module 1 may have a plurality of optical integrated circuits 60 arranged spaced apart from each other on the upper surface of a single metal layer 12M, and a plurality of electrical integrated circuits 70 arranged spaced apart from each other on the upper surface of the first laminate 51. In this case, one electrical integrated circuit 70 capable of transmitting and receiving signals can be connected to each optical integrated circuit 60.

[0057] The electrical integrated circuit 80 has a main body 81 and pads 82 provided on the main body 81. The main body 81 can be made of, for example, silicon. The pads 82 can be made of, for example, copper or aluminum. The electrical integrated circuit 80 is, for example, an IC chip that controls the electrical integrated circuit 70, etc. Examples of the electrical integrated circuit 80 include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an NPU (Neural Processing Unit), etc.

[0058] The electrical integrated circuit 80 is mounted on the upper surface of the first stack 51 of the wiring board 2. The electrical integrated circuit 80 can be flip-chip mounted on the upper surface of the first stack 51, for example. Specifically, the pads 82 of the electrical integrated circuit 80 are electrically connected to a portion of the wiring layer 24 that constitutes the wiring board 2 via a bonding material 120. The electrical integrated circuit 80 can transmit and receive electrical signals with the electrical integrated circuit 70.

[0059] The optical fiber array 90 has a housing 91 and one or more optical fibers 92. The housing 91 holds the optical fibers 92. The optical fibers 92 have a core that propagates optical signals and a cladding that surrounds the outer circumference of the core. The optical fiber array 90 can send and receive optical signals with the optical integrated circuit 60.

[0060] The optical fiber array 90 is bonded to the side surface of the core layer 10 and the end surface of the optical integrated circuit 60 via a bonding material 130. Specifically, the optical fiber array 90 is arranged such that the central axis of the core of the optical fiber 92 coincides with the central axis of the core of the optical waveguide 63 of the optical integrated circuit 60. In other words, the optical fiber array 90 is arranged such that the optical axis of the core of the optical fiber 92 coincides with the optical axis of the core of the optical waveguide 63 of the optical integrated circuit 60.

[0061] As the bonding material 130, for example, an optical adhesive can be used. By filling the gap between the optical integrated circuit 60 and the optical fiber array 90 with the optical adhesive, air reflection can be prevented and the coupling efficiency between the optical waveguide 63 of the optical integrated circuit 60 and the optical fiber 92 can be improved. As the optical adhesive, for example, an ultraviolet-curing optical adhesive can be used. It is preferable to use an optical adhesive that has a refractive index close to the refractive index of the core of the optical waveguide 63 and the refractive index of the core of the optical fiber 92.

[0062] The optical module 1 may have a connector that can be connected to an optical fiber array equipped with optical fibers, instead of an optical fiber array. The optical fiber array and connector are typical examples of optical components according to the present invention.

[0063] In this way, in the optical module 1, the optical integrated circuit 60 is placed on the upper surface of the metal layer 12M located at the bottom of the recess 51x of the wiring board 2. The metal layer 12M extends from the region that overlaps with the optical integrated circuit 60 in a plan view to the region that does not overlap with the optical integrated circuit 60 in a plan view. As a result, the metal layer 12M acts as a heat dissipation path for the optical integrated circuit 60, and the heat generated by the optical integrated circuit 60 can be effectively dissipated from the upper surface of the metal layer 12M, thereby improving the heat dissipation performance of the optical integrated circuit 60. In Figure 1, four optical integrated circuits 60 are placed in the recess 51x, but four recesses 51x may be formed, and an optical integrated circuit 60 may be placed in each of them.

[0064] Furthermore, by placing the optical integrated circuit 60 on the upper surface of the metal layer 12M, heat can be dissipated from the optical integrated circuit 60 without directly touching it, that is, without bonding a heat sink to the upper surface of the optical integrated circuit 60. Direct contact with the optical integrated circuit 60 would apply stress to it, potentially causing a misalignment between the optical axis of the core of the optical waveguide 63 in the optical integrated circuit 60 and the optical axis of the core of the optical fiber 92 in the optical fiber array 90. However, in the optical module 1, the heat dissipation of the optical integrated circuit 60 can be improved by the metal layer 12M without directly touching the optical integrated circuit 60, making it less likely for the misalignment caused by the stress described above to occur, and thus improving the stability of the optical properties of the optical module 1.

[0065] Furthermore, if the second laminate 52 has a metal layer 32M located on the lower surface 10b of the core layer 10, the heat generated by the optical integrated circuit 60 can be dissipated from the metal layer 32M by electrically connecting the metal layer 32M to the metal layer 12M via the through wiring 11. Therefore, the heat dissipation performance of the optical integrated circuit 60 can be further improved. From the viewpoint of improving heat dissipation, it is preferable that the metal layer 32M extends from a region that overlaps with the optical integrated circuit 60 in a plan view to a region that does not overlap with the optical integrated circuit 60 in a plan view.

[0066] Furthermore, if the second laminate 52 has a plurality of metal layers arranged alternately with an insulating layer in between in the layer below the metal layer 32M, the heat generated by the optical integrated circuit 60 can be dissipated from the metal layer 32M by electrically connecting each of the plurality of metal layers to the metal layer 32M via via wiring. Therefore, the heat dissipation performance of the optical integrated circuit 60 can be further improved. From the viewpoint of improving heat dissipation, it is preferable that each of the plurality of metal layers extends from a region that overlaps with the optical integrated circuit 60 in a plan view to a region that does not overlap with the optical integrated circuit 60 in a plan view. In the example of the wiring substrate 2, the metal layers located below the metal layer 32M and contributing to the heat dissipation performance of the optical integrated circuit 60 are the metal layers 34M, 36M, 38M, 40M, 42M, and the wiring layer 44 connected to the metal layer 42M.

[0067] Furthermore, since the electrical integrated circuit 70 is located on the upper surface of the first stack 51, heat can be easily dissipated by attaching a heat sink or the like to the upper surface of the electrical integrated circuit 70. Since the electrical integrated circuit 70 does not transmit or receive light, heat dissipation by directly touching the electrical integrated circuit 70 will not cause problems such as optical axis misalignment.

[0068] [Manufacturing method for optical modules] Figures 4 and 5 illustrate the manufacturing process of the optical module according to the first embodiment and show a cross-section corresponding to Figure 3.

[0069] First, in the process shown in Figure 4(a), a wiring board 2 having a core layer 10, a first laminate 51, and a second laminate 52 is prepared. The details of the wiring board 2 are as described with reference to Figure 3, etc., but at this point the recesses 51x have not been formed. The wiring board 2 can be manufactured, for example, by a well-known build-up method. The wiring board 2 may also be prepared by purchase or other means.

[0070] Next, in the process shown in Figure 4(b), recesses 51x are formed in the wiring board 2, opening to the top and side surfaces of the first laminate 51. The recesses 51x can be formed, for example, by counterboring using a router bit. The top surface of the metal layer 12M and the top surface of the insulating layer 13 are exposed at the bottom of the recesses 51x.

[0071] Next, in the process shown in Figure 4(c), an optical integrated circuit 60 having a main body 61, pads 62, and optical waveguides 63 is prepared. Then, the optical integrated circuit 60 is placed on the upper surface of the metal layer 12M constituting the wiring board 2 with the pads 62 facing upwards. The optical integrated circuit 60 can be placed on the upper surface of the metal layer 12M via a bonding material 110, for example, a thermally conductive material.

[0072] Next, in the process shown in Figure 5(a), a conductive bonding material 120 is placed on the wiring layer 24 exposed within the opening of the solder resist layer 25 that constitutes the wiring substrate 2, and on the pads 62 of the optical integrated circuit 60.

[0073] Next, in the process shown in Figure 5(b), the electrical integrated circuit 70 is mounted on the first laminate 51 and the optical integrated circuit 60 that constitute the wiring board 2, and the electrical integrated circuit 80 is mounted on the first laminate 51 that constitutes the wiring board 2. Mounting can be done, for example, by reflow or thermal compression bonding. After mounting, some of the pads 72 of the electrical integrated circuit 70 are electrically connected to the wiring layer 24 exposed in the openings of the solder resist layer 25 via the bonding material 120. Also, some of the pads 72 of the electrical integrated circuit 70 are electrically connected to the pads 62 of the optical integrated circuit 60 via the bonding material 120. Furthermore, the pads 82 of the electrical integrated circuit 80 are electrically connected to the wiring layer 24 exposed in the openings of the solder resist layer 25 via the bonding material 120.

[0074] Next, in the process shown in Figure 5(c), an optical fiber array 90 having a housing 91 and one or more optical fibers 92 is prepared. Then, the housing 91 of the optical fiber array 90 is bonded to the side surface of the core layer 10 and the end surface of the optical integrated circuit 60 via a bonding material 130. At this time, the optical fiber array 90 is positioned so that the optical axis of the core of the optical fiber 92 coincides with the optical axis of the core of the optical waveguide 63 of the optical integrated circuit 60. Through these steps, the optical module 1 is completed.

[0075] Alternatively, instead of the above process, the pads 62 of the optical integrated circuit 60 and the pads 72 of the electrical integrated circuit 70 may be pre-bonded via the bonding material 120, and then mounted onto the wiring board 2.

[0076] <Variations of the first embodiment> A modified example of the first embodiment shows an optical module in which other components are arranged in addition to the optical integrated circuit within a recess of the wiring board. In the modified example of the first embodiment, descriptions of components that are the same as those described in the previously described embodiment may be omitted.

[0077] Figure 6 is a partial plan view illustrating an optical module according to Modification 1 of the first embodiment. Figure 7 is a partial cross-sectional view illustrating an optical module according to Modification 1 of the first embodiment, showing a cross-section along line BB in Figure 6.

[0078] Referring to Figures 6 and 7, the optical module 1A differs from the optical module 1 in that the wiring board 2 is replaced by the wiring board 2A, and the optical integrated circuit 60A and the optical waveguide 150 are arranged in the recess 51x of the wiring board 2A.

[0079] The optical integrated circuit 60A has a body 61, pads 62, a plurality of optical waveguides 63, and via wiring 64. The via wiring 64 is provided inside the body 61 and electrically connects the pads 62 to optical elements etc. arranged inside the body 61. The via wiring 64 can be made of, for example, copper. The optical integrated circuit 60A is arranged on the upper surface of the metal layer 12M such that the optical waveguides 63 are located on the side furthest from the electrical integrated circuit 70. The via wiring 64 may be connected to the metal layer 12M.

[0080] The optical waveguide 150 has a plurality of cores 151 and a cladding 152. The optical waveguide 150 is, for example, a polymer waveguide or a glass waveguide. The optical waveguide 150 is located on the upper surface 10a of the core layer 10 located within the recess 51x. In a plan view, the optical waveguide 150 is located between the optical integrated circuit 60 and the optical fiber array 90.

[0081] The optical waveguide 150 is arranged such that the optical axis of each core 151 coincides with the optical axis of each core of the optical waveguide 63. Furthermore, the optical waveguide 150 is arranged such that the optical axis of each core 151 coincides with the optical axis of each core of the optical fiber 92. This enables the optical integrated circuit 60A to transmit and receive optical signals to and from the optical fiber array 90 via the optical waveguide 150.

[0082] In the optical waveguide 150, the multiple cores 151 have a fan-out structure in which the pitch of the connection portion with the optical fiber 92 of the optical fiber array 90 is wider than the pitch of the connection portion with the optical waveguide 63. This allows the optical waveguide 63 to be easily optically connected to the core of the optical fiber 92 with a wider pitch via the cores 151, even if the pitch of the optical waveguide 63 is narrowed due to miniaturization and high integration of the optical integrated circuit 60A. For example, an optical waveguide 63 with a pitch of 10 to 20 μm can be easily optically connected to the core of an optical fiber 92 with a pitch of 100 to 200 μm. It is also possible to optically connect multiple optical integrated circuits 60A to a single optical fiber array 90 via one or more optical waveguides 150.

[0083] Furthermore, if the core layer 10 is made of glass, the core layer 10 is less prone to warping, thus reducing stress on the optical waveguide 150 placed on the core layer 10. As a result, misalignment is less likely to occur between the optical axis of the core 151 of the optical waveguide 150, the optical axis of the optical waveguide 63, and the optical axis of the core of the optical fiber 92, thereby improving the stability of the optical properties of the optical module 1A.

[0084] Figure 8 is a partial cross-sectional view illustrating an optical module according to a modified example 2 of the first embodiment, and shows the cross-section corresponding to Figure 7.

[0085] Referring to Figure 8, optical module 1B differs from optical module 1 in that the wiring board 2 is replaced by wiring board 2B, and the optical integrated circuit 60, optical waveguide 150, and spacer 160 are arranged within the recess 51x of wiring board 2B. The optical waveguide 150 is positioned on the upper surface 10a of the core layer 10 located within the recess 51x via the spacer 160. The spacer 160 is fixed to the upper surface 10a of the core layer 10, for example, by adhesive.

[0086] Similar to the first embodiment, the optical integrated circuit 60 is positioned on the upper surface of the metal layer 12M such that the optical waveguide 63 is located closer to the electrical integrated circuit 70. The optical waveguide 150 is positioned such that the optical axis of the core 151 coincides with the optical axis of the core of the optical waveguide 63. The optical waveguide 150 is also positioned such that the optical axis of the core 151 coincides with the optical axis of the core of the optical fiber 92. This enables the optical integrated circuit 60 to transmit and receive optical signals to and from the optical fiber array 90 via the optical waveguide 150. If the optical waveguide 150 has multiple cores 151, the multiple cores 151 may have a fan-out structure.

[0087] The spacer 160 is preferably made of glass or silicon, having a thermal expansion coefficient similar to that of the core layer 10. A glass or silicon spacer 160 has a low thermal expansion coefficient and is less prone to warping. Therefore, it can relieve stress on the optical waveguide 150 placed on the spacer 160, suppress optical axis misalignment between the adjacent optical integrated circuit 60 and optical fiber array 90, and obtain a good optical connection.

[0088] Figure 9 is a plan view illustrating an optical module according to modification 3 of the first embodiment. Referring to Figure 9, the optical module 1C differs from the optical module 1 in that, in a plan view, the electrical integrated circuit 70 is larger than the optical integrated circuit 60. Specifically, in a plan view, the length of the sides of the electrical integrated circuit 70 in the direction along each side of the wiring board 2 is longer than the length of the sides of the optical integrated circuit 60 in the direction along each side of the wiring board 2.

[0089] Thus, the size relationship between the electrical integrated circuit 70 and the optical integrated circuit 60 in a plan view can be arbitrarily selected. As shown in Figure 9, even when the electrical integrated circuit 70 is larger than the optical integrated circuit 60 in a plan view, the heat dissipation of the optical integrated circuit 60 can be improved, just as when the electrical integrated circuit 70 is smaller than the optical integrated circuit 60 in a plan view, as shown in Figure 1. In Figure 9, four optical integrated circuits 60 are arranged in the recess 51x, but four recesses 51x may be formed, and an optical integrated circuit 60 may be placed in each of them.

[0090] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of Symbols]

[0091] 1,1A,1B,1C Optical Module 2,2A,2B Wiring board 10-core layer 10a Top 10b Bottom side 11. Through-wiring 12,14,16,18,20,22,24,32,34,36,38,40,42,44 wiring layer 12M,32M,34M,36M,38M,40M,42M metal layer 13,15,17,19,21,23,33,35,37,39,41,43 Insulating layer 25,45 Solder Resist Layer 51. First layer 51x recess 52 Second Laminate 60,60A Optical Integrated Circuit 61, 71, 81 Main unit 62, 72, 82 pads 63 Optical waveguide 64 via wiring 70,80 Electrical Integrated Circuits 90 Optical fiber arrays 91 Housing 92 Optical Fiber 110,120,130 Bonding material 150 Optical waveguide 151 cores 152 Clad 160 Spacer

Claims

1. A wiring board having a core layer, a first laminate laminated on the upper surface of the core layer, recesses opening on the upper and side surfaces of the first laminate, and a first metal layer disposed on the upper surface of the core layer with its upper surface exposed at the bottom of the recess, An optical integrated circuit having a pad and disposed on the upper surface of the first metal layer, The first laminate is disposed on the upper surface and includes an electrical integrated circuit capable of transmitting and receiving signals with the optical integrated circuit, The optical integrated circuit is positioned with the side opposite to the side on which the pad is provided facing the first metal layer, The first metal layer extends from a region overlapping with the optical integrated circuit in a plan view to a region not overlapping with the optical integrated circuit in a plan view, forming an optical module.

2. The wiring board further comprises a second laminate stacked on the lower surface of the core layer, The second laminate has a second metal layer disposed on the lower surface of the core layer, The second metal layer is electrically connected to the first metal layer via through-wiring that penetrates the core layer. The optical module according to claim 1, wherein the second metal layer extends from a region that overlaps with the optical integrated circuit in a plan view to a region that does not overlap with the optical integrated circuit in a plan view.

3. The second laminate has a plurality of third metal layers arranged alternately with an insulating layer in between in the layer below the second metal layer. Each of the plurality of third metal layers is electrically connected to the second metal layer via via wiring that penetrates the insulating layer. The optical module according to claim 2, wherein each of the plurality of third metal layers extends from a region that overlaps with the optical integrated circuit in a plan view to a region that does not overlap with the optical integrated circuit in a plan view.

4. A plurality of optical integrated circuits are arranged spaced apart from each other on the upper surface of one of the first metal layers, The first laminate comprises a plurality of electrical integrated circuits arranged spaced apart from each other on the upper surface of the first laminate, The optical module according to claim 1, wherein one electrical integrated circuit capable of transmitting and receiving signals is connected to each of the optical integrated circuits.

5. The optical module according to claim 1, wherein the side surface of the core layer has an optical component capable of transmitting and receiving optical signals with the optical integrated circuit.

6. The optical integrated circuit has a first optical waveguide, The optical module according to claim 5, wherein the optical integrated circuit is capable of transmitting and receiving optical signals with the optical component via a second optical waveguide.

7. The second optical waveguide has a plurality of cores, The optical module according to claim 6, wherein the plurality of cores have a fan-out structure in which the pitch of the connection portion with the optical component is wider than the pitch of the connection portion with the first optical waveguide.

8. The optical integrated circuit is arranged on the upper surface of the first metal layer such that the first optical waveguide is located on the side furthest from the electrical integrated circuit. The optical module according to claim 6, wherein the second optical waveguide is located on the upper surface of the core layer.

9. The optical integrated circuit is arranged on the upper surface of the first metal layer such that the first optical waveguide is located on the side closer to the electrical integrated circuit. The optical module according to claim 6, wherein the second optical waveguide is disposed on the upper surface of the core layer via a glass spacer.

10. The optical module according to any one of claims 1 to 9, wherein the core layer is made of glass.

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