Method and system for clock data recovery lock-in

Abstract

The application provides a clock data recovery locking method and system, comprising the following steps: a current Vctl acquisition step: acquiring the current temperature of a clock data recovery chip CDR, determining the corresponding Vctl value according to the current temperature, and recording the Vctl value as TVctl, wherein Vctl represents voltage control; a locking judgment step: recording the locked Vctl as LVctl, comparing LVctl and TVctl, and judging whether locking is completed. The CDR locking time is relatively fast, so that the light emitting time and the main and standby switching time of the optical module are relatively short; the locking quality of the CDR is relatively good, so that the receiving sensitivity of the optical module is relatively good.

Description

Technical Field

[0001] This invention relates to the technical field of clock data recovery locking, specifically to a locking method and system for clock data recovery. More particularly, it preferably relates to a locking method and system for a clock data recovery (CDR). Background Technology

[0002] CDR (Clock Data Recovery) is widely used in optical modules, and its locking method significantly affects the locking time, output time, and receiver sensitivity of the optical module. Optical modules generally have requirements for CDR locking time and quality. For example, since the server master / slave failover time is 50ms, the locking time of the optical module must be less than 20ms; the MSA (Multi-Source Agreement) protocol specifies that the time from power-on to output time is 300ms. If CDR locking takes too much time, the optical module cannot meet these requirements. Locking quality is reflected in sensitivity; good locking quality results in high sensitivity, and vice versa. CDR stands for Clock Data Recovery; MSA stands for Multi-Source Agreement.

[0003] Chinese Patent Publication No. CN113114225A discloses a clock data recovery circuit and its operation method. The technology of this invention is used to implement a clock data recovery circuit with improved characteristics, such as pull-up and / or pull-down characteristics. In various embodiments, the clock data recovery circuit includes a phase detector for receiving an input signal and outputting a reference clock signal. The phase detector then outputs two signals to a charge pump. The output of the charge pump drives an oscillator control voltage to rise or fall based on the current from the charge pump. A lock-in detector detects whether a lock-in has occurred by comparing the oscillator control voltage with a preset threshold voltage. A lock-in is indicated when the circuit stabilizes to a frequency substantially close to the input signal and the oscillator control voltage substantially close to the threshold voltage. A controller circuit can control the circuit to scan a frequency range available until a lock-in occurs.

[0004] Chinese invention patent document CN107682007A discloses a fast-locking, low-jitter clock data recovery circuit based on a dual-loop system. The circuit comprises a frequency-locked loop (LLL) consisting of a frequency band switching circuit, a multi-band VCO, a resistor divider circuit, a 2-to-1 multiplexer circuit, and a low-pass filter. The 2-to-1 multiplexer circuit, low-pass filter, multi-band VCO, BBPD, and four charge pumps constitute a phase-locked loop (PLL). The frequency band switching circuit outputs a frequency band control word and a loop selection signal based on the output clock clk0 of the multi-band VCO and the reference clock clk_ref. The resistor divider circuit divides the power supply voltage vdd, and its output is connected to the LLL input of the 2-to-1 multiplexer circuit. The 2-to-1 multiplexer circuit selects between the LLL and PLL based on the loop selection signal.

[0005] Regarding the aforementioned technologies, the inventors believe that many current CDR locking methods do not give much consideration to locking time and locking quality, resulting in longer optical module output time and primary / backup switching time, as well as poor optical module receiving sensitivity. Summary of the Invention

[0006] In view of the deficiencies in the prior art, the purpose of this invention is to provide a locking method and system for clock data recovery.

[0007] A locking method for clock data recovery according to the present invention includes the following steps:

[0008] Current Vctl acquisition steps: Obtain the current temperature of the clock data recovery chip CDR, determine the corresponding Vctl value based on the current temperature, denoted as TVctl, where Vctl represents voltage control;

[0009] Locking determination steps: Record the locked Vctl as LVctl, compare LVctl and TVctl to determine whether locking is complete.

[0010] Preferably, the locking method further includes a chip testing step;

[0011] The chip testing steps include the following steps:

[0012] Steps to obtain the phase difference value: Test the characteristics of multiple chip voltage-controlled oscillators, scan the frequency band and Vctl of the voltage-controlled oscillators, obtain test data, and statistically analyze the test data to find the phase difference x of Vctl between adjacent frequency bands at the same frequency;

[0013] Steps to obtain the temperature relationship: With a fixed frequency band, scan Vctl at different temperatures, and statistically fit the relationship between temperature T and Vctl.

[0014] Vctl=a+bT

[0015] Where a and b represent constants;

[0016] In the current Vctl acquisition step, the clock data recovery unit measures the current temperature of the internally integrated temperature sensor chip. Based on the temperature relationship between temperature T and Vctl in the temperature relationship acquisition step, the current Vctl value is determined and denoted as TVctl.

[0017] Preferably, the locking method further includes the following steps:

[0018] TBctl acquisition steps: Select the software-controlled Vctl with the multiplexer, and record it as SVctl. Set the SVctl value to TVctl. Then scan the frequency band. According to the phase error accumulator, select the frequency band when the phase error accumulator is set to the preset value and record it as TBctl. Set TBctl into clock data recovery.

[0019] SNR calculation steps: The equalizer controls the signal equalization and selects the Vctl generated by the loop to the multiplexer, which is denoted as AVctl. The clock data recovery loop is closed, and then the analog-to-digital converter (ADC) samples the input signal and calculates the signal-to-noise ratio (SNR).

[0020] SNR determination steps: If the SNR is greater than the locking threshold, proceed to the locking determination step; if the SNR is less than or equal to the locking threshold, set the frequency band value sequentially according to the number of loops: TBctl value + first predetermined value, TBctl value - first predetermined value, TBctl value + second predetermined value, and TBctl value - second predetermined value. Repeat the SNR calculation steps. If the SNR is still less than or equal to the threshold after four loops, proceed to the current Vctl acquisition step.

[0021] Preferably, in the locking determination step, LVctl and TVctl are compared. If the difference is less than or equal to x determined in the difference value acquisition step, the locking is completed. If the difference is greater than x, it indicates that there is a deviation in the selection of the frequency band. The correct frequency band value is calculated based on the LVctl value, and the SNR calculation step is repeated.

[0022] Preferably, in the locking determination step, (LVctl-TVctl) / x is rounded down to [(LVctl-TVctl) / x], the frequency band value is configured as the current frequency band value + [(LVctl-TVctl) / x], and the SNR calculation step is repeated.

[0023] According to a clock data recovery locking system and a clock data recovery locking method provided by the present invention, the system includes the following modules:

[0024] Current Vctl acquisition module: acquires the current temperature of the clock data recovery chip CDR, determines the corresponding Vctl value based on the current temperature, denoted as TVctl, where Vctl represents voltage control;

[0025] Locking determination module: The locked Vctl is recorded as LVctl. LVctl and TVctl are compared to determine whether the locking is complete.

[0026] Preferably, the locking system also includes a chip testing module;

[0027] The chip testing module includes the following modules:

[0028] Phase difference acquisition module: Tests the characteristics of multiple chip voltage-controlled oscillators, scans the frequency band and Vctl of the voltage-controlled oscillators, obtains test data, performs statistical analysis on the test data, and calculates the phase difference x of Vctl between adjacent frequency bands at the same frequency;

[0029] Temperature Relationship Acquisition Module: With a fixed frequency band, Vctl is scanned at different temperatures, and the relationship between temperature T and Vctl is statistically fitted.

[0030] Vctl=a+bT

[0031] Where a and b represent constants;

[0032] In the current Vctl acquisition module, the clock data recovery module measures the current temperature of the internally integrated temperature sensor chip. Based on the relationship between temperature T and Vctl in the temperature relationship acquisition module, the current Vctl value is determined and denoted as TVctl.

[0033] Preferably, the locking system further includes the following modules:

[0034] TBctl acquisition module: Select the software-controlled Vctl by the multiplexer, denoted as SVctl, set the SVctl value to TVctl, then scan the frequency band, select the frequency band when the phase error accumulator is at the preset value according to the phase error accumulator, denoted as TBctl, and set TBctl into clock data recovery;

[0035] SNR Calculation Module: The equalizer controls the signal equalization and selects the Vctl generated by the loop to the multiplexer, denoted as AVctl. The clock data recovery loop is closed, and then the analog-to-digital converter (ADC) samples the input signal and calculates the signal-to-noise ratio (SNR).

[0036] SNR Judgment Module: If the SNR is greater than the locking threshold, enter the locking judgment module; if the SNR is less than or equal to the locking threshold, set the frequency band value sequentially according to the number of loops: TBctl value + first predetermined value, TBctl value - first predetermined value, TBctl value + second predetermined value, and TBctl value - second predetermined value, and repeat the SNR calculation module. If the SNR is still less than or equal to the threshold after four loops, enter the current Vctl acquisition module.

[0037] Preferably, in the locking judgment module, LVctl and TVctl are compared. If the difference is less than or equal to x determined in the difference value acquisition module, the locking is completed. If the difference is greater than x, it indicates that there is a deviation in the selection of the frequency band. The correct frequency band value is calculated based on the LVctl value, and the SNR calculation module is repeated.

[0038] Preferably, in the locking judgment module, (LVctl-TVctl) / x is rounded down to [(LVctl-TVctl) / x], the frequency band value is configured as the current frequency band value + [(LVctl-TVctl) / x], and the SNR calculation module is repeated.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The CDR locking time of this invention is relatively fast, which makes the optical module's light output time and main / standby switchover time shorter;

[0041] 2. The CDR of this invention has better locking quality, resulting in better receiving sensitivity of the optical module;

[0042] 3. The CDR locking method of this invention is relatively easy to implement in software. Attached Figure Description

[0043] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0044] Figure 1 This is a diagram of the CDR structure.

[0045] Figure 2 Flowchart for locking CDR;

[0046] Figure 3 The graph shows the relationship between frequency and VCO and Vctl.

[0047] Figure 4 This is a graph showing the relationship between temperature and Vctl. Detailed Implementation

[0048] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0049] Embodiment 1 of the present invention discloses a locking method for a CDR, wherein the CDR structure is as follows: Figure 1As shown: VCO is a voltage-controlled oscillator with two control parts: a frequency band control (Bctl) and a voltage control (Vctl). Bctl is the frequency band control, which is a coarse adjustment, equivalent to selecting a frequency range. The VCO of this invention has 64 frequency bands, with a value range of [0, 63]. Vctl is the voltage control, which is a fine adjustment, equivalent to selecting a certain frequency within this frequency range. The VCO of this invention has 64 Vctl values, with a value range of [0, 63]. Once CDR is locked, the frequency band does not change, while Vctl tracks the input signal, changing with the input signal and temperature.

[0050] The PD (phase detector) is used to compare the phase difference between the input signal (after high-frequency compensation) and the VCO (Voltage Controlled Oscillator) output signal. This phase difference, along with the loop filter, generates the Avctl (Average Volume Transformer). The input signal is externally supplied to the CDR (Cyclic Radiator). The VCO is a voltage-controlled oscillator whose output frequency corresponds to the input control voltage; a given input voltage corresponds to the output sine wave of that frequency.

[0051] The phase error accumulator is a frequency difference indicator; the larger its value, the closer the input signal frequency is to the VCO output frequency. Equalization performs high-frequency compensation on the input signal.

[0052] Figure 1 The direction of the subtraction head in the diagram indicates the signal flow direction within the chip. The storage module stores the data sampled by the ADC into the RAM inside the CDR, and then the software calculates the SNR based on this data; the loop filter and phase detector together generate the AVCTL; the DAC is a digital-to-analog converter that generates the SVCTL. RAM stands for Random Access Memory.

[0053] CDR locking process as follows Figure 2 As shown, it includes the following steps:

[0054] Step 1: Test the characteristics of the CDR VCO chip, testing a sufficient number of chips (e.g., 10 chips). Scan the VCO's frequency band and Vctl at three temperatures. Taking 25 degrees Celsius as an example, the following test results are obtained. Statistically analyze these data, noting the difference x in Vctl between adjacent frequency bands at the same frequency. Figure 3 shown. Three temperatures refer to -40 degrees, 25 degrees and 85 degrees.

[0055] With a fixed frequency band, Vctl is scanned at different temperatures, such as Figure 4 As shown, according to the statistical fitting relationship between temperature T and Vctl: Vctl=a+bT. a and b are both constants. Figure 4 In this context, m is the Vctl value at -40 degrees, n is the Vctl value at 25 degrees, and l is the Vctl value at 85 degrees.

[0056] Step 2: Measure the current temperature of the chip using the temperature sensor integrated inside the CDR. Then, determine the current Vctl value based on the relationship between temperature T and Vctl from Step 1, denoted as TVctl (Tvctl). The temperature sensor is integrated inside the chip, and the temperature can be obtained by reading the register.

[0057] Step 3: Select the software-controlled Vctl (denoted as SVctl, Svctl) on the multiplexer and set its value to TVctl. Then, scan 64 frequency bands. Based on the phase error accumulator, select the frequency band where it reaches its maximum value and denote it as TBctl (Tbctl). This frequency band is closest to the target frequency. Set TBctl into the CDR (VCO). The software-controlled Vctl is obtained by writing to the chip's internal registers. That is, query the phase error accumulator and denote the frequency band corresponding to when this accumulator is at its maximum as TBctl (Tbctl).

[0058] Step 4: The equalization control module equalizes the control signal and simultaneously selects the Vctl generated by the loop (denoted as AVctl) through the multiplexer, closing the CDR loop. Then, the ADC samples the input signal (the input signal after high-frequency compensation) and calculates the SNR. The Vctl generated by the loop is obtained by reading the chip register. ADC stands for Analog-to-Digital Converter. DAC stands for Digital-to-Analog Converter. SNR stands for Signal-to-Noise Ratio.

[0059] Step 5: If the SNR is greater than the set locking threshold at this time, proceed to the next step. Otherwise, set the frequency band value to TBctl value +1 / -1 and +2 / -2 according to the number of loops (i is 4 values ​​+1, -1, +2, -2, i.e., add one, subtract one, add two, subtract two), and repeat step 4. If the SNR is still less than the threshold after four loops, proceed to step 2.

[0060] Step 6: Compare the locked Vctl value (denoted as LVctl) with TVctl. If the difference is within x determined in Step 1, the locking is complete. If the difference is greater than x, it indicates a deviation in the frequency band selection. Calculate the correct frequency band value based on the LVctl value. Round (LVctl-TVctl) / x (denoted as [(LVctl-TVctl) / x]), configure the frequency band value as the current frequency band value + [(LVctl-TVctl) / x], and repeat Step 4. The current frequency band value is TBctl. The locked Vctl value is obtained by reading the register.

[0061] Embodiment 2 of the present invention discloses a locking method for clock data recovery, comprising the following steps:

[0062] The chip testing process includes two steps: obtaining the phase difference value and obtaining the temperature relationship. The phase difference value acquisition step involves testing the characteristics of multiple chip voltage-controlled oscillators (VCOs), scanning the VCO's frequency band and Vctl, obtaining test data, and statistically analyzing the test data to find the phase difference x of Vctl between adjacent frequency bands at the same frequency. The temperature relationship acquisition step involves fixing the frequency band, scanning Vctl at different temperatures, and statistically fitting the relationship between temperature T and Vctl.

[0063] Vctl=a+bT

[0064] Where a and b represent constants.

[0065] Current Vctl acquisition steps: Obtain the current temperature of the clock data recovery chip (CDR), determine the corresponding Vctl value based on the current temperature, denoted as TVctl, where Vctl represents voltage control. The temperature sensor integrated within the clock data recovery chip measures the current temperature of the chip, and determines the current Vctl value based on the relationship between temperature T and Vctl obtained in the temperature relationship acquisition step, denoted as TVctl.

[0066] TBctl acquisition steps: Select the software-controlled Vctl on the multiplexer, denoted as SVctl. Set the SVctl value to TVctl. Then scan the frequency band. Based on the phase error accumulator, select the frequency band where the phase error accumulator reaches its preset value (maximum value), denoted as TBctl. Set TBctl into the clock data recovery chip. In other words, query the phase error accumulator, record the frequency band corresponding to the accumulator's maximum value as TBctl, and set TBctl into the clock data recovery chip.

[0067] SNR calculation steps: The equalizer controls the signal equalization and selects the Vctl generated by the loop to the multiplexer, denoted as AVctl. The clock data recovery loop is closed, and then the analog-to-digital converter (ADC) samples the input signal and calculates the signal-to-noise ratio (SNR).

[0068] SNR determination steps: If the SNR is greater than the locking threshold, proceed to the locking determination step; if the SNR is less than or equal to the locking threshold, set the frequency band value sequentially according to the number of loops: TBctl value + first predetermined value, TBctl value - first predetermined value, TBctl value + second predetermined value, and TBctl value - second predetermined value. Repeat the SNR calculation steps. If the SNR is still less than or equal to the threshold after four loops, proceed to the current Vctl acquisition step.

[0069] Locking determination steps: The locked Vctl is denoted as LVctl. LVctl and TVctl are compared to determine if locking is complete. If the difference between LVctl and TVctl is less than or equal to x determined in the difference acquisition step, locking is complete; if the difference is greater than x, it indicates a deviation in frequency band selection. The correct frequency band value is calculated based on the LVctl value, and the SNR calculation steps are repeated. (LVctl-TVctl) / x is rounded down to [(LVctl-TVctl) / x]. The frequency band value is configured as the current frequency band value + [(LVctl-TVctl) / x], and the SNR calculation steps are repeated.

[0070] This invention also discloses a locking system for a clock data recovery (CDR), employing a locking method based on clock data recovery, comprising the following modules:

[0071] The chip testing module includes a phase difference acquisition module and a temperature relationship acquisition module. The phase difference acquisition module tests the characteristics of multiple chip voltage-controlled oscillators (VCOs), scans the VCO's frequency band and Vctl, obtains test data, and statistically analyzes the data, finding the Vctl difference *x* between adjacent frequency bands at the same frequency. The temperature relationship acquisition module, with a fixed frequency band, scans Vctl at different temperatures and statistically fits the relationship between temperature *T* and Vctl.

[0072] Vctl=a+bT

[0073] Where a and b represent constants.

[0074] The current Vctl acquisition module acquires the current temperature of the clock data recovery chip (CDR) and determines the corresponding Vctl value, denoted as TVctl, based on the current temperature. Vctl represents voltage control. The temperature sensor integrated within the clock data recovery module measures the chip's current temperature and determines the current Vctl value, denoted as TVctl, based on the relationship between temperature T and Vctl in the temperature relationship acquisition module.

[0075] TBctl Acquisition Module: The multiplexer selects the software-controlled Vctl, denoted as SVctl. The SVctl value is set to TVctl. Then, the frequency band is scanned. Based on the phase error accumulator, the frequency band where the phase error accumulator reaches its preset value (maximum value) is selected and denoted as TBctl. TBctl is then set into the clock data recovery module. The phase error accumulator is queried, and the frequency band corresponding to the accumulator's maximum value is denoted as TBctl. TBctl is then set into the clock data recovery chip.

[0076] SNR Calculation Module: The equalizer controls the signal equalization and selects the Vctl generated by the loop through the multiplexer, denoted as AVctl. The clock data recovery loop is closed, and then the analog-to-digital converter (ADC) samples the input signal and calculates the signal-to-noise ratio (SNR).

[0077] SNR Judgment Module: If the SNR is greater than the locking threshold, enter the locking judgment module; if the SNR is less than or equal to the locking threshold, set the frequency band value sequentially according to the number of loops: TBctl value + first predetermined value, TBctl value - first predetermined value, TBctl value + second predetermined value, and TBctl value - second predetermined value, and repeat the SNR calculation module. If the SNR is still less than or equal to the threshold after four loops, enter the current Vctl acquisition module.

[0078] Lock-in determination module: The locked Vctl is denoted as LVctl. LVctl and TVctl are compared to determine if locking is complete. If the difference between LVctl and TVctl is less than or equal to x determined in the difference acquisition module, locking is complete; if the difference is greater than x, it indicates a deviation in frequency band selection. The correct frequency band value is calculated based on the LVctl value, and the SNR calculation module is repeated. The integer part of (LVctl-TVctl) / x is rounded down to [(LVctl-TVctl) / x]. The frequency band value is configured as the current frequency band value + [(LVctl-TVctl) / x], and the SNR calculation module is repeated.

[0079] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0080] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A locking method for clock data recovery, characterized in that, Includes the following steps: Current Vctl acquisition steps: Obtain the current temperature of the clock data recovery chip CDR, determine the corresponding Vctl value based on the current temperature, denoted as TVctl, where Vctl represents voltage control; Locking determination steps: Record the locked Vctl as LVctl, compare LVctl and TVctl to determine whether locking is complete; The locking method also includes a chip testing step; The chip testing steps include the following steps: Steps for obtaining the phase difference value: Test the characteristics of multiple chip voltage-controlled oscillators, scan the frequency band and Vctl of the voltage-controlled oscillators, obtain test data, and statistically analyze the test data to find the phase difference x of Vctl between adjacent frequency bands at the same frequency; Steps for obtaining the temperature relationship: With a fixed frequency band, scan Vctl at different temperatures, and statistically fit the relationship between temperature T and Vctl. Vctl=a+bT Where a and b represent constants; In the current Vctl acquisition step, the clock data recovery unit measures the current temperature of the internally integrated temperature sensor chip. Based on the temperature relationship between temperature T and Vctl in the temperature relationship acquisition step, the current Vctl value is determined and denoted as TVctl. The locking method also includes the following steps: TBctl acquisition steps: Select the software-controlled Vctl with the multiplexer, and record it as SVctl. Set the SVctl value to TVctl. Then scan the frequency band. According to the phase error accumulator, select the frequency band when the phase error accumulator is set to the preset value and record it as TBctl. Set TBctl into clock data recovery. SNR calculation steps: The equalizer controls the signal equalization and selects the Vctl generated by the loop to the multiplexer, which is denoted as AVctl. The clock data recovery loop is closed, and then the analog-to-digital converter (ADC) samples the input signal and calculates the signal-to-noise ratio (SNR). SNR determination steps: If the SNR is greater than the locking threshold, proceed to the locking determination step; if the SNR is less than or equal to the locking threshold, set the frequency band value sequentially according to the number of loops: TBctl value + first predetermined value, TBctl value - first predetermined value, TBctl value + second predetermined value, and TBctl value - second predetermined value. Repeat the SNR calculation steps. If the SNR is still less than or equal to the threshold after four loops, proceed to the current Vctl acquisition step. In the locking determination step, LVctl and TVctl are compared. If the difference is less than or equal to x determined in the phase difference acquisition step, the locking is completed. If the difference is greater than x, it indicates that there is a deviation in the selection of the frequency band. The correct frequency band value is calculated based on the LVctl value, and the SNR calculation step is repeated. In the locking determination step, (LVctl-TVctl) / x is rounded down to [(LVctl-TVctl) / x], the frequency band value is configured as the current frequency band value + [(LVctl-TVctl) / x], and the SNR calculation step is repeated.

2. A locking system for clock data recovery, characterized in that, The locking method for clock data recovery according to claim 1 includes the following modules: Current Vctl acquisition module: acquires the current temperature of the clock data recovery chip CDR, determines the corresponding Vctl value based on the current temperature, denoted as TVctl, where Vctl represents voltage control; Lock detection module: The locked Vctl is recorded as LVctl. LVctl and TVctl are compared to determine whether the locking is complete. The locking system also includes a chip testing module; The chip testing module includes the following modules: Phase difference acquisition module: Tests the characteristics of multiple chip voltage-controlled oscillators, scans the frequency band and Vctl of the voltage-controlled oscillators, obtains test data, performs statistical analysis on the test data, and calculates the phase difference x of Vctl between adjacent frequency bands at the same frequency; Temperature Relationship Acquisition Module: With a fixed frequency band, Vctl is scanned at different temperatures, and the relationship between temperature T and Vctl is statistically fitted. Vctl=a+bT Where a and b represent constants; In the current Vctl acquisition module, the clock data recovery module measures the current temperature of the internally integrated temperature sensor chip, and determines the current Vctl value based on the relationship between temperature T and Vctl in the temperature relationship acquisition module, denoted as TVctl. The locking system also includes the following modules: TBctl acquisition module: Select the software-controlled Vctl by the multiplexer, denoted as SVctl, set the SVctl value to TVctl, then scan the frequency band, select the frequency band when the phase error accumulator is at the preset value according to the phase error accumulator, denoted as TBctl, and set TBctl into clock data recovery; SNR Calculation Module: The equalizer controls the signal equalization and selects the Vctl generated by the loop to the multiplexer, denoted as AVctl. The clock data recovery loop is closed, and then the analog-to-digital converter (ADC) samples the input signal and calculates the signal-to-noise ratio (SNR). SNR Judgment Module: If the SNR is greater than the locking threshold, enter the locking judgment module; if the SNR is less than or equal to the locking threshold, set the frequency band value to TBctl value + first predetermined value, TBctl value - first predetermined value, TBctl value + second predetermined value and TBctl value - second predetermined value in sequence according to the number of loops, and then repeat the SNR calculation module. If the SNR is still less than or equal to the threshold after four loops, enter the current Vctl acquisition module. In the locking judgment module, LVctl and TVctl are compared. If the difference is less than or equal to x determined in the difference value acquisition module, the locking is completed. If the difference is greater than x, it indicates that there is a deviation in the selection of the frequency band. The correct frequency band value is calculated based on the LVctl value, and the SNR calculation module is repeated. In the locking judgment module, (LVctl-TVctl) / x is rounded down to [(LVctl-TVctl) / x], the frequency band value is configured as the current frequency band value + [(LVctl-TVctl) / x], and the SNR calculation module is repeated.

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