Photoelectric conversion device, system

Abstract

To provide a technique capable of suppressing electrical crosstalk occurring between pixel output lines in a photoelectric conversion device that includes a plurality of the pixel out put lines for each row of pixels.SOLUTION: A photoelectric conversion device includes: a semiconductor layer in which pixels are arranged in a matrix, each pixel including a photoelectric conversion part and a transistor used for reading out a signal from the photoelectric conversion part; and multilayer wiring including a first wiring layer, a first interlayer insulation layer, a second wiring layer, a second interlayer insulation layer and a third wiring layer in this order, the multilayer wiring being laminated on the semiconductor layer. The multilayer wiring includes a plurality of output lines for each row of pixels, each output line being used to acquire a signal from each pixel. Each of the output lines includes first wiring arranged in the first wiring layer, second wiring arranged in the second wiring layer, and a connection penetrating through the first interlayer insulation layer to connect between the first wiring and the second wiring, a thickness of the first interlayer insulation layer being less than a thickness of the second interlayer insulation layer.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] In recent years, CMOS image sensors have been widely used in imaging devices such as digital still cameras and digital video cameras. In order to meet the requirements such as an increase in the number of pixels and a higher readout speed, improvements in the wiring structure have been proposed.

[0003] Patent Document 1 describes providing a plurality of pixel output lines for each column of pixels and arranging adjacent pixel output lines in different wiring layers.

[0004] Patent Document 2 discloses a stacked photoelectric conversion device including a pixel chip and a logic chip. In order to prevent crosstalk interference from the logic chip to the pixel chip, it is described that wirings other than the vertical signal lines are laid out in a layer above the vertical signal lines in the pixel chip.

[0005] Patent Document 3 describes, in order to reduce the resistance of the wiring connecting the transfer transistor gates of a plurality of pixels, each wiring connecting the transfer transistor gates is composed of upper and lower two wiring layers, and the upper and lower two wiring layers are connected by a backside via.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] As described in Patent Document 1, by providing multiple pixel output lines for each row of pixels, the number of pixels that can be read simultaneously can be increased, and thus it is expected that the screen readout speed can be increased. Furthermore, in Patent Document 1, since adjacent pixel output lines are placed on different wiring layers, it is possible to suppress the increase in the pixel array pitch, and thus potentially realize an imaging device with a large number of pixels.

[0008] However, if multiple pixel output lines are provided for each row of pixels, and adjacent pixel output lines are placed on different wiring layers, a problem arises in that electrical crosstalk is more likely to occur between the pixel output lines.

[0009] While the technology described in Patent Document 2 is effective in preventing crosstalk interference from logic chips to pixel chips, it is not capable of suppressing crosstalk that occurs between pixel output lines.

[0010] The technology described in Patent Document 3 is a method for reducing the resistance of wiring that connects the transfer transistor gates of multiple pixels, and is not a technology that can suppress crosstalk that occurs between pixel output lines.

[0011] Therefore, in a photoelectric converter in which multiple pixel output lines are provided for each row of pixels, and these multiple pixel output lines are constructed using multiple wiring layers, there was a need for a technology that could suppress electrical crosstalk that occurs between pixel output lines. [Means for solving the problem]

[0012] A first aspect of the present invention is a photoelectric conversion device comprising: a semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit; and a multilayer wiring laminated on the semiconductor layer, including a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer in that order, wherein the multilayer wiring includes a plurality of output lines provided for each row of pixels to extract signals from each of the pixels, and each of the output lines comprises a first wiring arranged in the first wiring layer, a second wiring arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wiring and the second wiring, and the thickness of the first interlayer insulating layer is smaller than the thickness of the second interlayer insulating layer.

[0013] Furthermore, a second aspect of the present invention is a photoelectric conversion device comprising: a semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit; and a multilayer wiring laminated on the semiconductor layer, including a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer in that order, wherein the multilayer wiring includes a plurality of output lines provided for each row of pixels to extract signals from each of the pixels, and control lines provided for each row of pixels to drive the transistor of each of the pixels, and each of the output lines comprises a first wiring arranged in the first wiring layer, a second wiring arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wiring and the second wiring, and the thickness of the first wiring and / or the second wiring is smaller than the thickness of the control lines.

[0014] Furthermore, a third aspect of the present invention is a photoelectric conversion device comprising: a semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit; and a multilayer wiring laminated on the semiconductor layer, including a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer in that order, wherein the multilayer wiring includes a plurality of output lines provided for each row of pixels to extract signals from each of the pixels, and each of the output lines comprises a first wiring arranged in the first wiring layer, a second wiring arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wiring and the second wiring, and the dielectric constant of the first interlayer insulating layer is smaller than the dielectric constant of the second interlayer insulating layer. [Effects of the Invention]

[0015] According to the present invention, in a photoelectric converter in which multiple pixel output lines are provided for each row of pixels, and these multiple pixel output lines are configured using multiple wiring layers, electrical crosstalk occurring between the pixel output lines can be suppressed. [Brief explanation of the drawing]

[0016] [Figure 1] A schematic block diagram of a photoelectric conversion device according to an embodiment. [Figure 2] An equivalent circuit diagram showing a portion of pixel region 102. [Figure 3] Equivalent circuit diagram of a single pixel (pixel 201) extracted from the upper left of Figure 2. [Figure 4] A timing chart to explain how pixels are driven. [Figure 5] A schematic plan view illustrating the configuration of pixel 201. [Figure 6] (a) A schematic cross-sectional view showing the cross-section of the portion indicated by line A-A' in Figure 5 in Embodiment 1. (b) A schematic cross-sectional view showing the cross-section of the portion indicated by line B-B' in Figure 5 in Embodiment 1. [Figure 7]Cross-sectional view schematically showing the cross-section of the portion indicated by the line C-C' in FIG. 5 in Embodiment 1. [Figure 8] (a) Cross-sectional view schematically showing the cross-section of the portion indicated by the line A-A' in FIG. 5 in Embodiment 2. (b) Cross-sectional view schematically showing the cross-section of the portion indicated by the line B-B' in FIG. 5 in Embodiment 2. [Figure 9] Cross-sectional view schematically showing the cross-section of the portion indicated by the line C-C' in FIG. 5 in Embodiment 2. [Figure 10] Cross-sectional view schematically showing the cross-section of the portion indicated by the line A-A' in FIG. 5 in Embodiment 3. [Figure 11] (a) Schematic diagram for explaining an apparatus provided with a photoelectric conversion device according to an embodiment. (b) Diagram showing an example of a photoelectric conversion system related to an in-vehicle camera according to an embodiment. (c) Diagram showing a photoelectric conversion system when imaging the front of a vehicle.

Embodiments for Carrying Out the Invention

[0017] A photoelectric conversion device which is an embodiment of the present invention will be described with reference to the drawings. Note that the embodiments shown below are examples, and for example, regarding the detailed configuration, those skilled in the art can appropriately modify and implement it within the scope not departing from the gist of the present invention. Note that in the drawings referred to in the following description of the embodiments, unless otherwise specified, elements denoted with the same reference numerals have the same functions.

[0018] Also, since the drawings may be schematically represented for the sake of illustration and explanation, they do not necessarily exactly match the actual shape, size, arrangement, etc. In the drawings, when a plurality of the same elements are arranged, the assignment of reference signs and their explanations may be omitted. Note that when explaining the pixel arrangement with reference to the drawings, "row" refers to the horizontal arrangement in the drawing, and "column" refers to the vertical arrangement in the drawing.

[0019] [Embodiment 1] Figure 1 is a schematic block diagram of a photoelectric converter according to this embodiment. The photoelectric converter 101 has a pixel region 102 in which a plurality of pixels including photoelectric converter elements are arranged two-dimensionally on a semiconductor layer (e.g., a silicon substrate), and a peripheral circuit section. The peripheral circuit section includes a vertical scanning circuit 103 for driving the pixels, a horizontal scanning circuit 105 for reading electrical signals from the pixels, and an output section 106 for outputting the electrical signals read from the pixels to the outside. Multilayer wiring is stacked on the semiconductor layer, and the multilayer wiring includes output lines and control lines connected to the pixels. The multilayer wiring has a layer structure in which a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer are stacked from top to bottom.

[0020] Figure 2 is an equivalent circuit diagram showing the circuit configuration of a portion of the pixel region 102. For ease of illustration, Figure 2 shows pixels in 3 rows and 2 columns, along with their wiring, from the pixel region 102 in which numerous pixels 201 are arranged in a two-dimensional matrix. In the example in Figure 2, three output lines 17-1, 17-2, and 17-3 are provided for each column of the matrix-arranged pixels. However, the number of output lines is not limited to this; multiple output lines are required for each column of pixels. The internal circuit configuration of each pixel is basically the same, but it is connected to appropriate control signal lines and output lines depending on its position in the two-dimensional arrangement. For example, for control signal lines extending in the row direction, pixels arranged in the same row are wired together. In the figure, the reference code of each control signal line is appended with (n) to indicate the nth row, (n+1) to indicate the n+1th row, and (n+2) to indicate the n+2nd row. For the sake of clarity, the reference symbols pSEL, pRES, pFDINC, pTX, etc., may refer to either a control signal line or the control signal transmitted on that control signal line.

[0021] Each pixel is connected to one of the output lines 17-1, 17-2, or 17-3, depending on its position. Although not shown in the equivalent circuit diagram Figure 2, by attaching a color filter to the photoelectric conversion section of each pixel, the color of light to be photoelectrically converted can be set for each pixel. A Bayer array is preferred as a method for arranging the color filters, but other arrangement methods may also be used. For example, the output lines can be configured such that output line 17-1 is for reading from red pixels, output line 17-2 is for reading from green pixels, and output line 17-3 is for reading from blue pixels.

[0022] Figure 3 is an equivalent circuit diagram of a single pixel (pixel 201) extracted from the upper left of Figure 2. Pixel 201 includes a photoelectric conversion unit 1, a floating diffusion unit 2, a transfer unit 11, a capacitance switching unit 12, a reset unit 13, an amplification unit 14, and a row selection unit 15, and is connected to a power supply 16. Pixel 201 is formed on a semiconductor layer, such as a silicon substrate.

[0023] The photoelectric conversion unit 1 is composed of a photoelectric conversion element such as a photodiode, but any element capable of photoelectric conversion is acceptable, and the method is not particularly limited. The photoelectric conversion unit 1 generates a signal charge corresponding to the amount of light received.

[0024] The transfer unit 11 is a toggle switch (transistor) that can turn the conductivity between the photoelectric conversion unit 1 and the floating diffusion unit 2 on and off. For example, it is turned on when transferring the signal charge generated in the photoelectric conversion unit 1 to the floating diffusion unit 2. The transfer unit 11 is driven by a transfer unit drive pulse pTX(n).

[0025] The floating diffusion unit 2 temporarily holds the signal charge transferred from the photoelectric conversion unit 1 via the transfer unit 11, and at the same time functions as a charge-voltage conversion unit that converts the held signal charge into a voltage signal.

[0026] The reset unit 13 and the capacitance switching unit 12 are switches (transistors) that are turned on / off by control signals, the reset unit drive pulse pRES(n) and the floating diffusion capacitance switching pulse pFDINC(n), respectively. For example, when resetting the charge of the floating diffusion unit 2, the reset unit 13 and the capacitance switching unit 12 are turned on simultaneously, and the floating diffusion unit 2 is connected to the power supply 16. Also, by turning on the capacitance switching unit 12 while the reset unit 13 is off, the gate capacitance of the capacitance switching unit can be added to the storage capacitance of the floating diffusion unit 2. The amplification unit 14 amplifies the voltage signal converted by the floating diffusion unit 2 and outputs it as a pixel signal.

[0027] The row selection unit 15 is an on / off switch (transistor) driven by the row selection drive pulse pSEL(n), which outputs the pixel signal amplified by the amplification unit 14 to one of the output lines 17-1, 17-2, or 17-3. In the pixel 201 illustrated in Figure 3, the row selection unit 15 is connected to output line 17-1 of the three output lines, so the pixel signal is output to output line 17-1. Although the row selection unit 15 enables selective reading of rows from the pixel matrix, it can be omitted if this is not necessary.

[0028] Next, the pixel driving method will be explained with reference to Figure 4. Figure 4 illustrates a timing chart from reset to output of the pixel signal in the case of low brightness (low amount of received light). The horizontal axis represents time, and the vertical axis represents the voltage level (on / off) of each control signal. From top to bottom in the figure, the graphs of the row selection drive pulse pSEL, reset unit drive pulse pRES, floating diffusion capacitance switching pulse pFDINC, and transfer unit drive pulse pTX are shown.

[0029] First, at time t1, the capacitance switching unit 12, reset unit 13, and row selection unit 15 are turned on. This selects the pixel in question and resets the charge of the floating diffusion unit 2. The photoelectric conversion unit 1 generates and stores signal charge.

[0030] Next, at time t2, the capacitance switching unit 12 is turned off. This reduces the capacitance of the floating diffusion unit 2 to match the low brightness, thereby reducing noise during signal readout. A reset level signal for the CDS is output to the output line 17 via the amplification unit 14 and the row selection unit 15. The photoelectric conversion unit 1 generates and stores signal charge. Next, at time t3, the transfer unit 11 is turned on, and the signal charge accumulated in the photoelectric conversion unit 1 is transferred to the floating diffusion unit 2.

[0031] Then, at time t4, the transfer unit 11 is turned off, ending the transfer of signal charge to the floating diffusion unit 2. The amplification unit 14 amplifies the voltage level of the floating diffusion unit 2, and the amplified voltage signal is output to the output line as a pixel signal via the row selection unit 15.

[0032] Next, the configuration of the output line and control signal line in Embodiment 1 will be described. Figure 5 is a schematic plan view illustrating the configuration of pixel 201. In this figure, for illustrative purposes, the region where elements such as the photoelectric conversion unit 1 and transistors are located is shown as a rectangle. However, this does not necessarily mean that the shape of the elements is rectangular, but rather that the elements are located in this region. For example, a photodiode is located in the photoelectric conversion unit 1, and the reset unit 13, amplification unit 14, row selection unit 15, etc. are located in the pixel transistor region 401.

[0033] Although not necessarily explicit in the plan view of Figure 5, each output line (in this example, output lines 17-1, 17-2, and 17-3 arranged for each pixel row) is composed of multiple wiring layers arranged above and below each other, separated by an interlayer insulating layer. The upper and lower wiring layers are connected by connection parts 402 (e.g., connection vias). In other words, each output line is configured as a backed wiring. The connection parts 402 are preferably distributed at predetermined intervals (e.g., the pixel pitch in the row direction) in a plan view. This configuration reduces the resistance of the output lines, and even if a break occurs in any of the wiring layers, the pixel signal can still be output from the pixel 201 to the horizontal scanning circuit 105.

[0034] Figure 6(a) is a schematic cross-sectional view of the portion indicated by the line A-A' in Figure 5, that is, the portion where the control signal line pRES(n), which transmits the reset unit drive pulse, intersects with the output lines 17-1, 17-2, and 17-3. The portion where other control lines connected to pixels intersect with the output lines 17-1, 17-2, and 17-3 also has a cross-sectional structure similar to that of Figure 6(a). These other control lines include, for example, the control signal line pFDINC, which transmits the floating diffusion capacitance switching pulse, the control signal line pTX, which transmits the transfer unit drive pulse, and the control signal line pSEL, which transmits the row selection drive pulse.

[0035] The output line 17-1 shown in Figure 5 is composed of two layers: the upper wiring 17-1U and the lower wiring 17-1L shown in Figure 6(a). Similarly, the output line 17-2 shown in Figure 5 is composed of two layers: the upper wiring 17-2U and the lower wiring 17-2L shown in Figure 6(a), and the output line 17-3 shown in Figure 5 is composed of two layers: the upper wiring 17-3U and the lower wiring 17-3L shown in Figure 6(a). The upper and lower wiring of each output line are formed on the same wiring layer. The upper wiring of each output line is formed on the first wiring layer, and the lower wiring is formed on the second wiring layer. Although this example shows an output line composed of two layers of upper and lower wiring, the number of wiring layers constituting the output line is not limited to this, and for example, there may be three or more layers.

[0036] To reduce crosstalk, it is preferable that the upper wiring (first wiring) and lower wiring (second wiring) of each output line have substantially the same width when viewed from above, and are arranged to overlap vertically so that their outer edges substantially overlap. The cross-sectional view in Figure 6(a) illustrates this case. However, the upper wiring and lower wiring of each output line do not necessarily have to have the same width when viewed from above. Also, the way the upper wiring (first wiring) and lower wiring (second wiring) overlap when viewed from above may be such that one encompasses the other, or that only a portion of each overlaps. Vias (connection parts) connecting the upper wiring (first wiring) and lower wiring (second wiring) can be provided in the overlapping portion. Note that "viewed from above" in the above description may be rephrased as the appearance when viewed from a direction perpendicular to the main surface of the semiconductor layer. Furthermore, "substantially the same" and "substantially overlapping" mean excluding unavoidable factors such as manufacturing errors.

[0037] In the illustrated example, the upper and lower wiring of each output line have a width W and a height (thickness) H. Each output line is arranged at a distance S in the row direction. A first interlayer insulating layer with a thickness T1 is formed between the upper and lower wiring of each output line. Below the lower wiring of each output line, with a second interlayer insulating layer with a thickness T2 in between, a control signal line pRES(n) that transmits the reset unit drive pulse is arranged along the row direction.

[0038] Now, let's consider the parasitic capacitance of output line 17-2. If we let C1 be the parasitic capacitance between adjacent output lines in the same layer, and C2 be the parasitic capacitance between output line 17-2 and control signal line pRES(n), then the parasitic capacitance Ca of output line 17-2 is Ca = 4 × C1 + C2. Here, if we consider the parasitic capacitance C2 as the capacitance of a parallel plate with width W and thickness T2, then as T2 increases, C2 can be reduced. Similarly, the parasitic capacitance between output line 17-1 and control signal line pRES(n), and between output line 17-3 and control signal line pRES(n) can also be reduced as T2 increases.

[0039] Furthermore, the same principle applies to points where different control lines and output lines intersect in a plan view. Also, although the control line is positioned below the output line in this example, the same considerations apply when the control line is positioned above the output line.

[0040] Figure 6(b) is a cross-sectional view taken along the row direction of the portion indicated by the line B-B' in Figure 5, that is, the portion where the upper wiring 17-2U and the lower wiring 17-2L, which constitute the output line 17-2, are connected by the connector 402 (via).

[0041] Here, if we let C1' be the parasitic capacitance between output line 17-2, which is connected by connection section 402 (connection via), and adjacent output lines in the same layer, then C1' can be expressed by equation (1). Note that ε is the dielectric constant of the interlayer insulating film.

number

[0042] Here, since C1' is monotonically increasing in the range T1>0, C1' can be reduced by reducing the thickness T1 of the first interlayer insulating layer between the two wiring layers that make up the output line. The same applies when the output line is composed of three or more layers. To elaborate, in Figure 6(b), the wiring thickness H(x) in the range where coordinate X is 0 ≤ X ≤ S is expressed by equation (2).

number

[0043] If ΔC is the smallest volume per unit length of thickness Δx, then ΔC is expressed by equation (3).

number

[0044] If we consider C1' to be the equivalent capacitance of several small capacitances ΔC connected in series, then the relationship in equation (4) holds.

number

[0045] Now let's consider how C1' changes with respect to T1. Differentiating C1' with respect to T1 gives us equation (5).

number

[0046] Now, let the denominator of equation (5) be f(T1), and differentiating f(T1) with respect to T1 gives us equation (6).

number

[0047] Since T1 > 0, equation (6) is always positive. Also, since f(0) = 0, f(T1) is always positive and monotonically increasing in the range T1 > 0. Therefore, equation (5) is always positive in the range T1 > 0, and C1' is monotonically increasing in the range T1 > 0. In other words, by making T1 as small as possible, it is possible to make C1' small.

[0048] Figure 7 is a cross-sectional view taken along the row direction of the portion indicated by the line C-C' in Figure 5, that is, the portion where the upper and lower wiring constituting output line 17-1 and output line 17-3 are connected by a connection portion 402 (via) that penetrates the first interlayer insulating layer.

[0049] Here, the parasitic capacitance between an output line connected by connection section 402 (connection via) and an adjacent output line on the same layer is represented by C1' in equation (1). Therefore, as described above, C1' can be reduced by thinning the thickness T1 of the interlayer insulating film between the two wiring layers that constitute the output line. The same applies when the output line is composed of three or more layers.

[0050] From the above, if the thickness T1 of the first interlayer insulating layer between the upper and lower wirings (which may be three or more layers) constituting each output line is reduced, and the thickness T2 of the second interlayer insulating layer between the control line formed in a layer different from the output line and the output line is increased, it becomes possible to reduce the parasitic capacitance of the output line.

[0051] In the present embodiment, a configuration is used in which the thickness T1 of the first interlayer insulating layer separating the upper wiring and the lower wiring of each output line is smaller than the thickness T2 of the second interlayer insulating layer separating each output line and the control line, that is, T1 < T2.

[0052] According to the present embodiment having such a configuration, since the parasitic capacitance between adjacent output lines can be reduced, electrical crosstalk generated between the output lines can be suppressed. For example, when output line 17-1 is configured for reading from a red pixel, output line 17-2 is configured for reading from a green pixel, and output line 17-3 is configured for reading from a blue pixel, it is possible to suppress degradation of the read image due to color mixing caused by crosstalk.

[0053] Furthermore, according to the present embodiment, compared with the case where the thickness T1 and the thickness T2 are equal, the capacitance between the output line and the control line can be reduced without changing the resistance of the output line. Therefore, the settling of the control signal (for example, the reset unit drive signal) and the pixel output signal is accelerated, and the readout speed of the pixel signal can be increased.

[0054] [Embodiment 2] The photoelectric conversion device according to Embodiment 2 will be described. Regarding matters common to Embodiment 1, the description will be simplified or omitted. Regarding the matters described with reference to FIGS. 1 to 5 in Embodiment 1, the same applies to the present embodiment.

[0055] FIG. 8(a) is a cross-sectional view schematically showing a cross-section of a portion indicated by the line A-A' in FIG. 5, that is, a portion where the control signal line pRES(n) for transmitting the reset unit drive pulse intersects the output lines 17-1, 17-2, and 17-3. Regarding the content common to that described with reference to FIG. 6(a) for Embodiment 1, the description will be omitted.

[0056] FIG. 8(b) is a cross-sectional view taken along the row direction of a portion indicated by line B-B' in FIG. 5, that is, a portion where the upper wiring 17-2U and the lower wiring 17-2L constituting the output line 17-2 are connected by a connection portion 402 (connection via). Regarding the content common to that described with reference to FIG. 6(b) in Embodiment 1, it is omitted.

[0057] FIG. 9 is a cross-sectional view taken along the row direction of a portion indicated by line C-C' in FIG. 5, that is, a portion where the respective upper wirings and lower wirings constituting the output line 17-1 and the output line 17-3 are connected by a connection portion 402 (connection via). Regarding the content common to that described with reference to FIG. 7 in Embodiment 1, it is omitted.

[0058] From the above-described formula (1), it can be understood that the parasitic capacitance C1' between adjacent output lines in the same layer as the output line connected by the connection portion 402 (connection via) can be reduced by decreasing H, which is the height (thickness) of the output line.

[0059] In the present embodiment, as shown in FIG. 8(a), a configuration is adopted in which H, which is the height (thickness) of the output line, is smaller than HS, which is the height (thickness) of the control line, that is, H < HS. In the illustrated example, as a desirable embodiment, the wiring heights (thicknesses) of the upper wiring (first wiring) and the lower wiring (second wiring) constituting each output line are made equal, but the thicknesses of the upper and lower wirings do not necessarily have to be equal. Also, a configuration may be adopted in which either one of the upper wiring and the lower wiring and the control line satisfy H < HS. Further, even when each output line is formed of three or more layers of underlayer wirings, the heights (thicknesses) of all the wirings do not necessarily have to be equal, and one or more wirings and the control line may be configured to satisfy H < HS.

[0060] According to this embodiment with the above configuration, parasitic capacitance between adjacent output lines can be reduced, thereby suppressing electrical crosstalk between output lines. For example, when output line 17-1 is configured for reading from red pixels, output line 17-2 for reading from green pixels, and output line 17-3 for reading from blue pixels, it is possible to suppress degradation of the readout image due to color mixing caused by crosstalk.

[0061] [Embodiment 3] A photoelectric conversion device according to Embodiment 3 will now be described. Note that matters common to Embodiment 1 will be simplified or omitted from the explanation. Matters described in Embodiment 1 with reference to Figures 1 to 7 are also applicable to this embodiment.

[0062] From the aforementioned equation (1), it can be seen that the parasitic capacitance C1' between adjacent output lines in the same layer as the output line connected by connection part 402 (connection via) can be reduced by decreasing the dielectric constant ε of the interlayer insulating layer.

[0063] In this embodiment, a configuration is used in which the dielectric constant of the first interlayer insulating layer, which is placed between the upper wiring (first wiring) and the lower wiring (second wiring) that constitute the output line, is smaller than the dielectric constant of the second interlayer insulating layer, which is placed between the output line and the control signal line.

[0064] Figure 10 is a schematic cross-sectional view of the portion indicated by the line A-A' in Figure 5, that is, the portion where the control signal line pRES(n) that transmits the reset unit drive pulse intersects with the output lines 17-1, 17-2, and 17-3. In this embodiment, a configuration is used in which the dielectric constant ε1 of the first interlayer insulating layer 701, which is placed between the upper and lower wiring constituting the output line, is smaller than the dielectric constant ε2 of the second interlayer insulating layer 702, which is placed between the output line and the control signal line, i.e., ε1 < ε2. Such a configuration can be manufactured by changing the material type, material composition, film deposition conditions, etc., of the first interlayer insulating layer 701 and the second interlayer insulating layer 702. Since the same signal is propagated between the upper and lower wiring constituting the output line, the dielectric breakdown voltage of the first interlayer insulating layer 701 may be small, so even low dielectric constant materials with relatively small dielectric breakdown voltages that cannot be used between wirings with large voltage differences can be used.

[0065] According to this embodiment with the above configuration, parasitic capacitance between adjacent output lines can be reduced, thereby suppressing electrical crosstalk between output lines. For example, when output line 17-1 is configured for reading from red pixels, output line 17-2 for reading from green pixels, and output line 17-3 for reading from blue pixels, it is possible to suppress degradation of the readout image due to color mixing caused by crosstalk.

[0066] Furthermore, according to this embodiment, the capacitance between the output line and the control line can be reduced without changing the resistance of the output line, compared to the case where ε1 and ε2 are equal. As a result, the static settlement of the control signal (e.g., reset unit drive signal) and the pixel output signal is accelerated, and the readout speed of the pixel signal can be increased.

[0067] [Embodiment 4] As Embodiment 4, a system equipped with the photoelectric conversion device according to the present invention will be described. Figure 11(a) is a schematic diagram illustrating a device 9191 equipped with a semiconductor device 930. The photoelectric conversion device of each embodiment described above can be used as the semiconductor device 930. The device 9191 equipped with the semiconductor device 930 will be described in detail.

[0068] The semiconductor device 930 includes a semiconductor device 910 (photoelectric converter) in which multiple pixel output lines are provided for each row of pixels 900 arranged on the light-receiving section 901 of the semiconductor substrate 902, and these multiple pixel output lines are constructed using multiple wiring layers. In addition to the semiconductor device 910, the semiconductor device 930 may also include a package 920 that houses the semiconductor device 910. The package 920 may include a substrate on which the semiconductor device 910 is fixed, and a cover made of glass or the like that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the substrate and terminals provided on the semiconductor device 910.

[0069] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, shutter, or mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0070] The processing unit 960 processes the signals output from the semiconductor device 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0071] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. The device 9191 displays signals output from the semiconductor device 930 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the semiconductor device 930. The mechanical device 990 may be controlled based on signals output from the semiconductor device 930.

[0072] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the semiconductor device 930 for vibration damping.

[0073] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft. The mechanical device 990 in the transport device may be used as a mobile device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) through its imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, an office machine such as a copier, or an industrial machine such as a robot.

[0074] According to the embodiments described above, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. Increasing value here means at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0075] Therefore, by using the semiconductor device 930 according to this embodiment in the device 9191, the value of the device can also be improved. For example, by mounting the semiconductor device 930 on a transport device, excellent performance can be obtained when taking external images of the transport device or measuring the external environment. Therefore, when manufacturing and selling transport devices, deciding to mount the semiconductor device according to this embodiment on the transport device is advantageous in improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained from the semiconductor device to assist in driving and / or perform autonomous driving. Furthermore, its implementation in vehicles, ships, aircraft, etc., is not limited to equipment used for transport purposes, but can also be suitably implemented in drones that perform aerial photography for various purposes, such as inspecting buildings and agricultural facilities, and monitoring natural phenomena. Furthermore, the photoelectric conversion system and mobile body of this embodiment will be described with reference to Figures 11(b) and 11(c).

[0076] Figure 11(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device described in any of the embodiments described above. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), etc.

[0077] The photoelectric conversion system 8 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to the control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to the warning device 830, which issues a warning to the driver based on the judgment result of the collision judgment unit 804. For example, if the collision judgment result of the collision judgment unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0078] In this embodiment, the photoelectric conversion system 8 images the area around the vehicle, for example, in front of or behind it. Figure 11(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement. The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0079] [Other embodiments] It should be noted that the present invention is not limited to the embodiments and examples described above, and many modifications are possible within the technical concept of the present invention. For example, different embodiments described above can be combined and implemented. That is, any two or three of the following can be combined and implemented: setting the thickness of the interlayer insulating film as in Embodiment 1, setting the thickness of the wiring layer as in Embodiment 2, and setting the dielectric constant of the interlayer insulating layer as in Embodiment 3.

[0080] Furthermore, the photoelectric conversion device to which the present invention can be applied is not limited to a specific form; for example, the light receiving unit may be either a front-illuminated type or a back-illuminated type. Alternatively, a stacked type photoelectric conversion device may be used, in which a semiconductor chip equipped with a light receiving unit and a semiconductor chip equipped with a logic unit are stacked. The image signal output from the photoelectric conversion device may be an analog signal or a digital signal.

[0081] This embodiment includes the following configuration. [Configuration 1] A semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit, A multilayer wiring comprising a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer, stacked on the semiconductor layer, The multilayer wiring includes multiple output lines provided for each row of pixels in order to extract a signal from each of the pixels. Each of the output lines comprises a first wire arranged in the first wiring layer, a second wire arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wire and the second wire. The thickness of the first interlayer insulating layer is less than the thickness of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features. [Configuration 2] A semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit, A multilayer wiring comprising a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer, stacked on the semiconductor layer, The multilayer wiring includes multiple output lines provided for each row of pixels to extract a signal from each of the pixels, and control lines provided for each row of pixels to drive the transistor of each of the pixels. Each of the output lines comprises a first wire arranged in the first wiring layer, a second wire arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wire and the second wire. The thickness of the first wiring and / or the second wiring is less than the thickness of the control line. A photoelectric conversion device characterized by the following features. [Configuration 3] A semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit, A multilayer wiring comprising a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer, stacked on the semiconductor layer, The multilayer wiring includes multiple output lines provided for each row of pixels in order to extract a signal from each of the pixels. Each of the output lines comprises a first wire arranged in the first wiring layer, a second wire arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wire and the second wire. The dielectric constant of the first interlayer insulating layer is smaller than the dielectric constant of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features. [Structure 4] In the photoelectric conversion device described in configuration 2 or 3, The thickness of the first interlayer insulating layer is less than the thickness of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features. [Composition 5] In the photoelectric conversion device described in configuration 1 or 3, The aforementioned multilayer wiring includes control lines, The thickness of the first wiring and / or the second wiring is less than the thickness of the control line. A photoelectric conversion device characterized by the following features. [Composition 6] In the photoelectric conversion device described in configuration 1 or 2, The dielectric constant of the first interlayer insulating layer is smaller than the dielectric constant of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features. [Composition 7] In the photoelectric conversion device described in any one of configurations 1 to 6, When viewed through from a direction perpendicular to the main surface of the semiconductor layer, the first wiring and the second wiring overlap in at least a portion of their respective areas. A photoelectric conversion device characterized by the following features. [Structure 8] In the photoelectric conversion device described in Configuration 7, The first wiring and the second wiring are substantially of equal width. When viewed from a direction perpendicular to the main surface of the semiconductor layer, the outer edge of the first wiring and the outer edge of the second wiring substantially overlap. A photoelectric conversion device characterized by the following features. [Composition 9] In the photoelectric conversion device described in configuration 7 or 8, When viewed from a direction perpendicular to the main surface of the semiconductor layer, the connection portion is located in the area where the first wiring and the second wiring overlap. A photoelectric conversion device characterized by the following features. [Configuration 10] In the photoelectric conversion device described in any one of items 1 to 9, The aforementioned connecting portions are provided in multiple locations along the direction of the pixel rows, at predetermined intervals. A photoelectric conversion device characterized by the following features. [Composition 11] A system characterized by comprising a photoelectric converter according to any one of configurations 1 to 10, and a processing device for processing image data output from the photoelectric converter. [Composition 12] In the photoelectric conversion device described in any one of configurations 1 to 10, The multilayer wiring includes control lines provided for each row of pixels to drive the transistors of each pixel, The control line is arranged in the third wiring layer. A photoelectric conversion device characterized by the following features. [Explanation of Symbols]

[0082] 1... Photoelectric conversion section / 2... Floating diffusion section / 11... Transfer section / 12... Capacitance switching section / 13... Reset section / 14... Amplification section / 15... Row selection section / 16... Power supply / 17-1, 17-2, 17-3... Output lines / 17-1U, 17-2U, 17-3U... Upper wiring / 17-1L, 17-2L, 17-3L... Lower wiring / 10 1...Photoelectric converter / 102...Pixel area / 103...Vertical scanning circuit / 105...Horizontal scanning circuit / 106...Output section / 201...Pixel / 401...Pixel transistor area / 402...Connection section / 701...First interlayer insulating layer / 702...Second interlayer insulating layer / 900...Pixel / 901...Light receiving section / 902...Semiconductor substrate / 930...Semiconductor device

Claims

1. A semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit, A multilayer wiring comprising a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer, stacked on the semiconductor layer, The multilayer wiring includes multiple output lines provided for each row of pixels in order to extract a signal from each of the pixels. Each of the output lines comprises a first wire arranged in the first wiring layer, a second wire arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wire and the second wire. The thickness of the first interlayer insulating layer is smaller than the thickness of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features.

2. A semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit, A multilayer wiring comprising a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer, stacked on the semiconductor layer, The multilayer wiring includes multiple output lines provided for each row of pixels to extract a signal from each of the pixels, and control lines provided for each row of pixels to drive the transistor of each of the pixels. Each of the output lines comprises a first wire arranged in the first wiring layer, a second wire arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wire and the second wire. The thickness of the first wiring and / or the second wiring is less than the thickness of the control line. A photoelectric conversion device characterized by the following features.

3. A semiconductor layer in which pixels are arranged in a matrix, each comprising a photoelectric conversion unit and a transistor used for reading signals from the photoelectric conversion unit, A multilayer wiring comprising a first wiring layer, a first interlayer insulating layer, a second wiring layer, a second interlayer insulating layer, and a third wiring layer, stacked on the semiconductor layer, The multilayer wiring includes multiple output lines provided for each row of pixels in order to extract a signal from each of the pixels. Each of the output lines comprises a first wire arranged in the first wiring layer, a second wire arranged in the second wiring layer, and a connection portion that penetrates the first interlayer insulating layer and connects the first wire and the second wire. The dielectric constant of the first interlayer insulating layer is smaller than the dielectric constant of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features.

4. In the photoelectric conversion device according to claim 2 or 3, The thickness of the first interlayer insulating layer is smaller than the thickness of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features.

5. In the photoelectric conversion device according to claim 1 or 3, The aforementioned multilayer wiring includes control lines, The thickness of the first wiring and / or the second wiring is less than the thickness of the control line. A photoelectric conversion device characterized by the following features.

6. In the photoelectric conversion device according to claim 1 or 2, The dielectric constant of the first interlayer insulating layer is smaller than the dielectric constant of the second interlayer insulating layer. A photoelectric conversion device characterized by the following features.

7. In the photoelectric conversion device according to any one of claims 1 to 3, When viewed through from a direction perpendicular to the main surface of the semiconductor layer, the first wiring and the second wiring overlap in at least a portion. A photoelectric conversion device characterized by the following features.

8. In the photoelectric conversion device according to claim 7, The first wiring and the second wiring are substantially of equal width. When viewed from a direction perpendicular to the main surface of the semiconductor layer, the outer edge of the first wiring and the outer edge of the second wiring substantially overlap. A photoelectric conversion device characterized by the following features.

9. In the photoelectric conversion device according to claim 7, When viewed from a direction perpendicular to the main surface of the semiconductor layer, the connection portion is located in the area where the first wiring and the second wiring overlap. A photoelectric conversion device characterized by the following features.

10. In the photoelectric conversion device according to any one of claims 1 to 3, The aforementioned connecting portions are provided in multiple locations along the direction of the pixel rows, at predetermined intervals. A photoelectric conversion device characterized by the following features.

11. A system comprising a photoelectric converter according to any one of claims 1 to 3, and a processing device for processing image data output from the photoelectric converter.

12. In the photoelectric conversion device according to claim 1, The multilayer wiring includes control lines provided for each row of pixels to drive the transistors of each pixel, The control line is arranged in the third wiring layer. A photoelectric conversion device characterized by the following features.

13. In the photoelectric conversion device according to claim 2, The control line is arranged in the third wiring layer. A photoelectric conversion device characterized by the following features.

14. In the photoelectric conversion device according to claim 3, The multilayer wiring includes control lines provided for each row of pixels to drive the transistors of each pixel, The control line is arranged in the third wiring layer. A photoelectric conversion device characterized by the following features.

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