Photodetection device and method for manufacturing photodetection device

Abstract

To provide a photodetection device having improved detection accuracy while suppressing manufacturing costs.SOLUTION: A photodetection device 1 includes a semiconductor substrate 10. In the semiconductor substrate 10, an APD 11 and a temperature compensation diode 12 are formed spaced apart from each other when viewed from a direction perpendicular to a principal surface 10a. The semiconductor substrate 10 includes a peripheral carrier absorption portion 13 that surrounds the APD 11 when viewed from a direction perpendicular to the principal surface 10a and absorbs carriers located around the APD 11. A part of the peripheral carrier absorption portion 13 is located between the APD 11 and the temperature compensation diode 12 when viewed from a direction perpendicular to the principal surface 10a.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a light detection device and a method for manufacturing a light detection device. [Background technology]

[0002] A configuration is known in which a bias voltage applied to an avalanche photodiode is controlled to perform stable light detection against temperature (for example, Patent Document 1). In Patent Document 1, a voltage according to the breakdown voltage of a temperature compensation diode is applied to the avalanche photodiode as a bias voltage. Hereinafter, in this specification, "avalanche photodiode" will be referred to as "APD." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 07-27607 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, in order to realize temperature compensation for the gain of the APD for signal detection, an APD having temperature characteristics equivalent to that of the APD for signal detection is used as the above-mentioned temperature compensation diode. The closer the temperature characteristics of the APD for signal detection and the APD as the temperature compensation diode are, the more accurate the temperature compensation of the photodetector can be. However, in order to obtain the desired temperature compensation accuracy, it was necessary to carry out an inspection to select and combine APDs having the desired temperature characteristics for the relationship between the gain and the bias voltage. For this reason, it was difficult to reduce the manufacturing cost of a photodetector equipped with two APDs having the desired temperature characteristics.

[0005] Photodetectors are used for various purposes. For this reason, it is necessary to ensure the detection accuracy of photodetectors in the environment according to each application. For example, when a photodetector is used for in-vehicle applications, it is necessary to ensure the detection accuracy in a high-temperature environment of 100°C or higher. However, in such a high-temperature environment, carriers are generated by heat in the semiconductor substrate that constitutes the APD. If the generated carriers reach the APD, photon shot noise occurs in the detection result of the APD.

[0006] An object of one aspect of the present invention is to provide a photodetector having improved detection accuracy while keeping manufacturing costs down.Another object of the present invention is to provide a method for manufacturing a photodetector having improved detection accuracy while keeping manufacturing costs down.Another object of the present invention is to provide a photodetector having improved detection accuracy while keeping manufacturing costs down. [Means for solving the problem]

[0007] In a photodetector according to one aspect of the present invention, a voltage corresponding to a breakdown voltage applied to a temperature compensating diode is applied as a bias voltage to the APD, thereby performing temperature compensation of the multiplication factor of the APD. The photodetector includes a semiconductor substrate. The semiconductor substrate has a first main surface and a second main surface opposed to each other. The APD and the temperature compensating diode are formed on the semiconductor substrate and spaced apart from each other when viewed from a direction perpendicular to the first main surface. The semiconductor substrate has a peripheral carrier absorption portion that absorbs carriers located in the periphery. The peripheral carrier absorption portion surrounds the APD when viewed from a direction perpendicular to the first main surface. A portion of the peripheral carrier absorption portion is located between the APD and the temperature compensating diode when viewed from a direction perpendicular to the first main surface.

[0008] In one embodiment, the peripheral carrier absorption portion surrounds the APD when viewed from a direction perpendicular to the first main surface, which prevents carriers generated by heat in the semiconductor substrate in a high-temperature environment from reaching the APD, thereby improving detection accuracy.

[0009] In one of the above embodiments, the APD and the temperature compensation diode are formed on the same semiconductor substrate. In this case, the temperature compensation diode and the APD having the same temperature characteristics with respect to the gain and bias voltage can be formed more easily and with higher accuracy than when the temperature compensation diode and the APD are formed on different semiconductor substrates. Therefore, temperature compensation for the gain can be realized while keeping manufacturing costs down.

[0010] When a breakdown voltage is applied to the temperature compensation diode, the temperature compensation diode may emit light. When the temperature compensation diode emits light, carriers are generated in the semiconductor substrate due to the light emitted by the temperature compensation diode. Therefore, when the temperature compensation diode and the APD are formed on the same semiconductor substrate, the carriers may affect the detection result of the APD.

[0011] In one embodiment, the peripheral carrier absorption section is located between the APD and the temperature compensation diode. Therefore, carriers generated by the light emission of the temperature compensation diode are absorbed by the peripheral carrier absorption section before reaching the APD. As a result, carriers caused by the temperature compensation diode are prevented from reaching the APD, and the detection accuracy is further improved.

[0012] Therefore, in the above-described photodetector, temperature compensation for the multiplication factor is realized while keeping manufacturing costs down, and the detection accuracy is improved.

[0013] In the above aspect, an avalanche photodiode array including an avalanche photodiode may be formed on the first main surface side of the semiconductor substrate. The peripheral carrier absorption section may surround the avalanche photodiode array when viewed from a direction perpendicular to the first main surface. A part of the peripheral carrier absorption section may be located between the avalanche photodiode array and the temperature compensation diode when viewed from a direction perpendicular to the first main surface. In this case, even if carriers are generated in the semiconductor substrate due to heat in a high-temperature environment, the generated carriers are prevented from reaching the APD array. Carriers from the temperature compensation diode are also prevented from reaching the APD array.

[0014] In one aspect, the photodetector may include a first electrode, a second electrode, and a third electrode. The first electrode may be connected to the APD and may output a signal from the APD. The second electrode may be connected to a temperature compensation diode. The third electrode may be connected to the peripheral carrier absorption section. In this case, a desired potential can be applied to each of the APD, the temperature compensation diode, and the peripheral carrier absorption section. When a voltage is applied to the peripheral carrier absorption section, carriers generated due to the temperature compensation diode can be further absorbed.

[0015] In one of the above aspects, a fourth electrode may be provided. The APD, the temperature compensation diode, and the peripheral carrier absorption unit may be connected in parallel to the fourth electrode. Since the APD and the temperature compensation diode are connected in parallel, a potential corresponding to the breakdown voltage of the temperature compensation diode can be applied to the APD. Since the peripheral carrier absorption unit is also connected in parallel to the APD and the temperature compensation diode, a potential can be applied to the peripheral carrier absorption unit without providing a separate power supply. If a voltage is applied to the peripheral carrier absorption unit, carriers generated due to the temperature compensation diode can be further absorbed.

[0016] In one aspect, the semiconductor substrate may include a semiconductor region of a first conductivity type. The APD and the temperature compensation diode may each include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer may be of a second conductivity type different from the first conductivity type. The second semiconductor layer may be of the first conductivity type having a higher impurity concentration than the semiconductor region. The second semiconductor layer may be located between the semiconductor region and the first semiconductor layer. In this case, the temperature compensation diode has a configuration similar to that of the APD. Therefore, it is possible to easily form a temperature compensation diode whose temperature characteristics regarding the gain and bias voltage are very similar to those of the APD.

[0017] In the above aspect, the peripheral carrier absorption portion may include a third semiconductor layer of the second conductivity type. In this case, the peripheral carrier absorption portion can further absorb carriers generated due to the temperature compensation diode.

[0018] In the above aspect, the peripheral carrier absorption portion may include a third semiconductor layer of the first conductivity type. In this case, the peripheral carrier absorption portion can further absorb carriers generated due to the temperature compensation diode.

[0019] In the above embodiment, the impurity concentration in the second semiconductor layer of the temperature compensation diode may be higher than the impurity concentration in the second semiconductor layer of the APD, in which case temperature compensation for the multiplication factor of the APD operating in linear mode can be achieved.

[0020] In a method for manufacturing a photodetector according to another aspect of the present invention, a semiconductor wafer having a first main surface and including a semiconductor region of a first conductivity type is prepared. In the semiconductor wafer, ions are implanted into a first location and a second location spaced apart from each other when viewed in a direction perpendicular to the first main surface, thereby forming a first semiconductor layer and a second semiconductor layer at the first location and the second location, respectively. The first semiconductor layer is of a second conductivity type different from the first conductivity type. The second semiconductor layer is located between the semiconductor region and the first semiconductor layer. The second semiconductor layer is of the first conductivity type and has a higher impurity concentration than the semiconductor region. In the manufacturing method, ions are further implanted into the second semiconductor layer at the first location.

[0021] In the above-mentioned another aspect, the APD and the temperature compensation diode are formed on the same semiconductor substrate. In this case, the temperature compensation diode and the APD having the same temperature characteristics with respect to the gain and the bias voltage can be manufactured more easily and with higher accuracy than when the temperature compensation diode and the APD are formed on different semiconductor substrates. In other words, the temperature compensation for the gain can be realized while suppressing the manufacturing cost.

[0022] In the above-mentioned another aspect, a first semiconductor layer and a second semiconductor layer are formed at the first location and the second location, respectively, by implanting ions into the first location and the second location. Then, ions are further implanted into the second semiconductor layer at the first location. In this case, it is possible to easily manufacture a temperature compensation diode and an APD that have the same temperature characteristics regarding the gain and bias voltage, and that are each set to a desired breakdown voltage. If the temperature compensation diode and the APD are each set to a desired breakdown voltage, the detection accuracy is improved.

[0023] Therefore, in the above manufacturing method, temperature compensation for the multiplication factor is realized while keeping manufacturing costs down, and detection accuracy is improved.

[0024] In the above-mentioned another aspect, the first ion implantation step may include a step of forming a first semiconductor layer at each of the first and second locations and a third semiconductor layer of a second conductivity type at a third location by a single ion implantation process, and a step of forming a second semiconductor layer at each of the first and second locations. The third location may be separated from the first and second locations when viewed from a direction perpendicular to the first main surface. The first and third semiconductor layers may be formed by implanting impurity ions of the second conductivity type at the first and second locations and the third location. The second semiconductor layer may be formed by implanting impurity ions of the first conductivity type at the first and second locations. In this case, the peripheral carrier absorption portion is formed without increasing the number of ion implantation steps. Therefore, the manufacturing cost is reduced.

[0025] A photodetector according to yet another aspect of the present invention includes a semiconductor substrate. The semiconductor substrate has a first main surface and a second main surface facing each other. The semiconductor substrate has a first APD, a second APD, and a peripheral carrier absorption portion. The first APD has a light incident surface on the first main surface side. The second APD is spaced apart from the first APD and is light-shielded when viewed in a direction perpendicular to the first main surface. The peripheral carrier absorption portion surrounds the first APD when viewed in a direction perpendicular to the first main surface. The peripheral carrier absorption portion absorbs carriers located in the periphery. A portion of the peripheral carrier absorption portion is located between the first APD and the second APD when viewed in a direction perpendicular to the first main surface.

[0026] In the above-mentioned further another aspect, the peripheral carrier absorption portion surrounds the APD when viewed from a direction perpendicular to the first main surface, which prevents carriers caused by heat generated in the semiconductor substrate in a high-temperature environment from reaching the APD, thereby improving detection accuracy.

[0027] In the above-mentioned further another aspect, the two APDs are formed on the same semiconductor substrate. In this case, the two APDs having the desired temperature characteristics can be formed more easily and with higher accuracy than when the two APDs are formed on different semiconductor substrates. Therefore, a photodetector including two APDs having the desired temperature characteristics can be realized while suppressing manufacturing costs.

[0028] When a breakdown voltage is applied to the second APD, the second APD may emit light. When two APDs are formed on the same semiconductor substrate and one APD emits light, carriers are generated in the semiconductor substrate by the light emitted from that APD. Therefore, the carriers generated by the second APD may affect the detection result of the first APD.

[0029] In one embodiment, a part of the peripheral carrier absorption section is located between the first APD and the second APD. Therefore, carriers generated by the light emission of the second APD are absorbed by the peripheral carrier absorption section before reaching the first APD. As a result, carriers originating from the second APD are prevented from reaching the first APD, and detection accuracy is improved.

[0030] Therefore, in the above-described light detection device, the manufacturing cost is suppressed, and the detection accuracy is improved. Effect of the Invention

[0031] One aspect of the present invention can provide a photodetector having improved detection accuracy while keeping manufacturing costs down. Another aspect of the present invention can provide a method for manufacturing a photodetector having improved detection accuracy while keeping manufacturing costs down. Yet another aspect of the present invention can provide a photodetector having improved detection accuracy while keeping manufacturing costs down. [Brief description of the drawings]

[0032] [Figure 1] FIG. 1 is a schematic cross-sectional view of a photodetector according to this embodiment. [Diagram 2] FIG. 2 is a plan view of the light detection device. [Diagram 3] FIG. 3 is a schematic plan view of a semiconductor substrate. [Figure 4] FIG. 4 is a diagram for explaining the circuit configuration of the photodetector. [Diagram 5] FIG. 5 is a schematic cross-sectional view of a light detection device according to a modified example of this embodiment. [Figure 6] FIG. 6 is a schematic plan view of a semiconductor substrate according to a modified example of the present embodiment. [Figure 7] FIG. 7 is a schematic plan view of a semiconductor substrate according to a modified example of the present embodiment. [Figure 8] FIG. 8 is a schematic plan view of a semiconductor substrate according to a modified example of the present embodiment. [Figure 9] FIG. 9 is a schematic plan view of a semiconductor substrate according to a modified example of the present embodiment. [Figure 10] FIG. 10 is a schematic plan view of a semiconductor substrate according to a modified example of this embodiment. [Figure 11] FIG. 11 is a schematic plan view of a semiconductor substrate according to a modified example of this embodiment. [Figure 12] FIG. 12 is a diagram for explaining the circuit configuration of a photodetector according to a modified example of this embodiment. [Figure 13] FIG. 13 is a flowchart for explaining a method for manufacturing a semiconductor substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0034] First, a photodetector according to the present embodiment will be described with reference to Fig. 1 to Fig. 3. The photodetector 1 includes a semiconductor substrate 10. Fig. 1 is a schematic cross-sectional view of the photodetector. Fig. 2 is a plan view of the photodetector. Fig. 3 is a schematic plan view of the semiconductor substrate included in the photodetector.

[0035] The semiconductor substrate 10 has an APD 11 and a temperature compensating diode 12. The APD 11 and the temperature compensating diode 12 have the same temperature characteristics with respect to the relationship between the gain and the bias voltage. In this embodiment, the breakdown voltage of the APD 11 is different from the breakdown voltage of the temperature compensating diode 12. In this embodiment, the breakdown voltage of the APD 11 is higher than the breakdown voltage of the temperature compensating diode 12.

[0036] In the photodetector 1, a breakdown voltage is applied to the temperature compensating diode 12, and a voltage corresponding to the breakdown voltage is applied to the APD 11 as a bias voltage. In this embodiment, the breakdown voltage of the temperature compensating diode 12 is applied to the APD 11 as a bias voltage. The APD 11 and the temperature compensating diode 12 have the same temperature characteristics regarding the relationship between the gain and the bias voltage. In this case, when the environmental temperature changes, the breakdown voltage applied to the temperature compensating diode 12 changes. Due to the change in the breakdown voltage applied to the temperature compensating diode 12, the bias voltage applied to the APD 11 also changes in response to the environmental temperature so that the gain of the APD 11 is maintained. That is, in the photodetector 1, the temperature compensating diode 12 performs temperature compensation for the gain of the APD 11.

[0037] 1, a semiconductor substrate 10 has principal surfaces 10a and 10b facing each other. The APD 11 and the temperature compensation diode 12 are formed on the semiconductor substrate 10 spaced apart from each other when viewed in a direction perpendicular to the principal surface 10a. The APD 11 has a light incident surface 11a on the principal surface 10a side. The temperature compensation diode 12 is a light-shielded APD.

[0038] The semiconductor substrate 10 has a peripheral carrier absorption portion 13 in addition to the APD 11 and the temperature compensation diode 12. A part of the peripheral carrier absorption portion 13 is located between the APD 11 and the temperature compensation diode 12 when viewed from a direction perpendicular to the main surface 10a. The peripheral carrier absorption portion 13 surrounds the APD 11. The peripheral carrier absorption portion 13 is a region that absorbs carriers located in the periphery.

[0039] Next, the configuration of the photodetector in this embodiment will be described in more detail with reference to Fig. 1. The semiconductor substrate 10 includes a semiconductor region 21 and semiconductor layers 31, 32, 33, 34, and 35. The APD 11 and the temperature compensation diode 12 each include the semiconductor region 21 and semiconductor layers 31, 32, and 35.

[0040] The peripheral carrier absorption unit 13 includes the semiconductor region 21 and the semiconductor layers 33 and 35. The peripheral carrier absorption unit 13 absorbs carriers located in the periphery in the semiconductor layer 33. That is, the semiconductor layer 33 functions as a peripheral carrier absorption layer that absorbs peripheral carriers. In this embodiment, the peripheral carrier absorption unit 13 is a portion of the semiconductor substrate 10 that is surrounded by edges 13a and 13b of the peripheral carrier absorption layer when viewed from a direction perpendicular to the main surface 10a. In this embodiment, the edges 13a and 13b are edges of the semiconductor layer 33. The edge 13b is located closer to the APD 11 than the edge 13a.

[0041] The semiconductor region 21 and the semiconductor layers 32, 34, and 35 are of a first conductivity type, and the semiconductor layers 31 and 33 are of a second conductivity type. The semiconductor impurities are added by, for example, a diffusion method or an ion implantation method. In this embodiment, the first conductivity type is P type, and the second conductivity type is N type. When the semiconductor substrate 10 is based on Si, a Group 13 element such as B is used as the P type impurity, and a Group 15 element such as N, P, or As is used as the N type impurity.

[0042] The semiconductor region 21 is located on the major surface 10a side of the semiconductor substrate 10. The semiconductor region 21 constitutes a part of the major surface 10a. The semiconductor region 21 is, for example, P - It is a type.

[0043] The semiconductor layer 31 constitutes a part of the principal surface 10a. When viewed from a direction perpendicular to the principal surface 10a, the semiconductor layer 31 is in contact with the semiconductor region 21 and is surrounded by the semiconductor region 21. The semiconductor layer 31 is, for example, N + In this embodiment, the semiconductor layer 31 constitutes the cathode of each of the APD 11 and the temperature compensation diode 12.

[0044] The semiconductor layer 32 is located between the semiconductor region 21 and the semiconductor layer 31. In other words, the semiconductor layer 32 contacts the semiconductor layer 31 on the principal surface 10a side and contacts the semiconductor region 21 on the principal surface 10b side. The semiconductor layer 32 has a higher impurity concentration than the semiconductor region 21. The semiconductor layer 32 is, for example, a P-type. In this embodiment, the impurity concentration of the semiconductor layer 32 of the temperature compensation diode 12 is higher than the impurity concentration of the semiconductor layer 32 of the APD 11. The semiconductor layer 32 forms an avalanche region in each of the APD 11 and the temperature compensation diode 12.

[0045] The semiconductor layer 33 constitutes a part of the principal surface 10a. When viewed from a direction perpendicular to the principal surface 10a, the semiconductor layer 33 is in contact with the semiconductor region 21 and is surrounded by the semiconductor region 21. In this embodiment, the peripheral carrier absorption portion 13 is made of the semiconductor layer 33 and is in contact only with the semiconductor region 21 in the semiconductor substrate 10. The peripheral carrier absorption portion 13 does not include a layer corresponding to the avalanche region. In this embodiment, the semiconductor layer 33 has the same impurity concentration as the semiconductor layer 31. The semiconductor layer 33 is, for example, N + It is a type.

[0046] The semiconductor layer 34 constitutes a part of the principal surface 10a. When viewed from a direction perpendicular to the principal surface 10a, the semiconductor layer 34 is in contact with the semiconductor region 21 and is surrounded by the semiconductor region 21. In this embodiment, the semiconductor layer 34 has a higher impurity concentration than the semiconductor region 21 and the semiconductor layer 32. The semiconductor layer 34 is, for example, P + The semiconductor layer 34 is connected to the semiconductor layer 35 at a portion not shown. The semiconductor layer 34 constitutes the anode of the photodetector 1. The semiconductor layer 34 constitutes the anodes of the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13, for example.

[0047] The semiconductor layer 35 is located closer to the principal surface 10b of the semiconductor substrate 10 than the semiconductor region 21. The semiconductor layer 35 constitutes the entire surface of the principal surface 10b. The semiconductor layer 35 contacts the semiconductor region 21 on the principal surface 10a side. In this embodiment, the semiconductor layer 35 has a higher impurity concentration than the semiconductor region 21 and the semiconductor layer 32. The semiconductor layer 35 is, for example, P + The semiconductor layer 35 constitutes the anode of the photodetector 1. The semiconductor layer 35 constitutes the anodes of the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13, for example.

[0048] The photodetector 1 further includes an insulating film 41, electrodes 42, 43, 44, and 45, a passivation film 46, and an antireflection film 47, which are provided on the main surface 10a of the semiconductor substrate 10. The insulating film 41 is laminated on the main surface 10a of the semiconductor substrate 10. The insulating film 41 is, for example, a silicon oxide film. The electrodes 42, 43, 44, and 45 are each disposed on the insulating film 41. The passivation film 46 is laminated on the insulating film 41 and the electrodes 42, 43, 44, and 45. The antireflection film 47 is laminated on the main surface 10a of the semiconductor substrate 10.

[0049] The electrode 42 penetrates the insulating film 41 and is connected to the semiconductor layer 31 of the APD 11. A portion of the electrode 42 is exposed from the passivation film 46 and constitutes a pad electrode 52 of the APD 11. The electrode 42 outputs a signal from the APD 11 at the pad electrode 52. The electrode 43 penetrates the insulating film 41 and is connected to the semiconductor layer 31 of the temperature compensation diode 12. A portion of the electrode 43 is exposed from the passivation film 46 and constitutes, for example, a pad electrode 53 of the temperature compensation diode 12.

[0050] The electrode 44 penetrates the insulating film 41 and is connected to the semiconductor layer 33 of the peripheral carrier absorption unit 13. A part of the electrode 44 is exposed from the passivation film 46 and constitutes, for example, a pad electrode 54 of the peripheral carrier absorption unit 13. The electrode 45 penetrates the insulating film 41 and is connected to the semiconductor layer 34. That is, the electrode 45 is connected to the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13. In other words, the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13 are connected in parallel to each other with respect to the electrode 45. A part of the electrode 45 is exposed from the passivation film 46 and constitutes, for example, a pad electrode 55.

[0051] In this embodiment, when the photodetector 1 is viewed from a direction perpendicular to the main surface 10a, the pad electrodes 52, 53, 54, and 55 are arranged around the APD 11 as shown in FIG. 2. In this embodiment, the pad electrode 52 is a pad electrode for the cathode of the APD 11. The pad electrode 53 is a pad electrode for the cathode of the temperature compensation diode 12. The pad electrode 54 is a pad electrode for the cathode of the peripheral carrier absorption unit 13. The pad electrode 55 is a pad electrode for the anode of the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13.

[0052] The APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13 are connected in parallel to the pad electrode 55. When a reverse bias is applied to the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13, a positive voltage is applied to the cathode pad electrode, and a negative voltage is applied to the anode pad electrode.

[0053] The antireflection film 47 is laminated on the semiconductor layer 31 of the APD 11. A part of the antireflection film 47 is exposed from the passivation film 46. Therefore, light transmitted through the antireflection film 47 can be incident on the semiconductor layer 31 of the APD 11. The semiconductor layer 31 of the temperature compensation diode 12 and the semiconductor layer 33 of the peripheral carrier absorption section 13 are covered with the insulating film 41 and are light-shielded. Therefore, when the photodetector 1 is viewed from the principal surface 10a side in a direction perpendicular to the principal surface 10a, the semiconductor layer 31 of the APD 11 can be seen as shown in FIG. 2. The semiconductor layer 31 of the temperature compensation diode 12 and the semiconductor layer 33 of the peripheral carrier absorption section 13 cannot be seen.

[0054] 3 is a schematic plan view of the semiconductor substrate 10 viewed from the principal surface 10a in a direction perpendicular to the principal surface 10a. As shown in FIG. 3, the semiconductor layer 31 of the APD 11 and the semiconductor layer 31 of the temperature compensation diode 12 are circular when viewed from a direction perpendicular to the principal surface 10a. The semiconductor layer 33 of the peripheral carrier absorption section 13 is annular when viewed from a direction perpendicular to the principal surface 10a, and is spaced apart from and surrounds the semiconductor layer 31 of the APD 11. A part of the semiconductor layer 33 is located between the semiconductor layer 31 of the APD 11 and the semiconductor layer 31 of the temperature compensation diode 12 when viewed from a direction perpendicular to the principal surface 10a. In other words, the peripheral carrier absorption section 13 is located between the APD 11 and the temperature compensation diode 12 when viewed from a direction perpendicular to the principal surface 10a.

[0055] When viewed from a direction perpendicular to the main surface 10a, on the line segment connecting the APD 11 and the temperature compensating diode 12 at the shortest distance, the shortest distance between the APD 11 and the peripheral carrier absorption section 13 is smaller than the shortest distance between the portion 13c of the peripheral carrier absorption section 13 and the temperature compensating diode 12. The portion 13c is the portion of the edges 13a, 13b of the peripheral carrier absorption section 13 that is closest to the APD 11 on the line segment connecting the APD 11 and the temperature compensating diode 12 at the shortest distance. In other words, the portion 13c is the portion of the edge 13b of the peripheral carrier absorption section 13 that is closest to the temperature compensating diode 12 when viewed from a direction perpendicular to the main surface 10a.

[0056] More specifically, on a line segment that connects the semiconductor layer 31 of the APD 11 and the semiconductor layer 31 of the temperature compensation diode 12 at the shortest distance when viewed from a direction perpendicular to the main surface 10a, the distance L1 is smaller than the distance L2. As shown in FIG. 1 and FIG. 3, the distance L1 is the shortest distance between the semiconductor layer 31 of the APD 11 and the peripheral carrier absorption unit 13 when viewed from a direction perpendicular to the main surface 10a. The distance L2 is the shortest distance between the portion 13c of the peripheral carrier absorption unit 13 and the semiconductor layer 31 of the temperature compensation diode 12 when viewed from a direction perpendicular to the main surface 10a. L2 / L1 is, for example, greater than 1 and equal to or less than 50. L2 / L1 may be equal to or greater than 20 and equal to or less than 50.

[0057] 1, on the line segment connecting the semiconductor layer 32 of the APD 11 and the semiconductor layer 32 of the temperature compensation diode 12 at the shortest distance when viewed from the direction perpendicular to the main surface 10a, the distance L3 is smaller than the distance L4. When viewed from the direction perpendicular to the main surface 10a, the distance L3 is the shortest distance between the semiconductor layer 32 of the APD 11 and the peripheral carrier absorption unit 13. When viewed from the direction perpendicular to the main surface 10a, the distance L4 is the shortest distance between the portion 13c of the peripheral carrier absorption unit 13 and the semiconductor layer 32 of the temperature compensation diode 12.

[0058] Next, the operation of the photodetector in this embodiment will be described with reference to Fig. 4. The photodetector 1 is used in a state where a power supply 61 and a current limiting circuit 62 are connected to a pad electrode 55. The power supply 61 has a positive side connected to a ground 63 and a negative side connected to the pad electrode 55 via the current limiting circuit 62. The pad electrodes 53 and 54 are connected to grounds 64 and 65, respectively. The grounds 64 and 65 may be connected to each other. The pad electrode 52 is connected to a signal readout circuit (not shown).

[0059] In this embodiment, the pad electrode 55 is P + The semiconductor layer 34 is connected to a P +The APD 11 is connected to the semiconductor layer 35 of the semiconductor device 30. Therefore, the anodes of the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13 are connected in parallel to each other with respect to the pad electrode 55. As a result, a negative potential is applied to the anodes of the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13 by the power supply 61.

[0060] The difference between the potential applied to the pad electrode 53 and the potential applied to the pad electrode 55 is the breakdown voltage of the temperature compensation diode 12. Therefore, a potential corresponding to the breakdown voltage applied to the temperature compensation diode 12 is applied to the anode of the APD 11. As a result, a voltage corresponding to the breakdown voltage applied to the temperature compensation diode 12 is applied to the APD 11 as a bias voltage. Similarly, a voltage corresponding to the breakdown voltage applied to the temperature compensation diode 12 is also applied to the anode of the peripheral carrier absorbing unit 13 as a bias voltage.

[0061] In this embodiment, the combination of the power supply 61 and the current limiting circuit 62 is connected to the pad electrode 55, so that the breakdown voltage of the temperature compensation diode 12 is applied to the pad electrode 55. Therefore, the breakdown voltage of the temperature compensation diode 12 is applied to the APD 11 and the peripheral carrier absorbing section 13 as a bias voltage. In this embodiment, the output voltage of the power supply 61 is equal to or higher than the operating voltage of the APD 11. In other words, the output voltage of the power supply 61 is equal to or higher than the upper limit of the temperature fluctuation of the breakdown voltage of the temperature compensation diode 12. For example, the output voltage of the power supply 61 is equal to or higher than 300V. The current limiting circuit 62 is formed of, for example, a current mirror circuit or a resistor. In this case, the multiplication factor of the APD 11 can be set arbitrarily according to, for example, the breakdown voltage difference between the temperature compensation diode 12 and the APD 11. If the amplification factor of the APD 11 is set to an optimal multiplication factor Mopt with a high S / N ratio, the detection accuracy can be improved.

[0062] In this embodiment, the APD 11, the temperature compensation diode 12, and the anode of the peripheral carrier absorption unit 13 are integrally formed by the semiconductor layer 35. For example, at an ambient temperature of 25° C., if the potential applied to the pad electrode 53 is 0 V and the breakdown voltage of the temperature compensation diode 12 is 130 V, a potential of −130 V is applied to the anode of the APD 11 and the anode of the peripheral carrier absorption unit 13. Therefore, if the breakdown voltage of the APD 11 is 150 V at an ambient temperature of 25° C., the APD 11 operates in a state where the potential difference between the anode and cathode is 20 V lower than the breakdown voltage.

[0063] The APD 11 and the temperature compensating diode 12 have the same temperature characteristics regarding the relationship between the gain and the bias voltage. Therefore, as long as the temperature compensating diode 12 is in a breakdown state, the APD 11 operates while maintaining the gain when a bias voltage 20 V lower than the breakdown voltage is applied at an ambient temperature of 25° C. In other words, in the photodetector 1, a voltage that brings the temperature compensating diode 12 into a breakdown state is applied to the temperature compensating diode 12, thereby realizing temperature compensation for the gain of the APD 11.

[0064] In this embodiment, a configuration has been described in which a so-called reach-through type APD 11 operates in a linear mode. The photodetector 1 may be configured such that the reach-through type APD 11 operates in a Geiger mode. In a configuration in which the APD 11 operates in the Geiger mode, a quenching resistor is connected to the APD 11. The semiconductor substrate 10 is configured such that the impurity concentration of the semiconductor layer 32 of the temperature compensation diode 12 is lower than the impurity concentration of the semiconductor layer 32 of the APD 11.

[0065] Next, a photodetector according to a modified example of this embodiment will be described with reference to Figs. 5 and 6. Fig. 5 is a schematic cross-sectional view of a photodetector according to this modified example. Fig. 6 is a schematic plan view of the semiconductor substrate shown in Fig. 5. This modified example is generally similar to or the same as the above-described embodiment. This modified example differs from the above-described embodiment in that the semiconductor layer 31 of the temperature compensation diode 12 and the semiconductor layer 33 of the peripheral carrier absorption section 13 are connected by a semiconductor layer of the same conductivity type as the semiconductor layers 31 and 33. Hereinafter, the differences between the above-described embodiment and the modified example will be mainly described.

[0066] The semiconductor substrate 10A has a semiconductor layer 71 that connects the semiconductor layer 31 of the temperature compensation diode 12 and the semiconductor layer 33 of the peripheral carrier absorption portion 13. The semiconductor layer 71 has the same conductivity type as the semiconductor layers 31 and 33. In the semiconductor substrate 10A, the semiconductor layer 71 has the same second conductivity type as the semiconductor layers 31 and 33, and is located at the same height as the semiconductor layers 31 and 33 in the thickness direction of the semiconductor substrate 10. The semiconductor layer 71 is, for example, N + It is a type.

[0067] In the semiconductor substrate 10A, the semiconductor layer 31 of the APD 11 and the semiconductor layer 31 of the temperature compensation diode 12 are also circular when viewed from a direction perpendicular to the principal surface 10a. The semiconductor layer 33 of the peripheral carrier absorption portion 13 is annular when viewed from a direction perpendicular to the principal surface 10a, and is spaced apart from and surrounds the semiconductor layer 31 of the APD 11. A portion of the semiconductor layer 33 is located between the semiconductor layer 31 of the APD 11 and the semiconductor layer 31 of the temperature compensation diode 12 when viewed from a direction perpendicular to the principal surface 10a. In other words, the peripheral carrier absorption portion 13 is located between the APD 11 and the temperature compensation diode 12 when viewed from a direction perpendicular to the principal surface 10a.

[0068] When viewed from a direction perpendicular to the main surface 10a, the semiconductor layer 71 connects the edge 13a of the peripheral carrier absorption portion 13 to the semiconductor layer 33 of the temperature compensation diode 12 between the semiconductor layer 31 of the APD 11 and the semiconductor layer 31 of the temperature compensation diode 12. In the actual semiconductor substrate 10A, the semiconductor layer 71 and the semiconductor layer 31 of the temperature compensation diode 12 are integrated to such an extent that the boundary between them is not discernible. Similarly, the semiconductor layer 71 and the semiconductor layer 33 of the peripheral carrier absorption portion 13 are integrated to such an extent that the boundary between them is not discernible.

[0069] Next, a photodetector according to another modified example of this embodiment will be described with reference to Figs. 7 to 10. Figs. 7 to 10 are schematic plan views of a semiconductor substrate of a photodetector according to another modified example. These modified examples are generally similar to or the same as the above-described embodiment. These modified examples differ from the above-described embodiment in that the photodetector has a semiconductor substrate on which an APD array including a plurality of APDs is formed. The following mainly describes the differences between the above-described embodiment and the modified examples.

[0070] First, the semiconductor substrate 10B shown in Fig. 7 will be described. The semiconductor substrate 10B has an APD array 80 including a plurality of APDs 81, a temperature compensation diode 82, and a peripheral carrier absorption section 83 on the principal surface 10a side. The APD array 80 is formed on the semiconductor substrate 10B at a distance from the temperature compensation diode 82 and the peripheral carrier absorption section 83 when viewed from a direction perpendicular to the principal surface 10a. The APDs 81 are formed on the semiconductor substrate 10B at a distance from each other when viewed from a direction perpendicular to the principal surface 10a.

[0071] In the semiconductor substrate 10B, the APDs 81 and the temperature compensation diodes 82 are rectangular and of equal size, and are arranged in a line in one direction. In the semiconductor substrate 10B, the APDs 81 are arranged at equal intervals. The temperature compensation diode 82 is located at the end of the arrangement of the APDs 81 and the temperature compensation diodes 82.

[0072] The peripheral carrier absorption section 83 surrounds the APD array 80 when viewed from a direction perpendicular to the main surface 10a. A part of the peripheral carrier absorption section 83 is located between the APD array 80 and the temperature compensation diode 82 when viewed from a direction perpendicular to the main surface 10a. Specifically, a part of the peripheral carrier absorption section 83 is located between the temperature compensation diode 82 and the APD 81a that is closest to the temperature compensation diode 82 among the multiple APDs 81 when viewed from a direction perpendicular to the main surface 10a.

[0073] Each of the APDs 81 and the temperature compensating diodes 82 includes a semiconductor region 21 and semiconductor layers 31, 32, and 35, similar to the APD 11 and the temperature compensating diode 12 in the above-described embodiment. The peripheral carrier absorption portion 83 includes a semiconductor region 21 and semiconductor layers 33 and 35. The semiconductor layer 33 of the peripheral carrier absorption portion 83 is annular when viewed from a direction perpendicular to the main surface 10a. The peripheral carrier absorption portion 83 absorbs carriers located in the periphery of the semiconductor layer 33.

[0074] The peripheral carrier absorption portion 83 means a portion of the semiconductor substrate 10B surrounded by edges 83a and 83b of the peripheral carrier absorption layer when viewed from a direction perpendicular to the main surface 10a. In the semiconductor substrate 10B, the edges 83a and 83b are edges of the semiconductor layer 33. The edge 83b is located closer to the APD 81 than the edge 83a.

[0075] The APD 81a, the temperature compensation diode 82, and the peripheral carrier absorption unit 83 have the same arrangement relationship as the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption unit 13 in the above-mentioned embodiment. Specifically, on a line segment that connects the semiconductor layer 31 of the APD 81a and the semiconductor layer 31 of the temperature compensation diode 82 at the shortest distance when viewed from a direction perpendicular to the main surface 10a, the distance L1 is smaller than the distance L2. In the semiconductor substrate 10B, the distance L1 is the shortest distance between the semiconductor layer 31 of the APD 81a and the peripheral carrier absorption unit 83 when viewed from a direction perpendicular to the main surface 10a. The distance L2 is the shortest distance between the portion 83c of the peripheral carrier absorption unit 83 and the semiconductor layer 31 of the temperature compensation diode 82 when viewed from a direction perpendicular to the main surface 10a.

[0076] The portion 83c is the portion of the edges 83a, 83b of the peripheral carrier absorption portion 83 that is closest to the APD 81a on the line segment that connects the APD 81a and the temperature compensation diode 82 at the shortest distance. L2 / L1 is, for example, greater than 1 and equal to or less than 50. L2 / L1 may be equal to or greater than 20 and equal to or less than 50.

[0077] As with the semiconductor substrate 10, when viewed from a direction perpendicular to the principal surface 10a, the distance L3 is smaller than the distance L4 on the line segment connecting the semiconductor layer 32 of the APD 81a and the semiconductor layer 32 of the temperature compensation diode 82 at the shortest distance. In the semiconductor substrate 10B, the distance L3 is the shortest distance between the semiconductor layer 32 of the APD 81a and the peripheral carrier absorption unit 83 when viewed from a direction perpendicular to the principal surface 10a. The distance L4 is the shortest distance between the portion 83c of the peripheral carrier absorption unit 83 and the semiconductor layer 32 of the temperature compensation diode 82 when viewed from a direction perpendicular to the principal surface 10a.

[0078] Next, the semiconductor substrate 10C shown in Fig. 8 will be described. The semiconductor substrate 10C has an APD array 85 including a plurality of APDs 86, a temperature compensation diode 87, and peripheral carrier absorption units 88, 89 on the main surface 10a side. The APD array 85 is formed on the semiconductor substrate 10C at a distance from the temperature compensation diode 87 and the peripheral carrier absorption units 88, 89 when viewed from a direction perpendicular to the main surface 10a. The APDs 86 are formed on the semiconductor substrate 10C at a distance from each other when viewed from a direction perpendicular to the main surface 10a.

[0079] In the semiconductor substrate 10C, the APDs 86 and the temperature compensation diodes 87 are rectangular and of equal size, and are arranged in a line in one direction. In the semiconductor substrate 10C, the APDs 86 are arranged in two groups. The temperature compensation diode 87 is arranged between the two groups when viewed from a direction perpendicular to the main surface 10a. In other words, the temperature compensation diode 87 is sandwiched between two APD arrays 85a and 85b, each of which has a plurality of APDs 86 arranged therein. In each of the APD array 85a and the APD array 85b, the APDs 86 are arranged at equal intervals. The APD array 85a and the APD array 85b are arranged symmetrically with respect to a straight line passing through the temperature compensation diode 87 in a direction parallel to the main surface 10a and perpendicular to the arrangement direction of the APDs 86.

[0080] The peripheral carrier absorption units 88 and 89 surround the multiple APDs 86 for each of the above-mentioned groups when viewed from a direction perpendicular to the main surface 10a. In other words, the peripheral carrier absorption unit 88 surrounds the APD array 85a. The peripheral carrier absorption unit 89 surrounds the APD array 85b. The peripheral carrier absorption units 88 and 89 are arranged symmetrically with respect to a straight line passing through the temperature compensation diode 87 in a direction parallel to the main surface 10a and perpendicular to the arrangement direction of the multiple APDs 86. The peripheral carrier absorption units 88 and 89 have an annular semiconductor layer 33 when viewed from a direction perpendicular to the main surface 10a.

[0081] A part of the peripheral carrier absorption section 88 is located between the APD array 85a and the temperature compensation diode 87 when viewed from a direction perpendicular to the main surface 10a. Specifically, a part of the peripheral carrier absorption section 88 is located between the temperature compensation diode 87 and the APD 86a that is closest to the temperature compensation diode 87 among the multiple APDs 86 included in the APD array 85a when viewed from a direction perpendicular to the main surface 10a. A part of the peripheral carrier absorption section 89 is located between the APD array 85b and the temperature compensation diode 87 when viewed from a direction perpendicular to the main surface 10a. Specifically, a part of the peripheral carrier absorption section 89 is located between the temperature compensation diode 87 and the APD 86b that is closest to the temperature compensation diode 87 among the multiple APDs 86 included in the APD array 85b when viewed from a direction perpendicular to the main surface 10a.

[0082] Each of the APDs 86 and the temperature compensating diodes 87 includes a semiconductor region 21 and semiconductor layers 31, 32, and 35, similar to the APD 11 and the temperature compensating diode 12 in the above-described embodiment. The peripheral carrier absorption portions 88 and 89 include a semiconductor region 21 and semiconductor layers 33 and 35. The semiconductor layer 33 of the peripheral carrier absorption portions 88 and 89 is annular when viewed from a direction perpendicular to the main surface 10a. The peripheral carrier absorption portions 88 and 89 absorb carriers located peripherally in the semiconductor layer 33.

[0083] In the semiconductor substrate 10C, the peripheral carrier absorption portion 88 means a portion of the semiconductor substrate 10C surrounded by edges 88a and 88b of the peripheral carrier absorption layer when viewed from a direction perpendicular to the main surface 10a. The peripheral carrier absorption portion 89 means a portion of the semiconductor substrate 10C surrounded by edges 89a and 89b of the peripheral carrier absorption layer when viewed from a direction perpendicular to the main surface 10a. In the semiconductor substrate 10C, the edges 88a, 88b, 89a, and 89b are edges of the semiconductor layer 33. The edge 88b is located closer to the APD 86 than the edge 88a. The edge 89b is located closer to the APD 86 than the edge 89a.

[0084] The APD 86a, the temperature compensating diode 87, and the peripheral carrier absorption unit 88 have a positional relationship similar to that of the APD 11, the temperature compensating diode 12, and the peripheral carrier absorption unit 13 in the above-mentioned embodiment. The APD 86b, the temperature compensating diode 87, and the peripheral carrier absorption unit 89 have a positional relationship similar to that of the APD 11, the temperature compensating diode 12, and the peripheral carrier absorption unit 13.

[0085] For example, when viewed from a direction perpendicular to the main surface 10a, on a line segment connecting the semiconductor layer 31 of the APDs 86a and 86b and the semiconductor layer 31 of the temperature compensation diode 87 at the shortest distance, the distance L1 is smaller than the distance L2. In the semiconductor substrate 10C, the distance L1 is the shortest distance between the semiconductor layer 31 of the APD 86a and the peripheral carrier absorption portion 88, and is also the shortest distance between the semiconductor layer 31 of the APD 86b and the peripheral carrier absorption portion 89, when viewed from a direction perpendicular to the main surface 10a. The distance L2 is the shortest distance between the portion 88c of the peripheral carrier absorption portion 88 and the semiconductor layer 31 of the temperature compensation diode 87, and is also the shortest distance between the portion 89c of the peripheral carrier absorption portion 89 and the semiconductor layer 31 of the temperature compensation diode 87, when viewed from a direction perpendicular to the main surface 10a.

[0086] The portion 88c is the portion of the edges 88a, 88b of the peripheral carrier absorption portion 88 that is closest to the APD 86a on the line segment connecting the APD 86a and the temperature compensating diode 87 at the shortest distance. The portion 89c is the portion of the edges 89a, 89b of the peripheral carrier absorption portion 89 that is closest to the APD 86b on the line segment connecting the APD 86b and the temperature compensating diode 87 at the shortest distance. L2 / L1 is, for example, greater than 1 and equal to or less than 50. L2 / L1 may be equal to or greater than 20 and equal to or less than 50.

[0087] Next, the semiconductor substrate 10D shown in Fig. 9 will be described. The semiconductor substrate 10D has an APD array 90 including a plurality of APDs 91, a temperature compensation diode 92, and a peripheral carrier absorption section 93 on the main surface 10a side. The APD array 90 is formed on the semiconductor substrate 10D at a distance from the temperature compensation diode 92 and the peripheral carrier absorption section 93 when viewed from a direction perpendicular to the main surface 10a. The APDs 91 are formed on the semiconductor substrate 10D at a distance from each other when viewed from a direction perpendicular to the main surface 10a.

[0088] In the semiconductor substrate 10D, the APDs 91 are rectangular and of equal size, and are arranged in a line in one direction. In the semiconductor substrate 10D, the APDs 91 are arranged at equal intervals. The temperature compensation diode 92 and the APD array 90 are arranged in a direction perpendicular to the direction in which the APDs 91 are arranged and parallel to the main surface 10a.

[0089] The peripheral carrier absorption section 93 surrounds the APD array 90 when viewed from a direction perpendicular to the main surface 10a. A part of the peripheral carrier absorption section 93 is located between the APD array 90 and the temperature compensation diode 92 when viewed from a direction perpendicular to the main surface 10a. Specifically, a part of the peripheral carrier absorption section 93 is located between the temperature compensation diode 92 and the APD 91a that is closest to the temperature compensation diode 92 among the multiple APDs 91 when viewed from a direction perpendicular to the main surface 10a. The APD 91a is the APD that is located at the center of the APD array 90 among the multiple APDs 91.

[0090] Each APD 91 and temperature compensation diode 92 includes a semiconductor region 21 and semiconductor layers 31, 32, and 35, similar to the APD 11 and temperature compensation diode 12 in the above-described embodiment. The peripheral carrier absorption portion 93 includes a semiconductor region 21 and semiconductor layers 33 and 35. The semiconductor layer 33 of the peripheral carrier absorption portion 93 is annular when viewed from a direction perpendicular to the main surface 10a. The peripheral carrier absorption portion 93 absorbs carriers located peripherally in the semiconductor layer 33.

[0091] The peripheral carrier absorption portion 93 means a portion of the semiconductor substrate 10D surrounded by edges 93a and 93b of the peripheral carrier absorption layer when viewed from a direction perpendicular to the main surface 10a. The edges 93a and 93b are edges of the semiconductor layer 33. The edge 93b is located closer to the APD 91 than the edge 93a. The APD 91a, the temperature compensating diode 92, and the peripheral carrier absorption portion 93 have the same positional relationship as the APD 11, the temperature compensating diode 12, and the peripheral carrier absorption portion 13 in the above-mentioned embodiment.

[0092] Next, the semiconductor substrate 10E shown in Fig. 10 will be described. The semiconductor substrate 10E has, on the main surface 10a side, an APD array 95 including a plurality of APDs 96, a temperature compensation diode 97, and a peripheral carrier absorption section 98. The APD array 95 is formed on the semiconductor substrate 10E at a distance from the temperature compensation diode 97 and the peripheral carrier absorption section 98 when viewed from a direction perpendicular to the main surface 10a. The APDs 96 are formed on the semiconductor substrate 10E at a distance from each other when viewed from a direction perpendicular to the main surface 10a.

[0093] In the semiconductor substrate 10E, the APDs 96 are rectangular and of equal size, and are two-dimensionally arranged in a matrix. In the semiconductor substrate 10E, the APDs 96 are arranged at equal intervals. The temperature compensation diodes 97 and the APD array 95 are aligned in the column direction of the APDs 96.

[0094] The peripheral carrier absorption section 98 surrounds the APD array 95 when viewed from a direction perpendicular to the main surface 10a. A part of the peripheral carrier absorption section 98 is located between the APD array 95 and the temperature compensation diode 97 when viewed from a direction perpendicular to the main surface 10a. Specifically, a part of the peripheral carrier absorption section 98 is located between the temperature compensation diode 97 and the APD 96a that is closest to the temperature compensation diode 97 among the multiple APDs 96 when viewed from a direction perpendicular to the main surface 10a. The APD 96a is the APD that is located in the center of the row that is closest to the temperature compensation diode 97 among the multiple APDs 96.

[0095] Like the APD 11 and the temperature compensation diode 12 in the above-described embodiment, each of the APDs 96 and the temperature compensation diode 97 includes a semiconductor region 21 and semiconductor layers 31, 32, and 35. The peripheral carrier absorption unit 98 includes a semiconductor region 21 and semiconductor layers 33 and 35. The peripheral carrier absorption unit 98 absorbs carriers located peripherally in the semiconductor layer 33.

[0096] The peripheral carrier absorption portion 98 refers to a portion of the semiconductor substrate 10E that is surrounded by edges 98a, 98b of the peripheral carrier absorption layer when viewed from a direction perpendicular to the main surface 10a. The edges 98a, 98b are edges of the semiconductor layer 33. The edge 98b is located closer to the APD 96 than the edge 98a. The APD 96a, the temperature compensating diode 97, and the peripheral carrier absorption portion 98 have the same positional relationship as the APD 11, the temperature compensating diode 12, and the peripheral carrier absorption portion 13 in the above-mentioned embodiment.

[0097] Next, a photodetector according to another modified example of this embodiment will be described with reference to FIG. 11. FIG. 11 is a schematic cross-sectional view of a photodetector according to this modified example. This modified example is generally similar or the same as the above-described embodiment. This modified example differs from the above-described embodiment in that a so-called reverse type APD is formed on the semiconductor substrate of the photodetector, and that the APD of the semiconductor substrate operates in Geiger mode. The semiconductor substrate 10 shown in FIG. 1 has a so-called reach-through type APD, and the APD operates in linear mode. In contrast, the semiconductor substrate 10F of the photodetector 1F according to this modified example has a so-called reverse type APD, and the APD operates in Geiger mode. Hereinafter, differences between the above-described embodiment and the modified example will be mainly described.

[0098] The semiconductor substrate 10F has an APD 101, a temperature compensation diode 102, and a peripheral carrier absorption portion 103, which correspond to the APD 11, the temperature compensation diode 12, and the peripheral carrier absorption portion 13 of the semiconductor substrate 10, respectively. The APD 101 has a light incident surface 101a on the main surface 10a side, which corresponds to the light incident surface 11a of the APD 11. The semiconductor substrate 10F includes a semiconductor region 21 and semiconductor layers 31, 33, 34, 35, and 36. The semiconductor substrate 10F is different from the semiconductor substrate 10 in that it includes a semiconductor layer 36 instead of the semiconductor layer 32. The APD 101 and the temperature compensation diode 102 include a semiconductor region 21 and semiconductor layers 31, 35, and 36, respectively. As shown in FIG. 11, the semiconductor layer 34 is in contact with the semiconductor layer 35.

[0099] The peripheral carrier absorption portion 103 includes the semiconductor region 21 and the semiconductor layers 33 and 35. The peripheral carrier absorption portion 103 absorbs carriers located in the periphery of the semiconductor layer 33. That is, the semiconductor layer 33 functions as a peripheral carrier absorption layer that absorbs peripheral carriers. In this modification, the peripheral carrier absorption portion 103 is a portion of the semiconductor substrate 10F that is surrounded by edges 103a and 103b of the peripheral carrier absorption layer when viewed from a direction perpendicular to the main surface 10a. In this embodiment, the edges 103a and 103b are edges of the semiconductor layer 33. The edge 103b is located closer to the APD 101 than the edge 103a.

[0100] In the semiconductor substrate 10F, the semiconductor layer 36 is located between the semiconductor region 21 and the semiconductor layer 35. In other words, the semiconductor layer 36 is in contact with the semiconductor region 21 on the principal surface 10a side and in contact with the semiconductor layer 35 on the principal surface 10b side. In this modification, the impurity concentration of the semiconductor layer 36 of the temperature compensation diode 102 is lower than the impurity concentration of the semiconductor layer 36 of the APD 101.

[0101] In the semiconductor substrate 10F, the semiconductor region 21 and the semiconductor layers 31, 33, and 36 are of the first conductivity type, and the semiconductor layers 34 and 35 are of the second conductivity type. In this modification, the first conductivity type is P type, and the second conductivity type is N type. When the semiconductor substrate 10F is based on Si, a Group 13 element such as B is used as the P-type impurity, and a Group 15 element such as N, P, or As is used as the N-type impurity.

[0102] In the semiconductor substrate 10F, the semiconductor layers 31 and 33 have a higher impurity concentration than the semiconductor region 21. The semiconductor layer 36 has a higher impurity concentration than the semiconductor region 21 and a lower impurity concentration than the semiconductor layers 31 and 33. Specifically, the semiconductor region 21 is, for example, P - The semiconductor layers 31 and 33 are, for example, P + The semiconductor layer 31 constitutes the anode of each of the APD 101 and the temperature compensation diode 102.

[0103] In the semiconductor substrate 10F, the semiconductor layer 34 has the same impurity concentration as the semiconductor layer 35. The semiconductor layers 34 and 35 are, for example, N + The semiconductor layers 34 and 35 form the cathode of the photodetector 1F. The semiconductor layers 34 and 35 form the cathodes of the APD 101, the temperature compensation diode 102, and the peripheral carrier absorption unit 103, for example.

[0104] In this modification, a quenching resistor 105 is provided on a part of the electrode 42. The quenching resistor 105 is a resistor for detecting the P + The quenching resistor 105 is electrically connected to the semiconductor layer 31 of the semiconductor device 100. The quenching resistor 105 is electrically connected to the pad electrode 52 on the side opposite to the semiconductor layer 31. In this modification, the pad electrode 52 is a pad electrode for the anode of the APD 101. The pad electrode 53 is a pad electrode for the anode of the temperature compensation diode 102. The pad electrode 54 is a pad electrode for the anode of the peripheral carrier absorption unit 103. The pad electrode 55 is a pad electrode for the cathodes of the APD 101, the temperature compensation diode 102, and the peripheral carrier absorption unit 103.

[0105] The APD 101, the temperature compensation diode 102, and the peripheral carrier absorption unit 103 are connected in parallel to the pad electrode 55. When a reverse bias is applied to the APD 101, the temperature compensation diode 102, and the peripheral carrier absorption unit 103, a positive voltage is applied to the anode pad electrode, and a negative voltage is applied to the cathode pad electrode.

[0106] When viewed from a direction perpendicular to the main surface 10a, on the line segment connecting the APD 101 and the temperature compensating diode 102 at the shortest distance, the shortest distance between the APD 101 and the peripheral carrier absorption section 103 is smaller than the shortest distance between the portion 103c of the peripheral carrier absorption section 103 and the temperature compensating diode 102. The portion 103c is the portion of the edges 103a, 103b of the peripheral carrier absorption section 103 that is closest to the APD 101 on the line segment connecting the APD 101 and the temperature compensating diode 102 at the shortest distance. In other words, when viewed from a direction perpendicular to the main surface 10a, the portion 103c is the portion of the edge 103b of the peripheral carrier absorption section 103 that is closest to the temperature compensating diode 102.

[0107] More specifically, on a line segment connecting the semiconductor layer 31 of the APD 101 and the semiconductor layer 31 of the temperature compensation diode 102 at the shortest distance when viewed from a direction perpendicular to the main surface 10a, the distance L1 is smaller than the distance L2. The distance L1 is the shortest distance between the semiconductor layer 31 of the APD 101 and the peripheral carrier absorption portion 103 when viewed from a direction perpendicular to the main surface 10a. The distance L2 is the shortest distance between the portion 103c of the peripheral carrier absorption portion 103 and the semiconductor layer 31 of the temperature compensation diode 92 when viewed from a direction perpendicular to the main surface 10a. L2 / L1 is, for example, greater than 1 and equal to or less than 50. L2 / L1 may be equal to or greater than 20 and equal to or less than 50.

[0108] 11, on the line segment connecting the semiconductor layer 36 of the APD 101 and the semiconductor layer 36 of the temperature compensation diode 102 at the shortest distance when viewed from the direction perpendicular to the main surface 10a, the distance L3 is smaller than the distance L4. When viewed from the direction perpendicular to the main surface 10a, the distance L3 is the shortest distance between the semiconductor layer 36 of the APD 101 and the peripheral carrier absorption unit 103. When viewed from the direction perpendicular to the main surface 10a, the distance L4 is the shortest distance between the portion 103c of the peripheral carrier absorption unit 103 and the semiconductor layer 36 of the temperature compensation diode 102.

[0109] Next, the operation of a photodetector including a semiconductor substrate 10F will be described with reference to Fig. 12. The photodetector 1F is used in a state where a power supply 61 and a current limiting circuit 62 are connected to a pad electrode 55, similar to the photodetector 1. In the photodetector 1F, the negative side of the power supply 61 is connected to a ground 63, and the positive side is connected to the pad electrode 55 via the current limiting circuit 62. The pad electrodes 53 and 54 are connected to grounds 64 and 65, respectively. The grounds 64 and 65 may be connected to each other. The pad electrode 52 is connected to a signal readout circuit (not shown).

[0110] In this modification, the pad electrode 55 is N + The semiconductor layer 34 is connected to the N + The cathodes of the APD 101, the temperature compensation diode 102, and the peripheral carrier absorption unit 103 are connected in parallel to the pad electrode 55. As a result, a positive potential is applied to the cathodes of the APD 101, the temperature compensation diode 102, and the peripheral carrier absorption unit 103 by the power supply 61.

[0111] The difference between the potential applied to the pad electrode 53 and the potential applied to the pad electrode 55 is the breakdown voltage of the temperature compensation diode 102. Therefore, a potential corresponding to the breakdown voltage applied to the temperature compensation diode 102 is applied to the cathode of the APD 101. As a result, a voltage corresponding to the breakdown voltage applied to the temperature compensation diode 102 is applied to the APD 101 as a bias voltage. Similarly, a voltage corresponding to the breakdown voltage applied to the temperature compensation diode 102 is also applied to the cathode of the peripheral carrier absorbing unit 103 as a bias voltage.

[0112] In this modification, the combination of the power supply 61 and the current limiting circuit 62 is connected to the pad electrode 55, so that the breakdown voltage of the temperature compensation diode 102 is applied to the pad electrode 55. Therefore, the breakdown voltage of the temperature compensation diode 102 is applied to the APD 101 and the peripheral carrier absorbing section 103 as a bias voltage. In this modification, the output voltage of the power supply 61 is equal to or higher than the operating voltage of the APD 101. In other words, the output voltage of the power supply 61 is equal to or higher than the upper limit of the temperature fluctuation of the breakdown voltage of the temperature compensation diode 102. For example, the output voltage of the power supply 61 is equal to or higher than 300V. The current limiting circuit 62 is formed of, for example, a current mirror circuit or a resistor. In this case, the multiplication factor of the APD 101 can be set arbitrarily according to the breakdown voltage difference between the temperature compensation diode 102 and the APD 101. If the amplification factor of the APD 101 is set to an optimal multiplication factor Mopt with a high S / N ratio, the detection accuracy can be improved.

[0113] In this modification, the APD 101, the temperature compensation diode 102, and the cathode of the peripheral carrier absorption unit 103 are integrally formed by the semiconductor layer 35. For example, at an ambient temperature of 25° C., if the potential applied to the pad electrode 53 is 0 V and the breakdown voltage of the temperature compensation diode 12 is 50 V, a potential of +50 V is applied to the cathode of the APD 101 and the cathode of the peripheral carrier absorption unit 13. If the breakdown voltage of the APD 101 is 48 V at an ambient temperature of 25° C., the APD 101 operates in a state where the potential difference between the anode and the cathode is 2 V higher than the breakdown voltage.

[0114] The APD 101 and the temperature compensating diode 102 have the same temperature characteristics regarding the relationship between the gain and the bias voltage. Therefore, as long as the temperature compensating diode 102 is in a breakdown state, the APD 101 operates while maintaining the gain when a bias voltage 2 V higher than the breakdown voltage is applied at an ambient temperature of 25° C. In other words, in the photodetector 1F, a voltage that brings the temperature compensating diode 102 into a breakdown state is applied to the temperature compensating diode 102, thereby realizing temperature compensation for the gain of the APD 101.

[0115] In this modification, a configuration has been described in which a so-called reverse type APD 101 operates in Geiger mode. The photodetector 1F may be configured in which the reverse type APD 101 operates in linear mode. In a configuration in which the APD 101 operates in linear mode, the quenching resistor 105 is not required. The semiconductor substrate 10F is configured so that the impurity concentration of the semiconductor layer 36 of the temperature compensation diode 102 is higher than the impurity concentration of the semiconductor layer 36 of the APD 101.

[0116] Next, the effects of the photodetector in the above-mentioned embodiment and modified example will be described. The photodetector 1 is used for various purposes. Therefore, it is required to ensure the detection accuracy of the photodetector 1 in an environment according to each purpose. For example, when the photodetector 1 is used for an in-vehicle purpose, it is required to ensure the detection accuracy in a high-temperature environment of 100°C or more. However, in such a high-temperature environment, carriers are generated by heat in the semiconductor substrate 10 constituting the APD 11. Therefore, if the generated carriers reach the APD 11, photon shot noise occurs in the detection result of the APD 11.

[0117] In the semiconductor substrate 10, 10A of the photodetector 1, the peripheral carrier absorption portion 13 surrounds the APD 11 when viewed from a direction perpendicular to the main surface 10a. This prevents carriers generated in the semiconductor substrate 10, 10A from reaching the APD 11 in a high-temperature environment, improving detection accuracy. In the semiconductor substrate 10F, the peripheral carrier absorption portion 103 surrounds the APD 101 when viewed from a direction perpendicular to the main surface 10a. This prevents carriers generated in the semiconductor substrate 10F from reaching the APD 101 in a high-temperature environment, improving detection accuracy.

[0118] In the semiconductor substrate 10B, the peripheral carrier absorption portion 83 surrounds the APD array 80 when viewed from a direction perpendicular to the main surface 10a. In the semiconductor substrate 10C, the peripheral carrier absorption portion 88 surrounds the APD array 85a, and the peripheral carrier absorption portion 89 surrounds the APD array 85b when viewed from a direction perpendicular to the main surface 10a. In the semiconductor substrate 10D, the peripheral carrier absorption portion 93 surrounds the APD array 90 when viewed from a direction perpendicular to the main surface 10a. In the semiconductor substrate 10E, the peripheral carrier absorption portion 98 surrounds the APD array 95 when viewed from a direction perpendicular to the main surface 10a. Therefore, carriers generated in the semiconductor substrates 10B, 10C, 10D, and 10E are prevented from reaching the APD arrays 80, 85a, 85b, 90, and 95 in a high-temperature environment, and detection accuracy is improved.

[0119] Conventionally, when manufacturing a photodetector having an APD and a temperature compensation diode having the same temperature characteristics, an inspection was required to select and combine an APD having a desired temperature characteristic regarding the relationship between the gain and the bias voltage. This made it difficult to reduce costs. In this regard, in the photodetector 1, 1F, the APDs 11, 81, 86, 91, 96, 101 and the temperature compensation diodes 12, 82, 87, 92, 97, 102 are formed on the same semiconductor substrate 10, 10A, 10B, 10C, 10D, 10E, 10F, respectively. In this case, the temperature compensation diodes 12, 82, 87, 92, 97, 102 and the APDs 11, 81, 86, 91, 96, 101 having equivalent temperature characteristics over a wide temperature range for the gain and bias voltage can be formed more easily and with higher accuracy than when the temperature compensation diodes 12, 82, 87, 92, 97, 102 and the APDs 11, 81, 86, 91, 96, 101 are formed on different semiconductor substrates. Therefore, temperature compensation for the gain can be realized while keeping manufacturing costs down.

[0120] When a breakdown voltage is applied to the temperature compensation diodes 12, 82, 87, 92, 97, 102, the temperature compensation diodes 12, 82, 87, 92, 97, 102 may emit light. When the temperature compensation diodes 12, 82, 87, 92, 97, 102 emit light, carriers are generated in the semiconductor substrate by the light emitted by the temperature compensation diodes 12, 82, 87, 92, 97, 102. Therefore, when the temperature compensation diodes 12, 82, 87, 92, 97, 102 and the APDs 11, 81, 86, 91, 96, 101 are formed on the same semiconductor substrate, the carriers may affect the detection results of the APDs 11, 81, 86, 91, 96, 101.

[0121] In the semiconductor substrates 10 and 10A of the photodetector 1, the peripheral carrier absorption portion 13 is located between the APD 11 and the temperature compensation diode 12. When viewed from a direction perpendicular to the main surface 10a, on a line segment connecting the APD 11 and the temperature compensation diode 12 at the shortest distance, the shortest distance between the APD 11 and the peripheral carrier absorption portion 13 is shorter than the shortest distance between a portion 13c of the peripheral carrier absorption portion 13 and the temperature compensation diode 12.

[0122] Similarly, in the semiconductor substrate 10B, the peripheral carrier absorption portion 83 is located between the APD array 80 and the temperature compensating diode 82. In the semiconductor substrate 10C, the peripheral carrier absorption portion 88 is located between the APD array 85a and the temperature compensating diode 87, and the peripheral carrier absorption portion 89 is located between the APD array 85b and the temperature compensating diode 87. In the semiconductor substrate 10D, the peripheral carrier absorption portion 93 is located between the APD array 90 and the temperature compensating diode 92. In the semiconductor substrate 10E, the peripheral carrier absorption portion 98 is located between the APD array 95 and the temperature compensating diode 97. In the semiconductor substrate 10F, the peripheral carrier absorption portion 103 is located between the APD 101 and the temperature compensating diode 102.

[0123] For example, on the line segment connecting the APD 11 and the temperature compensating diode 12 at the shortest distance when viewed from a direction perpendicular to the main surface 10a, a distance L1 between the semiconductor layer 31 of the APD 11 and the peripheral carrier absorption portion 13 is smaller than a distance L2 between a portion 13c of the peripheral carrier absorption portion 13 and the semiconductor layer 31 of the temperature compensating diode 12. On the line segment connecting the APD 11 and the temperature compensating diode 12 at the shortest distance when viewed from a direction perpendicular to the main surface 10a, a distance L3 between the semiconductor layer 32 of the APD 11 and the peripheral carrier absorption portion 13 is smaller than a distance L4 between the portion 13c of the peripheral carrier absorption portion 13 and the semiconductor layer 32 of the temperature compensating diode 12. In the semiconductor substrate 10F of the photodetector 1F, when viewed from a direction perpendicular to the main surface 10a, on the line segment connecting the APD 101 and the temperature compensation diode 102 at the shortest distance, the distance L3 between the semiconductor layer 36 of the APD 101 and the peripheral carrier absorption portion 103 is smaller than the distance L4 between the portion 103c of the peripheral carrier absorption portion 103 and the semiconductor layer 36 of the temperature compensation diode 102.

[0124] In these configurations, carriers generated by the emission of the temperature compensation diodes 12, 82, 87, 92, 97, 102 are absorbed by the peripheral carrier absorption section 13, 83, 88, 89, 93, 98, 103 before reaching the APD 11, 81, 86, 91, 96, 101. As a result, carriers caused by the temperature compensation diodes 12, 82, 87, 92, 97, 102 are prevented from reaching the APD 11, 81, 86, 91, 96, 101, and detection accuracy is improved. Therefore, in the above-mentioned photodetector 1, 1F, temperature compensation for the multiplication factor is realized while suppressing manufacturing costs, and detection accuracy is improved. L2 / L1 is, for example, greater than 1 and equal to or less than 50. L2 / L1 may be equal to or greater than 20 and equal to or less than 50. In this case, carriers originating from the temperature compensation diodes 12, 82, 87, 92, 97, and 102 are further prevented from reaching the APDs 11, 81, 86, 91, 96, and 101.

[0125] The photodetector 1, 1F includes electrodes 42, 43, 44, and 45. As shown in FIG. 1 and FIG. 11, for example, the electrode 42 is connected to the APD 11, 101 and outputs a signal from the APD 11, 101. The electrode 43 is connected to the temperature compensation diode 12, 102, and the electrode 44 is connected to the peripheral carrier absorption unit 13, 103. In this case, a desired potential can be applied to each of the APD 11, 101, the temperature compensation diode 12, 102, and the peripheral carrier absorption unit 13, 103. In this way, when a voltage is applied to the peripheral carrier absorption unit 13, 83, 88, 89, 93, 98, and 103, carriers generated due to the temperature compensation diode 12, 82, 87, 92, 97, and 102 can be further absorbed.

[0126] In each of the semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, and 10F, the APDs 11, 81, 86, 91, 96, and 101, the temperature compensation diodes 12, 82, 87, 92, 97, and 102, and the peripheral carrier absorption units 13, 83, 88, 89, 93, 98, and 103 are connected in parallel to the electrode 45. For example, since the APD 11 and the temperature compensation diode 12 are connected in parallel, a potential corresponding to the breakdown voltage of the temperature compensation diode 12 can be applied to the APD 11. Since the peripheral carrier absorption unit 13 is also connected in parallel to the APD 11 and the temperature compensation diode 12, a potential can be applied to the peripheral carrier absorption unit 13 without providing a separate power supply. When a voltage is applied to the peripheral carrier absorbing portions 13, 83, 88, 89, 93, 98, and 103, the carriers generated due to the temperature compensation diodes 12, 82, 87, 92, 97, and 102 can be further absorbed.

[0127] As shown in FIG. 1, the semiconductor substrate 10 includes a semiconductor region 21 of a first conductivity type. The APD 11 and the temperature compensation diode 12 each include a semiconductor layer 31 and a semiconductor layer 32. The semiconductor layer 31 is of a second conductivity type. The semiconductor layer 32 is of a first conductivity type having a higher impurity concentration than the semiconductor region 21. The semiconductor layer 32 is located between the semiconductor region 21 and the semiconductor layer 31. In this manner, the temperature compensation diodes 12, 82, 87, 92, and 97 have the same configuration as the APDs 11, 81, 86, 91, and 96. For this reason, it is possible to easily form the temperature compensation diodes 12, 82, 87, 92, and 97 whose temperature characteristics regarding the gain and bias voltage are very similar to those of the APDs 11, 81, 86, 91, and 96.

[0128] In the semiconductor substrates 10, 10A, 10B, 10C, 10D, and 10E having the reach-through APDs 11, 81, 86, 91, and 96, respectively, the peripheral carrier absorption portions 13, 83, 88, 89, 93, and 98 include the second conductivity type semiconductor layer 33. Therefore, the peripheral carrier absorption portions 13, 83, 88, 89, 93, and 98 can further absorb carriers generated due to the temperature compensation diodes 12, 82, 87, 92, and 97.

[0129] The semiconductor substrate 10F includes a semiconductor region 21 of a first conductivity type. The APD 101 and the temperature compensation diode 102 include a semiconductor layer 35 and a semiconductor layer 36, respectively. In the semiconductor substrate 10F, the semiconductor layer 35 is of a second conductivity type. The semiconductor layer 36 is of a first conductivity type having a higher impurity concentration than the semiconductor region 21. The semiconductor layer 36 is located between the semiconductor region 21 and the semiconductor layer 35. In this manner, the temperature compensation diode 102 has the same configuration as the APD 101. For this reason, it is possible to easily form the temperature compensation diode 102 whose temperature characteristics regarding the gain and bias voltage are very similar to those of the APD 101.

[0130] In the semiconductor wafer 10F having the reverse-type APD 101, the peripheral carrier absorption portion 103 includes the first conductivity type semiconductor layer 33. Therefore, the peripheral carrier absorption portion 103 can absorb more carriers generated due to the temperature compensation diode 102.

[0131] In the semiconductor substrates 10, 10A, 10B, 10C, 10D, and 10E, the impurity concentration in the semiconductor layer 32 of the temperature compensation diode 12, 82, 87, 92, and 97 is higher than the impurity concentration in the semiconductor layer 32 of the APD 11, 81, 86, 91, and 96. In this case, in the photodetector 1, for example, the breakdown voltage of the APD 11, 81, 86, 91, and 96 is higher than the breakdown voltage of the temperature compensation diode 12, 82, 87, 92, and 97. As a result, temperature compensation for the multiplication factor of the APD 11, 81, 86, 91, and 96 operating in the linear mode is realized. When the APD 101 of the semiconductor substrate 10F is operated in the linear mode, the semiconductor substrate 10F is configured so that the impurity concentration in the semiconductor layer 36 of the temperature compensation diode 102 is higher than the impurity concentration in the semiconductor layer 36 of the APD 101. In this case, for example, the breakdown voltage of the APD 101 is greater than the breakdown voltage of the temperature compensation diode 102 in the photodetector 1F.

[0132] In the semiconductor substrate 10F, the impurity concentration in the semiconductor layer 36 of the temperature compensation diode 102 may be lower than the impurity concentration in the semiconductor layer 36 of the APD 101. In this case, for example, in the photodetector 1F, the breakdown voltage of the APD 101 may be lower than the breakdown voltage of the temperature compensation diode 102. As a result, temperature compensation for the multiplication factor of the APD 101 operating in the Geiger mode may be realized. When the APDs 11, 81, 86, 91, and 96 of the semiconductor substrates 10, 10A, 10B, 10C, 10D, and 10E are operated in the Geiger mode, the semiconductor substrates 10, 10A, 10B, 10C, 10D, and 10E are configured such that the impurity concentration in the semiconductor layer 32 of the temperature compensation diodes 12, 82, 87, 92, and 97 is lower than the impurity concentration in the semiconductor layer 32 of the APDs 11, 81, 86, 91, and 96. In this case, in the photodetector 1, for example, the breakdown voltage of the APDs 11, 81, 86, 91, and 96 is smaller than the breakdown voltage of the temperature compensation diodes 12, 82, 87, 92, and 97.

[0133] Next, an example of a method for manufacturing the photodetector will be described with reference to Fig. 13. Fig. 13 is a flowchart showing a method for manufacturing the semiconductor substrate 10 of the photodetector 1.

[0134] First, a semiconductor wafer is prepared (step S1). The semiconductor wafer is a substrate before being processed into a semiconductor substrate 10, and has main surfaces 10a and 10b facing each other. The semiconductor wafer includes a semiconductor region of a first conductivity type corresponding to the semiconductor region 21. The semiconductor region is provided on the main surface 10a side of the semiconductor wafer, and constitutes the entire surface of the main surface 10a. For example, the semiconductor region of the semiconductor wafer may be a P - In this embodiment, a semiconductor layer 35 of the first conductivity type having a higher impurity concentration than the semiconductor region of the semiconductor wafer is formed in the semiconductor wafer by adding impurities from the main surface 10b side. For example, the semiconductor layer 35 is P + It is a type.

[0135] Subsequently, in a first ion implantation step (step S2), impurity ions are implanted into the main surface 10a side by ion implantation to add impurities, thereby forming the second conductive type semiconductor layers 31 and 33 and the first conductive type semiconductor layers 32 and . + semiconductor layer 32 is P-type, and semiconductor layer 34 is P + In this embodiment, the semiconductor layer 31 and the semiconductor layer 33 are formed by injecting impurity ions of the second conductivity type into different locations spaced apart from each other in a single ion implantation process. The semiconductor layer 32 is formed by injecting impurity ions of the first conductivity type after the semiconductor layers 31 and 33 are formed. The semiconductor layer 32 may be formed by injecting impurity ions of the first conductivity type before the semiconductor layers 31 and 33 are formed.

[0136] The semiconductor layers 31 and 32 are formed at positions overlapping each other when viewed from a direction perpendicular to the main surface 10a. The semiconductor layer 32 is formed by implanting a first conductive type impurity into a position deeper than the semiconductor layer 31 when viewed from the main surface 10a side. The semiconductor layers 31 and 32 are formed at a plurality of positions separated from each other when viewed from a direction perpendicular to the main surface 10a in a region that becomes one semiconductor substrate 10. The plurality of positions include a position where the APD 11 is disposed and a position where the temperature compensation diode 12 is disposed. In the first ion implantation process, the second conductive type impurity is doped at each position so that the impurity concentration of the semiconductor layer 31 is uniform. Similarly, the first conductive type impurity is doped at each position so that the impurity concentration of the semiconductor layer 32 is uniform.

[0137] Next, in a second ion implantation step (step S3), impurities are further added to the semiconductor layer 32 only at some of the above-mentioned multiple locations by an ion implantation method. In this embodiment, impurities of the first conductivity type are further implanted into the semiconductor layer 32 only at the locations where the temperature compensation diode 12 is disposed. Therefore, in the photodetector 1, the impurity concentration in the semiconductor layer 32 of the temperature compensation diode 12 is higher than the impurity concentration in the semiconductor layer 32 of the APD 11. In this case, the photodetector 1 is configured so that the breakdown voltage of the APD 11 is higher than the breakdown voltage of the temperature compensation diode 12.

[0138] In the second ion implantation step, impurities of the first conductivity type may be further implanted into the semiconductor layer 32 only in the location where the APD 11 is disposed, not in the location where the temperature compensation diode 12 is disposed. In this case, in the photodetector 1, the impurity concentration in the semiconductor layer 32 of the temperature compensation diode 12 is lower than the impurity concentration in the semiconductor layer 32 of the APD 11. In this case, the photodetector is configured so that the breakdown voltage of the APD 11 is smaller than the breakdown voltage of the temperature compensation diode 12.

[0139] Through the above steps, the semiconductor substrate 10 of the photodetector 1 is formed. In this embodiment, the semiconductor layers 31, 32, 33, and 34 are formed after the semiconductor layer 35 has already been formed. However, the semiconductor layer 35 may be formed after the semiconductor layers 31, 32, 33, and 34 are formed.

[0140] In the above manufacturing method, ions are implanted into a plurality of different locations to form the semiconductor layer 31 and the semiconductor layer 32 at each location. After that, ions are further implanted into the semiconductor layer 32 at some locations. Therefore, the temperature compensation diode 12 and the APD 11 can be easily manufactured, which have the same temperature characteristics with respect to the multiplication factor and the bias voltage, and are set to the desired breakdown voltage. In this case, for example, the multiplication factor of the APD 11 can be arbitrarily set according to the breakdown voltage difference between the temperature compensation diode 12 and the APD 11. Therefore, if the temperature compensation diode 12 and the APD 11 are set to the desired breakdown voltage, the detection accuracy can be improved. For example, if the multiplication factor of the APD 11 is set to an optimal multiplication factor Mopt with a high S / N ratio according to the breakdown voltage difference between the temperature compensation diode 12 and the APD 11, the detection accuracy can be improved. In this way, in the above manufacturing method, temperature compensation for the multiplication factor is realized while suppressing the manufacturing cost, and the detection accuracy can be improved.

[0141] In this embodiment, in the first ion implantation step, the semiconductor layer 31 and the semiconductor layer 33 are formed by a single ion implantation process. Therefore, the peripheral carrier absorption portion 13 is formed without increasing the number of ion implantation steps. Therefore, the manufacturing cost is reduced.

[0142] The above describes the embodiments and modifications of the present invention, but the present invention is not necessarily limited to the above-described embodiments and modifications, and various modifications are possible without departing from the spirit of the present invention.

[0143] For example, the above-described manufacturing method can be applied not only to the manufacturing of the semiconductor substrate 10 of the photodetector 1 but also to the manufacturing of the semiconductor substrates 10A, 10B, 10C, 10D, and 10E. The above-described manufacturing method can be applied not only to the manufacturing of the photodetector 1 but also to the manufacturing of the photodetector 1F.

[0144] In the semiconductor substrates 10B, 10C, 10D, and 10E, the peripheral carrier absorption portion may surround each of the APDs included in the APD array. In other words, the peripheral carrier absorption portion may surround each of the APDs included in the APD array. Any APD included in the APD array may be used as a temperature compensation diode. In this case, carriers generated from the APD used as the temperature compensation diode are prevented from reaching the other APDs.

[0145] In the above-described modified example, the semiconductor substrate 10F includes the semiconductor layer 36. However, the APD 101 of the semiconductor substrate 10F does not need to include the semiconductor layer 36 and still functions as an APD. In a configuration in which the semiconductor substrate 10F does not include the semiconductor layer 36, for example, the semiconductor region 21 and the semiconductor layer 35 are in contact with each other without the semiconductor layer 36 sandwiched therebetween. [Explanation of symbols]

[0146] 1, 1F... Light detection device, 10, 10A, 10B, 10C, 10D, 10E, 10F... Semiconductor substrate, 10a, 10b... Main surface, 11, 81, 81a, 86, 86a, 91, 91a, 96, 96a, 101... APD, 11a, 101a... Light incidence surface, 12, 82, 87, 92, 97, 102... Temperature compensation diode, 13, 83, 88, 89, 93, 98, 103... Peripheral carrier absorption Collection, 13a, 13b, 83a, 83b, 88a, 88b, 89a, 89b, 93a, 93b, 98a, 98b, 103a, 103b...Edge, 13c, 83c, 88c, 89c, 103c ...part, 21...semiconductor region, 31,32,33,36...semiconductor layer, 42,43,44,45...electrode, 80,85a,85b,90,95...APD array, L1,L2,L3,L4...distance.

Claims

1. A light detection device, The semiconductor substrate has a first main surface and a second main surface facing each other, and an avalanche photodiode and a temperature compensation diode are formed on it spaced apart from each other when viewed from a direction perpendicular to the first main surface. The semiconductor substrate surrounds the avalanche photodiode when viewed from a direction perpendicular to the first main surface, and has a peripheral carrier absorption portion that absorbs carriers located around it. A portion of the peripheral carrier absorption section is located between the avalanche photodiode and the temperature compensation diode when viewed from a direction perpendicular to the first main surface. By applying a voltage corresponding to the breakdown voltage applied to the temperature compensation diode as a bias voltage to the avalanche photodiode, the temperature compensation for the multiplication factor of the avalanche photodiode is performed. The temperature compensation diode is not surrounded by the peripheral carrier absorption section.

2. A light detection device according to claim 1, An avalanche photodiode array, including the avalanche photodiode, is formed on the first main surface side of the semiconductor substrate. The peripheral carrier absorption section surrounds the avalanche photodiode array when viewed from a direction perpendicular to the first main surface. A portion of the peripheral carrier absorption section is located between the avalanche photodiode array and the temperature compensation diode when viewed from a direction perpendicular to the first main surface.

3. A light detection device according to claim 1 or 2, A first electrode connected to the avalanche photodiode and outputting a signal from the avalanche photodiode, A second electrode connected to the temperature compensation diode, The system comprises a third electrode connected to the aforementioned peripheral carrier absorption section.

4. A light detection device according to claim 3, The avalanche photodiode, the temperature compensation diode, and the peripheral carrier absorption section are connected in parallel to each other to form a fourth electrode.

5. A light detection device according to any one of claims 1 to 4, The semiconductor substrate includes a first-conductivity semiconductor region. The avalanche photodiode and the temperature compensation diode each include a first semiconductor layer of a second conductivity type different from the first conductivity type, and a second semiconductor layer of the first conductivity type disposed between the semiconductor region and the first semiconductor layer, and having a higher impurity concentration than the semiconductor region.

6. The photodetector according to claim 5, The peripheral carrier absorption portion includes the third semiconductor layer of the second conductivity type.

7. The photodetector according to claim 5, The peripheral carrier absorption portion includes the third semiconductor layer of the first conductivity type.

8. A light detection device according to claim 6 or 7, The impurity concentration in the second semiconductor layer of the temperature compensation diode is higher than the impurity concentration in the second semiconductor layer of the avalanche photodiode.

9. A light detection device according to any one of claims 6 to 8, The impurity concentration in the second semiconductor layer of the temperature compensation diode is lower than the impurity concentration in the second semiconductor layer of the avalanche photodiode.

10. A method for manufacturing a photodetector according to any one of claims 1 to 9, A step of preparing a semiconductor wafer having the first main surface and including a semiconductor region of the first conductivity type, A first ion implantation step in which ions are implanted into a semiconductor wafer at a first location and a second location spaced apart from each other when viewed from a direction perpendicular to the first main surface, thereby forming a first semiconductor layer of a second conductivity type different from the first conductivity type and a second semiconductor layer of the first conductivity type located between the semiconductor region and the first semiconductor layer and having a higher impurity concentration than the semiconductor region, respectively at the first location and the second location. The method includes a second ion implantation step of further implanting ions into the second semiconductor layer at the first location.

11. A method for manufacturing a light detection device according to claim 10, The first ion implantation step is, A step of forming the first semiconductor layer in each of the first and second locations and the third semiconductor layer in the third location by implanting the second conductivity type impurity ions into the first location and the second location and a third location spaced apart from the first location and the second location when viewed from a direction perpendicular to the first main surface, in a single ion implantation process, The process includes the step of forming the second semiconductor layer in the first and second locations by implanting the first conductivity type of impurity ions into the first and second locations, respectively.

12. A light detection device, A semiconductor substrate having a first main surface and a second main surface facing each other, The aforementioned semiconductor substrate is A first avalanche photodiode having a light incident surface on the first main surface side, Viewed from a direction perpendicular to the first main surface, a second avalanche photodiode is spaced apart from the first avalanche photodiode and is shielded from light, The first avalanche photodiode is surrounded by a peripheral carrier absorption portion, which, when viewed from a direction perpendicular to the first main surface, absorbs carriers located in the periphery. A portion of the peripheral carrier absorption section is located between the first avalanche photodiode and the second avalanche photodiode when viewed from a direction perpendicular to the first main surface. The second avalanche photodiode is not surrounded by the peripheral carrier absorption region.

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