Structure

Abstract

1. A structure comprising a plurality of III-V nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystalline graphene layer, the graphene layer being supported directly on a crystalline substrate, such as a III-V semiconductor, sapphire, SiC, or diamond substrate, and the epitaxy, crystallographic orientation, and facet orientation of the nanowires or nanopyramids being directed by the crystalline substrate.

Description

[Technical Field]

[0001] This invention relates to the use of a thin polycrystalline or single-crystal graphene layer as a buffer between epitaxially grown nanowires or nanopyramids on a graphene layer and a crystalline substrate. However, epitaxial growth is determined by the crystal orientation of the crystalline substrate in a method called remote epitaxy. This results in an array of nanowires or nanopyramids having parallel facets, i.e., nanowires or nanopyramids whose crystal orientation and facet orientation are determined by the crystalline substrate.

[0002] The resulting structure, optionally separated from the substrate, can be formed, for example, into an LED or photodetector for emitting or detecting light in the visible or UV spectrum, particularly into UV-LEDs and UV photodetectors. The nanowires or nanopyramids preferably have a conductive and ideally reflective top contact electrode material to enable flip-chip configuration.

[0003] In another aspect of the present invention, a structure or device is disclosed characterized by graphene as a hole mask layer. Nanowires / nanopyramids are grown through the pores in the graphene layer and are therefore in direct epitaxial relationship with the underlying substrate, but remote epitaxy can occur for any structure (e.g., nanoislands) grown on the graphene layer (i.e., outside the pores). [Background technology]

[0004] In recent years, as nanotechnology has become an important engineering field, interest in semiconductor nanocrystals (such as nanowires and nanopyramids) has been growing. Nanowires, also known as nanowhiskers, nanorods, nanopillars, or nanocolumns by some authors, have found important applications in various electrical devices such as sensors, solar cells, and light-emitting diodes (LEDs).

[0005] The present invention relates to an LED and a photodetector that emit or detect light such as visible light, preferably in the ultraviolet (UV) spectrum. Ultraviolet light can be classified into three different wavelength types: UV-A: 315~400nm, UV-B: 280~315nm, and UV-C: 100~280nm.

[0006] This invention relates to UV-LEDs based on nanowires or nanopyramids, rather than films of semiconductor materials. Ideally, the inventors are exploring UV-LEDs based on AlGaN, AlN, or AlInGaN nanowires or nanopyramids. AlGaN or AlInGaN nanowire or nanopyramid-based materials are ideal for realizing LEDs that cover the entire UV-A, UV-B, and UV-C bands.

[0007] The inventors propose a solution involving growing nanowires (NWs) or nanopyramids (NPs) on a specific crystalline substrate covered with a thin graphene layer. In particular, the inventors are investigating the growth of AlN / AlGaN / AlInGaN NWs or NPs on a graphene layer. Graphene functions as a transparent and conductive contact for the NWs or NPs. Because graphene is transparent across the entire ultraviolet wavelength range, especially in the UV-C wavelength region, it can be used as a bottom contact for NW or NP-based UV-LED devices.

[0008] Growing nanowires on graphene is not a new concept. Patent Document 1 discusses growing semiconductor nanowires on a graphene substrate using molecular beam epitaxy (MBE). Patent Document 2 concerns an improvement on the disclosure of Patent Document 1, using graphene top contacts on the graphene-grown nanowires. However, these prior art documents do not relate to UV-LED flip chips. More recently, core-shell nanowires grown on graphene have been disclosed (Patent Document 3).

[0009] However, the use of nanowires grown on graphene for LEDs such as UV-LEDs is known from Patent Document 4. However, in all of these disclosures, the growth of the nanowires is determined by the lattice matching between the graphene layer and the NW or NP, rather than the lattice matching with the underlying substrate.

[0010] Surprisingly, it has been found that when a very thin layer of graphene is used, nanowires / nanopyramids can be grown epitaxially, and the crystal orientation of the nanowires / nanopyramids coincides with that of the underlying substrate rather than the graphene layer. Thus, although the graphene layer functions as a buffer between the substrate and the nanowires or nanopyramids, growth occurs in the crystal direction / facet direction that reflects the substrate rather than the graphene. This is called "remote epitaxy". The resulting nanowire array has facets that are more parallel and regular. This improves the electronic properties of the material.

[0011] Furthermore, remote epitaxy allows for the selection of a substrate that provides a very close lattice match to the nanowires or nanopyramids. The substrate can even be of the same material as the nanowires or nanopyramids. And the nanowires or nanopyramids can be grown defect-free and with a selected orientation.

[0012] Epitaxy - the growth of crystalline materials on a substrate - is important for the semiconductor industry but is often limited by the need for lattice matching between two material systems. It has been found that the weak van der Waals potential of the thin layer of graphene does not completely shield the stronger potential field of the substrate. This makes it possible for epitaxial growth to occur despite the presence of the graphene layer.

[0013] Generally, the lattice constants of III-V semiconductors do not match those of conventional substrates. As understood in the art, the mismatch in lattice constants between the substrate and the epitaxial nanowire introduces strain into the epitaxial nanowire, which may prevent epitaxial growth from occurring without defects. Usually, non-silicon substrates are employed as seeds for the epitaxial growth of most functional semiconductors. However, since non-Si substrates having lattice constants matching those of functional materials are expensive, the development of non-Si electronic / photonic devices may be restricted.

[0014] One way to address the high cost of non-silicon substrates is the "layer transfer" technique, in which the functional device layer is grown on a lattice-matched substrate and then removed and transferred to another substrate. The remaining lattice-matched substrate can then be reused to fabricate another device layer, thereby reducing costs. Patent Document 5 improves on a conventional layer transfer technique using a graphene-based intermediate layer between the lattice-matched substrate and the semiconductor top layer. However, in this document, the upper film is then separated from the graphene layer.

[0015] The inventors have found that a preferred device design includes a flip-chip design in which a graphene layer can be used as the emission side of the LED, thereby improving the light extraction efficiency.

[0016] Furthermore, it is noteworthy that the graphene layer (supporting the nanowires / nanopyramids) can be detached from the substrate, allowing the graphene + nanowire / nanopyramid structure to be separated from the substrate. This is important because the substrate may be an expensive material or may be opaque to light. Once detached from the graphene layer, the substrate can be reused to grow more graphene-supported nanowires / nanopyramids. Moreover, removing the substrate avoids the lack of transparency that may occur due to the presence of the substrate. Thus, the claimed solution solves many problems. Beneficial, defect-free nanowires or nanopyramids can be lattice-matched to the growth substrate, thus providing an ideal means for them. This is achieved in a way that allows for the reuse of potentially expensive crystalline substrates. Within the device, the graphene layer is used as a conductive layer to connect the nanowires.

[0017] Non-patent document 1 describes the possibility of growing a thin film on a GaAs substrate having a graphene buffer layer.

[0018] Non-patent document 2 discloses remote heteroepitaxy of ZnO microrods on a GaN substrate across an entire graphene layer via hydrothermal growth.

[0019] However, previously, no one had considered growing III-V nanowires or nanopyramids on a graphene buffer layer having a substrate that directs the epitaxial growth of nanowires or nanopyramids downwards. Furthermore, an article in Non-Patent Literature 1 suggests that the grown thin film can be separated from the substrate and the graphene layer. Thus, essentially, the graphene layer functions to prevent direct bonding between the substrate and the thin film. Previously, no one had found that the graphene layer could function as an electrode and be separated from the substrate. [Prior art documents] [Patent Documents]

[0020] [Patent Document 1] International Publication No. 2012 / 080252 [Patent Document 2] International Publication No. 2013 / 104723 [Patent Document 3] International Publication No. 2013 / 190128 [Patent Document 4] International Publication No. 2017 / 009394 [Patent Document 5] International Publication No. 2017 / 0044577 [Non-patent literature]

[0021] [Non-Patent Document 1] Nature, Vol 544, 30 April 2017 [Non-Patent Document 2] Appl. Phys. Lett. 113, 233103 (2018) [Overview of the project] [Problems that the invention aims to solve]

[0022] The inventors have also found that remote epitaxial effects can be beneficial even if nanowires / nanopyramids are grown through pores in the graphene layer. In certain embodiments of the invention, the structure or device uses graphene as a hole mask layer. NW / NPs grown directly from the substrate within the pores of the graphene layer, and additional nanostructures grown directly on the top surface of the graphene, i.e., outside the pores, can also become epitaxial with the substrate beneath the graphene (or with the intermediate layer between the substrate and the graphene layer) through remote epitaxy. This can result in structural and optical / electrical advantages, particularly if the NW / NPs are grown to coalesce. [Means for solving the problem]

[0023] Therefore, in one embodiment, the present invention is The present invention provides a composition of matter comprising a plurality of III-V nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystal graphene layer, wherein the graphene layer is directly supported on a crystalline substrate such as a III-V semiconductor, sapphire, SiC, or diamond substrate, and the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate.

[0024] The present invention also relates to a method for manufacturing a structure that can be used in the following LEDs and photodetectors. In this embodiment, the present invention (i) Epitaxial growth of III-V nanowires or nanopyramids on a polycrystalline or single-crystal graphene layer directly supported on a crystalline substrate such as a III-V semiconductor, sapphire, SiC, or a sapphire substrate, wherein the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate during epitaxial growth. (ii) A method is provided which includes optionally separating the substrate from the graphene layer having the grown III-V nanowires or nanopyramids.

[0025] The resulting graphene layer / nanowire / nanopyramid structure, with or without a substrate, may be used in the following embodiments of LEDs and photodetectors. In fact, a key feature of the present invention is that the III-V semiconductor nanowires or nanopyramids epitaxially grown on a graphene layer have a crystalline orientation and facet orientation determined by the crystalline substrate on which the nanowires or nanopyramids are grown.

[0026] In another embodiment, the present invention (i) Epitaxial growth of III-V group nanowires or nanopyramids on a polycrystalline or single-crystal graphene layer directly supported on a crystalline substrate such as a III-V group semiconductor, sapphire, SiC, or a sapphire substrate, wherein the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate, and the nanowires or nanopyramids have pn junctions or pin junctions. (ii) A method is provided which includes arbitrarily separating the substrate from the graphene layer.

[0027] In another embodiment, the present invention The method involves epitaxially growing III-V group nanowires or nanopyramids through holes on a hole pattern mask supported on a polycrystalline or single-crystal graphene layer directly supported on a crystalline substrate such as a III-V group semiconductor, sapphire, SiC, or a sapphire substrate, wherein the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate, and the nanowires or nanopyramids have pn junctions or pin junctions during epitaxial growth. (ii) A method is provided which includes arbitrarily separating the substrate from the graphene layer.

[0028] In another embodiment, the present invention Light-emitting diode device, III-V nanowires or nanopyramids epitaxially grown through holes on a hole pattern mask supported on a polycrystalline or single-crystal graphene layer directly supported on a crystalline substrate such as a III-V semiconductor, sapphire, SiC, or a sapphire substrate, wherein the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate, and the nanowires or nanopyramids are III-V nanowires or nanopyramids having pn junctions or pin junctions. A first electrode that is in electrical contact with the graphene layer, The nanowire or nanopyramid comprises a second electrode in contact with at least a portion of its apex and optionally in the form of a light-reflecting layer, The present invention provides a light-emitting diode device in which, when in use, light is emitted from the device in substantially the opposite direction to the light-reflecting layer.

[0029] In another embodiment, the present invention A light-emitting diode device, A plurality of III-V nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystal graphene layer, wherein the graphene layer is directly supported on a crystalline substrate such as a III-V semiconductor, sapphire, SiC, or diamond substrate, and the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate, and the nanowires or nanopyramids are III-V nanowires or nanopyramids having pn junctions or pin junctions. A light-reflecting layer in contact with at least a portion of the top of the nanowire or nanopyramid, and optionally a light-reflecting layer that functions as a second electrode, The device comprises a second electrode electrically in contact with at least a portion of the top of the nanowire or nanopyramid, the second electrode being essential when the light-reflecting layer does not function as an electrode, The present invention provides a light-emitting diode device in which the nanowire or nanopyramid comprises at least one III-V compound semiconductor, and when in use, light is emitted from the device in substantially the opposite direction to the light-reflecting layer.

[0030] In a second embodiment, the present invention relates to a photodetector. The device of the present invention may be configured to detect light by absorbing light and then generating a photocurrent, rather than emitting light.

[0031] Therefore, in another embodiment, the present invention is A light detection device, A plurality of III-V nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystal graphene layer, wherein the graphene layer is directly supported on a crystalline substrate such as a III-V semiconductor, sapphire, SiC, or diamond substrate, and the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate, and the nanowires or nanopyramids are III-V nanowires or nanopyramids having pn junctions or pin junctions. A first electrode that is in electrical contact with the graphene layer, The nanowire or nanopyramid comprises a second electrode in contact with at least a portion of its apex and optionally in the form of a light-reflecting layer, The present invention provides a photodetection device in which the nanowire or nanopyramid comprises at least one III-V compound semiconductor, and light is absorbed by the device during use.

[0032] In another aspect of the present invention, a graphene hole mask is used, and nanowires / nanopyramids are grown directly on a substrate (or on an intermediate layer positioned between the substrate and the graphene layer) through holes in the graphene. Thus, in another aspect of the present invention, A substrate made of sapphire, Si, SiC, Ga2O3, or a III-V semiconductor, A III-V semiconductor intermediate layer is directly placed on the upper surface of the substrate, The intermediate layer comprises a graphene layer directly provided on the upper surface of the intermediate layer, Multiple pores exist that penetrate the graphene layer, The present invention provides a structure in which multiple nanowires or nanopyramids are grown from the intermediate layer within the pores, and the nanowires or nanopyramids contain at least one semiconducting III-V compound.

[0033] In another embodiment, the present invention The graphene layer is directly supported on a substrate of sapphire, Si, SiC, Ga2O3, or a III-V semiconductor. Multiple pores exist that penetrate the graphene layer, The present invention provides a structure in which multiple nanowires or nanopyramids are grown from the substrate within the pores, and the nanowires or nanopyramids contain at least one semiconducting III-V compound.

[0034] In another embodiment, the present invention (I) To obtain a structure in which a graphene layer is directly supported on a III-V intermediate layer, and the intermediate layer is directly supported on a substrate of sapphire, Si, SiC, Ga2O3, or a III-V semiconductor, (II) Etching a plurality of holes penetrating the graphene layer, (III) A method is provided which includes growing a plurality of nanowires or nanopyramids containing at least one semiconductive III-V compound from the intermediate layer within the pores.

[0035] In another embodiment, the present invention (I) To obtain a structure in which a graphene layer is directly supported on a substrate of sapphire, Si, SiC, Ga2O3, or a III-V semiconductor, (II) Etching a plurality of holes penetrating the graphene layer, (III) A method is provided which includes growing a plurality of nanowires or nanopyramids containing at least one semiconductive III-V compound from the substrate within the pores.

[0036] In another embodiment, the present invention provides products obtained by the methods specified above or below. In another embodiment, the present invention provides devices such as optoelectronic devices (e.g., solar cells, photodetectors, or LEDs) comprising the structures specified above or below. [Brief explanation of the drawing]

[0037] [Figure 1] The present invention shows a structure having nanowires grown on a thin polycrystalline or single-crystal graphene layer. [Figure 2] This demonstrates possible flip-chip designs. [Figure 3] This invention presents one possible nanowire. [Figure 4] This shows another chip design where nanowires grow radially and form a core-shell structure. [Figure 5] This shows nanowires that grow radially and have the same constituent elements as those in Figure 3 within the shell structure. [Figure 6] This shows a photodetector. [Figure 7a] This is a theoretical top cross-sectional view of a regular hexagonal array of nanowires on polycrystalline graphene. [Figure 7b] This is a theoretical top cross-sectional view of a hexagonal nanowire grown on polycrystalline graphene. [Figure 8] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs fabricated using this method. [Figure 9] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs fabricated using this method. [Figure 10] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs fabricated using this method. [Figure 11] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs fabricated using this method. [Figure 12] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs fabricated using this method. [Figure 13] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs fabricated using this method. [Figure 14] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs manufactured using this method. [Figure 15a-c] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs manufactured using this method. [Figure 15d] This paper describes experimental results regarding nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and LEDs manufactured using this method. [Modes for carrying out the invention]

[0038] [Definition] A III-V group compound semiconductor means one that contains at least one group III element and at least one group V element. It may contain two or more elements from each group, for example, AlGaN (i.e., a ternary compound), AlInGaN (i.e., a quaternary compound), etc. The notation Al(In)GaN means either AlGaN or AlInGaN, meaning the presence of In is optional. Elements enclosed in parentheses may or may not be included.

[0039] As used herein, the term nanowire refers to a solid wire-like structure of nanometer dimensions. Preferably, a nanowire has a uniform diameter over most of its length, for example, at least 75% of its length. The term nanowire is intended to encompass the use of nanorods, nanopillars, nanocolumns, or nanowhiskers, some of which may have tapered end structures. Essentially, a nanowire can be described as a one-dimensional form whose width or diameter is in nanometer dimensions and whose length is generally in the range of several hundred nanometers to several micrometers. Ideally, the diameter of a nanowire is 50 to 500 nm, but the diameter may exceed several microns (referred to as microwires).

[0040] Ideally, the diameters of the base and top of a nanowire should be approximately the same (for example, within 20% of each other).

[0041] The term nanopyramid refers to a solid pyramidal structure. As used herein, the term pyramidal is used to define a structure having a base and tapering sides toward a single point approximately above the center of the base. It will be understood that a single vertex may appear chamfered, for example, a pyramid may appear to have a flat apex. Generally, the chamfered portion corresponds to less than 50% of the total length of the edge of the nanopyramid, e.g., less than 40%, less than 30%, less than 20%, less than 10%, less than 5%. A nanopyramid may have multiple faces, such as 3 to 8 or 4 to 7. Therefore, the base of a nanopyramid may be square, pentagonal, hexagonal, heptagonal, octagonal, etc. The pyramid is formed such that the faces taper toward the center point from the base (thus forming triangular faces). The triangular faces are typically terminated by (1-101) or (1-102) faces. The triangular faces with (1-101) facets may converge to a single point at the tip, or they may form new facets ((1-102) faces) before converging to the tip. In some cases, the nanopyramid is truncated, with its apex terminated by a {0001} face. The base itself may have portions with a uniform cross-section until it begins to tapere to form a pyramidal structure. Thus, the thickness of the base may be up to 500 nm, for example, up to 200 nm, or 50 nm, etc.

[0042] The base of the nanopyramid can have a diameter of 50 to 500 nm at its widest point. In other embodiments, the base of the nanopyramid can have a diameter of 200 nm to 1 micrometer at its widest point. The height of the nanopyramid may be 200 nm to several microns, and its length may be 400 nm to 1 micron, etc.

[0043] It will be understood that the graphene layer supports multiple nanowires or nanopyramids. This is sometimes referred to as an array of nanowires or nanopyramids.

[0044] The term graphene refers to the sp² crystal structure of a honeycomb crystal. 2 It refers to a planar sheet of bonded carbon atoms. The term graphene layer refers to the sp² of a honeycomb crystal structure. 2 A graphene layer refers to a layer containing one or more planar sheets of bonded carbon atoms. Therefore, in a typical embodiment, the graphene layer is planar, i.e., flat. While graphene is typically used, graphene derivatives can also be used. Graphene derivatives are surface-modified graphenes. For example, hydrogen atoms can bond to the graphene surface to form graphane. Graphene in which oxygen atoms, along with carbon and hydrogen atoms, are bonded to the surface is called graphene oxide. Surface modification may also be affected by chemical doping or oxygen / hydrogen or nitrogen plasma treatment.

[0045] The term epitaxy derives from the Greek word "epi," meaning "above," and "taxis," meaning "in an ordered manner." The atomic arrangement of nanowires or nanopyramids is based on the crystallographic structure of the substrate. In this specification, epitaxial growth means the growth of nanowires or nanopyramids on a thin layer of graphene that follows the orientation of the substrate. This is called remote epitaxy. Therefore, generally, the orientation of nanowires or nanopyramids differs from that of nanowires or nanopyramids that follow the orientation of the graphene layer. Therefore, generally, nanowires / nanopyramids are not lattice-matched with graphene.

[0046] Nanowires / nanopyramids are grown such that their crystal orientation and facet orientation are directed by a crystalline substrate. Therefore, the crystal orientation and facet orientation are identical for all nanowires / nanopyramids.

[0047] When remote epitaxy occurs, the growing nanowire / nanopyramid adopts its crystal (and therefore facet) orientation from the crystalline substrate beneath the graphene layer. Thus, the nanowire / nanopyramid can be considered to have parallel facets (see Figure 7a). On the other hand, when nanowires are epitaxially grown from polycrystalline graphene, the facets of the resulting nanowires are randomly oriented within different domains / particles; that is, the sides (facets) of a hexagonal nanowire may be parallel within one graphene domain / particle, but will be randomly oriented, not parallel, with respect to the sides (facets) of a hexagonal nanowire in adjacent graphene domains / particles (see Figure 7b). The cross-section of the nanowire can be hexagonal or quadrangular, preferably hexagonal. Remote epitaxy occurs when all crystal and facet orientations are the same.

[0048] Remote epitaxy can be used to improve the electrical / optical properties of the final device. Regular arrays of nanowires / nanopyramids contribute to these improvements.

[0049] Therefore, for multiple nanowires / nanopyramids, the orientations of these nanowires / nanopyramids are regular.

[0050] Selective Region Growth (SAG) is a promising method for growing oriented nanowires or nanopyramids. This method differs from self-assembly methods, which use a gas-liquid-solid (VLS) process and utilize a metal catalyst as a nucleation site for nanowire or nanopyramid growth. Another self-assembly method is a catalyst-free method for growing nanowires or nanopyramids, in which the nanowires or nanopyramids are nucleated at random locations. In self-assembly methods, the length and diameter of the nanowires or nanopyramids vary considerably.

[0051] In the SAG method, a mask with a nanohole pattern is generally required on the substrate.

[0052] Therefore, in one embodiment, a graphene layer supports a mask with patterned pores. Nanowires or nanopyramids are nucleated within the pores of the patterned mask on the graphene layer. This results in nanowires or nanopyramids of uniform size and in predetermined locations.

[0053] The term "mask" refers to a masking material deposited directly onto a graphene layer. Ideally, the masking material does not absorb emitted light (which may be visible light, UV-A, UV-B, or UV-C) in the case of an LED, or does not absorb incident light of the object being detected in the case of a photodetector. Preferably, the mask should also be nonconductive. The mask may contain one or more materials, such as Al2O3, SiO2, Si3N4, TiO2, W2O3, etc. Silica masks are particularly preferred. The pore pattern in the masking material can then be fabricated using electron beam lithography or nanoimprint lithography and dry or wet etching. The use of a mask also helps to reinforce the graphene / NW / NP ensemble when removing it from the substrate.

[0054] MBE is a method for forming deposits on a crystalline substrate. The MBE process is carried out by heating the crystalline substrate in a vacuum to activate the substrate's lattice structure. Then, an atomic mass beam or molecular mass beam is directed towards the surface of the substrate. The term "element" used above is intended to encompass the application of atoms, molecules, or ions of that element. When the atoms or molecules directed towards the substrate reach the substrate surface, they collide with the activated lattice structure of the substrate, as will be described in detail below. Over time, the incoming atoms form nanowires or nanopyramids.

[0055] Metallic organometallic vapor deposition (MOVPE), also known as metal-organic chemical vapor deposition (MOCVD), is an alternative to MBE (Metallic Beam Epitaxy) for forming deposits on crystalline substrates. In MOVPE, the deposit material is supplied in the form of an organometallic precursor, which decomposes upon reaching the high temperature of the substrate, leaving atoms on the substrate surface. Furthermore, this method requires a carrier gas (typically H2 and / or N2) to transport the deposit material (atoms / molecules) across the entire substrate surface. These atoms react with other atoms, forming an epitaxial layer on the graphene surface. By carefully selecting the deposition parameters, nanowires or nanopyramids can be formed.

[0056] The term SPSL refers to short-period superlattices.

[0057] It will be understood that nanowires or nanopyramids preferably have pn junctions or pin junctions. The orientation of the junction is not important (i.e., the junction can be a nip junction, np junction, pin junction, or pn junction). In most cases, it is preferable to grow the n-type layer first, followed by the i-type layer (if used), and then the p-type layer.

[0058] [Detailed description of the invention] This invention relates to a structure or a flip-chip photodetector that can be used in the manufacture of flip-chip LEDs. Although this invention primarily describes LEDs, the reader will see that essentially the same device can be used as a photodetector. Furthermore, while this invention preferably relates to the emission and detection of ultraviolet light, the device can also be applied to other regions of the electromagnetic spectrum, particularly the visible region.

[0059] The device according to the present invention comprises a nanostructured LED having a plurality of nanowires or nanopyramids grown on a polycrystalline or monocrystalline graphene layer, wherein the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by a crystalline substrate, the crystalline substrate supporting the graphene layer during the growth process. Each nanowire or nanopyramid protrudes from the graphene layer, and these ideally include pn junctions or pin junctions. The present invention preferably relates to a device in which all nanowires or nanopyramids include the necessary junctions, but also includes a device in which a small number of nanowires or nanopyramids may not include such junctions. Ideally, all nanowires or nanopyramids include the necessary junctions.

[0060] The top of each nanowire or nanopyramid may be provided with a light-reflecting layer. This light-reflecting layer may simply be in contact with the top of the nanowire or nanopyramid, or it may surround the top of the nanowire or nanopyramid. The light-reflecting layer may function as the top contact electrode of the device, or a separate top electrode may be provided. If an electrode is provided, the light-reflecting layer may be in electrical contact with this electrode, and this electrode is in electrical contact with at least a portion of the top of the nanowire or nanopyramid. Therefore, it is important that there is an electrode that is in good electrical contact with both the top of the nanowire or nanopyramid and the external circuit. When a light-reflecting layer is present, it is preferable that light is emitted from the device in a direction substantially parallel and opposite to the direction of nanowire growth, or absorbed by the device in a direction substantially parallel and identical to the direction of nanowire growth. Therefore, generally, light is emitted from the portion of the device where the bottom of the nanowire is located or absorbed by the portion of the device. In certain embodiments, at least 50%, for example, at least 60%, for example, at least 70%, for example, at least 80%, for example, at least 90%, for example, at least 95%, for example, at least 99% of the light is emitted from or absorbed by the device along the aforementioned direction.

[0061] Each nanowire or nanopyramid also has an electrode that is in electrical contact with the bottom via a graphene layer. Therefore, there is a circuit via a top electrode that is in electrical contact with the other electrode via a pn junction or pin junction in the nanowire or nanopyramid.

[0062] When a forward voltage is applied between the electrodes, light, preferably ultraviolet light, is generated in the active region within the nanowire or nanopyramid, and the device functions as an LED.

[0063] When a reverse voltage is applied between the electrodes and the device is exposed to light, preferably ultraviolet light, the active region within the nanowire or nanopyramid absorbs the light and converts it into a photocurrent, thereby allowing the device to function as a photodetector.

[0064] By epitaxially growing nanowires or nanopyramids oriented by a substrate, the resulting material becomes homogeneous, thereby improving various final properties, such as mechanical, optical, or electrical properties. Epitaxial nanowires or nanopyramids may be grown from solid, gaseous, or liquid precursors. Since epitaxy is determined by the crystalline substrate, the grown nanowires or nanopyramids may have crystalline and facet orientations oriented by the substrate.

[0065] [Graphene layer] The graphene layer may contain graphene and / or graphene derivatives. The graphene layer may be polycrystalline or monocrystalline. The following description of the graphene layer applies to both cases where a graphene "buffer" layer is used (i.e., there are no pores for NW / NP to grow directly on the graphene) or where graphene is used as a hole pattern mask (i.e., there are pores for NW / NP to grow). The thickness of the graphene layer should preferably be 5 nm or less, particularly 3.0 nm or less, and most preferably 15 angstroms or less. The preferred thickness range is 0.3 to 10 nm, preferably 1 to 5 nm, 1 to 3 nm or 1 to 2 nm, more preferably 0.3 to 5 nm, 0.3 to 3 nm or 0.3 to 2 nm. Ideally, the number of layers of graphene or its derivatives should be 10 or less, preferably 5 or less, preferably 4 or less layers of graphene, preferably 3 or less layers of graphene, preferably 1 to 5 layers of graphene, preferably 1 to 4 layers of graphene, for example, 2 to 4 layers or 1 to 2 layers of graphene. A thickness of 3 layers or less is most preferable (this is called a small number of layer graphene). It is particularly preferable to have a planar sheet of graphene with a thickness of one atom. Having a thin graphene layer is important not only for optical / electronic properties but also for the remote epitaxial effect. Generally, the best results regarding remote epitaxy are obtained when using 3 to 4 layers or less of graphene (corresponding to about 1 to 2 nm).

[0066] Generally, graphene layers are planar or flat. Therefore, generally, graphene layers are flat, planar sheets. Consequently, generally, the distance between the base of the nanowire / nanopyramid and the top surface of the crystalline substrate corresponds to the thickness of the graphene layer. Therefore, the distance between the base of the nanowire / nanopyramid and the top surface of the crystalline substrate is preferably 5 nm or less, particularly 3.0 nm or less, and especially 15 angstroms or less. The preferred range is 0.3 to 10 nm, preferably 1 to 5 nm, 1 to 3 nm or 1 to 2 nm, more preferably 0.3 to 5 nm, 0.3 to 3 nm or 0.3 to 2 nm.

[0067] The area of ​​the graphene layer is not limited. This area is 0.5 mm². 2 For example, up to 5mm 2 , or more (10cm) 2 It can be set to (e.g., up to). Thus, the area of ​​the graphene layer is limited only by practical requirements.

[0068] Graphene layers can be deposited directly onto a substrate by any convenient method. Graphene can also be grown by sublimation or by self-assembly on a substrate. Graphene can even be grown directly onto a substrate by MBE or MOCVD.

[0069] Alternatively, graphene can be grown on a Ni film or Cu foil using chemical vapor deposition (CVD). These CVD-grown graphene layers can be chemically exfoliated from the metal foil, such as the Ni or Cu film, by etching or electrochemical exfoliation. The exfoliated graphene layer is then transferred and deposited on a substrate for nanowire or nanopyramid growth. During exfoliation and transfer, the thin graphene layer may be supported using electron beam resist or photoresist.

[0070] While it is preferable to use the graphene layer without modification, the surface of the graphene layer can be modified. For example, it can be treated with a plasma of hydrogen, oxygen, nitrogen, NO2, or a combination thereof. Oxidation of the graphene layer may also promote the nucleation of nanowires or nanopyramids. For example, it may be preferable to pre-treat the graphene layer to ensure purity before the growth of nanowires or nanopyramids. Treatment with strong acids such as HF or BOE is optional. The graphene layer may be washed with isopropanol, acetone, or n-methyl-2-pyrrolidone to remove surface impurities.

[0071] The washed graphene layer can be further modified by doping. Solutions of FeCl3, AuCl3, or GaCl3 can be used in the doping process.

[0072] The graphene layer possesses excellent optical, electrical, thermal, and mechanical properties. The graphene layer is extremely thin yet very strong, lightweight, flexible, and opaque. The high electrical and thermal conductivity and transparency of the graphene layer are of paramount importance in this invention. Therefore, importantly, the presence of the graphene layer provides electrical contact with the nanowire without affecting the LED / photodetector's ability to emit or absorb light.

[0073] [substrate] The crystalline substrate guides the epitaxial growth of nanowires or nanopyramids via remote epitaxy. The substrate is preferably a crystalline III-V semiconductor, sapphire, SiC, or diamond. When a graphene layer acts as a hole mask (see below), the nanowires / nanopyramids are epitaxially grown directly onto the crystalline substrate through pores in the graphene layer. In this case, the crystalline substrate guides the epitaxial growth of other structures (e.g., nanoislands) growing on the graphene layer outside the pores.

[0074] The thickness of the substrate is not critical, but in one embodiment, it may be transparent. The substrate may rest on a support, which is preferably transparent. Such a support may be the same thickness as required to support the substrate. As used herein, the term transparent means that the substrate / support transmits light, particularly ultraviolet light. In particular, it is preferable that the substrate / support is transparent to UV-B and UV-C light.

[0075] A suitable support structure contains silica.

[0076] Once the nanowires or nanopyramids have grown, the substrate may be removed (for example, by exfoliating the graphene layer). Removing the substrate may allow its use in further growth preparation processes. Additionally, exfoliating the substrate leaves behind a transparent structure ideal for use in LEDs or photodetectors.

[0077] The substrate is preferably a group III-V compound. The group III elements are B, Al, Ga, In, and Tl. Here, the preferred choices are Ga, Al, and In.

[0078] The options for family V are N, P, As, and Sb. All of these are preferable, with N being particularly preferred.

[0079] Of course, two or more Group III elements and / or two or more Group V elements can be used. Preferred compounds for the substrate include AlAs, GaSb, GaP, GaN, AlN, AlGaN, AlGaInN, GaAs, InP, InN, InGaAs, InSb, InAs, or AlGaAs. Compounds based on Al, Ga, and In in combination with N are most preferred. The use of GaN, AlGaN, AlInGaN, or AlN is highly preferred.

[0080] In another preferred option, the substrate is GaAs, InP, or GaP. Depending on the properties of the substrate, a separate support may be required.

[0081] Generally, a crystalline substrate is a uniform layer, i.e., not made up of multiple stacked layers. In certain embodiments, for example, the substrate is not a distributed Bragg mirror. In certain embodiments, the substrate is thicker than the graphene layer. Exemplary thicknesses of crystalline substrates are 1 nm to 2 mm, e.g., 1 nm to 1 mm, e.g., 1 nm to 500 μm, e.g., 10 nm to 1000 nm, e.g., 50 nm to 500 nm. Other suitable ranges for crystalline substrate thickness are 1 μm to 5 mm, e.g., 100 μm to 3 mm, e.g., 300 μm to 1 mm. The thickness of the substrate or wafer may vary depending on the wafer size. For example, it may range from 300 μm (e.g., a 2-inch wafer) to 1 mm (e.g., an 8-inch wafer).

[0082] [Growth of nanowires or nanopyramids] For the preparation of commercially important nanowires or nanopyramids, it is preferable that they be epitaxially grown, with the crystal orientation and facet orientation determined by the substrate. Furthermore, it is ideal that they be grown perpendicular to the crystalline substrate, and therefore, <0001> (In the case of a hexagonal crystal structure) direction or <111> (In the case of a cubic crystal structure) growth in the direction of the crystal is ideal.

[0083] The inventors have concluded that epitaxial growth occurs despite the presence of a graphene layer. When the graphene layer functions as a hole mask (see below), nanowires / nanopyramids epitaxially grow directly onto the crystalline substrate / interlayer through pores in the graphene layer. In this case, the crystalline substrate also guides the epitaxial growth of other structures (e.g., nanoislands) growing on the graphene layer outside the pores. The descriptions below also apply in this case, where technically feasible.

[0084] In growing nanopyramids, triangular faces typically terminate at (1-101) or (1-102) faces. Triangular faces with (1-101) facets may converge to a single point at the apex, or they may form new facets ((1-102) faces) before converging to the apex. In some cases, the nanopyramid is truncated, with its apex terminated at a {0001} face.

[0085] Ideally, there should be no lattice mismatch between the growing nanowires or nanopyramids and the substrate, although nanowires or nanopyramids can accommodate far more lattice mismatches than thin films. However, the advantage of the present invention is that there is a very tight lattice match between the substrate and the growing NW or NP. In the case of a graphene hole mask in which NW / NP are grown directly on the substrate / interlayer, the substrate or interlayer can be a III-V semiconductor, just like the nanowires / nanopyramids, making it possible to minimize lattice mismatches.

[0086] The growth of nanowires / nanopyramids can be controlled by the flux ratio. Nanopyramids are recommended, for example, when high-V fluxes are used.

[0087] The grown nanowires are essentially one-dimensional in form, with a width or diameter in the nanometer range and a length generally in the range of several hundred nanometers to several micrometers. Ideally, the diameter of the nanowire is 500 nm or less. Ideally, the diameter of the nanowire is 50 to 500 nm, but the diameter may exceed several micrometers (called microwires).

[0088] Therefore, the length of the nanowires grown in this invention may range from 250 nm to several microns, for example, up to 5 microns. Preferably, the length of the nanowires is at least 1 micron. When growing multiple nanowires, it is preferable that all nanowires satisfy these dimensional requirements. Ideally, at least 90% of the nanowires grown on the graphene layer should have a length of at least 1 micron. It is preferable that substantially all nanowires have a length of at least 1 micron.

[0089] The nanopyramids may have a height of 250 nm to 1 micron, or a height of 400 to 800 nm, or even approximately 500 nm.

[0090] Furthermore, it is preferable that the grown nanowires or nanopyramids have the same dimensions, for example, that the difference between them is within 10%. Therefore, it is preferable that at least 90% (preferably substantially all) of the nanowires or nanopyramids on the graphene layer (or substrate / interlayer) have the same diameter and / or the same length (i.e., the difference between them is within 10% of their respective diameters / lengths). Thus, essentially, those skilled in the art are looking for nanowires or nanopyramids that are homogeneous and substantially dimensionally identical.

[0091] The length of a nanowire or nanopyramid is often controlled by the length of time the growth process is performed. Generally, the longer the process, the (considerably) longer the nanowire or nanopyramid will be.

[0092] Nanowires generally have a hexagonal cross-sectional shape. The cross-sectional diameter (i.e., its thickness) of a nanowire may range from 25 nm to several hundred nm. Suitable nanowire diameters are 1 to 1000 nm, for example, 5 to 800 nm, 10 to 500 nm, or 50 to 500 nm. In some embodiments, nanowires can be microwires, so their size can be up to 2 μm. However, it is preferable that nanowires have a cross-sectional diameter of less than 1.0 μm. As mentioned above, the diameter is ideally constant over most of the nanowire, for example, at least 75% of its length. Generally, the difference in diameter along the length of the nanowire is less than 20%, for example, less than 10%, for example, less than 5%. The diameter of a nanowire can be controlled by manipulating the proportion of atoms used in the manufacture of the nanowire, as will be further described below. The diameter of a nanowire can be controlled by manipulating growth parameters such as substrate temperature and / or the proportion of atoms used in the manufacture of the nanowire, as will be further described below.

[0093] In fact, the length and diameter of nanowires or nanopyramids can be influenced by the temperature at which they are formed. Higher temperatures result in a higher aspect ratio (i.e., longer and / or thinner nanowires or nanopyramids). The diameter can also be controlled by manipulating the size of the nanopore openings in the mask layer. Those skilled in the art can manipulate the growth process to design nanowires or nanopyramids of desired dimensions.

[0094] It is preferable that hexagonal nanowires have their sides oriented parallel to each other, rather than randomly. When nanowires are epitaxially grown on polycrystalline graphene, they tend to be randomly oriented within different graphene domains / particles. Therefore, in the case of polycrystalline graphene, one way to determine whether nanowire growth is substrate-based (remote) epitaxy is to determine whether the hexagonal nanowires actually have parallel facets. If the hexagonal nanowires have parallel facets within different graphene domains, such nanowires will epitaxially grow in an orientation consistent with the substrate. If the hexagonal nanowires are randomly oriented within different graphene domains / particles, this is characteristic of nanowires epitaxially grown on polycrystalline graphene. Figures 7a and 7b show a comparison between growth with parallel facets and growth within multiple domains / particles.

[0095] In the case of single-crystal graphene, it is possible to determine whether the epitaxy is determined by the graphene or the underlying crystalline substrate by comparing the crystal orientations of the crystalline substrate, the single-crystal graphene, and the nanowire (see Nanotechnology 29 (2018) 445702. https: / / doi.org / 10.1088 / 1361-6528 / aadb78 and Adv. Funct. Mater. 2019, 1905056 https: / / doi.org / 10.1002 / adfm.201905056).

[0096] The nanowires or nanopyramids of the present invention are formed from at least one III-V compound semiconductor. The III-V compounds described herein with respect to nanowires or nanopyramids are also suitable for III-V semiconductor substrates. As described below, it is preferable that the nanowires or nanopyramids consist mostly of doped III-V compounds. Two or more different III-V compounds may be present, but it is preferable that all present compounds are III-V compounds.

[0097] The group III element options are B, Al, Ga, In, and Tl. Here, the preferred options are Ga, Al, and In.

[0098] The group V options are N, P, As, and Sb. All of these are preferred, and particularly N is preferred.

[0099] Of course, two or more group III elements and / or two or more group V elements can be used. Preferred compounds for manufacturing nanowires or nanopillars include AlAs, GaSb, GaP, GaN, AlN, AlGaN, AlGaInN, GaAs, InP, InN, InGaAs, InSb, InAs, or AlGaAs. Compounds based on Al, Ga, and In combined with N are most preferred. The use of GaN, AlGaN, AlInGaN, or AlN is highly preferred.

[0100] Most preferably, the nanowire or nanopillar consists of Ga, Al, In, and N (along with any doping atoms described later).

[0101] The use of binary materials is possible, but here it is preferred to use ternary nanowires or nanopillars in which there are two group III cations and one group V anion, such as AlGaN. Thus, this ternary compound may be represented by the formula XYZ (where X is a group III element, Y is a group III element different from X, and Z is a group V element). The molar ratio of X to Y in XYZ is preferably 0.1 - 0.9, that is, the formula is preferably X x Y 1-x Z (where the subscript x is 0.1 - 0.9).

[0102] Quaternary systems can also be used, with the formula A x B 1-x C y D 1-y (where A and B are different group III elements, and C and D are group V elements) or the formula A x B y C1-x-y It can be represented by D (wherein A, B, and C are different Group III elements, and D is a Group V element). Here again, the subscripts x and y are generally between 0.1 and 0.9. Other options will be obvious to those skilled in the art.

[0103] The growth of AlGaN and AlInGaN nanowires or nanopyramids is particularly preferred. The wavelength of light emitted by devices containing these nanowires or nanopyramids can be tuned by manipulating the Al, In, and Ga content. Alternatively, the properties of the emitted light can be altered by changing the pitch and / or diameter of the nanowires or nanopyramids.

[0104] It is even more preferable that the nanowire or nanopyramid contains regions of different compounds. Therefore, the nanowire or nanopyramid may contain a region of a first III-V semiconductor, such as GaN, followed by regions of a different III-V semiconductor, such as AlGaN. The nanowire or nanopyramid may contain two or more, or three or more, regions. These regions may be layers of axially grown nanowires or shells of radially grown nanowires or nanopyramids.

[0105] To facilitate the separation of the graphene layer from the substrate, an inert filler may be used to surround the grown NW or NP.

[0106] [doping] The nanowires or nanopyramids of the present invention may include pn junctions or pin junctions. Therefore, the devices of the present invention, particularly those based on pin junctions, optionally have undoped intrinsic semiconductor regions between p-type and n-type semiconductor regions. Some p-type and n-type regions are typically highly doped for use in ohmic contacts. The intrinsic regions may be a single or multiple active layers consisting of multiple quantum wells and multiple quantum barriers.

[0107] Therefore, it is preferable that the nanowires or nanopyramids are doped. Doping generally involves introducing impurity ions into the nanowires or nanopyramids, for example, during MBE or MOVPE growth. The doping level is 10 15 / cm 3 ~10 20 / cm 3 It can be controlled. Nanowires or nanopyramids can be p-doped or n-doped as desired. Doped semiconductors are extrinsic conductors.

[0108] By doping an intrinsic semiconductor with donor (acceptor) impurities, an n(p)-type semiconductor can have an electron (hole) concentration higher than the hole (electron) concentration. Suitable donors (acceptors) for III-V group compounds, particularly nitrides, can be Si(Mg, Be, and Zn). The dopant can be introduced during the growth process or by ion implantation after the formation of nanowires or nanopyramids.

[0109] To increase the external quantum efficiency (EQE) of LEDs, it is necessary to increase the carrier injection efficiency. However, as the ionization energy of Mg acceptors increases with increasing Al content in AlGaN alloys, it becomes difficult to obtain higher hole concentrations in AlGaN alloys with high Al content. To increase hole injection efficiency (particularly in barrier layers with high Al content), the inventors have devised several strategies that can be used individually or in combination.

[0110] Therefore, there are challenges to be addressed in the doping process. The nanowires or nanopyramids of the present invention preferably contain Al. The use of Al is beneficial because the high Al content results in a high band gap, enabling UV-C LED emission from the active layer of the nanowires or nanopyramids and / or avoiding absorption of emitted light in the doped barrier layer. A high band gap makes it less likely that ultraviolet light will be absorbed by this portion of the nanowires or nanopyramids. Therefore, it is preferable to use AlN or AlGaN for the nanowires or nanopyramids.

[0111] However, p-type doping of AlGaN or AlN to obtain high conductivity (high hole concentration) is difficult because the ionization energy of Mg or Be acceptors increases with increasing Al content in the AlGaN alloy. The inventors have proposed various solutions to maximize conductivity (i.e., maximize hole concentration) in AlGaN alloys with higher average Al content.

[0112] When nanowires or nanopyramids contain AlN or AlGaN, a challenge is to achieve high conductivity by introducing p-type dopants.

[0113] One solution involves short-period superlattices (SPSLs). This method involves growing a superlattice structure consisting of alternating layers with different Al content, instead of a more uniform AlGaN layer with a higher Al composition. For example, a barrier layer with 35% Al content, for instance, alternating layers of Al x Ga 1-x N:Mg / Al y Ga 1-yIt can be replaced with an SPSL consisting of N:Mg(x = 0.30 / y = 0.40) with a thickness of 1.8 to 2.0 nm. Due to the low ionization energy of the acceptor in the layer with a lower Al composition, the hole injection efficiency is improved without impairing the barrier height of the barrier layer. This effect is further enhanced by the polarization field at the interface. Following the SPSL, a highly p-type doped GaN:Mg layer can be provided for better hole injection.

[0114] More generally, the inventors propose introducing, instead of a p-type doped Al z Ga 1-z N alloy (where x < z < y), a p-type doped Al x Ga 1-x N / Al y Ga 1-y N short-period superlattice (that is, thin layers in which Al x Ga 1-x N and Al y Ga 1-y N overlap alternately), where the Al mole fraction x is lower than y, into a nanowire or nanopyramid structure. It will be understood that x may be a low value such as 0 (that is, GaN), and y may be a high value such as 1 (that is, AlN). The superlattice period should preferably be 5 nm or less, such as 2 nm. In this case, the superlattice functions as a single Al z Ga 1-z N alloy (z is the layer thickness weighted average of x and y), but has a higher conductivity than the Al x Ga 1-x N layer because the p-type doping efficiency for the Al z Ga 1-z N alloy is higher.

[0115] In a nanowire or nanopyramid having a p-type doped superlattice, it is preferable that the p-type dopant is an alkaline earth metal such as Mg or Be.

[0116] A further option for solving the doping problem of Al-containing nanowires / nanopyramids is based on a similar principle. Instead of superlattices containing thin AlGaN layers with low or no Al content, nanostructures can be designed that have a gradient of Al content (mole fraction) in the direction of AlGaN growth within the nanowires or nanopyramids. Thus, as the nanowires or nanopyramids grow, the Al content is decreased / increased, and then increased / decreased again, creating an Al content gradient within the nanowires or nanopyramids.

[0117] This is sometimes called polarization doping. In one method, a gradient is applied in the layer from GaN to AlN, or from AlN to GaN. The gradient regions from GaN to AlN and from AlN to GaN can result in n-type and p-type conductivity, respectively. This can occur due to the presence of dipoles of different sizes compared to adjacent dipoles. The gradient regions from GaN to AlN and from AlN to GaN can be further doped with n-type and p-type dopants, respectively.

[0118] In a preferred embodiment, Be is used as the dopant, and p-type doping is employed in AlGaN nanowires.

[0119] Therefore, one option is to start with GaN nanowires / nanopyramids, increase the Al content, and gradually decrease the Ga content to form AlN with a growth thickness of perhaps more than 100 nm. This gradient region can function as either a p-type or n-type region, depending on the crystal plane, polarity, and whether the Al content is decreasing or increasing in the gradient region. Next, the reverse process is carried out to generate GaN again, producing either an n-type or p-type region (the opposite region to the one prepared earlier). These gradient regions can then be further doped with n-type dopants such as Si and p-type dopants such as Mg or Be to obtain n-type or p-type regions with high charge carrier density, respectively. The crystal plane and polarity are determined by the type of nanowire / nanopyramid, as is well known in the art.

[0120] Therefore, in another embodiment, the nanowire or nanopyramid of the present invention comprises Al, Ga, and N atoms, and the Al concentration is changed during the growth of the nanowire or nanopyramid to create an Al concentration gradient within the nanowire or nanopyramid.

[0121] In a third embodiment, the challenges related to doping in Al-containing nanowires or nanopyramids are addressed using tunnel junctions. A tunnel junction is a barrier, such as a thin layer, between two conductive materials. In this invention, the barrier functions as a central ohmic electrical contact in a semiconductor device.

[0122] In one method, a thin electron blocking layer is inserted immediately after the active region, followed by a p-type doped AlGaN barrier layer having a higher Al content than that used in the active layer. The p-type doped barrier layer is followed by a highly p-type doped barrier layer and a very thin tunnel junction layer, and then an n-type doped AlGaN layer. The tunnel junction layer is selected so that electrons tunnel from the valence band in p-AlGaN to the conduction band in n-AlGaN, generating holes that are injected into the p-AlGaN layer.

[0123] More generally, it is preferable that the nanowire or nanopyramid has two regions of doped GaN (one p-type doped region and one n-type doped region) separated by an Al layer, such as a very thin Al layer. The thickness of the Al layer may be several nanometers, or it may be 1 to 10 nm, etc. It will be understood that there are other material options that can function as tunnel junctions containing a highly doped InGaN layer.

[0124] The fact that it is possible to grow a doped GaN layer on top of an Al layer is particularly surprising.

[0125] Accordingly, in one embodiment, the present invention provides a nanowire or nanopyramid having p-type doped (Al)GaN regions and n-type doped (Al)GaN regions separated by an Al layer.

[0126] The nanowires or nanopyramids of the present invention can be grown to have a radial or axial heterostructure configuration. For example, in the case of axially heterostructured nanowires or nanopyramids, a pn junction can be formed axially by first growing a p-type doped core and then subsequently growing an n-type doped core (or vice versa). The core can also be heterostructured axially, and the shell can be heterostructured radially. Intrinsic regions can be located between doped cores in the case of pin-type nanowires or nanopyramids. In the case of radially heterostructured nanowires or nanopyramids, a pn junction can be formed radially by first growing a p-type doped nanowire core or p-type doped nanopyramid core and then growing an n-type doped semiconductor shell (or vice versa). Intrinsic shells can be located between doped regions in the case of pin-type nanowires or nanopyramids.

[0127] The nanowires are preferably grown axially and thus formed from a first section and a second section along the axial direction of the nanowire or nanopyramid. These two sections are doped differently to create a pn junction or a pin junction. The top or bottom section of the nanowire is a p-type doped section or an n-type doped section.

[0128] In a PIN nanowire or nanopyramid, when charge carriers are injected into their respective p and n regions, they recombine in the i region, and this recombination generates light. In the case of a pn junction, the recombination occurs in the space charge region (because there is no intrinsic region). Light is generated randomly within each nanowire or nanopyramid and emitted in all directions. One problem with such structures is that only a portion of the generated light can be directed in the desired direction, so a considerable amount is wasted. Therefore, the use of a reflective layer ensures that the emitted light is directed in the desired direction, in particular, away from the reflective layer, from the device. Specifically, light is reflected through the graphene layer and the substrate (if present) (these are on the opposite side of the light-reflecting layer).

[0129] In embodiments of the photodetector, a reflective layer is not essential, but if present, it can reflect light that would otherwise be lost to nanowires or nanopyramids for detection.

[0130] The nanowires or nanopyramids of the present invention are preferably grown epitaxially. The crystal orientation is determined by the substrate. Thus, at the junction between the base of the nanowire or nanopyramid and the graphene layer, crystal planes are epitaxially formed within the nanowire or nanopyramid. These planes stack on top of each other in the same crystallographic direction, causing the nanowire or nanopyramid to grow epitaxially. The nanowires or nanopyramids are preferably grown vertically. As used herein, the term vertical means that the nanowires or nanopyramids are grown perpendicular to the graphene layer. In experimental science, the growth angle does not have to be exactly 90°, but it will be understood that the term vertical means that the nanowires or nanopyramids are within a range of about 10° from the vertical / perpendicular direction, for example, within a range of 5°. Epitaxial growth is expected to result in close contact between the nanowires or nanopyramids and the graphene layer. To further enhance contact properties, the graphene layer can be doped to match the primary carriers of the grown nanowires or nanopyramids.

[0131] The bottom contact is preferably ohmic.

[0132] It is preferable that the nanowires or nanopyramids grow nearly parallel to each other.

[0133] It will be understood that there are many surfaces within the substrate where epitaxial growth can occur. It is preferable that substantially all nanowires or nanopyramids grow from the same surface. It is preferable that this surface is parallel to the substrate surface. Ideally, the grown nanowires or nanopyramids are substantially parallel. It is preferable that the nanowires or nanopyramids grow substantially perpendicular to the substrate.

[0134] In the case of nanowires or nanopyramids having a cubic crystal structure, the nanowires or nanopyramids of the present invention are... <111> It is preferable for the nanowire to grow in the direction. If the nanowire has a hexagonal crystal structure, the growth is <0001> It occurs in the direction.

[0135] Nanowires or nanopyramids are preferably grown by MBE or MOVPE. In the MBE method, molecular beams of each reactant are supplied to the graphene layer, preferably, for example, group III and group V elements are supplied simultaneously. Nucleation and growth of nanowires or nanopyramids on the graphene layer can be more precisely controlled using MBE techniques, for example, by using migration-enhanced epitaxy (MEE) or atomic layer MBE (ALMBE) which can alternately supply group III and group V elements.

[0136] A preferred technique for nitrides is plasma-assisted solid-source (MBE), in which very pure elements such as gallium, aluminum, and indium are heated in a separate effusion cell until they slowly begin to evaporate. Generally, an RF plasma nitrogen source is used to generate a low-energy nitrogen atom beam. The gaseous elements then condense on a graphene layer, where they can react with each other. In the case of gallium and nitrogen, single-crystal GaN is formed. The use of the term "beam" implies that the evaporated atoms (e.g., gallium) and nitrogen atoms from the plasma source do not interact with each other or with the vacuum chamber gas until they reach the graphene layer.

[0137] MBE is measured when the background pressure is typically around 10 -10 ~10 -9 This process is carried out in an ultra-high vacuum at Torr. Nanostructures generally grow slowly, for example, at a rate of up to a few micrometers per hour. This allows for the epitaxial growth of nanowires or nanopyramids, maximizing their structural performance.

[0138] The properties of the emitted light are determined by the diameter and composition of the nanowire or nanopyramid. Temperature and flux can be used to adjust the band gap of the nanowire or nanopyramid (Nanotechnology 25 (2014) 455201).

[0139] In the MOVPE method, the substrate / graphene layer is held in a reactor, where a carrier gas and organometallic gases of each reactant, such as organometallic precursors containing Group III elements and organometallic precursors containing Group V elements, are supplied to the substrate / graphene layer. Common carrier gases are hydrogen, nitrogen, or a mixture of these two. Nucleation and growth of nanowires or nanopyramids on the graphene layer can be more precisely controlled using MOVPE technology, for example, by employing pulsed layer growth techniques that allow for the alternating supply of Group III and Group V elements.

[0140] [Selective area growth of nanowires or nanopyramids] The nanowires or nanopyramids of the present invention are preferably grown by selective region growth (SAG). When the NW or NP are grown on a graphene layer by remote epitaxy, this method may require a mask having a nanohole pattern deposited on the graphene layer. The growth methods described below are equally applicable when the nanowires / nanopyramids are grown from the substrate / interlayer through pores in the graphene mask (where technically feasible).

[0141] To produce arrays of nanowires or nanopyramids that are more uniform and regular in height and diameter, the inventors envision the use of a mask on a graphene layer. This mask has regular pores, allowing the nanowires or nanopyramids to grow uniformly in size and in a regular arrangement across the entire substrate. The pore pattern of the mask can be easily fabricated using conventional light / electron beam lithography or nanoimprint lithography. Focused ion beam techniques may also be used to generate a regular array of nucleation sites on the graphene surface from which the nanowires or nanopyramids are grown.

[0142] Therefore, a mask can be applied to a graphene layer and etched to expose holes on the surface of the graphene layer, possibly in a regular pattern. Furthermore, the size and pitch of the holes can be carefully controlled. By arranging the holes regularly, nanowires or nanopyramids in a regular pattern can be grown. If the graphene itself acts as a hole mask, no further mask layer is necessary.

[0143] Furthermore, the size of the pores can be controlled to ensure that only one nanowire or nanopyramid can grow within each pore. Ultimately, the pores can be made large enough to allow the growth of nanowires or nanopyramids. In this way, an array of regular nanowires or nanopyramids can be grown.

[0144] By changing the size of the pores, the size of the nanowires or nanopyramids can be controlled. By changing the pore pitch, the light extraction from the nanowires or nanopyramids can be optimized.

[0145] The mask material can be any material that does not damage the underlying graphene layer during deposition. Preferred options include oxides, nitrides, and fluorides. The mask must also be transparent to emitted light (LED) and incident light (photodetector). The minimum pore size may be 50 nm, preferably at least 100-200 nm. The thickness of the mask can be 10-100 nm, for example, 10-40 nm.

[0146] The mask itself can be made of an inert compound, such as silicon dioxide or silicon nitride. In particular, the hole pattern mask includes at least one insulating material such as SiO2, Si3N4, MoO2, W2O3, BN (e.g., h-BN), AlN, MgF2, CaF2, HfO2, TiO2, or Al2O3, which is deposited, for example, by electron beam deposition, CVD, PE-CVD, sputtering, or ALD. Thus, the mask can be provided on the graphene layer surface by any convenient technique, such as electron beam deposition, CVD, plasma-enhanced CVD, sputtering, and atomic layer deposition (ALD).

[0147] The use of a Ti mask that has been nitrided or oxidized before nanowire growth is particularly preferred because it has been shown to enable the growth of uniform NWs (see, for example, J. Crystal Growth 311 (2009) 2063-68).

[0148] In the selective region growth method, nanowires or nanopyramids of uniform length and diameter are generated at predetermined locations. It is also possible to grow the nanowires or nanopyramids without a mask having a nanohole pattern. In this case, the nanowires or nanopyramids will be non-uniform in size (length and diameter) and will be placed at random locations. In one embodiment, it is preferable to grow the nanowires or nanopyramids of the present invention without using a mask. Furthermore, the inventors have found that the nanowire density can be maximized in the absence of a mask. Nanowire densities of at least 20 nanowires per square micrometer, for example, at least 25 nanowires per square micrometer, are possible. These extremely high nanowire densities are particularly relevant to GaN or AlGaN nanowires.

[0149] Next, when growing nanowires or nanopyramids, the graphene temperature can be set to a temperature suitable for the growth of the target nanowire or nanopyramid. The growth temperature may be in the range of 300°C to 1000°C. However, a specific temperature is adopted depending on the material properties and growth method of the nanowire or nanopyramid. For GaN grown by MBE, the preferred temperature is 700°C to 950°C, for example, 750°C to 900°C, or 760°C. For AlGaN, the range is slightly higher, for example, 780°C to 980°C, or 830°C to 950°C, or 840°C.

[0150] Therefore, it will be understood that nanowires or nanopyramids can contain different III-V semiconductors within them, for example, starting with a GaN base followed by an AlGaN component or an AlGaInN component.

[0151] In MBE, the growth of nanowires or nanopyramids is initiated by simultaneously opening the shutters of the Ga effusion cell, nitrogen plasma cell, and dopant cell, thereby initiating the growth of doped GaN nanowires or nanopyramids (hereinafter referred to as "bases"). The length of the GaN base can be maintained between 10 nm and several hundred nanometers. Subsequently, the substrate temperature can be increased as needed, and the Al shutter can be opened to initiate the growth of AlGaN nanowires or nanopyramids. The growth of AlGaN nanowires or nanopyramids can also be initiated on the graphene layer without growing the GaN base. n-type and p-type doped nanowires or nanopyramids are obtained by opening the shutters of the n-type dopant cell and p-type dopant cell, respectively, during the growth of the nanowires or nanopyramids. Examples include a Si dopant cell for n-type doping of nanowires or nanopyramids, and a Mg dopant cell for p-type doping of nanowires or nanopyramids.

[0152] The growth rate can be controlled by the temperature of the effusion cell. A convenient growth rate is 0.05–2 μm per hour, for example, 0.1 μm per hour, which is the rate measured during conventional surface (layer-by-layer) growth. The Al / Ga ratio can be changed by varying the temperature of the effusion cell.

[0153] Depending on the properties of the nanowires or nanopyramids being grown, the molecular beam pressure can also be adjusted. A suitable level of beam equivalent pressure is 1 × 10⁻⁶. -7 ~1 × 10 -4 It's Torr.

[0154] The beam flux ratio between reactants (e.g., group III atoms and group V molecules) is variable, and the preferred flux ratio depends on other growth parameters and the properties of the nanowires or nanopyramids being grown. In the case of nitrides, the nanowires or nanopyramids are always grown under nitrogen-rich conditions.

[0155] The nanowires or nanopyramids of the present invention preferably include np-type or nip-type Al(In)GaN or AlGaN nanowires or nanopyramids. The active layer (i-region) is Al x1 Ga y1 N / Al x2 Ga y2 N(x1>x2 and x1+y1=x2+y2=1) can consist of multiple quantum wells or superlattice structures. The p-region includes (comprises) electron blocking layers (one or more quantum barrier layers) that can prevent minority carriers (electrons) from overflowing into the p-region.

[0156] Therefore, a preferred embodiment is one in which the nanowire or nanopyramid has multiple quantum wells. Thus, a preferred embodiment is one in which the nanowire or nanopyramid has an electron blocking layer. Ideally, the nanowire or nanopyramid has both an electron blocking layer and multiple quantum wells.

[0157] Therefore, in one embodiment of the present invention, a multi-stage growth method such as a two-stage growth method is employed, and for example, the nucleation of nanowires or nanopyramids and the growth of nanowires or nanopyramids are optimized separately.

[0158] A major advantage of MBE is that it allows for in-situ analysis of growing nanowires or nanopyramids using, for example, high-energy electron diffraction (RHEED). RHEED is a technique commonly used to characterize the surface of crystalline materials. This technique cannot be easily applied when the nanowires or nanopyramids are formed by other techniques such as MOVPE.

[0159] A major advantage of MOVPE is that it allows for the growth of nanowires or nanopyramids at much faster growth rates. This method is advantageous for the growth of radial heterostructured nanowires or nanopyramids and microwires, such as intrinsic AlN / Al(In)GaN multiple quantum wells (MQWs), AlGaN electron blocking layers (EBLs), and n-type doped GaN cores having shells consisting of p-type doped (Al)GaN shells. This method also enables the growth of axially heterostructured nanowires or nanopyramids using techniques such as continuous growth modes or pulsed growth techniques with modified growth parameters, such as lower V / III molar ratios and higher substrate temperatures.

[0160] More specifically, the reactor must be evacuated after the sample is placed, and oxygen and moisture in the reactor must be removed by N2 substitution. This is to avoid damage to the graphene at the growth temperature and to avoid undesirable reactions between the precursor and oxygen and moisture. The total pressure is set to 50-400 Torr. After N2 substitution in the reactor, thermal cleaning of the graphene layer is performed in an H2 atmosphere at a substrate temperature of approximately 1200°C. Subsequently, the substrate temperature can be set to a temperature suitable for the growth of the target nanowire or nanopyramid. The growth temperature may be in the range of 700°C to 1200°C. However, a specific temperature is adopted depending on the properties of the nanowire or nanopyramid material. In the case of GaN, preferred temperatures are 800°C to 1150°C, for example, 900°C to 1100°C, 1100°C or 1000°C, etc. In the case of AlGaN, the range is slightly higher, for example, 900°C to 1250°C, 1050°C to 1250°C, etc., for example, 1250°C or 1150°C.

[0161] The organometallic precursor can be either trimethylgallium (TMGa) or triethylgallium (TEGa) for Ga, either trimethylaluminum (TMAl) or triethylaluminum (TEAl) for Al, or either trimethylindium (TMIn) or triethylindium (TEIn) for In. The dopant precursor can be SiH4 for silicon, or bis(cyclopentadienyl)magnesium (Cp2Mg) or bis(methylcyclopentadienyl)magnesium ((MeCp)2Mg) for Mg. The flow rates of TMGa, TMAl, and TMIn can be maintained between 5 and 100 sccm. The flow rate of NH3 can be varied between 5 and 150 sccm.

[0162] In particular, the simple use of gas-solid phase growth can enable the growth of nanowires or nanopyramids. Therefore, in the case of MBE, nanowires or nanopyramids can be formed by simply applying reactants (e.g., In and N) to a graphene layer without the use of a catalyst. Thus, this is a further embodiment of the present invention, which directly grows semiconductor nanowires or nanopyramids formed from the aforementioned elements on a graphene layer. Thus, the term "direct" means that there is no catalyst to enable the growth.

[0163] In another embodiment, the present invention provides a structure comprising a plurality of III-V group nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystal graphene layer and a crystalline substrate for directing the growth of nanowires, preferably through holes in a hole pattern mask on the graphene layer, wherein the nanowires or nanopyramids are The present invention provides a structure having n-type doped regions and p-type doped regions separated by intrinsic regions that function as multiple quantum wells, wherein the p-type doped regions have an electron blocking layer.

[0164] The aforementioned region may be indicated by a layer within the nanowire or nanopyramid or by a shell on the core forming the nanowire or nanopyramid. Accordingly, the present invention further provides a plurality of radial III-V nanowires or nanopyramids epitaxially grown on a graphene layer and a substrate directing the growth of nanowires, comprising, in this order, an n-type doped core with a shell containing intrinsic multiple quantum wells, an electron block shell (EBL), and a p-type doped shell. The n-type doped region includes / comprises a hole block layer (one or more quantum barrier layers) to prevent overflow of minority charge carriers (holes) into the n-type doped region.

[0165] [Graphene Hole Mask] To position nanowires / nanopyramids, it is known that a mask with a hole array pattern is used, allowing the growth of nanowires / nanopyramids only in the region of the hole pattern, or primarily in the region of the hole pattern. The mask can also promote growth in the direction perpendicular to the substrate. Generally, a silica layer is coated onto the substrate, and holes of the desired pattern are formed by etching. Then, nanowires / nanopyramids grow only in the locations of these holes, or primarily in the locations of these holes. Mask layers are used in conjunction with nanowire growth on graphene (see WO2013 / 104723).

[0166] As described above, in another embodiment of the present invention, the inventors have found that by etching a graphene layer, holes can be formed for growing positioned NWs or NPs from the substrate or from an intermediate layer beneath the graphene. Surprisingly, the graphene layer with the hole pattern can still function as an electrode for the NWs or NPs, even though the NWs or NPs are grown from the substrate (or intermediate layer) rather than on the graphene layer itself. It is assumed that electrical contact will occur when the edges of the graphene layer come into contact with the edges of the NWs or NPs.

[0167] Accordingly, in a further embodiment of the present invention, the present invention provides the use of a graphene hole mask on a crystalline substrate. In this embodiment, nanowires / nanopyramids are grown through holes in a graphene mask that is directly provided on the crystalline substrate or on an intermediate layer located between the crystalline substrate and the graphene layer. The inventors have found that this arrangement has the advantage that NW / NPs can be directly epitaxially grown on the substrate / intermediate layer, and that additional nanostructures grown directly on the graphene surface, i.e., outside of the holes, can become epitaxially related to the intermediate layer / crystalline substrate beneath the graphene by remote epitaxy. This provides structural and optical / electrical advantages, particularly when the NW / NPs are grown to coalesce.

[0168] Therefore, in further embodiments of the present invention, A substrate made of sapphire, Si, SiC, Ga2O3, or a III-V semiconductor, A III-V semiconductor intermediate layer is directly placed on the upper surface of the substrate, The intermediate layer comprises a graphene layer directly provided on the upper surface of the intermediate layer, Multiple pores exist that penetrate the graphene layer, The present invention provides a structure in which multiple nanowires or nanopyramids are grown from the intermediate layer within the pores, and the nanowires or nanopyramids contain at least one semiconducting III-V compound.

[0169] In a further embodiment, the present invention is The graphene layer is directly supported on a substrate of sapphire, Si, SiC, Ga2O3, or a III-V semiconductor. Multiple pores exist that penetrate the graphene layer, The present invention provides a structure in which multiple nanowires or nanopyramids are grown from the substrate within the pores, and the nanowires or nanopyramids contain at least one semiconducting III-V compound.

[0170] In these embodiments, the graphene layer is typically grown directly onto a substrate or interlayer. Importantly, the graphene layer can function as an electrode to the nanowires or nanopyramids grown from the substrate or interlayer. Thus, typically, the graphene layer is in electrical contact with at least a portion of the nanowires or nanopyramids.

[0171] [Substrate layer when using a graphene hole mask] The substrate in this particular embodiment may be the same as the crystalline substrate described above. Furthermore, the following applies.

[0172] In embodiments having a graphene hole mask, the substrate is preferably a crystalline substrate because nanowires and nanopyramids can be grown from the substrate. Suitable substrates include sapphire, Si, SiC, Ga2O3, or III-V semiconductor substrates such as GaN, AlN, and GaAs. In all embodiments of the present invention, Ga2O3 is preferably β-Ga2O3. Suitable III-V semiconductors are those described above in relation to nanowires or nanopyramids.

[0173] Furthermore, regarding the options for the III-V semiconductor, the options for Group III are B, Al, Ga, In, and Tl. Here, the preferred options are Ga, Al, and In. The options for Group V are N, P, As, and Sb. The preferred option is N. Of course, two or more Group III elements and / or two or more Group V elements can be used in the substrate layer. Preferred III-V semiconductor compounds to be used in the substrate layer include BN, AlAs, GaSb, GaP, GaN, AlN, AlGaN, AlGaInN, GaAs, InP, InN, InGaN, InGaAs, InSb, InAs, or AlGaAs. Options include compounds based on Al, Ga, and In in combination with N. The use of GaN, AlGaN, AlInGaN, or AlN is highly preferred. These materials have strong ionic forces, which can consequently promote remote epitaxy (see above and below). AlN is particularly preferred because, in addition to having strong ionic forces, it is UVC permeable, making it more suitable for flip-chip UVC LEDs. AlN has much stronger ionic forces than, for example, sapphire, which can increase the yield of remote epitaxy for III-V island growth on graphene.

[0174] A mixture of the above substrate materials may be used. Particularly preferred options include sapphire, GaN, GaN / sapphire; AlGaN, AlGaN / sapphire; AlN, AlN / sapphire, Si; GaN / Si; AlGaN / Si; AlN / Si, SiC; GaN / SiC; AlGaN / SiC; AlN / SiC. A very preferred option is Ga2O3 or (Al x Ga 1-x )2O3 is an example. Combinations of AlN / sapphire, AlN / Si, or AlN / SiC are particularly preferred, with AlN / sapphire being preferred among them. In the above nomenclature, the first compound in a group (i.e., the compound before the " / ") is generally the intermediate layer, and the second compound is the substrate beneath the intermediate layer. The intermediate layer will be described in detail below.

[0175] The substrate may be crystalline, and its crystal orientation perpendicular to the surface may be

[0111] ,

[0110] , or

[0100] .

[0176] The use of sapphire with crystal orientation

[0001] is particularly preferred.

[0177] In certain embodiments, it is preferable to use a substrate made of sapphire, SiC, Ga2O3, or a III-V semiconductor (particularly a III-V semiconductor substrate). This is because, in the absence of an intermediate layer, it is possible to induce remote epitaxy through the graphene layer and influence the growth of nanostructures on the top surface of the graphene. In certain embodiments, a III-V semiconductor substrate is preferred, particularly when no intermediate layer is present (e.g., AlN).

[0178] In certain embodiments, the substrate is selected from sapphire, Si, SiC, Ga2O3, or a III-V semiconductor substrate if an intermediate layer is present, and from sapphire, SiC, Ga2O3, or a III-V semiconductor substrate if an intermediate layer is absent (because these can result in remote epitaxial effects).

[0179] Therefore, in a particular embodiment, the present invention is circuit board and An arbitrary III-V semiconductor intermediate layer is provided directly on the upper surface of the substrate, If the aforementioned intermediate layer exists, it is provided directly on its upper surface, or a graphene layer is provided directly on the upper surface of the substrate, Multiple pores exist that penetrate the graphene layer, Multiple nanowires or nanopyramids are grown in the pores from the substrate or the intermediate layer, and each nanowire or nanopyramid contains at least one semiconductive III-V compound. The present invention provides a structure in which, when an intermediate layer is present, the substrate is selected from sapphire, Si, SiC, Ga2O3, or a III-V semiconductor substrate, and when there is no intermediate layer, the substrate is selected from sapphire, SiC, Ga2O3, or a III-V semiconductor substrate.

[0180] [Interlayer / Remote Epitaxy / Nano Island when using Graphene Hole Masks] In certain embodiments, the substrate has an intermediate layer positioned on its upper surface. Such an intermediate layer is positioned between the substrate and the graphene layer. In other words, the structure comprises the substrate, the intermediate layer, and the graphene layer, in that order.

[0181] The intermediate layer is formed from at least one group III-V compound. If the semiconductor substrate is a group III-V semiconductor substrate, the intermediate layer is formed from different group III-V compounds. Generally, the intermediate layer is crystalline.

[0182] The Group III options are B, Al, Ga, In, and Tl. Preferred options are Ga, Al, and In. The Group V options are N, P, As, and Sb. Preferred option is N. Of course, it is also possible to use two or more Group III elements and / or two or more Group V elements in the intermediate layer. Preferred compounds for the intermediate layer include BN, AlAs, GaSb, GaP, GaN, AlN, AlGaN, AlGaInN, GaAs, InP, InN, InGaN, InGaAs, InSb, InAs, or AlGaAs. Options include Al, Ga, and In-based compounds combined with N. The use of GaN, AlGaN, AlInGaN, or AlN is highly preferred. These materials possess strong ionic forces, which can consequently promote remote epitaxy (see below). AlN is particularly preferred because, in addition to its strong ionic forces, it is UVC transparent, making it more suitable for flip-chip UVC LEDs. AlN, for example, has much stronger ionic forces than sapphire, which can increase the yield of remote epitaxy in III-V island growth on graphene.

[0183] In certain embodiments, there is a remote epitaxial relationship between the intermediate layer and the semiconductor nanostructure grown on the upper surface of the graphene layer. In other embodiments, there is a remote epitaxial relationship between the substrate and the semiconductor nanostructure grown on the upper surface of the graphene layer.

[0184] In certain embodiments, the interlayer has a thickness of less than 200 nm, preferably less than 100 nm, more preferably less than 75 nm, for example, about 50 nm. A suitable thickness range is 1 to 200 nm, preferably 10 to 100 nm, for example, 25 to 75 nm. By using a thin interlayer, it is possible to induce a remote epitaxial effect without using a substrate made entirely of expensive semiconductor material.

[0185] Preventing growth on the upper surface of the graphene layer outside the pore (i.e., the growth of so-called "nanoislands") is often difficult. Therefore, it is necessary to ensure high crystallinity of the III-V group structures growing on the upper surface of graphene. This is especially important in the case of "combination," that is, when positioned nanowires / nanopyramids grown from the pores bond together.

[0186] As described above, remote epitaxy is a phenomenon in which nanostructures (or even thinner films) can be epitaxically grown using a very thin graphene layer. Even if the graphene is polycrystalline, the crystal orientation of the nanostructure matches that of the substrate beneath it, not the graphene layer. Therefore, even though the graphene layer acts as a buffer between the substrate or interlayer and the nanostructure, the nanostructure grows in a crystal / facet orientation that reflects the substrate or interlayer, not the graphene. The resulting nanowire array will have parallel and more regular facets, even if the graphene is polycrystalline. This improves various properties of the material.

[0187] In embodiments having a graphene hole mask, nanowires / nanopyramids are grown such that the crystal orientation and facet orientation of the nanowires or nanopyramids are directed by the crystalline substrate / interlayer. Therefore, the crystal orientation and facet orientation are identical for all nanowires / nanopyramids.

[0188] When remote epitaxy occurs, the growing nanostructure adopts its crystal (and therefore facet) orientation from the crystalline layer beneath the graphene layer. Therefore, the nanostructure can be considered to have parallel facets. On the other hand, when nanostructures are epitaxially grown from polycrystalline graphene, the facets of the resulting nanowires are randomly oriented within different domains / particles; that is, the sides (facets) of a hexagonal nanowire may be parallel within one graphene domain / particle, but will be randomly oriented, not parallel, relative to the sides (facets) of a hexagonal nanowire in adjacent graphene domains / particles. The cross-section of the nanowire can be hexagonal or square, preferably hexagonal. Remote epitaxy occurs when all crystal and facet orientations are the same.

[0189] Preferably, the use of an intermediate layer when there is no additional hole mask on the top surface of the graphene is a particular embodiment that can result in higher quality growth for nanoisland formation occurring on the top surface of the graphene hole mask. Thus, in a particular embodiment, the structure comprises a graphene hole mask and an intermediate layer, preferably AlN, between the substrate and the graphene. In a particular embodiment, there is no masking layer of oxide, nitride, or fluoride. This setting has the advantages of 1) improved selectivity and 2) induction of remote epitaxy for III-V island formation on the graphene hole mask, which is often impossible to completely avoid.

[0190] This remote epitaxy ensures that the III-V island formation (i.e., nanoislands formed on graphene) is in-plane epitaxial with the III-V nanowires / nanopyramids, thus preventing defects from occurring when the nanowires / nanopyramids coalesce. Therefore, in certain embodiments, the structures of the present invention include III-V nanoislands nucleated by remote epitaxy on graphene (i.e., those not grown on the intermediate / substrate layer via pores in graphene). Generally, nanoislands are formed from the same material as nanowires / nanopyramids. This is because the growth of nanoislands occurs simultaneously with the growth of NW / NPs. Thus, the definition of III-V material for NWs and NPs also applies to nanoislands. The term "nanopyramid" encompasses nanopyramids, nanowires, nanomesas, and other structures, and is used herein to distinguish such structures from nanowires / nanopyramids grown within pores in graphene. Preferably, the epitaxy, crystal orientation, and facet orientation of the nanoislands are directed by the intermediate layer. Therefore, generally speaking, the crystal orientation of the nanoisland coincides with the crystal orientation of the nanowires and nanopyramids (grown within the pores), as well as the crystal orientation of the intermediate layer.

[0191] Remote epitaxy can be used to improve the electrical / optical properties of the final device.

[0192] [Combine] It can be beneficial to form large-area structures by coalescing positioned nanowires / nanopyramids. Coalition refers to the lateral bonding of two or more nanostructures during the growth process, generally referring to the inevitable bonding of "island" nanostructures grown between them. This results in a 2D or 3D structure. Such coalesced structures generally resemble corrugated (non-planar) thin films with pyramidal tips on their surface; that is, coalesced structures are generally raised. In certain embodiments, coalesced structures are not planar. Therefore, they generally differ from planar thin films grown on a substrate. For coalition to occur, the nanostructures preferably have the same crystalline lattice orientation so as to eliminate the formation of voids and most dislocations. That is, the coalescing nanowires / nanopyramids and bonding nanoislands preferably have substantially identical epitaxial relationships with respect to the substrate / interlayer.

[0193] For bonding to occur, it is preferable that there is no additional mask layer on the surface of the graphene, that is, no oxide / nitride / fluoride mask layer, because such a mask layer is amorphous and may result in a low-crystallinity bonded structure.

[0194] In certain embodiments, at least some or all of the nanowires / nanopyramids are coalesced. The coalesced structure may include nanostructures grown between the nanowires / nanopyramids, such as nanoislands, on top of the graphene itself.

[0195] The use of a substrate / interlayer that facilitates remote epitaxy via a graphene hole mask is particularly beneficial for coalescence. This is because not only do the crystal orientations and facet orientations of the nanowires / nanopyramids align with the substrate / interlayer, but any nanoislands formed on the graphene, i.e., outside the pores, also lattice-match with the substrate / interlayer through remote epitaxy. Therefore, nanoislands formed on the graphene can form part of the coalesced structure containing the nanowires / nanopyramids. Due to this remote epitaxy effect, the coalesced structure exhibits high crystallinity and is virtually defect-free. Generally, dislocations and stacking faults are rarely or never observed. Without remote epitaxy, when nanowires / nanopyramids coalesce, defective, inactive regions (dead "active" regions) are created between them.

[0196] [Patterning] When using a graphene hole mask, the positioned nanowires or nanopyramids must grow from the substrate or interlayer. This means that holes must be patterned to penetrate the graphene layer. The formation of these holes is a well-known process and can be carried out using electron beam lithography or other known techniques. The hole pattern on the mask can be easily fabricated using conventional lithography techniques such as optical / electron beam lithography or nanoimprint. Focused ion beam techniques may be used to generate a regular array of nucleation sites on the substrate surface or interlayer surface for the growth of nanowires or nanopyramids. The holes formed in the graphene layer can be arranged in any desired pattern.

[0197] The pore diameter is preferably 500 nm or less, 100 nm or less, and ideally 20-200 nm or less. Since the pore diameter sets the maximum diameter of the nanowire or nanopyramid, the pore size and the nanowire or nanopyramid diameter should coincide. However, a nanowire or nanopyramid diameter larger than the pore size can be achieved by changing the growth parameters or by adopting a core-shell type nanowire or nanopyramid shape. When a shell is applied to the nanowire, the base of the shell grows on the upper surface of the graphene layer. In this way, the base of the nanowire comes into contact with the graphene layer, resulting in stronger electrical contact.

[0198] The number of pores is a function of the area of ​​the substrate (and optionally the intermediate layer) and the density of the desired nanowires or nanopyramids.

[0199] The shape of the holes is not limited. They may be circular, but they may also be triangular, rectangular, elliptical, or other shapes.

[0200] Once nanowires or nanopyramids begin to grow within the pores, this tends to ensure initial growth of nanowires or nanopyramids substantially perpendicular to the substrate. This is a more preferred feature of the present invention. Preferably, one nanowire or nanopyramid grows per pore.

[0201] [Top Contact] To fabricate the device of the present invention, the top of the nanowire or nanopyramid must have a top electrode, and in the case of the LED embodiment, preferably a reflective layer. In some embodiments, these layers may be integral.

[0202] In one preferred embodiment, the top contact is formed using a separate graphene layer. The present invention then includes locating a graphene layer at the top of a formed nanowire or nanopyramid to form a top contact. The graphene top contact layer is preferably substantially parallel to the underlying graphene layer. It will also be understood that the area of ​​the graphene layer does not need to be the same as the area of ​​the other graphene layers. A number of graphene layers may be required to form a top contact with a graphene layer having an array of nanowires or nanopyramids.

[0203] The graphene layer used can be the same as that described in detail earlier. This graphene top contact should contain 10 or fewer layers of graphene or its derivatives, preferably 5 or fewer layers (this is called a minority-layer graphene). It is particularly preferable to use a planar sheet of graphene with a thickness of one atom.

[0204] The crystalline or "flake" graphene consists of a number of stacked (i.e., more than 10) graphene sheets. The thickness of the top contact is preferably 20 nm or less. More preferably, the thickness of the graphene top contact may be 5 nm or less.

[0205] When graphene is in direct contact with semiconductor nanowires or nanopyramids, the graphene typically forms a Schottky contact, creating a barrier at the contact junction that hinders the flow of current. Because of this problem, research on graphene deposited on semiconductors has been primarily limited to the use of graphene / semiconductor Schottky junctions.

[0206] The application of top contacts to the formed nanowires or nanopyramids can be achieved by any convenient method. Methods similar to those described above may be used to transfer the graphene layer to the substrate. Graphene layers derived from quiche graphite, highly oriented pyrolysis graphite (HOPG), or CVD can be exfoliated by mechanical or chemical methods. These layers can then be transferred to an etching solution such as HF or an acid solution to remove any impurities and Cu (Ni, Pt, etc.) (especially in the case of CVD-grown graphene layers) generated during the exfoliation process. The etching solution can be further replaced with another solution such as deionized water to clean the graphene layer. The graphene layer can then be easily transferred onto the formed nanowires or nanopyramids to form top contacts. Again, electron beam resist or photoresist may be used to support the thin graphene layer during the exfoliation and transfer processes, which can be easily removed after deposition.

[0207] It is preferable to etch and wash the graphene layer with water and then completely dry it before transferring it to the upper surface of the nanowire array or nanopyramid array. To enhance contact between the graphene layer and the nanowires or nanopyramids, gentle pressure and heat may be applied during this "dry" transfer.

[0208] Alternatively, the graphene layer can be moved to the top of the nanowire or nanopyramid array along with a solution (e.g., deionized water). As the solution dries, the graphene layer naturally adheres to the nanowire or nanopyramid beneath it. In this "wet" transfer method, the surface tension of the solution during the drying process can cause bending or breakage of the nanowire or nanopyramid array. To prevent this, it is preferable to use stronger nanowires or nanopyramids when using this wet method. Nanowires or nanopyramids with a diameter greater than 80 nm may be suitable. Alternatively, a hole pattern mask can be used to support the vertical nanowire or nanopyramid structure. Critical point drying techniques may be used to avoid damage caused by surface tension during the drying process. Another way to prevent this is to use an electrically insulating support as a filler between the nanowires or nanopyramids. The filler needs to be transparent to emitted light. The use of fillers is discussed below.

[0209] If a water droplet is present on a nanowire or nanopyramid array, and an attempt to remove it involves, for example, a nitrogen blow, the droplet will shrink due to evaporation, but will constantly try to maintain its spherical shape due to surface tension. This can damage or destroy nanostructures around or inside the droplet.

[0210] This problem can be avoided by the critical point drying method. By increasing the temperature and pressure, the phase boundary between the liquid and gas can be removed, and water can be easily removed.

[0211] Doping of graphene top contacts can also be utilized. The primary carriers of graphene top contacts can be controlled as either holes or electrons through doping. Preferably, the doping type is the same for graphene top contacts and semiconductor nanowires or nanopyramids.

[0212] Therefore, it will be understood that both the top graphene layer and the graphene layer can be doped. In some embodiments, the graphene layer can be doped by chemical methods, which involve the absorption of chemical solutions such as metal chlorides (FeCl3, AuCl3, or GaCl3), organic or inorganic molecules such as NO2, HNO3, aromatic molecules, or ammonia.

[0213] The surface of the graphene layer can also be doped during its growth by introducing dopants such as B, N, S, or Si using substitution doping methods.

[0214] [Reflective layer / electrode] The device comprises two electrodes. The first electrode is positioned in contact with the graphene layer. This electrode may be based on a metallic element such as Ni, Au, Ti, or Al, a mixture thereof, or a stack thereof (e.g., a Ti / Al / Ni / Au stack). Pd, Cu, or Ag may also be used. The first electrode is often an n-electrode. This electrode may be on any surface of the graphene layer, preferably on the same surface as the grown nanowire or nanopyramid.

[0215] A second electrode is positioned as a top contact at the apex of the grown nanowire or nanopyramid. This electrode is often a p-electrode. It is preferable that this electrode forms good ohmic contact with the nanowire or nanopyramid. Suitable electrode materials include Ni, Ag, Pd, and Cu. In particular, a Ni / Au stack can be used. This electrode can also function as a heat sink. As will be described in more detail below, the LED device of the present invention is preferably in the form of a flip chip. Thus, the top contact electrode is located at the bottom of the flip chip assembly. Therefore, it is preferable that this electrode either reflects light or has a light-reflecting layer. The light-reflecting layer is ideally a metal. The light-reflecting contact layer can be formed in several ways, but PVD (physical vapor deposition) and well-known masking techniques are preferred methods. The reflector is preferably made of aluminum or silver, but other metals or metal alloys can also be used. The purpose of the light-reflecting layer is to prevent light from emitting from the structure in directions other than the preferred direction and to focus the emitted light in a single direction. Furthermore, the light-reflecting layer can function as a top contact electrode for nanowires or nanopyramids. Light emitted by the LED is directed in the opposite direction to the reflective layer, i.e., outwards from the top of the flip-chip. If a graphene top contact layer is present, it is preferable that a light-reflecting layer is also present.

[0216] The reflective layer needs to reflect light and can also function as a heat sink. An appropriate thickness is 20-400 nm, for example, 50-200 nm.

[0217] In embodiments of photodetectors, a reflective layer is not required, but in some cases, such a layer may be used to reflect incident light off nanowires or nanopyramids to improve photodetection.

[0218] [Filler] Using fillers to surround a flip-chip assembly is within the scope of the present invention, provided that the fillers are, for example, transparent to ultraviolet light. Fillers may be present in the spaces between nanowires or nanopyramids and / or around the entire assembly. Different fillers may be used in the spaces between nanowires or nanopyramids than those used in the rest of the assembly. The presence of fillers imparts strength to the material.

[0219] Therefore, in one embodiment, by separating the graphene layer containing epitaxially grown nanowires or nanopyramids in a substrate-based orientation from the substrate, the substrate can be reused for growing the nanowires or nanopyramids. Furthermore, removing the substrate avoids problems associated with the transparency of the substrate. In any electronic device of the present invention, semiconductor nanowires / nanopyramids can be used with or without the substrate on which they are grown. However, the key is to use the substrate during the growth process to enable the formation of nanowires / nanopyramids with parallel facets.

[0220] [application] The present invention relates to LEDs, particularly UV-LEDs, and more specifically, UV-A, UV-B, or UV-C LEDs. The LEDs are preferably designed as so-called "flip-chip" devices, where the chip is inverted compared to conventional devices.

[0221] The entire LED array may feature contact pads for flip-chip bonding that are dispersed and spaced apart to reduce the average series resistance. Such nanostructured LEDs can be placed on a carrier having contact pads at locations corresponding to the p-type and n-type contact pads on a nanowire or nanopyramid LED chip, and mounted using soldering, ultrasonic welding, bonding, or conductive adhesive. The contact pads on the carrier can be electrically connected to appropriate power leads of the LED package.

[0222] Such nanowire-based LED devices are typically mounted on a carrier that provides a mechanical support and electrical connections. One preferred method for constructing more efficient LEDs is to fabricate a flip-chip device. A highly reflective light-reflecting layer is formed on top of the nanowire or nanopyramid. The substrate can be removed as part of the process, leaving behind a graphene layer as an electrode that allows light to be emitted through the layer forming the base for the nanowire or nanopyramid. If the substrate is transparent, it obviously does not need to be removed. The support may be transparent enough for light to be transmitted through the substrate layer and emitted. If an intermediate layer is present, similar considerations apply to the intermediate layer as well. In certain embodiments, the intermediate layer is transparent. Emitted light directed towards the top of the nanowire or nanopyramid is reflected when it strikes the reflective layer, thereby creating a clearly advantageous direction for light away from the structure. This method of fabricating the structure makes it possible to direct the majority of the emitted light in the desired direction, thereby increasing the efficiency of the LED. Thus, the present invention enables the fabrication of visible LEDs and UV-LEDs.

[0223] The present invention also relates to a photodetector in which a device absorbs light and generates a photocurrent. A light-reflecting layer can reflect the light incident on the device back to the nanowire or nanopyramid to improve photodetection.

[0224] The present invention will now be further described in relation to the non-limiting embodiments and drawings described below.

[0225] [Brief description of the drawing] Figure 1 shows a structure of the present invention having nanowires grown on a thin polycrystalline or single-crystal graphene layer. The polycrystalline or single-crystal graphene layer is directly supported on a crystalline substrate, and the epitaxy is determined by the crystalline substrate.

[0226] Figure 2 shows a possible flip-chip design. Therefore, during use, light passes through and is emitted from the top of the device (2) (indicated as hv). The crystalline substrate 1 is preferably formed from sapphire or AlN. Other crystalline transparent substrates can also be used. When the substrate remains in place during use, it is important that the substrate is transparent to the emitted light, as it is located at the top of the device, allowing light to be emitted from the device.

[0227] Layer 3 is a polycrystalline or single-crystal graphene layer, which may have a thickness of 1 atomic layer.

[0228] The nanowires 4 are grown from a polycrystalline or single-crystal graphene layer 3 employing remote epitaxy. Ideally, the nanowires are formed from Al(In)GaN, AlN, or GaN, doped, and have nip or np junctions.

[0229] The filler 5 can be placed between the grown nanowires. The top electrode / light-reflecting layer 6 is located on the top of the nanowire 4. The light-reflecting layer may also have a p electrode containing Ni or Au. When in use, this layer reflects the light emitted by the device, ensuring that the light passes through and is emitted from the top of the device on the opposite side of the reflective layer. This is a so-called flip-chip configuration because the device is inverted compared to a conventional LED.

[0230] The electrode 10 is located on a polycrystalline or single-crystal graphene layer 3. This electrode may contain Ti, Al, Ni, and / or Au. The graphene layer may include a mask 7 and nanowires may be grown at limited locations on the polycrystalline or single-crystal graphene.

[0231] The entire device is soldered to the conductive track / pad 13 on the submount 8 via a solder layer 9.

[0232] As a forward current passes through the device, visible or ultraviolet light is generated within the nanowire by the structure, and after being reflected by a reflective layer in some cases, it is emitted from the top of the device.

[0233] When a reverse current passes through the device and the device is exposed to visible or ultraviolet light, the nanowire functions as a photodetector by absorbing the visible or ultraviolet light through its structure and converting it into an electric current.

[0234] Figure 3 shows one possible nanowire of the present invention. The nanowire has different compositions in the axial direction by changing the elements supplied during the growth stage. First, an n-type doped GaN material, or preferably an n-type AlGaN material, is deposited, followed by n-AlGaN deposition. As shown in the figure, the central part of the nanowire has a series of multiple quantum wells formed from (In)(Al)GaN. This is followed by an AlGaN-based p-type doped region, a p-Al(Ga)N-based electron blocking layer, and finally a p-GaN layer.

[0235] Figure 4 shows another chip design in which nanowires grow radially and form a core-shell structure. Therefore, during use, light passes through and is emitted from the top of the device (indicated as hv). The crystalline substrate 1 is preferably formed of sapphire or a III-V semiconductor. When the substrate remains during use, it is important that the substrate is transparent to emitted light so that light can be emitted from the device, as the substrate is located at the top of the device.

[0236] Layer 3 is a polycrystalline or single-crystal graphene layer, which may have a thickness of at least one atomic layer, for example, a maximum thickness of 5 nm.

[0237] The nanowire 4 grows epitaxially from layer 3 so as to reflect the underlying crystalline substrate. Ideally, the nanowire is formed from Al(In)GaN, AlN or GaN, doped, and a nip junction or np junction is formed. A mask layer 7 can be provided on the polycrystalline or single-crystalline graphene.

[0238] The filler 5 can be disposed between the grown nanowires. The top electrode / light reflection layer 6 is disposed on the top of the nanowire 4. The light reflection layer may also include a p electrode containing Ni or / and Au, or itself may be an electrode. In use, this layer reflects the light emitted by the device, ensuring that the light passes through the top of the device on the opposite side of the reflection layer and is emitted. This is a so-called flip-chip arrangement because the device is upside down compared to a conventional LED.

[0239] The electrode 10 is disposed on the polycrystalline or single-crystalline graphene layer 3. When a forward current passes through the device, visible light or ultraviolet light is generated within the nanowire by the structure, and in some cases, after being reflected by the reflection layer, it is emitted from the top of the device.

[0240] The entire device is soldered via the solder layer 9 to the conductive tracks / pads 13 on the submount 8.

[0241] When a reverse current passes through the device and the device is exposed to visible light or ultraviolet light, the nanowire absorbs the visible light or ultraviolet light by the structure and converts it into an electric current, thereby functioning as a photodetector.

[0242] Figure 5 shows a nanowire that grows radially and has the same components as those in Figure 3 within its shell structure. The nanowire has different components in the radial direction by changing the elements supplied during the growth stage. First, n-type doped (Al)GaN material is deposited, followed by n-AlGaN. As shown in the figure, the central shell of the nanowire has a series of multiple quantum wells formed from (In)(Al)GaN. This is followed by a p-type doped region based on AlGaN, an electron block shell based on p-Al(Ga)N, and finally a p-GaN shell.

[0243] Figure 6 shows the photodetector. Therefore, during use, light (2) (indicated as hv) is received through the top of the device. The crystalline substrate 1 is preferably made of sapphire or AlN. When the substrate remains during use, it is important that the support is transparent to incident light so that light can be incident on the device, as the substrate is located at the very top of the device.

[0244] Layer 3 is a polycrystalline or single-crystal graphene layer, which may have a thickness of 1 atomic layer.

[0245] The nanowires 4 are epitaxially grown from the crystalline substrate layer 3. Ideally, the nanowires are formed from Al(In)GaN, AlN, or GaN, doped, and have nip or np junctions.

[0246] The filler 5 can be placed between the grown nanowires. The top electrode layer 11 is located at the top of the nanowire 4. This electrode is ideally a p electrode containing Ni or Au.

[0247] The electrode 10 is placed on a polycrystalline or single-crystal graphene layer 3. The graphene layer may include a mask 7, and nanowires may be grown at limited locations on the polycrystalline or single-crystal graphene.

[0248] The entire device is soldered to the conductive track / pad 13 on the submount 8 via a solder layer 9.

[0249] When a reverse current passes through the device and the device is exposed to visible or ultraviolet light, the nanowire functions as a photodetector by absorbing the visible or ultraviolet light through its structure and converting it into an electric current.

[0250] Figure 7a is a theoretical top cross-sectional view of a regular hexagonal array of nanowires on polycrystalline graphene, where the crystalline structure of the crystalline substrate determines the nanowire orientation by remote epitaxy (the nanowires have facets parallel to each other).

[0251] Figure 7b is a theoretical top cross-sectional view of hexagonal nanowires grown on polycrystalline graphene, where the crystalline substrate does not affect the nanowire orientation. The nanowires grow in two different domains / particles, with different facet orientations. In this example, the nanowires are epitaxially grown on each graphene domain / particle (the nanowires on each domain / particle have the same facet orientation).

[0252] Figures 8 to 15 show experimental results for nanowires / nanopyramids positioned using graphene on a crystalline substrate / interlayer as a hole mask, and for LEDs fabricated using this method.

[0253] Figure 8 (Case 1.1) shows a positioned flat-chip nanowire epitaxially grown on a crystalline substrate / interlayer supporting a graphene mask layer with etched holes. The nanowire first epitaxially nucleates on the substrate / interlayer through the pores in the graphene. The nanowire continues to grow both axially and radially, while also growing on the upper surface of the graphene layer, maintaining an epitaxial relationship with the substrate / interlayer. The graphene layer forms electrical contact with the nanowire through both contact with the graphene surface and contact with the edges of the graphene pores. Thus, the graphene layer forms a conductive transparent electrode. The nanowire can be grown in either an axial or radial heterostructure to fabricate axial or radial nip / pin junction nanowire device structures, respectively. In the case of a radial nip / pin junction nanowire device structure, the growth of the p / n nanowire shell layer on the graphene must be avoided (a gap is required) to avoid shortening between the n / p nanowire core and the p / n nanowire shell.

[0254] Figure 9 (Case 1.2) is similar to Figure 8, differing only in that the nanowires have pyramidal tips. Figure 9 shows a pyramidal, positioned nanowire epitaxially grown on a crystalline substrate / interlayer supporting a pore-etched graphene mask layer.

[0255] Figure 10 (Case 1.3) is similar to the axial nip-joint device in Figure 9, but the nanowires in Figure 10 are completely bonded as a result of the growth of further n-AlGaN nanowire shell layers. Therefore, Figure 10 shows a pyramidal-tipped, positioned nanowire epitaxially grown on a crystalline substrate / interlayer supporting a porosity-etched graphene mask layer, but these nanowires are completely bonded as a result of the growth of further n-AlGaN nanowire shell layers.

[0256] Figure 11 (Case 1.4) is similar to Figure 10, but it shows aggregated nanopyramids instead of aggregated nanowires. Therefore, Figure 11 shows positioned nanopyramids epitaxially grown on a crystalline substrate / interlayer supporting a porosity-etched graphene mask layer, and these nanopyramids are completely aggregated as a result of further n-AlGaN nanowire shell layer growth.

[0257] Figure 12 shows the growth of nanopyramids on a graphene hole mask layer on a sapphire (0001) substrate. The grown structure is a coalesced axial nnip-junction GaN / AlGaN nanopyramid light-emitting diode (LED) structure (schematically shown in Figure 11 above). Figure 12a is a top-view SEM image taken after the initial growth of the n-AlGaN nanopyramids, and Figure 12b is a top-view SEM image taken after the n-AlGaN / n-AlGaN / i-GaN / p-AlGaN nanopyramid LED structure has fully grown.

[0258] Figure 13 shows the device characteristics of the sample shown in Figure 12b, which was fabricated into a 50 μm × 50 μm flip-chip LED. (a) is the current-voltage curve, and (b) is the electroluminescence (EL) spectrum of the corresponding LED, which emits light at 360 nm.

[0259] Figure 14 is a schematic diagram of growing nanopyramids (e.g., NW of AlGaN) directly in pores from an intermediate layer (e.g., AlN) and growing nanoislands / thin films (e.g., AlGaN) on graphene via remote epitaxy. With remote epitaxy, growth on graphene also exhibits good crystalline quality. A device structure with nip junctions is then obtained.

[0260] Figure 15 shows the growth of nanopyramids on a graphene hole mask layer on an AlN / sapphire (0001) substrate. The grown aggregate structure is an axial nnip-junction GaN / AlGaN nanopyramid light-emitting diode (LED) structure (schematically shown in Figure 11 above). Figure 15a is a top-view SEM image taken after the initial growth of the n-GaN nanopyramids, and Figure 15b is a top-view SEM image taken after the n-GaN / n-AlGaN / i-GaN / p-AlGaN nanopyramid LED structure has fully grown. Figure 15c shows top-view SEM images of seven positioned n-GaN nanopyramids, including one n-GaN triangle-based nanopyramid nucleated on the graphene mask by remote epitaxy. It can be seen that the nanoisland is nucleated such that its three facets are parallel to the facet orientations of three of the six facets of the hexagonal nanopyramid. Figure 15d shows the current-voltage curve of the sample shown in Figure 15, which was fabricated into a 50 μm × 50 μm flip-chip LED.

Claims

1. A structure comprising multiple III-V nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystal graphene layer, The graphene layer is directly supported on a crystalline substrate of single-crystal sapphire, or on an intermediate layer of crystalline group III-V semiconductor directly provided on the upper surface of a crystalline substrate of single-crystal sapphire. The nanowires or nanopyramids are grown through pores formed in the graphene layer, from the crystalline substrate if the intermediate layer is not provided, and from the intermediate layer if the intermediate layer is provided. The epitaxy, crystal orientation, and facet orientation of the nanowire or nanopyramid are oriented by the crystalline substrate. The plurality of group III-V nanowires or nanopyramids contain aluminum structure.

2. Epitaxial growth of group III-V nanowires or nanopyramids on a polycrystalline or single-crystal graphene layer, The graphene layer is directly supported on a crystalline substrate of single-crystal sapphire, or on an intermediate layer of crystalline group III-V semiconductor directly provided on the upper surface of a crystalline substrate of single-crystal sapphire. The nanowires or nanopyramids are grown through pores formed in the graphene layer, from the crystalline substrate if the intermediate layer is not provided, and from the intermediate layer if the intermediate layer is provided. A method comprising epitaxial growth of the nanowire or nanopyramid such that the epitaxy, crystal orientation, and facet orientation of the nanowire or nanopyramid are oriented by the crystalline substrate.

3. A plurality of III-V group nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystal graphene layer, wherein the graphene layer is directly supported on a crystalline substrate of single-crystal sapphire, or on an intermediate layer of crystalline III-V semiconductor directly provided on the upper surface of a crystalline substrate of single-crystal sapphire, the epitaxy, crystal orientation, and facet orientation of the nanowires or nanopyramids are oriented by the crystalline substrate, and the nanowires or nanopyramids are III-V group nanowires or nanopyramids having pn junctions or pin junctions. A first electrode that is in electrical contact with the graphene layer, The system comprises a second electrode in contact with at least a portion of the top of the nanowire or nanopyramid, The nanowires or nanopyramids are grown through pores formed in the graphene layer, from the crystalline substrate if the intermediate layer is not provided, and from the intermediate layer if the intermediate layer is provided. A light-emitting diode or photodetector device in which the nanowire or nanopyramid comprises at least one group III-V compound semiconductor.

4. The device according to claim 3, wherein the graphene layer has a thickness of 15 angstroms or less.

5. The device according to claim 3 or 4, wherein the nanowire or nanopyramid comprises GaN, AlGaN, InGaN, or AlInGaN.

6. The device according to any one of claims 3 to 5, wherein the nanowire or nanopyramid has multiple quantum wells.

7. The device according to any one of claims 3 to 6, wherein the nanowire or nanopyramid has an electron blocking layer which may be either a single barrier or a multiple quantum barrier.

8. A device according to any one of claims 3 to 7, which emits or absorbs in the UV spectrum.

9. The device according to any one of claims 3 to 8, wherein the pn junction or pin junction in the nanowire is axial or radial.

10. The device according to any one of claims 3 to 9, wherein the nanowire or nanopyramid has a tunnel junction having a GaN, AlN, AlGaN, or InGaN barrier layer.

11. The device according to any one of claims 3 to 10, wherein the nanowire or nanopyramid has an (Al)GaN / Al(GaN)N superlattice.

12. The device according to any one of claims 3 to 11, wherein the nanowire or nanopyramid comprises AlGaN, and the concentration of Al increases or decreases in one direction within the nanowire or nanopyramid.

13. The device according to any one of claims 3 to 12, wherein the nanowire or nanopyramid is doped with Si, Mg, Zn, or Be.

14. A device according to any one of claims 3 to 13, wherein the spaces between the nanowires or nanopyramids are filled with a supportive and electrically insulating filler material that is transparent to light emitted or absorbed in the device.

15. The device according to any one of claims 3 to 14, wherein, during use, light is emitted or absorbed in a direction substantially parallel and opposite to the growth direction of the nanowires.

16. The device according to any one of claims 3 to 14, wherein the graphene layer is a polycrystalline graphene layer.

17. A structure comprising multiple III-V nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystal graphene layer, The graphene layer is directly supported on a crystalline substrate of single-crystal sapphire, or on an intermediate layer of crystalline group III-V semiconductor directly provided on the upper surface of a crystalline substrate of single-crystal sapphire. The epitaxy, crystal orientation, and facet orientation of the nanowire or nanopyramid are oriented by the crystalline substrate. The nanowires or nanopyramids are grown through pores formed in the graphene layer, from the crystalline substrate if the intermediate layer is not provided, and from the intermediate layer if the intermediate layer is provided. A structure in which the nanowire or nanopyramid includes n-type doped regions and p-type doped regions separated by an intrinsic region, and the p-type doped region includes an electron-blocking layer.

18. A device comprising the structure described in claim 1 or 17.

19. The method according to claim 2, further comprising separating the crystalline substrate from the graphene layer having the grown nanowires or nanopyramids.

20. The device according to claim 3, wherein the second electrode in contact with at least a portion of the top of the nanowire or nanopyramid is in the form of a light-reflecting layer.

21. The device according to claim 6, wherein the multiple quantum wells include Al(In)GaN.

22. The device according to claim 12, wherein the one direction in the nanowire or nanopyramid is axial.

23. The device according to claim 18, wherein the device is an optoelectronic device.

24. The device according to claim 18, wherein the device is a solar cell, a photodetector, or an LED.

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