Driving circuit and liquid crystal display device

Abstract

To provide a drive circuit and liquid crystal display device that have high reliability in low power consumption.SOLUTION: A drive circuit of a liquid crystal display device according to the present embodiment comprises: a dummy DAC 180 that generates an adjustment voltage; a main DAC 190; a first voltage generator that supplies a first voltage to the dummy DAC; a second voltage generator that supplies a second voltage to the main DAC; a trimmable current source 140 that supplies a first current to the first voltage generator, and supplies a second current to the second voltage generator; a reference voltage / current generator that generates a reference voltage and reference current, and supplies the reference current to the trimmable current source 140; an ADC 110 that compares an output voltage from the dummy DAC 180 with a prescribed voltage, and supplies an adjustment signal for adjusting a current value to the trimmable current source 140 in accordance with a comparison result; and a start circuit 120.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a driving circuit and a liquid crystal display device.

Background Art

[0002] Patent Document 1 discloses a data line driving circuit for driving data lines of a liquid crystal display device. The data line driving circuit includes a first DAC, a second DAC, and a synthesizing circuit. The first DAC generates a gradation signal from gradation data. The second DAC generates a correction signal from correction data. The synthesizing circuit synthesizes the gradation signal and the correction signal to generate a data signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a driving circuit, there is a desire to operate with higher reliability while suppressing power consumption. For example, it is desirable to operate with high reliability even when there are fluctuations in the frame frequency or PVT (Process Voltage Temperature).

[0005] The present disclosure has been made in view of the above points, and an object thereof is to provide a driving circuit and a liquid crystal display device that can operate with higher reliability while suppressing power consumption.

Means for Solving the Problems

[0006] The drive circuit according to this embodiment is a drive circuit for driving a liquid crystal display device having a plurality of pixels, and comprises a dummy DAC (Digital to Analog Converter) that generates an adjustment voltage, a plurality of main DACs that generate a drive voltage to drive the pixels, a first voltage generator that supplies a first voltage to the dummy DAC, a second voltage generator that supplies a second voltage to the main DAC, a trimmable current source that supplies a first current to the first voltage generator and a second current to the second voltage generator, a reference voltage / reference current generator that generates a reference voltage and a reference current, supplies the reference voltage to the dummy DAC and the main DAC, and supplies the reference current to the trimmable current source, and an ADC (Analog to Digital Converter) that compares the adjustment voltage from the dummy DAC with a predetermined voltage and supplies an adjustment signal to the trimmable current source to adjust the current value according to the comparison result. The device comprises a converter and a start circuit for starting the operation of the ADC. When the adjustment voltage from the dummy DAC reaches the predetermined voltage, the ADC outputs a stop signal to stop the dummy DAC, the first voltage generator, and the start circuit, and the trimmable current source outputs a second current adjusted by the adjustment signal to the second voltage generator.

[0007] According to this disclosure, it is possible to provide a low-power, highly reliable drive circuit and a liquid crystal display device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram showing the configuration of a drive circuit using a DAC. [Figure 2] This is a timing chart showing the signal waveform. [Figure 3] This is a circuit diagram showing the configuration of the ADC. [Figure 4] This is a circuit diagram showing the configuration of the dummy DAC180. [Figure 5] This is a circuit diagram showing the configuration of the main DAC190. [Figure 6]This diagram shows the configuration of a liquid crystal display device using a drive circuit. [Modes for carrying out the invention]

[0009] Specific embodiments to which the present invention is applied will be described in detail below with reference to the drawings. However, this disclosure is not limited to the following embodiments. Also, for clarity of explanation, the following description and drawings have been simplified as appropriate.

[0010] The following describes the drive circuit according to this embodiment. Figure 1 is a circuit diagram showing the configuration of a resistor string DAC 100 provided in the drive circuit 100. The drive circuit 100 is equipped with a resistor string DAC. The drive circuit 100 receives gradation data indicating the gradation of each pixel as input. The drive circuit 100 drives each pixel according to the input data. Specifically, the drive circuit 100 supplies a drive voltage to the data line of the liquid crystal display device.

[0011] The drive circuit 100 includes an ADC 110, a start circuit 120, a 4-frequency divider circuit 130, a trimmable current source 140, a first bias voltage generator 150, a second bias voltage generator 160, a reference voltage / reference current generator 170, a dummy DAC 180, and multiple main DACs 190.

[0012] The drive circuit 100 receives data [1:b][1:c] and a clock signal Clock. Here, b represents the number of bits in the pixel, and c represents the number of columns. The drive circuit 100 is equipped with multiple main DACs 190, corresponding to the number of columns c. Each main DAC 190 receives data [1:b][1:c] and a clock signal Clock.

[0013] The main DAC190 converts the data[1:b][1:c] into analog signals in synchronization with the clock signal Clock. The main DAC190 generates a voltage representing a ramp waveform based on the reference voltage Vref[1:k]. A main DAC190 is provided for each column of the liquid crystal display. Each main DAC190 outputs a positive output signal OP[1:c] and a negative output signal ON[1:c]. Output signal ON[1:c] is the positive drive signal that drives the pixels of the liquid crystal display. Output signal ON[1:c] is the negative drive signal that drives the pixels of the liquid crystal display. By alternately outputting positive and negative output signals to the data lines, each pixel is driven in inverting direction.

[0014] The dummy DAC180 generates an adjustment voltage based on the reference voltage Vref[1:k] and outputs it as the output signal OD. The output signal OD from the dummy DAC180 is input to the ADC110. Two voltages Vmax and Vmin are input to the ADC110. The ADC110 is also input to three divided signals PH0, PH1, and PH2 from a 4-frequency divider circuit. The divided signals PH0, PH1, and PH2 are signals with the same frequency but different phases.

[0015] The ADC110 can detect the analog output signal OD from the dummy DAC180. The ADC110 generates a digital binary code Binary[1:n] and a one-hot code One-hot[1:m] from the analog output signal OD. The configuration of the ADC110 will be described later.

[0016] The ADC110 generates a binary code Binary[1:n], a one-hot code One-hot[1:m], and a stop signal LST, where n and m are the number of bits. The ADC110 outputs the stop signal LST to the dummy DAC180, the first bias voltage generator 150, and the start circuit 120. The ADC110 also outputs the binary code Binary[1:n] and the one-hot code One-hot[1:m] to the trimmable current source 140. As described later, the stop signal LST functions as a stop command to stop the operation of the start circuit 120, the first bias voltage generator 150, the ADC110, and the dummy DAC180.

[0017] The reference voltage / reference current generator 170 generates a stable reference voltage Vref[1:k], voltage Vmin, and voltage Vmax (where k is equal to 2^b). Furthermore, the reference voltage / reference current generator 170 generates a stable reference current Ib. The reference voltage / reference current generator 170 supplies the reference current Ib to the trimmable current source 140. The reference voltage / reference current generator 170 supplies voltages Vmin and Vmax to the ADC 110.

[0018] The reference voltage / reference current generator 170 supplies a reference voltage Vref[1:k] to the dummy DAC 180 and the main DAC 190. The reference voltage Vref[1:k] corresponds to the drive voltage for driving the pixels according to the grayscale. The reference voltage / reference current generator 170 has a resistor string for generating the reference voltage Vref[1:k]. In the resistor string, multiple resistors are connected in series. The reference voltage / reference current generator 170 generates a reference voltage Vref[1:k] corresponding to the number of grayscale levels by resistive voltage division. Of the reference voltages Vref[1:k], the reference voltage Vref[k] is the highest voltage and the reference voltage[1] is the lowest voltage. Voltage Vmax is lower than the reference voltage Vref[k]. Voltage Vmin is higher than the reference voltage Vref[1].

[0019] The trimable current source 140 receives the binary code Binary[1:n] from the ADC110 and the one-hot code One-hot[1:m]. The trimable current source 140 is controlled by the binary code Binary[1:n] and the one-hot code One-hot[1:m] to generate output currents Ib1 and Ib2. The binary code Binary[1:n] and the one-hot code One-hot[1:m] are adjustment signals for adjusting the current values of the output currents Ib1 and Ib2 described later.

[0020] Furthermore, the trimable current source 140 is supplied with a reference current Ib from the reference voltage and reference current generator 170. The trimable current source 140 generates two output currents Ib1 and Ib2 based on the reference current Ib. The trimable current source 140 outputs the output current Ib1 to the first bias voltage generator 150. The trimable current source 140 outputs the output current Ib2 to the second bias voltage generator 160. The output current Ib2 compensates for the voltage difference between the voltage Vmax and the reference voltage Vref[k], and the voltage difference between the voltage Vmin and the reference voltage Vref[1].

[0021] The first bias voltage generator 150 converts the output current Ib1 into a plurality of bias voltages Vb1[1:d]. The second bias voltage generator 160 converts the output current Ib2 into a plurality of bias voltages Vb2[1:d]. d is an integer of 2 or more.

[0022] The start circuit 120 is a circuit for starting the operation of the ADC 110 and other components. The start circuit 120 delays the start time of the clock signal Clock by one cycle and outputs it to the 4-frequency divider circuit 130. The 4-frequency divider circuit 130 divides the clock signal Clock by four to generate divided signals PH0, PH1, and PH2. The divided signals PH0, PH1, and PH2 have frequencies that are 1 / 4 of the clock signal Clock. The divided signals PH0, PH1, and PH2 each have different phases. The 4-frequency divider circuit 130 outputs the divided signals PH0, PH1, and PH2 to the ADC 110. The start circuit 120, the first bias voltage generator 150, the dummy DAC 180, and the ADC 110 terminate their operation in response to the stop signal LST.

[0023] The binary code Binary[1:n] and one-hot code One-hot[1:m] supplied from ADC110 control the output currents Ib1 and Ib2 of the trimmable current source 140 so that the main DAC190 can cope with large fluctuations in frame frequency.

[0024] When the values ​​of the binary code Binary[1:n] and the one-hot code One-hot[1:m] increase, the output currents Ib1 and Ib2 increase. When the values ​​of the binary code Binary[1:n] and the one-hot code One-hot[1:m] decrease, the output currents Ib1 and Ib2 decrease. The bias voltage Vb1[1:d] changes according to the output current Ib1. The bias voltage Vb2[1:d] changes according to the output current Ib2. This allows for correction of the output signals OP and ON of the main DAC190. In this way, the effects of frame frequency and PVT fluctuations can be reduced. Therefore, reliability can be improved and high display quality can be achieved.

[0025] Furthermore, the ADC110 outputs a stop signal LST to stop the adjustment operation. This reduces power consumption. For example, the ADC110 performs adjustment operations during initialization or power-on. Once the adjustment operation is complete, the ADC110 outputs a stop signal to the dummy DAC180, etc. After the adjustment operation is complete, the dummy DAC180 and ADC110, etc. stop operating during normal operation, thus reducing power consumption.

[0026] Figure 2 shows the timing chart for each signal. Divided signals PH0 to PH2 have the same frequency but different phases. Divided signals PH0 to PH2 have a frequency that is 1 / 4 of the clock signal Clock. With the period of the clock signal Clock being 1 cycle, divided signal PH1 is in the cycle following divided signal PH0. Divided signal PH2 is in the cycle following divided signal PH1.

[0027] When the clock signal Clock is input, the output signal OD goes high during the first cycle of the clock signal Clock. In the second cycle, the frequency divider signal PH0 goes high, and the ADC110 detects the output signal OD by comparing it with a predetermined voltage Vmax. In the third cycle, the frequency divider signal PH1 goes high, and the ADC110 detects the output signal OD by comparing it with a predetermined voltage Vmin. In the fourth cycle, when the frequency divider signal PH2 goes high, the ADC110 updates the output according to the comparison results of the second and third cycles, correcting the output signal OD.

[0028] Figure 3 is a circuit diagram showing an example of the configuration of ADC110. ADC110 comprises flip-flop circuits FF0 and FF1, and 1-bit quantizers CP0 and CP1. ADC110 also comprises finite state machines FSM01, FSM02, FSM11, FSM01, and FSM12, OR circuits o1, o2, o3, and o4, and an inverter i1. Furthermore, ADC110 comprises a decoder 111, an r-bit up / down counter 112, and an n-bit up / down counter 113.

[0029] The quantizers CP0 and CP1 are input to the adjustment output signal OD. The quantizer CP0 is supplied with a voltage Vmax. The quantizer CP0 functions as a comparator that compares the output signal OD with the voltage Vmax. In other words, the quantizer CP0 determines whether the output signal OD exceeds a predetermined voltage Vmax. The quantizer CP0 converts the output signal OD into a digital output according to the comparison result.

[0030] The quantizer CP1 is supplied with a voltage Vmin. The quantizer CP1 functions as a comparator that compares the output signal OD with the voltage Vmin. In other words, the quantizer CP1 determines whether the output signal OD exceeds a predetermined voltage Vmin. The quantizer CP1 converts the output signal OD into a digital output according to the comparison result. Also, when the stop signal LST is asserted, the quantizers CP0 and CP1 stop operating.

[0031] Quantizer CP0 outputs a digital signal indicating the comparison result to flip-flop circuit FF0. Quantizer CP1 outputs a digital signal indicating the comparison result to flip-flop circuit FF1. The flip-flop circuit FF0 is input to the frequency divider signal PH0, and the flip-flop circuit FF1 is input to the frequency divider signal PH1. Flip-flop circuits FF0 and FF1 sample the input data according to the timing of the frequency divider signals PH0 and PH1, respectively. Flip-flop circuit FF0 samples the input data sequentially in synchronization with the frequency divider signal PH0. Flip-flop circuit FF1 samples the input data sequentially in synchronization with the frequency divider signal PH1.

[0032] The flip-flop circuit FF0 generates logic 0 when the input data is logic 1 and outputs it to the OR circuit o3. The flip-flop circuit FF1 generates logic 1 when the input data is logic 1 and outputs it to the OR circuit o3. The OR circuit o3 outputs the logical OR of the two logics to the up / down counters 112 and 113. Therefore, when the input of flip-flop circuit FF0 is logic 1 and the input of flip-flop circuit FF1 is logic 0, the output of OR circuit o3 is logic 0, and otherwise the output of OR circuit o3 is logic 1.

[0033] Finite state machines FSM01 and FSM02 receive the inverted output of quantizer CP0 as input. Finite state machines FSM01 and FSM02 assert their outputs when they receive two consecutive bits 0 and 1. That is, if a digital signal indicating 1 is output immediately after a digital signal indicating 0 is output from quantizer CP0, finite state machines FSM01 and FSM02 assert their outputs. Therefore, finite state machines FSM01 and FSM02 can detect the timing when the value of the output data of quantizer CP0 switches from 0 to 1. In this way, ADC110 can detect when the output signal OD reaches a predetermined voltage Vmax.

[0034] Finite state machines FSM11 and FSM12 receive the output from quantizer CP1 as input. When finite state machines FSM11 and FSM12 receive two consecutive bits 1 and 0, they assert their outputs. In other words, if a digital signal indicating 0 is output immediately after a digital signal indicating 1 is output from quantizer CP1, finite state machines FSM11 and FSM12 assert their outputs. Therefore, finite state machines FSM11 and FSM12 can detect the timing when the value of the output data from quantizer CP1 switches from 1 to 0. In this way, ADC110 can detect when the output signal OD reaches a predetermined voltage Vmin.

[0035] Data from finite state machines FSM01 and FSM11 are input to OR circuit o1. OR circuit o1 outputs the logical OR of its two outputs as a stop signal LST. When the output of finite state machine FSM01 or finite state machine FSM11 is asserted, the operation of ADC110 and other devices stops. When the output signal OD reaches a predetermined voltage, ADC110 outputs the stop signal LST. This completes the adjustment process.

[0036] Data from finite state machines FSM02 and FSM12 are input to OR gate o2. OR gate o2 outputs the logical OR of the two logic signals to OR gate o4.

[0037] The up-down counters 112 and 113 are clock-driven by the frequency divider signal PH2. In other words, the up-down counters 112 and 113 perform counting operations in synchronization with the frequency divider signal PH2. The up-down counters 112 and 113 switch between count-up and count-down operations depending on the output of the OR circuit o3. When the output of the OR circuit o3 is logic 1, the up-down counters 112 and 113 perform count-up operations. On the other hand, when the output of the OR circuit o3 is logic 0, the up-down counters 112 and 113 perform count-down operations.

[0038] The r-bit up / down counter 112 outputs a count signal ca[1:r] indicating the count result to the decoder 111. The count signal ca[1:r] is an r-bit digital signal. Also, when the count signal of the r-bit up / down counter 112 reaches its maximum or minimum value, a stop signal st0 is asserted. The r-bit up / down counter 112 outputs the stop signal st0 to the OR circuit o4. The OR circuit o4 outputs the logical OR as a stop signal st1. The inverter i1 inverts the stop signal st1 to generate a stop signal st2. The inverter i1 outputs the stop signal st2 to the n-bit up / down counter 113.

[0039] The finite state machines FSM02 and FSM12, and the r-bit up / down counter 112, stop operating in response to the stop signal st1. The finite state machines FSM01 and FSM11, and the n-bit up / down counter 113 stop operating in response to the stop signal st2. Therefore, when the stop signal st0 is asserted, the finite state machines FSM02 and FSM12, and the r-bit up / down counter 112 stop operating, and the finite state machines FSM01 and FSM11, and the n-bit up / down counter 113 start operating.

[0040] The r-bit up / down counter 112 outputs a count signal ca[1:r] to the decoder 111. The decoder 111 decodes the count signal ca[1:r] and outputs the decoded data as a one-hot code One-hot[1:m]. To generate a one-hot code One-hot[1:m] for large fluctuations in the input frequency, the decoder 111 decodes the data of the count signal ca[1:r]. The decoder 111 decodes the r-bit data and outputs a 2^r signal. The n-bit up / down counter 113 outputs the count result as a binary code Binary[1:n]. The binary code Binary[1:n] is a binarized code used for fine corrections. In this way, the ADC 110 generates two adjustment signals.

[0041] Figure 4 is a circuit diagram showing an example of the configuration of the dummy DAC 180. The dummy DAC 180 comprises a decoder 181, a decoder 182, a frequency divider circuit 183, a voltage follower 184, and a voltage follower 185. The frequency divider circuit 183 divides the input clock signal Clock by two. The frequency divider circuit 183 also stops its operation in response to a stop signal LST.

[0042] The frequency divider circuit 183 outputs the divided clock signal to the decoder 181. The frequency divider circuit 183 inverts the divided clock signal and outputs it to the decoder 182. A reference voltage Vref[1:k] is supplied to the decoder. Decoders 181 and 182 perform decoding based on the divided clock signal and generate a digital code. The output of decoder 182 is an inverted digital code.

[0043] Decoders 181 and 182 output digital codes to voltage followers 184 and 185, respectively. Voltage followers 184 and 185 are biased with the voltage Vb1[1:d]. Therefore, the dummy DAC 180 can properly compensate for frame frequency and PVT fluctuations.

[0044] Voltage follower 184 outputs a positive polarity output signal OP. Voltage follower 185 outputs a negative polarity output signal ON. The positive polarity output signal OP is input to ADC110 as output signal OD. The output of voltage follower 185 is open.

[0045] Figure 5 is a circuit diagram showing the configuration of the main DAC 190. The main DAC 190 comprises a decoder 191, a decoder 192, a voltage follower 194, a voltage follower 195, and a latch circuit 196.

[0046] The latch circuit 196 receives the data Data[1:b] and the clock signal Clock as inputs. The latch circuit 196 latches the data Data[1:b] in synchronization with the clock signal Clock. The latch circuit 196 outputs the data Data[1:b] to the decoder 191. The latch circuit 196 inverts the data Data[1:b] and outputs it to the decoder 192.

[0047] Decoders 191 and 192 output digital codes to voltage followers 194 and 195, respectively. Voltage followers 194 and 195 are biased with a voltage of Vb2[1:d]. Voltage follower 184 outputs a positive output signal OP. Voltage follower 185 outputs a negative output signal ON. The positive output signal OP is input to ADC110 as output signal OD. The output of voltage follower 185 is open.

[0048] Thus, since the voltage followers 194 and 195 are biased with the bias voltage Vb2[1:d], the main DAC 190 can generate appropriately corrected output signals OP and ON.

[0049] By using such a drive circuit 100, it is possible to respond to fluctuations in frame frequency or PVT. It is possible to detect and correct the delay and slew rate of the DAC output that depend on PVT fluctuations. The reliability of the drive circuit 100 can be improved. In addition, since the operation of the ADC 110 and other components can be stopped after the adjustment is complete, power consumption can be reduced.

[0050] Furthermore, the output current Ib1 from the trimmable current source 140 is lower than the output current Ib2. The output current Ib2, which is higher than the output current Ib1, is supplied to the main DAC 190. Therefore, the voltage difference between voltage Vmax and reference voltage Vref[k], and the voltage difference between voltage Vmin and reference voltage Vref[1] can be appropriately compensated. High-precision correction can be performed, and reliability can be improved.

[0051] Furthermore, the ADC110 outputs two adjustment signals to the trimmable current source 140: a one-hot code (One-hot[1:m]) and a binary code (Binary[1:n]) for finer adjustments than the one-hot code (One-hot[1:m]). The one-hot code (One-hot[1:m]) is an adjustment signal for making relatively rough adjustments. The binary code (Binary[1:n]) is an adjustment signal for making fine adjustments. In this way, highly accurate corrections can be performed quickly.

[0052] Figure 6 is a block diagram showing the configuration of the backplane of the liquid crystal display device 200. The liquid crystal display device 200 comprises a horizontal drive circuit 3, a vertical drive circuit 2, and a pixel display unit 50. The liquid crystal display device 200 is, for example, an LCOS (Liquid-Crystal On-Silicon) display. The resistor string DAC circuit 320 of the horizontal drive circuit 3 corresponds to the drive circuit 100 in Figure 1.

[0053] The pixel display unit 50 is provided with multiple data lines 6, multiple gate lines 8, and multiple pixels 42. The multiple data lines 6 are arranged parallel to each other. The multiple gate lines 8 are arranged parallel to each other. The multiple data lines 6 and the multiple gate lines 8 are arranged to intersect each other. The gate lines 8 become row scan lines.

[0054] The liquid crystal display device 200 is equipped with multiple sets of data lines 6, each set consisting of two lines. The liquid crystal display device 200 uses one set of data lines 6 to invert the pixels 42. Hereinafter, the positive terminal data line 6 of one set of data lines 6 will be referred to as data line 6a, and the negative terminal data line 6 will be referred to as data line 6b.

[0055] Pixels 42 are located at the intersections of data lines 6 and gate lines 8. The pixels 42 are arranged in a matrix. Each pixel 42 is driven by one pair of data lines 6 and one gate line 8. The pixels 42 are equipped with pixel driving circuits and pixel electrodes for driving the liquid crystal.

[0056] The vertical drive circuit 2 performs vertical drive, selecting multiple gate lines 8 for each horizontal scanning period. The vertical drive circuit 2 operates on a clock signal Clock2. The vertical drive circuit 2 supplies scan signals to the multiple gate lines 8. In other words, the vertical drive circuit 2 supplies scan signals to sequentially select the gate lines 8 from the first row to the last row. As a result, pixels 42 are selected sequentially row by row. All gate lines 8 are selected within one vertical scanning period. The selected row of pixels 42 can then be used to write the video signal.

[0057] The horizontal drive circuit 3 performs horizontal driving to drive one row of pixels 42 within the horizontal scanning period. As a result, video signals are supplied to multiple data lines 6. As described above, two data lines 6a and 6b are connected to the pixels 42 as a pair. Therefore, two data lines 6a and 6b are commonly connected to one row of pixels 42.

[0058] The horizontal drive circuit 3 includes a resistor string DAC circuit 320 and a shift register 360. The shift register 360 sequentially transmits c columns of data in response to the clock signal Clock1. Once the shift register 360 has held c columns of data, it outputs it to the resistor string DAC circuit 320.

[0059] The resistor string DAC circuit 320 receives a clock signal Clock2 that is slower than the clock signal Clock1. The resistor string DAC circuit 320 is clock-driven by the clock signal Clock2. Each of the main DACs 190 in Figure 1 drives one row of pixels. The resistor string DAC circuit 320 corresponds to the drive circuit 100 in Figure 1. In other words, the main DAC 190 outputs the output signal OP to data line 6a and the output signal ON to data line 6b.

[0060] In this embodiment, the resistor string DAC circuit 320 corresponds to the drive circuit 100 in Figure 1. This makes it possible to realize a liquid crystal display device 200 with low power consumption and high reliability.

[0061] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0062] 100 drive circuit 110 ADC 120 Start Circuit 130 4 frequency divider circuit 140 Trimable current source 150 First bias voltage generator 160 Second bias voltage generator 170 Reference Voltage / Reference Current Generator 180 Dummy DAC 190 Main DAC

Claims

1. A drive circuit for driving a liquid crystal display device having multiple pixels, A dummy DAC (Digital to Analog Converter) that generates the adjustment voltage, Multiple main DACs that generate drive voltages to drive the aforementioned pixels, A first voltage generator that supplies a first voltage to the dummy DAC, A second voltage generator that supplies a second voltage to the main DAC, A trimmable current source that supplies a first current to the first voltage generator and a second current to the second voltage generator, A reference voltage / reference current generator that generates a reference voltage and a reference current, supplies the reference voltage to the dummy DAC and the main DAC, and supplies the reference current to the trimmable current source, An Analog-to-Digital Converter (ADC) compares the adjustment voltage from the dummy DAC with a predetermined voltage and supplies an adjustment signal to the trimmable current source to adjust the current value according to the comparison result. The system includes a start circuit for initiating the operation of the ADC, When the adjustment voltage from the dummy DAC reaches the predetermined voltage, the ADC outputs a stop signal to stop the dummy DAC, the first voltage generator, and the start circuit. The trimmable current source is a drive circuit that outputs a second current, adjusted by the adjustment signal, to the second voltage generator.

2. The drive circuit according to claim 1, characterized in that the first current is less than the second current.

3. The ADC supplies a first adjustment signal and a second adjustment signal to the trimmable current source as adjustment signals. The first adjustment signal is a signal consisting of one hot code, and the second adjustment signal is a signal consisting of a binary code. The drive circuit according to claim 1 or 2.

4. A liquid crystal display device comprising the drive circuit according to claim 1 or 2.

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